1154ebdb7SSuraj Kandpal /* SPDX-License-Identifier: MIT 2154ebdb7SSuraj Kandpal * 3154ebdb7SSuraj Kandpal * Copyright © 2025 Intel Corporation 4154ebdb7SSuraj Kandpal */ 5154ebdb7SSuraj Kandpal 6154ebdb7SSuraj Kandpal #ifndef __INTEL_LT_PHY_H__ 7154ebdb7SSuraj Kandpal #define __INTEL_LT_PHY_H__ 8154ebdb7SSuraj Kandpal 9154ebdb7SSuraj Kandpal #include <linux/types.h> 10154ebdb7SSuraj Kandpal 119dcf1836SSuraj Kandpal struct intel_atomic_state; 123a6f155cSSuraj Kandpal struct intel_display; 13154ebdb7SSuraj Kandpal struct intel_encoder; 14154ebdb7SSuraj Kandpal struct intel_crtc_state; 159dcf1836SSuraj Kandpal struct intel_crtc; 162435a11dSSuraj Kandpal struct intel_lt_phy_pll_state; 17154ebdb7SSuraj Kandpal 18154ebdb7SSuraj Kandpal void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 19154ebdb7SSuraj Kandpal const struct intel_crtc_state *crtc_state); 20fa5fd596SSuraj Kandpal void intel_lt_phy_pll_disable(struct intel_encoder *encoder); 21dc5742b6SSuraj Kandpal int 22dc5742b6SSuraj Kandpal intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, 23dc5742b6SSuraj Kandpal struct intel_encoder *encoder); 242435a11dSSuraj Kandpal int intel_lt_phy_calc_port_clock(struct intel_encoder *encoder, 252435a11dSSuraj Kandpal const struct intel_crtc_state *crtc_state); 2613ba213fSSuraj Kandpal void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, 2713ba213fSSuraj Kandpal const struct intel_crtc_state *crtc_state); 283a6f155cSSuraj Kandpal void intel_lt_phy_dump_hw_state(struct intel_display *display, 293a6f155cSSuraj Kandpal const struct intel_lt_phy_pll_state *hw_state); 303a6f155cSSuraj Kandpal bool 313a6f155cSSuraj Kandpal intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, 323a6f155cSSuraj Kandpal const struct intel_lt_phy_pll_state *b); 3389e0a91eSSuraj Kandpal void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, 3489e0a91eSSuraj Kandpal const struct intel_crtc_state *crtc_state, 3589e0a91eSSuraj Kandpal struct intel_lt_phy_pll_state *pll_state); 369dcf1836SSuraj Kandpal void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state, 379dcf1836SSuraj Kandpal struct intel_crtc *crtc); 38*6fedb7bfSSuraj Kandpal int 39*6fedb7bfSSuraj Kandpal intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state, 40*6fedb7bfSSuraj Kandpal u32 frequency_khz); 4110928925SSuraj Kandpal void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, 4210928925SSuraj Kandpal const struct intel_crtc_state *crtc_state); 4310928925SSuraj Kandpal void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); 44dc5742b6SSuraj Kandpal 45dc5742b6SSuraj Kandpal #define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35) 46154ebdb7SSuraj Kandpal 47154ebdb7SSuraj Kandpal #endif /* __INTEL_LT_PHY_H__ */ 48