1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2025 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "intel_cx0_phy.h" 9 #include "intel_cx0_phy_regs.h" 10 #include "intel_ddi.h" 11 #include "intel_ddi_buf_trans.h" 12 #include "intel_de.h" 13 #include "intel_display.h" 14 #include "intel_display_types.h" 15 #include "intel_display_utils.h" 16 #include "intel_dpll.h" 17 #include "intel_dpll_mgr.h" 18 #include "intel_hdmi.h" 19 #include "intel_lt_phy.h" 20 #include "intel_lt_phy_regs.h" 21 #include "intel_panel.h" 22 #include "intel_psr.h" 23 #include "intel_tc.h" 24 25 #define for_each_lt_phy_lane_in_mask(__lane_mask, __lane) \ 26 for ((__lane) = 0; (__lane) < 2; (__lane)++) \ 27 for_each_if((__lane_mask) & BIT(__lane)) 28 29 #define INTEL_LT_PHY_LANE0 BIT(0) 30 #define INTEL_LT_PHY_LANE1 BIT(1) 31 #define INTEL_LT_PHY_BOTH_LANES (INTEL_LT_PHY_LANE1 |\ 32 INTEL_LT_PHY_LANE0) 33 #define MODE_DP 3 34 #define MODE_HDMI_20 4 35 #define Q32_TO_INT(x) ((x) >> 32) 36 #define Q32_TO_FRAC(x) ((x) & 0xFFFFFFFF) 37 #define DCO_MIN_FREQ_MHZ 11850 38 #define REF_CLK_KHZ 38400 39 #define TDC_RES_MULTIPLIER 10000000ULL 40 41 struct phy_param_t { 42 u32 val; 43 u32 addr; 44 }; 45 46 struct lt_phy_params { 47 struct phy_param_t pll_reg4; 48 struct phy_param_t pll_reg3; 49 struct phy_param_t pll_reg5; 50 struct phy_param_t pll_reg57; 51 struct phy_param_t lf; 52 struct phy_param_t tdc; 53 struct phy_param_t ssc; 54 struct phy_param_t bias2; 55 struct phy_param_t bias_trim; 56 struct phy_param_t dco_med; 57 struct phy_param_t dco_fine; 58 struct phy_param_t ssc_inj; 59 struct phy_param_t surv_bonus; 60 }; 61 62 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_rbr = { 63 .config = { 64 0x83, 65 0x2d, 66 0x0, 67 }, 68 .addr_msb = { 69 0x87, 70 0x87, 71 0x87, 72 0x87, 73 0x88, 74 0x88, 75 0x88, 76 0x88, 77 0x88, 78 0x88, 79 0x88, 80 0x88, 81 0x88, 82 }, 83 .addr_lsb = { 84 0x10, 85 0x0c, 86 0x14, 87 0xe4, 88 0x0c, 89 0x10, 90 0x14, 91 0x18, 92 0x48, 93 0x40, 94 0x4c, 95 0x24, 96 0x44, 97 }, 98 .data = { 99 { 0x0, 0x4c, 0x2, 0x0 }, 100 { 0x5, 0xa, 0x2a, 0x20 }, 101 { 0x80, 0x0, 0x0, 0x0 }, 102 { 0x4, 0x4, 0x82, 0x28 }, 103 { 0xfa, 0x16, 0x83, 0x11 }, 104 { 0x80, 0x0f, 0xf9, 0x53 }, 105 { 0x84, 0x26, 0x5, 0x4 }, 106 { 0x0, 0xe0, 0x1, 0x0 }, 107 { 0x4b, 0x48, 0x0, 0x0 }, 108 { 0x27, 0x8, 0x0, 0x0 }, 109 { 0x5a, 0x13, 0x29, 0x13 }, 110 { 0x0, 0x5b, 0xe0, 0x0a }, 111 { 0x0, 0x0, 0x0, 0x0 }, 112 }, 113 }; 114 115 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr1 = { 116 .config = { 117 0x8b, 118 0x2d, 119 0x0, 120 }, 121 .addr_msb = { 122 0x87, 123 0x87, 124 0x87, 125 0x87, 126 0x88, 127 0x88, 128 0x88, 129 0x88, 130 0x88, 131 0x88, 132 0x88, 133 0x88, 134 0x88, 135 }, 136 .addr_lsb = { 137 0x10, 138 0x0c, 139 0x14, 140 0xe4, 141 0x0c, 142 0x10, 143 0x14, 144 0x18, 145 0x48, 146 0x40, 147 0x4c, 148 0x24, 149 0x44, 150 }, 151 .data = { 152 { 0x0, 0x4c, 0x2, 0x0 }, 153 { 0x3, 0xca, 0x34, 0xa0 }, 154 { 0xe0, 0x0, 0x0, 0x0 }, 155 { 0x5, 0x4, 0x81, 0xad }, 156 { 0xfa, 0x11, 0x83, 0x11 }, 157 { 0x80, 0x0f, 0xf9, 0x53 }, 158 { 0x84, 0x26, 0x7, 0x4 }, 159 { 0x0, 0xe0, 0x1, 0x0 }, 160 { 0x43, 0x48, 0x0, 0x0 }, 161 { 0x27, 0x8, 0x0, 0x0 }, 162 { 0x5a, 0x13, 0x29, 0x13 }, 163 { 0x0, 0x5b, 0xe0, 0x0d }, 164 { 0x0, 0x0, 0x0, 0x0 }, 165 }, 166 }; 167 168 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr2 = { 169 .config = { 170 0x93, 171 0x2d, 172 0x0, 173 }, 174 .addr_msb = { 175 0x87, 176 0x87, 177 0x87, 178 0x87, 179 0x88, 180 0x88, 181 0x88, 182 0x88, 183 0x88, 184 0x88, 185 0x88, 186 0x88, 187 0x88, 188 }, 189 .addr_lsb = { 190 0x10, 191 0x0c, 192 0x14, 193 0xe4, 194 0x0c, 195 0x10, 196 0x14, 197 0x18, 198 0x48, 199 0x40, 200 0x4c, 201 0x24, 202 0x44, 203 }, 204 .data = { 205 { 0x0, 0x4c, 0x2, 0x0 }, 206 { 0x1, 0x4d, 0x34, 0xa0 }, 207 { 0xe0, 0x0, 0x0, 0x0 }, 208 { 0xa, 0x4, 0x81, 0xda }, 209 { 0xfa, 0x11, 0x83, 0x11 }, 210 { 0x80, 0x0f, 0xf9, 0x53 }, 211 { 0x84, 0x26, 0x7, 0x4 }, 212 { 0x0, 0xe0, 0x1, 0x0 }, 213 { 0x43, 0x48, 0x0, 0x0 }, 214 { 0x27, 0x8, 0x0, 0x0 }, 215 { 0x5a, 0x13, 0x29, 0x13 }, 216 { 0x0, 0x5b, 0xe0, 0x0d }, 217 { 0x0, 0x0, 0x0, 0x0 }, 218 }, 219 }; 220 221 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_hbr3 = { 222 .config = { 223 0x9b, 224 0x2d, 225 0x0, 226 }, 227 .addr_msb = { 228 0x87, 229 0x87, 230 0x87, 231 0x87, 232 0x88, 233 0x88, 234 0x88, 235 0x88, 236 0x88, 237 0x88, 238 0x88, 239 0x88, 240 0x88, 241 }, 242 .addr_lsb = { 243 0x10, 244 0x0c, 245 0x14, 246 0xe4, 247 0x0c, 248 0x10, 249 0x14, 250 0x18, 251 0x48, 252 0x40, 253 0x4c, 254 0x24, 255 0x44, 256 }, 257 .data = { 258 { 0x0, 0x4c, 0x2, 0x0 }, 259 { 0x1, 0x4a, 0x34, 0xa0 }, 260 { 0xe0, 0x0, 0x0, 0x0 }, 261 { 0x5, 0x4, 0x80, 0xa8 }, 262 { 0xfa, 0x11, 0x83, 0x11 }, 263 { 0x80, 0x0f, 0xf9, 0x53 }, 264 { 0x84, 0x26, 0x7, 0x4 }, 265 { 0x0, 0xe0, 0x1, 0x0 }, 266 { 0x43, 0x48, 0x0, 0x0 }, 267 { 0x27, 0x8, 0x0, 0x0 }, 268 { 0x5a, 0x13, 0x29, 0x13 }, 269 { 0x0, 0x5b, 0xe0, 0x0d }, 270 { 0x0, 0x0, 0x0, 0x0 }, 271 }, 272 }; 273 274 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr10 = { 275 .config = { 276 0x43, 277 0x2d, 278 0x0, 279 }, 280 .addr_msb = { 281 0x85, 282 0x85, 283 0x85, 284 0x85, 285 0x86, 286 0x86, 287 0x86, 288 0x86, 289 0x86, 290 0x86, 291 0x86, 292 0x86, 293 0x86, 294 }, 295 .addr_lsb = { 296 0x10, 297 0x0c, 298 0x14, 299 0xe4, 300 0x0c, 301 0x10, 302 0x14, 303 0x18, 304 0x48, 305 0x40, 306 0x4c, 307 0x24, 308 0x44, 309 }, 310 .data = { 311 { 0x0, 0x4c, 0x2, 0x0 }, 312 { 0x1, 0xa, 0x20, 0x80 }, 313 { 0x6a, 0xaa, 0xaa, 0xab }, 314 { 0x0, 0x3, 0x4, 0x94 }, 315 { 0xfa, 0x1c, 0x83, 0x11 }, 316 { 0x80, 0x0f, 0xf9, 0x53 }, 317 { 0x84, 0x26, 0x4, 0x4 }, 318 { 0x0, 0xe0, 0x1, 0x0 }, 319 { 0x45, 0x48, 0x0, 0x0 }, 320 { 0x27, 0x8, 0x0, 0x0 }, 321 { 0x5a, 0x14, 0x2a, 0x14 }, 322 { 0x0, 0x5b, 0xe0, 0x8 }, 323 { 0x0, 0x0, 0x0, 0x0 }, 324 }, 325 }; 326 327 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr13_5 = { 328 .config = { 329 0xcb, 330 0x2d, 331 0x0, 332 }, 333 .addr_msb = { 334 0x87, 335 0x87, 336 0x87, 337 0x87, 338 0x88, 339 0x88, 340 0x88, 341 0x88, 342 0x88, 343 0x88, 344 0x88, 345 0x88, 346 0x88, 347 }, 348 .addr_lsb = { 349 0x10, 350 0x0c, 351 0x14, 352 0xe4, 353 0x0c, 354 0x10, 355 0x14, 356 0x18, 357 0x48, 358 0x40, 359 0x4c, 360 0x24, 361 0x44, 362 }, 363 .data = { 364 { 0x0, 0x4c, 0x2, 0x0 }, 365 { 0x2, 0x9, 0x2b, 0xe0 }, 366 { 0x90, 0x0, 0x0, 0x0 }, 367 { 0x8, 0x4, 0x80, 0xe0 }, 368 { 0xfa, 0x15, 0x83, 0x11 }, 369 { 0x80, 0x0f, 0xf9, 0x53 }, 370 { 0x84, 0x26, 0x6, 0x4 }, 371 { 0x0, 0xe0, 0x1, 0x0 }, 372 { 0x49, 0x48, 0x0, 0x0 }, 373 { 0x27, 0x8, 0x0, 0x0 }, 374 { 0x5a, 0x13, 0x29, 0x13 }, 375 { 0x0, 0x57, 0xe0, 0x0c }, 376 { 0x0, 0x0, 0x0, 0x0 }, 377 }, 378 }; 379 380 static const struct intel_lt_phy_pll_state xe3plpd_lt_dp_uhbr20 = { 381 .config = { 382 0x53, 383 0x2d, 384 0x0, 385 }, 386 .addr_msb = { 387 0x85, 388 0x85, 389 0x85, 390 0x85, 391 0x86, 392 0x86, 393 0x86, 394 0x86, 395 0x86, 396 0x86, 397 0x86, 398 0x86, 399 0x86, 400 }, 401 .addr_lsb = { 402 0x10, 403 0x0c, 404 0x14, 405 0xe4, 406 0x0c, 407 0x10, 408 0x14, 409 0x18, 410 0x48, 411 0x40, 412 0x4c, 413 0x24, 414 0x44, 415 }, 416 .data = { 417 { 0x0, 0x4c, 0x2, 0x0 }, 418 { 0x1, 0xa, 0x20, 0x80 }, 419 { 0x6a, 0xaa, 0xaa, 0xab }, 420 { 0x0, 0x3, 0x4, 0x94 }, 421 { 0xfa, 0x1c, 0x83, 0x11 }, 422 { 0x80, 0x0f, 0xf9, 0x53 }, 423 { 0x84, 0x26, 0x4, 0x4 }, 424 { 0x0, 0xe0, 0x1, 0x0 }, 425 { 0x45, 0x48, 0x0, 0x0 }, 426 { 0x27, 0x8, 0x0, 0x0 }, 427 { 0x5a, 0x14, 0x2a, 0x14 }, 428 { 0x0, 0x5b, 0xe0, 0x8 }, 429 { 0x0, 0x0, 0x0, 0x0 }, 430 }, 431 }; 432 433 struct intel_lt_phy_pll_params { 434 const char *name; 435 bool is_hdmi; 436 int clock_rate; 437 const struct intel_lt_phy_pll_state *state; 438 }; 439 440 #define __LT_PHY_PLL_PARAMS(__is_hdmi, __clock_rate, __state) { \ 441 .name = __stringify(__state), \ 442 .is_hdmi = __is_hdmi, \ 443 .clock_rate = __clock_rate, \ 444 .state = &__state, \ 445 } 446 447 #define LT_PHY_PLL_HDMI_PARAMS(__clock_rate, __state) __LT_PHY_PLL_PARAMS(true, __clock_rate, __state) 448 #define LT_PHY_PLL_DP_PARAMS(__clock_rate, __state) __LT_PHY_PLL_PARAMS(false, __clock_rate, __state) 449 450 static const struct intel_lt_phy_pll_params xe3plpd_lt_dp_tables[] = { 451 LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr), 452 LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1), 453 LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2), 454 LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3), 455 LT_PHY_PLL_DP_PARAMS(1000000, xe3plpd_lt_dp_uhbr10), 456 LT_PHY_PLL_DP_PARAMS(1350000, xe3plpd_lt_dp_uhbr13_5), 457 LT_PHY_PLL_DP_PARAMS(2000000, xe3plpd_lt_dp_uhbr20), 458 {} 459 }; 460 461 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_16 = { 462 .config = { 463 0xa3, 464 0x2d, 465 0x1, 466 }, 467 .addr_msb = { 468 0x87, 469 0x87, 470 0x87, 471 0x87, 472 0x88, 473 0x88, 474 0x88, 475 0x88, 476 0x88, 477 0x88, 478 0x88, 479 0x88, 480 0x88, 481 }, 482 .addr_lsb = { 483 0x10, 484 0x0c, 485 0x14, 486 0xe4, 487 0x0c, 488 0x10, 489 0x14, 490 0x18, 491 0x48, 492 0x40, 493 0x4c, 494 0x24, 495 0x44, 496 }, 497 .data = { 498 { 0x0, 0x4c, 0x2, 0x0 }, 499 { 0x3, 0xca, 0x2a, 0x20 }, 500 { 0x80, 0x0, 0x0, 0x0 }, 501 { 0x6, 0x4, 0x81, 0xbc }, 502 { 0xfa, 0x16, 0x83, 0x11 }, 503 { 0x80, 0x0f, 0xf9, 0x53 }, 504 { 0x84, 0x26, 0x5, 0x4 }, 505 { 0x0, 0xe0, 0x1, 0x0 }, 506 { 0x4b, 0x48, 0x0, 0x0 }, 507 { 0x27, 0x8, 0x0, 0x0 }, 508 { 0x5a, 0x13, 0x29, 0x13 }, 509 { 0x0, 0x5b, 0xe0, 0x0a }, 510 { 0x0, 0x0, 0x0, 0x0 }, 511 }, 512 }; 513 514 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_2_43 = { 515 .config = { 516 0xab, 517 0x2d, 518 0x1, 519 }, 520 .addr_msb = { 521 0x87, 522 0x87, 523 0x87, 524 0x87, 525 0x88, 526 0x88, 527 0x88, 528 0x88, 529 0x88, 530 0x88, 531 0x88, 532 0x88, 533 0x88, 534 }, 535 .addr_lsb = { 536 0x10, 537 0x0c, 538 0x14, 539 0xe4, 540 0x0c, 541 0x10, 542 0x14, 543 0x18, 544 0x48, 545 0x40, 546 0x4c, 547 0x24, 548 0x44, 549 }, 550 .data = { 551 { 0x0, 0x4c, 0x2, 0x0 }, 552 { 0x3, 0xca, 0x2f, 0x60 }, 553 { 0xb0, 0x0, 0x0, 0x0 }, 554 { 0x6, 0x4, 0x81, 0xbc }, 555 { 0xfa, 0x13, 0x83, 0x11 }, 556 { 0x80, 0x0f, 0xf9, 0x53 }, 557 { 0x84, 0x26, 0x6, 0x4 }, 558 { 0x0, 0xe0, 0x1, 0x0 }, 559 { 0x47, 0x48, 0x0, 0x0 }, 560 { 0x0, 0x0, 0x0, 0x0 }, 561 { 0x5a, 0x13, 0x29, 0x13 }, 562 { 0x0, 0x5b, 0xe0, 0x0c }, 563 { 0x0, 0x0, 0x0, 0x0 }, 564 }, 565 }; 566 567 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_3_24 = { 568 .config = { 569 0xb3, 570 0x2d, 571 0x1, 572 }, 573 .addr_msb = { 574 0x87, 575 0x87, 576 0x87, 577 0x87, 578 0x88, 579 0x88, 580 0x88, 581 0x88, 582 0x88, 583 0x88, 584 0x88, 585 0x88, 586 0x88, 587 }, 588 .addr_lsb = { 589 0x10, 590 0x0c, 591 0x14, 592 0xe4, 593 0x0c, 594 0x10, 595 0x14, 596 0x18, 597 0x48, 598 0x40, 599 0x4c, 600 0x24, 601 0x44, 602 }, 603 .data = { 604 { 0x0, 0x4c, 0x2, 0x0 }, 605 { 0x2, 0x8a, 0x2a, 0x20 }, 606 { 0x80, 0x0, 0x0, 0x0 }, 607 { 0x6, 0x4, 0x81, 0x28 }, 608 { 0xfa, 0x16, 0x83, 0x11 }, 609 { 0x80, 0x0f, 0xf9, 0x53 }, 610 { 0x84, 0x26, 0x5, 0x4 }, 611 { 0x0, 0xe0, 0x1, 0x0 }, 612 { 0x4b, 0x48, 0x0, 0x0 }, 613 { 0x27, 0x8, 0x0, 0x0 }, 614 { 0x5a, 0x13, 0x29, 0x13 }, 615 { 0x0, 0x5b, 0xe0, 0x0a }, 616 { 0x0, 0x0, 0x0, 0x0 }, 617 }, 618 }; 619 620 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_4_32 = { 621 .config = { 622 0xbb, 623 0x2d, 624 0x1, 625 }, 626 .addr_msb = { 627 0x87, 628 0x87, 629 0x87, 630 0x87, 631 0x88, 632 0x88, 633 0x88, 634 0x88, 635 0x88, 636 0x88, 637 0x88, 638 0x88, 639 0x88, 640 }, 641 .addr_lsb = { 642 0x10, 643 0x0c, 644 0x14, 645 0xe4, 646 0x0c, 647 0x10, 648 0x14, 649 0x18, 650 0x48, 651 0x40, 652 0x4c, 653 0x24, 654 0x44, 655 }, 656 .data = { 657 { 0x0, 0x4c, 0x2, 0x0 }, 658 { 0x1, 0x4d, 0x2a, 0x20 }, 659 { 0x80, 0x0, 0x0, 0x0 }, 660 { 0xc, 0x4, 0x81, 0xbc }, 661 { 0xfa, 0x16, 0x83, 0x11 }, 662 { 0x80, 0x0f, 0xf9, 0x53 }, 663 { 0x84, 0x26, 0x5, 0x4 }, 664 { 0x0, 0xe0, 0x1, 0x0 }, 665 { 0x4b, 0x48, 0x0, 0x0 }, 666 { 0x27, 0x8, 0x0, 0x0 }, 667 { 0x5a, 0x13, 0x29, 0x13 }, 668 { 0x0, 0x5b, 0xe0, 0x0a }, 669 { 0x0, 0x0, 0x0, 0x0 }, 670 }, 671 }; 672 673 static const struct intel_lt_phy_pll_state xe3plpd_lt_edp_6_75 = { 674 .config = { 675 0xdb, 676 0x2d, 677 0x1, 678 }, 679 .addr_msb = { 680 0x87, 681 0x87, 682 0x87, 683 0x87, 684 0x88, 685 0x88, 686 0x88, 687 0x88, 688 0x88, 689 0x88, 690 0x88, 691 0x88, 692 0x88, 693 }, 694 .addr_lsb = { 695 0x10, 696 0x0c, 697 0x14, 698 0xe4, 699 0x0c, 700 0x10, 701 0x14, 702 0x18, 703 0x48, 704 0x40, 705 0x4c, 706 0x24, 707 0x44, 708 }, 709 .data = { 710 { 0x0, 0x4c, 0x2, 0x0 }, 711 { 0x1, 0x4a, 0x2b, 0xe0 }, 712 { 0x90, 0x0, 0x0, 0x0 }, 713 { 0x6, 0x4, 0x80, 0xa8 }, 714 { 0xfa, 0x15, 0x83, 0x11 }, 715 { 0x80, 0x0f, 0xf9, 0x53 }, 716 { 0x84, 0x26, 0x6, 0x4 }, 717 { 0x0, 0xe0, 0x1, 0x0 }, 718 { 0x49, 0x48, 0x0, 0x0 }, 719 { 0x27, 0x8, 0x0, 0x0 }, 720 { 0x5a, 0x13, 0x29, 0x13 }, 721 { 0x0, 0x57, 0xe0, 0x0c }, 722 { 0x0, 0x0, 0x0, 0x0 }, 723 }, 724 }; 725 726 static const struct intel_lt_phy_pll_params xe3plpd_lt_edp_tables[] = { 727 LT_PHY_PLL_DP_PARAMS(162000, xe3plpd_lt_dp_rbr), 728 LT_PHY_PLL_DP_PARAMS(216000, xe3plpd_lt_edp_2_16), 729 LT_PHY_PLL_DP_PARAMS(243000, xe3plpd_lt_edp_2_43), 730 LT_PHY_PLL_DP_PARAMS(270000, xe3plpd_lt_dp_hbr1), 731 LT_PHY_PLL_DP_PARAMS(324000, xe3plpd_lt_edp_3_24), 732 LT_PHY_PLL_DP_PARAMS(432000, xe3plpd_lt_edp_4_32), 733 LT_PHY_PLL_DP_PARAMS(540000, xe3plpd_lt_dp_hbr2), 734 LT_PHY_PLL_DP_PARAMS(675000, xe3plpd_lt_edp_6_75), 735 LT_PHY_PLL_DP_PARAMS(810000, xe3plpd_lt_dp_hbr3), 736 {} 737 }; 738 739 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_252 = { 740 .config = { 741 0x84, 742 0x2d, 743 0x0, 744 }, 745 .addr_msb = { 746 0x87, 747 0x87, 748 0x87, 749 0x87, 750 0x88, 751 0x88, 752 0x88, 753 0x88, 754 0x88, 755 0x88, 756 0x88, 757 0x88, 758 0x88, 759 }, 760 .addr_lsb = { 761 0x10, 762 0x0c, 763 0x14, 764 0xe4, 765 0x0c, 766 0x10, 767 0x14, 768 0x18, 769 0x48, 770 0x40, 771 0x4c, 772 0x24, 773 0x44, 774 }, 775 .data = { 776 { 0x0, 0x4c, 0x2, 0x0 }, 777 { 0x0c, 0x15, 0x27, 0x60 }, 778 { 0x0, 0x0, 0x0, 0x0 }, 779 { 0x8, 0x4, 0x98, 0x28 }, 780 { 0x42, 0x0, 0x84, 0x10 }, 781 { 0x80, 0x0f, 0xd9, 0xb5 }, 782 { 0x86, 0x0, 0x0, 0x0 }, 783 { 0x1, 0xa0, 0x1, 0x0 }, 784 { 0x4b, 0x0, 0x0, 0x0 }, 785 { 0x28, 0x0, 0x0, 0x0 }, 786 { 0x0, 0x14, 0x2a, 0x14 }, 787 { 0x0, 0x0, 0x0, 0x0 }, 788 { 0x0, 0x0, 0x0, 0x0 }, 789 }, 790 }; 791 792 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_742p5 = { 793 .config = { 794 0x84, 795 0x2d, 796 0x0, 797 }, 798 .addr_msb = { 799 0x87, 800 0x87, 801 0x87, 802 0x87, 803 0x88, 804 0x88, 805 0x88, 806 0x88, 807 0x88, 808 0x88, 809 0x88, 810 0x88, 811 0x88, 812 }, 813 .addr_lsb = { 814 0x10, 815 0x0c, 816 0x14, 817 0xe4, 818 0x0c, 819 0x10, 820 0x14, 821 0x18, 822 0x48, 823 0x40, 824 0x4c, 825 0x24, 826 0x44, 827 }, 828 .data = { 829 { 0x0, 0x4c, 0x2, 0x0 }, 830 { 0x4, 0x15, 0x26, 0xa0 }, 831 { 0x60, 0x0, 0x0, 0x0 }, 832 { 0x8, 0x4, 0x88, 0x28 }, 833 { 0xfa, 0x0c, 0x84, 0x11 }, 834 { 0x80, 0x0f, 0xd9, 0x53 }, 835 { 0x86, 0x0, 0x0, 0x0 }, 836 { 0x1, 0xa0, 0x1, 0x0 }, 837 { 0x4b, 0x0, 0x0, 0x0 }, 838 { 0x28, 0x0, 0x0, 0x0 }, 839 { 0x0, 0x14, 0x2a, 0x14 }, 840 { 0x0, 0x0, 0x0, 0x0 }, 841 { 0x0, 0x0, 0x0, 0x0 }, 842 }, 843 }; 844 845 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_1p485 = { 846 .config = { 847 0x84, 848 0x2d, 849 0x0, 850 }, 851 .addr_msb = { 852 0x87, 853 0x87, 854 0x87, 855 0x87, 856 0x88, 857 0x88, 858 0x88, 859 0x88, 860 0x88, 861 0x88, 862 0x88, 863 0x88, 864 0x88, 865 }, 866 .addr_lsb = { 867 0x10, 868 0x0c, 869 0x14, 870 0xe4, 871 0x0c, 872 0x10, 873 0x14, 874 0x18, 875 0x48, 876 0x40, 877 0x4c, 878 0x24, 879 0x44, 880 }, 881 .data = { 882 { 0x0, 0x4c, 0x2, 0x0 }, 883 { 0x2, 0x15, 0x26, 0xa0 }, 884 { 0x60, 0x0, 0x0, 0x0 }, 885 { 0x8, 0x4, 0x84, 0x28 }, 886 { 0xfa, 0x0c, 0x84, 0x11 }, 887 { 0x80, 0x0f, 0xd9, 0x53 }, 888 { 0x86, 0x0, 0x0, 0x0 }, 889 { 0x1, 0xa0, 0x1, 0x0 }, 890 { 0x4b, 0x0, 0x0, 0x0 }, 891 { 0x28, 0x0, 0x0, 0x0 }, 892 { 0x0, 0x14, 0x2a, 0x14 }, 893 { 0x0, 0x0, 0x0, 0x0 }, 894 { 0x0, 0x0, 0x0, 0x0 }, 895 }, 896 }; 897 898 static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = { 899 .config = { 900 0x84, 901 0x2d, 902 0x0, 903 }, 904 .addr_msb = { 905 0x87, 906 0x87, 907 0x87, 908 0x87, 909 0x88, 910 0x88, 911 0x88, 912 0x88, 913 0x88, 914 0x88, 915 0x88, 916 0x88, 917 0x88, 918 }, 919 .addr_lsb = { 920 0x10, 921 0x0c, 922 0x14, 923 0xe4, 924 0x0c, 925 0x10, 926 0x14, 927 0x18, 928 0x48, 929 0x40, 930 0x4c, 931 0x24, 932 0x44, 933 }, 934 .data = { 935 { 0x0, 0x4c, 0x2, 0x0 }, 936 { 0x0, 0x95, 0x26, 0xa0 }, 937 { 0x60, 0x0, 0x0, 0x0 }, 938 { 0x8, 0x4, 0x81, 0x28 }, 939 { 0xfa, 0x0c, 0x84, 0x11 }, 940 { 0x80, 0x0f, 0xd9, 0x53 }, 941 { 0x86, 0x0, 0x0, 0x0 }, 942 { 0x1, 0xa0, 0x1, 0x0 }, 943 { 0x4b, 0x0, 0x0, 0x0 }, 944 { 0x28, 0x0, 0x0, 0x0 }, 945 { 0x0, 0x14, 0x2a, 0x14 }, 946 { 0x0, 0x0, 0x0, 0x0 }, 947 { 0x0, 0x0, 0x0, 0x0 }, 948 }, 949 }; 950 951 static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = { 952 LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252), 953 LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5), 954 LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485), 955 LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94), 956 {} 957 }; 958 959 static u8 intel_lt_phy_get_owned_lane_mask(struct intel_encoder *encoder) 960 { 961 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 962 963 if (!intel_tc_port_in_dp_alt_mode(dig_port)) 964 return INTEL_LT_PHY_BOTH_LANES; 965 966 return intel_tc_port_max_lane_count(dig_port) > 2 967 ? INTEL_LT_PHY_BOTH_LANES : INTEL_LT_PHY_LANE0; 968 } 969 970 static u8 intel_lt_phy_read(struct intel_encoder *encoder, u8 lane_mask, u16 addr) 971 { 972 return intel_cx0_read(encoder, lane_mask, addr); 973 } 974 975 static void intel_lt_phy_write(struct intel_encoder *encoder, 976 u8 lane_mask, u16 addr, u8 data, bool committed) 977 { 978 intel_cx0_write(encoder, lane_mask, addr, data, committed); 979 } 980 981 static void intel_lt_phy_rmw(struct intel_encoder *encoder, 982 u8 lane_mask, u16 addr, u8 clear, u8 set, bool committed) 983 { 984 intel_cx0_rmw(encoder, lane_mask, addr, clear, set, committed); 985 } 986 987 static void intel_lt_phy_clear_status_p2p(struct intel_encoder *encoder, 988 int lane) 989 { 990 struct intel_display *display = to_intel_display(encoder); 991 992 intel_de_rmw(display, 993 XE3PLPD_PORT_P2M_MSGBUS_STATUS_P2P(encoder->port, lane), 994 XELPDP_PORT_P2M_RESPONSE_READY, 0); 995 } 996 997 static void 998 assert_dc_off(struct intel_display *display) 999 { 1000 bool enabled; 1001 1002 enabled = intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF); 1003 drm_WARN_ON(display->drm, !enabled); 1004 } 1005 1006 static int __intel_lt_phy_p2p_write_once(struct intel_encoder *encoder, 1007 int lane, u16 addr, u8 data, 1008 i915_reg_t mac_reg_addr, 1009 u8 expected_mac_val) 1010 { 1011 struct intel_display *display = to_intel_display(encoder); 1012 enum port port = encoder->port; 1013 enum phy phy = intel_encoder_to_phy(encoder); 1014 int ack; 1015 u32 val; 1016 1017 if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 1018 XELPDP_PORT_P2P_TRANSACTION_PENDING, 1019 XELPDP_MSGBUS_TIMEOUT_MS)) { 1020 drm_dbg_kms(display->drm, 1021 "PHY %c Timeout waiting for previous transaction to complete. Resetting bus.\n", 1022 phy_name(phy)); 1023 intel_cx0_bus_reset(encoder, lane); 1024 return -ETIMEDOUT; 1025 } 1026 1027 intel_de_rmw(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane), 0, 0); 1028 1029 intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane), 1030 XELPDP_PORT_P2P_TRANSACTION_PENDING | 1031 XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED | 1032 XELPDP_PORT_M2P_DATA(data) | 1033 XELPDP_PORT_M2P_ADDRESS(addr)); 1034 1035 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val); 1036 if (ack < 0) 1037 return ack; 1038 1039 if (val & XELPDP_PORT_P2M_ERROR_SET) { 1040 drm_dbg_kms(display->drm, 1041 "PHY %c Error occurred during P2P write command. Status: 0x%x\n", 1042 phy_name(phy), val); 1043 intel_lt_phy_clear_status_p2p(encoder, lane); 1044 intel_cx0_bus_reset(encoder, lane); 1045 return -EINVAL; 1046 } 1047 1048 /* 1049 * RE-VISIT: 1050 * This needs to be added to give PHY time to set everything up this was a requirement 1051 * to get the display up and running 1052 * This is the time PHY takes to settle down after programming the PHY. 1053 */ 1054 udelay(150); 1055 intel_cx0_clear_response_ready_flag(encoder, lane); 1056 intel_lt_phy_clear_status_p2p(encoder, lane); 1057 1058 return 0; 1059 } 1060 1061 static void __intel_lt_phy_p2p_write(struct intel_encoder *encoder, 1062 int lane, u16 addr, u8 data, 1063 i915_reg_t mac_reg_addr, 1064 u8 expected_mac_val) 1065 { 1066 struct intel_display *display = to_intel_display(encoder); 1067 enum phy phy = intel_encoder_to_phy(encoder); 1068 int i, status; 1069 1070 assert_dc_off(display); 1071 1072 /* 3 tries is assumed to be enough to write successfully */ 1073 for (i = 0; i < 3; i++) { 1074 status = __intel_lt_phy_p2p_write_once(encoder, lane, addr, data, mac_reg_addr, 1075 expected_mac_val); 1076 1077 if (status == 0) 1078 return; 1079 } 1080 1081 drm_err_once(display->drm, 1082 "PHY %c P2P Write %04x failed after %d retries.\n", phy_name(phy), addr, i); 1083 } 1084 1085 static void intel_lt_phy_p2p_write(struct intel_encoder *encoder, 1086 u8 lane_mask, u16 addr, u8 data, 1087 i915_reg_t mac_reg_addr, 1088 u8 expected_mac_val) 1089 { 1090 int lane; 1091 1092 for_each_lt_phy_lane_in_mask(lane_mask, lane) 1093 __intel_lt_phy_p2p_write(encoder, lane, addr, data, mac_reg_addr, expected_mac_val); 1094 } 1095 1096 static void 1097 intel_lt_phy_setup_powerdown(struct intel_encoder *encoder, u8 lane_count) 1098 { 1099 /* 1100 * The new PORT_BUF_CTL6 stuff for dc5 entry and exit needs to be handled 1101 * by dmc firmware not explicitly mentioned in Bspec. This leaves this 1102 * function as a wrapper only but keeping it expecting future changes. 1103 */ 1104 intel_cx0_setup_powerdown(encoder); 1105 } 1106 1107 static void 1108 intel_lt_phy_powerdown_change_sequence(struct intel_encoder *encoder, 1109 u8 lane_mask, u8 state) 1110 { 1111 intel_cx0_powerdown_change_sequence(encoder, lane_mask, state); 1112 } 1113 1114 static void 1115 intel_lt_phy_lane_reset(struct intel_encoder *encoder, 1116 u8 lane_count) 1117 { 1118 struct intel_display *display = to_intel_display(encoder); 1119 enum port port = encoder->port; 1120 enum phy phy = intel_encoder_to_phy(encoder); 1121 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 1122 u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 1123 ? XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1) 1124 : XELPDP_LANE_PIPE_RESET(0); 1125 u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 1126 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | 1127 XELPDP_LANE_PHY_CURRENT_STATUS(1)) 1128 : XELPDP_LANE_PHY_CURRENT_STATUS(0); 1129 u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 1130 ? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) | 1131 XE3PLPDP_LANE_PHY_PULSE_STATUS(1)) 1132 : XE3PLPDP_LANE_PHY_PULSE_STATUS(0); 1133 1134 intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), 1135 XE3PLPD_MACCLK_RATE_MASK, XE3PLPD_MACCLK_RATE_DEF); 1136 1137 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port), 1138 XE3PLPDP_PHY_MODE_MASK, XE3PLPDP_PHY_MODE_DP); 1139 1140 intel_lt_phy_setup_powerdown(encoder, lane_count); 1141 intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, 1142 XELPDP_P2_STATE_RESET); 1143 1144 intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), 1145 XE3PLPD_MACCLK_RESET_0, 0); 1146 1147 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 1148 XELPDP_LANE_PCLK_PLL_REQUEST(0), 1149 XELPDP_LANE_PCLK_PLL_REQUEST(0)); 1150 1151 if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), 1152 XELPDP_LANE_PCLK_PLL_ACK(0), 1153 XE3PLPD_MACCLK_TURNON_LATENCY_MS)) 1154 drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n", 1155 phy_name(phy)); 1156 1157 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 1158 XELPDP_FORWARD_CLOCK_UNGATE, 1159 XELPDP_FORWARD_CLOCK_UNGATE); 1160 1161 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 1162 lane_pipe_reset | lane_phy_pulse_status, 0); 1163 1164 if (intel_de_wait_for_clear_ms(display, XELPDP_PORT_BUF_CTL2(display, port), 1165 lane_phy_current_status, 1166 XE3PLPD_RESET_END_LATENCY_MS)) 1167 drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n", 1168 phy_name(phy)); 1169 1170 if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port), 1171 lane_phy_pulse_status, 1172 XE3PLPD_RATE_CALIB_DONE_LATENCY_MS)) 1173 drm_warn(display->drm, "PHY %c PLL rate not changed\n", 1174 phy_name(phy)); 1175 1176 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_phy_pulse_status, 0); 1177 } 1178 1179 static void 1180 intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder, 1181 const struct intel_crtc_state *crtc_state, 1182 bool lane_reversal) 1183 { 1184 struct intel_display *display = to_intel_display(encoder); 1185 u32 val = 0; 1186 1187 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), 1188 XELPDP_PORT_REVERSAL, 1189 lane_reversal ? XELPDP_PORT_REVERSAL : 0); 1190 1191 val |= XELPDP_FORWARD_CLOCK_UNGATE; 1192 1193 /* 1194 * We actually mean MACCLK here and not MAXPCLK when using LT Phy 1195 * but since the register bits still remain the same we use 1196 * the same definition 1197 */ 1198 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && 1199 intel_hdmi_is_frl(crtc_state->port_clock)) 1200 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_DIV18CLK); 1201 else 1202 val |= XELPDP_DDI_CLOCK_SELECT_PREP(display, XELPDP_DDI_CLOCK_SELECT_MAXPCLK); 1203 1204 /* DP2.0 10G and 20G rates enable MPLLA*/ 1205 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) 1206 val |= XELPDP_SSC_ENABLE_PLLA; 1207 else 1208 val |= crtc_state->dpll_hw_state.ltpll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; 1209 1210 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), 1211 XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE | 1212 XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_SSC_ENABLE_PLLA | 1213 XELPDP_SSC_ENABLE_PLLB, val); 1214 } 1215 1216 static u32 intel_lt_phy_get_dp_clock(u8 rate) 1217 { 1218 switch (rate) { 1219 case 0: 1220 return 162000; 1221 case 1: 1222 return 270000; 1223 case 2: 1224 return 540000; 1225 case 3: 1226 return 810000; 1227 case 4: 1228 return 216000; 1229 case 5: 1230 return 243000; 1231 case 6: 1232 return 324000; 1233 case 7: 1234 return 432000; 1235 case 8: 1236 return 1000000; 1237 case 9: 1238 return 1350000; 1239 case 10: 1240 return 2000000; 1241 case 11: 1242 return 675000; 1243 default: 1244 MISSING_CASE(rate); 1245 return 0; 1246 } 1247 } 1248 1249 static bool 1250 intel_lt_phy_config_changed(struct intel_encoder *encoder, 1251 const struct intel_crtc_state *crtc_state) 1252 { 1253 u8 val, rate; 1254 u32 clock; 1255 1256 val = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, 1257 LT_PHY_VDR_0_CONFIG); 1258 rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, val); 1259 1260 /* 1261 * The only time we do not reconfigure the PLL is when we are 1262 * using 1.62 Gbps clock since PHY PLL defaults to that 1263 * otherwise we always need to reconfigure it. 1264 */ 1265 if (intel_crtc_has_dp_encoder(crtc_state)) { 1266 clock = intel_lt_phy_get_dp_clock(rate); 1267 if (crtc_state->port_clock == 1620000 && crtc_state->port_clock == clock) 1268 return false; 1269 } 1270 1271 return true; 1272 } 1273 1274 static struct ref_tracker *intel_lt_phy_transaction_begin(struct intel_encoder *encoder) 1275 { 1276 struct intel_display *display = to_intel_display(encoder); 1277 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1278 struct ref_tracker *wakeref; 1279 1280 intel_psr_pause(intel_dp); 1281 wakeref = intel_display_power_get(display, POWER_DOMAIN_DC_OFF); 1282 1283 return wakeref; 1284 } 1285 1286 static void intel_lt_phy_transaction_end(struct intel_encoder *encoder, struct ref_tracker *wakeref) 1287 { 1288 struct intel_display *display = to_intel_display(encoder); 1289 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1290 1291 intel_psr_resume(intel_dp); 1292 intel_display_power_put(display, POWER_DOMAIN_DC_OFF, wakeref); 1293 } 1294 1295 static const struct intel_lt_phy_pll_params * 1296 intel_lt_phy_pll_tables_get(struct intel_crtc_state *crtc_state, 1297 struct intel_encoder *encoder) 1298 { 1299 if (intel_crtc_has_dp_encoder(crtc_state)) { 1300 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1301 return xe3plpd_lt_edp_tables; 1302 1303 return xe3plpd_lt_dp_tables; 1304 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1305 return xe3plpd_lt_hdmi_tables; 1306 } 1307 1308 MISSING_CASE(encoder->type); 1309 return NULL; 1310 } 1311 1312 static bool 1313 intel_lt_phy_pll_is_ssc_enabled(struct intel_crtc_state *crtc_state, 1314 struct intel_encoder *encoder) 1315 { 1316 struct intel_display *display = to_intel_display(encoder); 1317 1318 if (intel_crtc_has_dp_encoder(crtc_state)) { 1319 if (intel_panel_use_ssc(display)) { 1320 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1321 1322 return (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); 1323 } 1324 } 1325 1326 return false; 1327 } 1328 1329 static u64 mul_q32_u32(u64 a_q32, u32 b) 1330 { 1331 u64 p0, p1, carry, result; 1332 u64 x_hi = a_q32 >> 32; 1333 u64 x_lo = a_q32 & 0xFFFFFFFFULL; 1334 1335 p0 = x_lo * (u64)b; 1336 p1 = x_hi * (u64)b; 1337 carry = p0 >> 32; 1338 result = (p1 << 32) + (carry << 32) + (p0 & 0xFFFFFFFFULL); 1339 1340 return result; 1341 } 1342 1343 static bool 1344 calculate_target_dco_and_loop_cnt(u32 frequency_khz, u64 *target_dco_mhz, u32 *loop_cnt) 1345 { 1346 u32 ppm_value = 1; 1347 u32 dco_min_freq = DCO_MIN_FREQ_MHZ; 1348 u32 dco_max_freq = 16200; 1349 u32 dco_min_freq_low = 10000; 1350 u32 dco_max_freq_low = 12000; 1351 u64 val = 0; 1352 u64 refclk_khz = REF_CLK_KHZ; 1353 u64 m2div = 0; 1354 u64 val_with_frac = 0; 1355 u64 ppm = 0; 1356 u64 temp0 = 0, temp1, scale; 1357 int ppm_cnt, dco_count, y; 1358 1359 for (ppm_cnt = 0; ppm_cnt < 5; ppm_cnt++) { 1360 ppm_value = ppm_cnt == 2 ? 2 : 1; 1361 for (dco_count = 0; dco_count < 2; dco_count++) { 1362 if (dco_count == 1) { 1363 dco_min_freq = dco_min_freq_low; 1364 dco_max_freq = dco_max_freq_low; 1365 } 1366 for (y = 2; y <= 255; y += 2) { 1367 val = div64_u64((u64)y * frequency_khz, 200); 1368 m2div = div64_u64(((u64)(val) << 32), refclk_khz); 1369 m2div = mul_q32_u32(m2div, 500); 1370 val_with_frac = mul_q32_u32(m2div, refclk_khz); 1371 val_with_frac = div64_u64(val_with_frac, 500); 1372 temp1 = Q32_TO_INT(val_with_frac); 1373 temp0 = (temp1 > val) ? (temp1 - val) : 1374 (val - temp1); 1375 ppm = div64_u64(temp0, val); 1376 if (temp1 >= dco_min_freq && 1377 temp1 <= dco_max_freq && 1378 ppm < ppm_value) { 1379 /* Round to two places */ 1380 scale = (1ULL << 32) / 100; 1381 temp0 = DIV_ROUND_UP_ULL(val_with_frac, 1382 scale); 1383 *target_dco_mhz = temp0 * scale; 1384 *loop_cnt = y; 1385 return true; 1386 } 1387 } 1388 } 1389 } 1390 1391 return false; 1392 } 1393 1394 static void set_phy_vdr_addresses(struct lt_phy_params *p, int pll_type) 1395 { 1396 p->pll_reg4.addr = PLL_REG_ADDR(PLL_REG4_ADDR, pll_type); 1397 p->pll_reg3.addr = PLL_REG_ADDR(PLL_REG3_ADDR, pll_type); 1398 p->pll_reg5.addr = PLL_REG_ADDR(PLL_REG5_ADDR, pll_type); 1399 p->pll_reg57.addr = PLL_REG_ADDR(PLL_REG57_ADDR, pll_type); 1400 p->lf.addr = PLL_REG_ADDR(PLL_LF_ADDR, pll_type); 1401 p->tdc.addr = PLL_REG_ADDR(PLL_TDC_ADDR, pll_type); 1402 p->ssc.addr = PLL_REG_ADDR(PLL_SSC_ADDR, pll_type); 1403 p->bias2.addr = PLL_REG_ADDR(PLL_BIAS2_ADDR, pll_type); 1404 p->bias_trim.addr = PLL_REG_ADDR(PLL_BIAS_TRIM_ADDR, pll_type); 1405 p->dco_med.addr = PLL_REG_ADDR(PLL_DCO_MED_ADDR, pll_type); 1406 p->dco_fine.addr = PLL_REG_ADDR(PLL_DCO_FINE_ADDR, pll_type); 1407 p->ssc_inj.addr = PLL_REG_ADDR(PLL_SSC_INJ_ADDR, pll_type); 1408 p->surv_bonus.addr = PLL_REG_ADDR(PLL_SURV_BONUS_ADDR, pll_type); 1409 } 1410 1411 static void compute_ssc(struct lt_phy_params *p, u32 ana_cfg) 1412 { 1413 int ssc_stepsize = 0; 1414 int ssc_steplen = 0; 1415 int ssc_steplog = 0; 1416 1417 p->ssc.val = (1 << 31) | (ana_cfg << 24) | (ssc_steplog << 16) | 1418 (ssc_stepsize << 8) | ssc_steplen; 1419 } 1420 1421 static void compute_bias2(struct lt_phy_params *p) 1422 { 1423 u32 ssc_en_local = 0; 1424 u64 dynctrl_ovrd_en = 0; 1425 1426 p->bias2.val = (dynctrl_ovrd_en << 31) | (ssc_en_local << 30) | 1427 (1 << 23) | (1 << 24) | (32 << 16) | (1 << 8); 1428 } 1429 1430 static void compute_tdc(struct lt_phy_params *p, u64 tdc_fine) 1431 { 1432 u32 settling_time = 15; 1433 u32 bias_ovr_en = 1; 1434 u32 coldstart = 1; 1435 u32 true_lock = 2; 1436 u32 early_lock = 1; 1437 u32 lock_ovr_en = 1; 1438 u32 lock_thr = tdc_fine ? 3 : 5; 1439 u32 unlock_thr = tdc_fine ? 5 : 11; 1440 1441 p->tdc.val = (u32)((2 << 30) + (settling_time << 16) + (bias_ovr_en << 15) + 1442 (lock_ovr_en << 14) + (coldstart << 12) + (true_lock << 10) + 1443 (early_lock << 8) + (unlock_thr << 4) + lock_thr); 1444 } 1445 1446 static void compute_dco_med(struct lt_phy_params *p) 1447 { 1448 u32 cselmed_en = 0; 1449 u32 cselmed_dyn_adj = 0; 1450 u32 cselmed_ratio = 39; 1451 u32 cselmed_thr = 8; 1452 1453 p->dco_med.val = (cselmed_en << 31) + (cselmed_dyn_adj << 30) + 1454 (cselmed_ratio << 24) + (cselmed_thr << 21); 1455 } 1456 1457 static void compute_dco_fine(struct lt_phy_params *p, u32 dco_12g) 1458 { 1459 u32 dco_fine0_tune_2_0 = 0; 1460 u32 dco_fine1_tune_2_0 = 0; 1461 u32 dco_fine2_tune_2_0 = 0; 1462 u32 dco_fine3_tune_2_0 = 0; 1463 u32 dco_dith0_tune_2_0 = 0; 1464 u32 dco_dith1_tune_2_0 = 0; 1465 1466 dco_fine0_tune_2_0 = dco_12g ? 4 : 3; 1467 dco_fine1_tune_2_0 = 2; 1468 dco_fine2_tune_2_0 = dco_12g ? 2 : 1; 1469 dco_fine3_tune_2_0 = 5; 1470 dco_dith0_tune_2_0 = dco_12g ? 4 : 3; 1471 dco_dith1_tune_2_0 = 2; 1472 1473 p->dco_fine.val = (dco_dith1_tune_2_0 << 19) + 1474 (dco_dith0_tune_2_0 << 16) + 1475 (dco_fine3_tune_2_0 << 11) + 1476 (dco_fine2_tune_2_0 << 8) + 1477 (dco_fine1_tune_2_0 << 3) + 1478 dco_fine0_tune_2_0; 1479 } 1480 1481 int 1482 intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state, 1483 u32 frequency_khz) 1484 { 1485 #define DATA_ASSIGN(i, pll_reg) \ 1486 do { \ 1487 lt_state->data[i][0] = (u8)((((pll_reg).val) & 0xFF000000) >> 24); \ 1488 lt_state->data[i][1] = (u8)((((pll_reg).val) & 0x00FF0000) >> 16); \ 1489 lt_state->data[i][2] = (u8)((((pll_reg).val) & 0x0000FF00) >> 8); \ 1490 lt_state->data[i][3] = (u8)((((pll_reg).val) & 0x000000FF)); \ 1491 } while (0) 1492 #define ADDR_ASSIGN(i, pll_reg) \ 1493 do { \ 1494 lt_state->addr_msb[i] = ((pll_reg).addr >> 8) & 0xFF; \ 1495 lt_state->addr_lsb[i] = (pll_reg).addr & 0xFF; \ 1496 } while (0) 1497 1498 bool found = false; 1499 struct lt_phy_params p; 1500 u32 dco_fmin = DCO_MIN_FREQ_MHZ; 1501 u64 refclk_khz = REF_CLK_KHZ; 1502 u32 refclk_mhz_int = REF_CLK_KHZ / 1000; 1503 u64 m2div = 0; 1504 u64 target_dco_mhz = 0; 1505 u64 tdc_fine, tdc_targetcnt; 1506 u64 feedfwd_gain ,feedfwd_cal_en; 1507 u64 tdc_res = 30; 1508 u32 prop_coeff; 1509 u32 int_coeff; 1510 u32 ndiv = 1; 1511 u32 m1div = 1, m2div_int, m2div_frac; 1512 u32 frac_en; 1513 u32 ana_cfg; 1514 u32 loop_cnt = 0; 1515 u32 gain_ctrl = 2; 1516 u32 postdiv = 0; 1517 u32 dco_12g = 0; 1518 u32 pll_type = 0; 1519 u32 d1 = 2, d3 = 5, d4 = 0, d5 = 0; 1520 u32 d6 = 0, d6_new = 0; 1521 u32 d7, d8 = 0; 1522 u32 bonus_7_0 = 0; 1523 u32 csel2fo = 11; 1524 u32 csel2fo_ovrd_en = 1; 1525 u64 temp0, temp1, temp2, temp3; 1526 1527 p.surv_bonus.val = (bonus_7_0 << 16); 1528 p.pll_reg4.val = (refclk_mhz_int << 17) + 1529 (ndiv << 9) + (1 << 4); 1530 p.bias_trim.val = (csel2fo_ovrd_en << 30) + (csel2fo << 24); 1531 p.ssc_inj.val = 0; 1532 found = calculate_target_dco_and_loop_cnt(frequency_khz, &target_dco_mhz, &loop_cnt); 1533 if (!found) 1534 return -EINVAL; 1535 1536 m2div = div64_u64(target_dco_mhz, (refclk_khz * ndiv * m1div)); 1537 m2div = mul_q32_u32(m2div, 1000); 1538 if (Q32_TO_INT(m2div) > 511) 1539 return -EINVAL; 1540 1541 m2div_int = (u32)Q32_TO_INT(m2div); 1542 m2div_frac = (u32)(Q32_TO_FRAC(m2div)); 1543 frac_en = (m2div_frac > 0) ? 1 : 0; 1544 1545 if (frac_en > 0) 1546 tdc_res = 70; 1547 else 1548 tdc_res = 36; 1549 tdc_fine = tdc_res > 50 ? 1 : 0; 1550 temp0 = tdc_res * 40 * 11; 1551 temp1 = div64_u64(((4 * TDC_RES_MULTIPLIER) + temp0) * 500, temp0 * refclk_khz); 1552 temp2 = div64_u64(temp0 * refclk_khz, 1000); 1553 temp3 = div64_u64(((8 * TDC_RES_MULTIPLIER) + temp2), temp2); 1554 tdc_targetcnt = tdc_res < 50 ? (int)(temp1) : (int)(temp3); 1555 tdc_targetcnt = (int)(tdc_targetcnt / 2); 1556 temp0 = mul_q32_u32(target_dco_mhz, tdc_res); 1557 temp0 >>= 32; 1558 feedfwd_gain = (m2div_frac > 0) ? div64_u64(m1div * TDC_RES_MULTIPLIER, temp0) : 0; 1559 feedfwd_cal_en = frac_en; 1560 1561 temp0 = (u32)Q32_TO_INT(target_dco_mhz); 1562 prop_coeff = (temp0 >= dco_fmin) ? 3 : 4; 1563 int_coeff = (temp0 >= dco_fmin) ? 7 : 8; 1564 ana_cfg = (temp0 >= dco_fmin) ? 8 : 6; 1565 dco_12g = (temp0 >= dco_fmin) ? 0 : 1; 1566 1567 if (temp0 > 12960) 1568 d7 = 10; 1569 else 1570 d7 = 8; 1571 1572 d8 = loop_cnt / 2; 1573 d4 = d8 * 2; 1574 1575 /* Compute pll_reg3,5,57 & lf */ 1576 p.pll_reg3.val = (u32)((d4 << 21) + (d3 << 18) + (d1 << 15) + (m2div_int << 5)); 1577 p.pll_reg5.val = m2div_frac; 1578 postdiv = (d5 == 0) ? 9 : d5; 1579 d6_new = (d6 == 0) ? 40 : d6; 1580 p.pll_reg57.val = (d7 << 24) + (postdiv << 15) + (d8 << 7) + d6_new; 1581 p.lf.val = (u32)((frac_en << 31) + (1 << 30) + (frac_en << 29) + 1582 (feedfwd_cal_en << 28) + (tdc_fine << 27) + 1583 (gain_ctrl << 24) + (feedfwd_gain << 16) + 1584 (int_coeff << 12) + (prop_coeff << 8) + tdc_targetcnt); 1585 1586 compute_ssc(&p, ana_cfg); 1587 compute_bias2(&p); 1588 compute_tdc(&p, tdc_fine); 1589 compute_dco_med(&p); 1590 compute_dco_fine(&p, dco_12g); 1591 1592 pll_type = ((frequency_khz == 10000) || (frequency_khz == 20000) || 1593 (frequency_khz == 2500) || (dco_12g == 1)) ? 0 : 1; 1594 set_phy_vdr_addresses(&p, pll_type); 1595 1596 lt_state->config[0] = 0x84; 1597 lt_state->config[1] = 0x2d; 1598 ADDR_ASSIGN(0, p.pll_reg4); 1599 ADDR_ASSIGN(1, p.pll_reg3); 1600 ADDR_ASSIGN(2, p.pll_reg5); 1601 ADDR_ASSIGN(3, p.pll_reg57); 1602 ADDR_ASSIGN(4, p.lf); 1603 ADDR_ASSIGN(5, p.tdc); 1604 ADDR_ASSIGN(6, p.ssc); 1605 ADDR_ASSIGN(7, p.bias2); 1606 ADDR_ASSIGN(8, p.bias_trim); 1607 ADDR_ASSIGN(9, p.dco_med); 1608 ADDR_ASSIGN(10, p.dco_fine); 1609 ADDR_ASSIGN(11, p.ssc_inj); 1610 ADDR_ASSIGN(12, p.surv_bonus); 1611 DATA_ASSIGN(0, p.pll_reg4); 1612 DATA_ASSIGN(1, p.pll_reg3); 1613 DATA_ASSIGN(2, p.pll_reg5); 1614 DATA_ASSIGN(3, p.pll_reg57); 1615 DATA_ASSIGN(4, p.lf); 1616 DATA_ASSIGN(5, p.tdc); 1617 DATA_ASSIGN(6, p.ssc); 1618 DATA_ASSIGN(7, p.bias2); 1619 DATA_ASSIGN(8, p.bias_trim); 1620 DATA_ASSIGN(9, p.dco_med); 1621 DATA_ASSIGN(10, p.dco_fine); 1622 DATA_ASSIGN(11, p.ssc_inj); 1623 DATA_ASSIGN(12, p.surv_bonus); 1624 1625 return 0; 1626 } 1627 1628 static int 1629 intel_lt_phy_calc_hdmi_port_clock(struct intel_display *display, 1630 const struct intel_lt_phy_pll_state *lt_state) 1631 { 1632 #define REGVAL(i) ( \ 1633 (lt_state->data[i][3]) | \ 1634 (lt_state->data[i][2] << 8) | \ 1635 (lt_state->data[i][1] << 16) | \ 1636 (lt_state->data[i][0] << 24) \ 1637 ) 1638 1639 int clk = 0; 1640 u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int; 1641 u64 temp0, temp1; 1642 /* 1643 * The algorithm uses '+' to combine bitfields when 1644 * constructing PLL_reg3 and PLL_reg57: 1645 * PLL_reg57 = (D7 << 24) + (postdiv << 15) + (D8 << 7) + D6_new; 1646 * PLL_reg3 = (D4 << 21) + (D3 << 18) + (D1 << 15) + (m2div_int << 5); 1647 * 1648 * However, this is likely intended to be a bitwise OR operation, 1649 * as each field occupies distinct, non-overlapping bits in the register. 1650 * 1651 * PLL_reg57 is composed of following fields packed into a 32-bit value: 1652 * - D7: max value 10 -> fits in 4 bits -> placed at bits 24-27 1653 * - postdiv: max value 9 -> fits in 4 bits -> placed at bits 15-18 1654 * - D8: derived from loop_cnt / 2, max 127 -> fits in 7 bits 1655 * (though 8 bits are given to it) -> placed at bits 7-14 1656 * - D6_new: fits in lower 7 bits -> placed at bits 0-6 1657 * PLL_reg57 = (D7 << 24) | (postdiv << 15) | (D8 << 7) | D6_new; 1658 * 1659 * Similarly, PLL_reg3 is packed as: 1660 * - D4: max value 256 -> fits in 9 bits -> placed at bits 21-29 1661 * - D3: max value 9 -> fits in 4 bits -> placed at bits 18-21 1662 * - D1: max value 2 -> fits in 2 bits -> placed at bits 15-16 1663 * - m2div_int: max value 511 -> fits in 9 bits (10 bits allocated) 1664 * -> placed at bits 5-14 1665 * PLL_reg3 = (D4 << 21) | (D3 << 18) | (D1 << 15) | (m2div_int << 5); 1666 */ 1667 pll_reg_5 = REGVAL(2); 1668 pll_reg_3 = REGVAL(1); 1669 pll_reg_57 = REGVAL(3); 1670 m2div_frac = pll_reg_5; 1671 1672 /* 1673 * From forward algorithm we know 1674 * m2div = 2 * m2 1675 * val = y * frequency * 5 1676 * So now, 1677 * frequency = (m2 * 2 * refclk_khz / (d8 * 10)) 1678 * frequency = (m2div * refclk_khz / (d8 * 10)) 1679 */ 1680 d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7; 1681 if (d8 == 0) { 1682 drm_WARN_ON(display->drm, 1683 "Invalid port clock using lowest HDMI portclock\n"); 1684 return xe3plpd_lt_hdmi_tables[0].clock_rate; 1685 } 1686 m2div_int = (pll_reg_3 & REG_GENMASK(14, 5)) >> 5; 1687 temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32; 1688 temp1 = (u64)m2div_int * REF_CLK_KHZ; 1689 1690 clk = div_u64((temp1 + temp0), d8 * 10); 1691 1692 return clk; 1693 } 1694 1695 int 1696 intel_lt_phy_calc_port_clock(struct intel_display *display, 1697 const struct intel_lt_phy_pll_state *lt_state) 1698 { 1699 int clk; 1700 u8 mode, rate; 1701 1702 mode = REG_FIELD_GET8(LT_PHY_VDR_MODE_ENCODING_MASK, 1703 lt_state->config[0]); 1704 /* 1705 * For edp/dp read the clock value from the tables 1706 * and return the clock as the algorithm used for 1707 * calculating the port clock does not exactly matches 1708 * with edp/dp clock. 1709 */ 1710 if (mode == MODE_DP) { 1711 rate = REG_FIELD_GET8(LT_PHY_VDR_RATE_ENCODING_MASK, 1712 lt_state->config[0]); 1713 clk = intel_lt_phy_get_dp_clock(rate); 1714 } else if (mode == MODE_HDMI_20) { 1715 clk = intel_lt_phy_calc_hdmi_port_clock(display, lt_state); 1716 } else { 1717 drm_WARN_ON(display->drm, "Unsupported LT PHY Mode!\n"); 1718 clk = 25200; 1719 } 1720 1721 return clk; 1722 } 1723 1724 int 1725 intel_lt_phy_pll_calc_state(struct intel_crtc_state *crtc_state, 1726 struct intel_encoder *encoder) 1727 { 1728 struct intel_display *display = to_intel_display(crtc_state); 1729 const struct intel_lt_phy_pll_params *tables; 1730 int i; 1731 1732 tables = intel_lt_phy_pll_tables_get(crtc_state, encoder); 1733 if (!tables) 1734 return -EINVAL; 1735 1736 for (i = 0; tables[i].name; i++) { 1737 int clock = intel_lt_phy_calc_port_clock(display, tables[i].state); 1738 1739 drm_WARN_ON(display->drm, !intel_dpll_clock_matches(clock, tables[i].clock_rate)); 1740 if (intel_dpll_clock_matches(crtc_state->port_clock, clock)) { 1741 crtc_state->dpll_hw_state.ltpll = *tables[i].state; 1742 if (intel_crtc_has_dp_encoder(crtc_state)) { 1743 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) 1744 crtc_state->dpll_hw_state.ltpll.config[2] = 1; 1745 } 1746 crtc_state->dpll_hw_state.ltpll.ssc_enabled = 1747 intel_lt_phy_pll_is_ssc_enabled(crtc_state, encoder); 1748 return 0; 1749 } 1750 } 1751 1752 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { 1753 return intel_lt_phy_calculate_hdmi_state(&crtc_state->dpll_hw_state.ltpll, 1754 crtc_state->port_clock); 1755 } 1756 1757 return -EINVAL; 1758 } 1759 1760 static void 1761 intel_lt_phy_program_pll(struct intel_encoder *encoder, 1762 const struct intel_crtc_state *crtc_state) 1763 { 1764 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 1765 int i, j, k; 1766 1767 intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_0_CONFIG, 1768 crtc_state->dpll_hw_state.ltpll.config[0], MB_WRITE_COMMITTED); 1769 intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG, 1770 crtc_state->dpll_hw_state.ltpll.config[1], MB_WRITE_COMMITTED); 1771 intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_VDR_2_CONFIG, 1772 crtc_state->dpll_hw_state.ltpll.config[2], MB_WRITE_COMMITTED); 1773 1774 for (i = 0; i <= 12; i++) { 1775 intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_MSB(i), 1776 crtc_state->dpll_hw_state.ltpll.addr_msb[i], 1777 MB_WRITE_COMMITTED); 1778 intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_X_ADDR_LSB(i), 1779 crtc_state->dpll_hw_state.ltpll.addr_lsb[i], 1780 MB_WRITE_COMMITTED); 1781 1782 for (j = 3, k = 0; j >= 0; j--, k++) 1783 intel_lt_phy_write(encoder, INTEL_LT_PHY_LANE0, 1784 LT_PHY_VDR_X_DATAY(i, j), 1785 crtc_state->dpll_hw_state.ltpll.data[i][k], 1786 MB_WRITE_COMMITTED); 1787 } 1788 } 1789 1790 static void 1791 intel_lt_phy_enable_disable_tx(struct intel_encoder *encoder, 1792 const struct intel_crtc_state *crtc_state) 1793 { 1794 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1795 bool lane_reversal = dig_port->lane_reversal; 1796 u8 lane_count = crtc_state->lane_count; 1797 bool is_dp_alt = 1798 intel_tc_port_in_dp_alt_mode(dig_port); 1799 enum intel_tc_pin_assignment tc_pin = 1800 intel_tc_port_get_pin_assignment(dig_port); 1801 u8 transmitter_mask = 0; 1802 1803 /* 1804 * We have a two transmitters per lane and total of 2 PHY lanes so a total 1805 * of 4 transmitters. We prepare a mask of the lanes that need to be activated 1806 * and the transmitter which need to be activated for each lane. TX 0,1 correspond 1807 * to LANE0 and TX 2, 3 correspond to LANE1. 1808 */ 1809 1810 switch (lane_count) { 1811 case 1: 1812 transmitter_mask = lane_reversal ? REG_BIT8(3) : REG_BIT8(0); 1813 if (is_dp_alt) { 1814 if (tc_pin == INTEL_TC_PIN_ASSIGNMENT_D) 1815 transmitter_mask = REG_BIT8(0); 1816 else 1817 transmitter_mask = REG_BIT8(1); 1818 } 1819 break; 1820 case 2: 1821 transmitter_mask = lane_reversal ? REG_GENMASK8(3, 2) : REG_GENMASK8(1, 0); 1822 if (is_dp_alt) 1823 transmitter_mask = REG_GENMASK8(1, 0); 1824 break; 1825 case 3: 1826 transmitter_mask = lane_reversal ? REG_GENMASK8(3, 1) : REG_GENMASK8(2, 0); 1827 if (is_dp_alt) 1828 transmitter_mask = REG_GENMASK8(2, 0); 1829 break; 1830 case 4: 1831 transmitter_mask = REG_GENMASK8(3, 0); 1832 break; 1833 default: 1834 MISSING_CASE(lane_count); 1835 transmitter_mask = REG_GENMASK8(3, 0); 1836 break; 1837 } 1838 1839 if (transmitter_mask & BIT(0)) { 1840 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0), 1841 LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0), 1842 LT_PHY_TX_LANE_ENABLE); 1843 } else { 1844 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(0), 1845 0, LT_PHY_TXY_CTL10_MAC(0), 0); 1846 } 1847 1848 if (transmitter_mask & BIT(1)) { 1849 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1), 1850 LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1), 1851 LT_PHY_TX_LANE_ENABLE); 1852 } else { 1853 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE0, LT_PHY_TXY_CTL10(1), 1854 0, LT_PHY_TXY_CTL10_MAC(1), 0); 1855 } 1856 1857 if (transmitter_mask & BIT(2)) { 1858 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0), 1859 LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(0), 1860 LT_PHY_TX_LANE_ENABLE); 1861 } else { 1862 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(0), 1863 0, LT_PHY_TXY_CTL10_MAC(0), 0); 1864 } 1865 1866 if (transmitter_mask & BIT(3)) { 1867 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1), 1868 LT_PHY_TX_LANE_ENABLE, LT_PHY_TXY_CTL10_MAC(1), 1869 LT_PHY_TX_LANE_ENABLE); 1870 } else { 1871 intel_lt_phy_p2p_write(encoder, INTEL_LT_PHY_LANE1, LT_PHY_TXY_CTL10(1), 1872 0, LT_PHY_TXY_CTL10_MAC(1), 0); 1873 } 1874 } 1875 1876 void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 1877 const struct intel_crtc_state *crtc_state) 1878 { 1879 struct intel_display *display = to_intel_display(encoder); 1880 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1881 bool lane_reversal = dig_port->lane_reversal; 1882 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 1883 enum phy phy = intel_encoder_to_phy(encoder); 1884 enum port port = encoder->port; 1885 struct ref_tracker *wakeref = 0; 1886 u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 1887 ? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) | 1888 XE3PLPDP_LANE_PHY_PULSE_STATUS(1)) 1889 : XE3PLPDP_LANE_PHY_PULSE_STATUS(0); 1890 u8 rate_update; 1891 1892 wakeref = intel_lt_phy_transaction_begin(encoder); 1893 1894 /* 1. Enable MacCLK at default 162 MHz frequency. */ 1895 intel_lt_phy_lane_reset(encoder, crtc_state->lane_count); 1896 1897 /* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */ 1898 intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal); 1899 1900 /* 3. Change owned PHY lanes power to Ready state. */ 1901 intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, 1902 XELPDP_P2_STATE_READY); 1903 1904 /* 1905 * 4. Read the PHY message bus VDR register PHY_VDR_0_Config check enabled PLL type, 1906 * encoded rate and encoded mode. 1907 */ 1908 if (intel_lt_phy_config_changed(encoder, crtc_state)) { 1909 /* 1910 * 5. Program the PHY internal PLL registers over PHY message bus for the desired 1911 * frequency and protocol type 1912 */ 1913 intel_lt_phy_program_pll(encoder, crtc_state); 1914 1915 /* 6. Use the P2P transaction flow */ 1916 /* 1917 * 6.1. Set the PHY VDR register 0xCC4[Rate Control VDR Update] = 1 over PHY message 1918 * bus for Owned PHY Lanes. 1919 */ 1920 /* 1921 * 6.2. Poll for P2P Transaction Ready = "1" and read the MAC message bus VDR 1922 * register at offset 0xC00 for Owned PHY Lanes*. 1923 */ 1924 /* 6.3. Clear P2P transaction Ready bit. */ 1925 intel_lt_phy_p2p_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE, 1926 LT_PHY_RATE_CONTROL_VDR_UPDATE, LT_PHY_MAC_VDR, 1927 LT_PHY_PCLKIN_GATE); 1928 1929 /* 7. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */ 1930 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 1931 XELPDP_LANE_PCLK_PLL_REQUEST(0), 0); 1932 1933 /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */ 1934 if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port), 1935 XELPDP_LANE_PCLK_PLL_ACK(0), 1936 XE3PLPD_MACCLK_TURNOFF_LATENCY_US)) 1937 drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n", 1938 phy_name(phy)); 1939 1940 /* 1941 * 9. Follow the Display Voltage Frequency Switching - Sequence Before Frequency 1942 * Change. We handle this step in bxt_set_cdclk(). 1943 */ 1944 /* 10. Program DDI_CLK_VALFREQ to match intended DDI clock frequency. */ 1945 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 1946 crtc_state->port_clock); 1947 1948 /* 11. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 1. */ 1949 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 1950 XELPDP_LANE_PCLK_PLL_REQUEST(0), 1951 XELPDP_LANE_PCLK_PLL_REQUEST(0)); 1952 1953 /* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */ 1954 if (intel_de_wait_for_set_ms(display, XELPDP_PORT_CLOCK_CTL(display, port), 1955 XELPDP_LANE_PCLK_PLL_ACK(0), 1956 XE3PLPD_MACCLK_TURNON_LATENCY_MS)) 1957 drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n", 1958 phy_name(phy)); 1959 1960 /* 1961 * 13. Ungate the forward clock by setting 1962 * PORT_CLOCK_CTL[Forward Clock Ungate] = 1. 1963 */ 1964 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 1965 XELPDP_FORWARD_CLOCK_UNGATE, 1966 XELPDP_FORWARD_CLOCK_UNGATE); 1967 1968 /* 14. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */ 1969 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 1970 lane_phy_pulse_status, 1971 lane_phy_pulse_status); 1972 /* 1973 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over 1974 * PHY message bus for Owned PHY Lanes. 1975 */ 1976 rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE); 1977 rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE; 1978 intel_lt_phy_write(encoder, owned_lane_mask, LT_PHY_RATE_UPDATE, 1979 rate_update, MB_WRITE_COMMITTED); 1980 1981 /* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */ 1982 if (intel_de_wait_for_set_ms(display, XELPDP_PORT_BUF_CTL2(display, port), 1983 lane_phy_pulse_status, 1984 XE3PLPD_RATE_CALIB_DONE_LATENCY_MS)) 1985 drm_warn(display->drm, "PHY %c PLL rate not changed\n", 1986 phy_name(phy)); 1987 1988 /* 17. SW clears PORT_BUF_CTL2 [PHY Pulse Status]. */ 1989 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 1990 lane_phy_pulse_status, 1991 lane_phy_pulse_status); 1992 } else { 1993 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock); 1994 } 1995 1996 /* 1997 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change. 1998 * We handle this step in bxt_set_cdclk() 1999 */ 2000 /* 19. Move the PHY powerdown state to Active and program to enable/disable transmitters */ 2001 intel_lt_phy_powerdown_change_sequence(encoder, owned_lane_mask, 2002 XELPDP_P0_STATE_ACTIVE); 2003 2004 intel_lt_phy_enable_disable_tx(encoder, crtc_state); 2005 intel_lt_phy_transaction_end(encoder, wakeref); 2006 } 2007 2008 void intel_lt_phy_pll_disable(struct intel_encoder *encoder) 2009 { 2010 struct intel_display *display = to_intel_display(encoder); 2011 enum phy phy = intel_encoder_to_phy(encoder); 2012 enum port port = encoder->port; 2013 struct ref_tracker *wakeref; 2014 u8 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 2015 u32 lane_pipe_reset = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 2016 ? (XELPDP_LANE_PIPE_RESET(0) | 2017 XELPDP_LANE_PIPE_RESET(1)) 2018 : XELPDP_LANE_PIPE_RESET(0); 2019 u32 lane_phy_current_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 2020 ? (XELPDP_LANE_PHY_CURRENT_STATUS(0) | 2021 XELPDP_LANE_PHY_CURRENT_STATUS(1)) 2022 : XELPDP_LANE_PHY_CURRENT_STATUS(0); 2023 u32 lane_phy_pulse_status = owned_lane_mask == INTEL_LT_PHY_BOTH_LANES 2024 ? (XE3PLPDP_LANE_PHY_PULSE_STATUS(0) | 2025 XE3PLPDP_LANE_PHY_PULSE_STATUS(1)) 2026 : XE3PLPDP_LANE_PHY_PULSE_STATUS(0); 2027 2028 wakeref = intel_lt_phy_transaction_begin(encoder); 2029 2030 /* 1. Clear PORT_BUF_CTL2 [PHY Pulse Status]. */ 2031 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 2032 lane_phy_pulse_status, 2033 lane_phy_pulse_status); 2034 2035 /* 2. Set PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> Pipe Reset to 1. */ 2036 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 2037 lane_pipe_reset); 2038 2039 /* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */ 2040 if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port), 2041 lane_phy_current_status, 2042 XE3PLPD_RESET_START_LATENCY_US)) 2043 drm_warn(display->drm, "PHY %c failed to reset lane\n", 2044 phy_name(phy)); 2045 2046 /* 4. Clear for PHY pulse status on owned PHY lanes. */ 2047 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), 2048 lane_phy_pulse_status, 2049 lane_phy_pulse_status); 2050 2051 /* 2052 * 5. Follow the Display Voltage Frequency Switching - 2053 * Sequence Before Frequency Change. We handle this step in bxt_set_cdclk(). 2054 */ 2055 /* 6. Program PORT_CLOCK_CTL[PCLK PLL Request LN0] = 0. */ 2056 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 2057 XELPDP_LANE_PCLK_PLL_REQUEST(0), 0); 2058 2059 /* 7. Program DDI_CLK_VALFREQ to 0. */ 2060 intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0); 2061 2062 /* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */ 2063 if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port), 2064 XELPDP_LANE_PCLK_PLL_ACK(0), 2065 XE3PLPD_MACCLK_TURNOFF_LATENCY_US)) 2066 drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n", 2067 phy_name(phy)); 2068 2069 /* 2070 * 9. Follow the Display Voltage Frequency Switching - 2071 * Sequence After Frequency Change. We handle this step in bxt_set_cdclk(). 2072 */ 2073 /* 10. Program PORT_CLOCK_CTL register to disable and gate clocks. */ 2074 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), 2075 XELPDP_DDI_CLOCK_SELECT_MASK(display) | XELPDP_FORWARD_CLOCK_UNGATE, 0); 2076 2077 /* 11. Program PORT_BUF_CTL5[MacCLK Reset_0] = 1 to assert MacCLK reset. */ 2078 intel_de_rmw(display, XE3PLPD_PORT_BUF_CTL5(port), 2079 XE3PLPD_MACCLK_RESET_0, XE3PLPD_MACCLK_RESET_0); 2080 2081 intel_lt_phy_transaction_end(encoder, wakeref); 2082 } 2083 2084 void intel_lt_phy_set_signal_levels(struct intel_encoder *encoder, 2085 const struct intel_crtc_state *crtc_state) 2086 { 2087 struct intel_display *display = to_intel_display(encoder); 2088 const struct intel_ddi_buf_trans *trans; 2089 u8 owned_lane_mask; 2090 struct ref_tracker *wakeref; 2091 int n_entries, ln; 2092 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2093 2094 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2095 return; 2096 2097 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 2098 2099 wakeref = intel_lt_phy_transaction_begin(encoder); 2100 2101 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 2102 if (drm_WARN_ON_ONCE(display->drm, !trans)) { 2103 intel_lt_phy_transaction_end(encoder, wakeref); 2104 return; 2105 } 2106 2107 for (ln = 0; ln < crtc_state->lane_count; ln++) { 2108 int level = intel_ddi_level(encoder, crtc_state, ln); 2109 int lane = ln / 2; 2110 int tx = ln % 2; 2111 u8 lane_mask = lane == 0 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1; 2112 2113 if (!(lane_mask & owned_lane_mask)) 2114 continue; 2115 2116 intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL8(tx), 2117 LT_PHY_TX_SWING_LEVEL_MASK | LT_PHY_TX_SWING_MASK, 2118 LT_PHY_TX_SWING_LEVEL(trans->entries[level].lt.txswing_level) | 2119 LT_PHY_TX_SWING(trans->entries[level].lt.txswing), 2120 MB_WRITE_COMMITTED); 2121 2122 intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL2(tx), 2123 LT_PHY_TX_CURSOR_MASK, 2124 LT_PHY_TX_CURSOR(trans->entries[level].lt.pre_cursor), 2125 MB_WRITE_COMMITTED); 2126 intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL3(tx), 2127 LT_PHY_TX_CURSOR_MASK, 2128 LT_PHY_TX_CURSOR(trans->entries[level].lt.main_cursor), 2129 MB_WRITE_COMMITTED); 2130 intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_TXY_CTL4(tx), 2131 LT_PHY_TX_CURSOR_MASK, 2132 LT_PHY_TX_CURSOR(trans->entries[level].lt.post_cursor), 2133 MB_WRITE_COMMITTED); 2134 } 2135 2136 intel_lt_phy_transaction_end(encoder, wakeref); 2137 } 2138 2139 void intel_lt_phy_dump_hw_state(struct intel_display *display, 2140 const struct intel_lt_phy_pll_state *hw_state) 2141 { 2142 int i, j; 2143 2144 drm_dbg_kms(display->drm, "lt_phy_pll_hw_state:\n"); 2145 for (i = 0; i < 3; i++) { 2146 drm_dbg_kms(display->drm, "config[%d] = 0x%.4x,\n", 2147 i, hw_state->config[i]); 2148 } 2149 2150 for (i = 0; i <= 12; i++) 2151 for (j = 3; j >= 0; j--) 2152 drm_dbg_kms(display->drm, "vdr_data[%d][%d] = 0x%.4x,\n", 2153 i, j, hw_state->data[i][j]); 2154 } 2155 2156 bool 2157 intel_lt_phy_pll_compare_hw_state(const struct intel_lt_phy_pll_state *a, 2158 const struct intel_lt_phy_pll_state *b) 2159 { 2160 if (a->tbt_mode || b->tbt_mode) 2161 return true; 2162 2163 /* 2164 * With LT PHY values other than VDR0_CONFIG and VDR2_CONFIG are 2165 * unreliable. They cannot always be read back since internally 2166 * after power gating values are not restored back to the 2167 * shadow VDR registers. Thus we do not compare the whole state 2168 * just the two VDR registers. 2169 */ 2170 if (a->config[0] == b->config[0] && 2171 a->config[2] == b->config[2]) 2172 return true; 2173 2174 return false; 2175 } 2176 2177 void intel_lt_phy_pll_readout_hw_state(struct intel_encoder *encoder, 2178 const struct intel_crtc_state *crtc_state, 2179 struct intel_lt_phy_pll_state *pll_state) 2180 { 2181 u8 owned_lane_mask; 2182 u8 lane; 2183 struct ref_tracker *wakeref; 2184 int i, j, k; 2185 2186 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); 2187 if (pll_state->tbt_mode) 2188 return; 2189 2190 owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder); 2191 lane = owned_lane_mask & INTEL_LT_PHY_LANE0 ? : INTEL_LT_PHY_LANE1; 2192 wakeref = intel_lt_phy_transaction_begin(encoder); 2193 2194 pll_state->config[0] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_0_CONFIG); 2195 pll_state->config[1] = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_VDR_1_CONFIG); 2196 pll_state->config[2] = intel_lt_phy_read(encoder, lane, LT_PHY_VDR_2_CONFIG); 2197 2198 for (i = 0; i <= 12; i++) { 2199 for (j = 3, k = 0; j >= 0; j--, k++) 2200 pll_state->data[i][k] = 2201 intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, 2202 LT_PHY_VDR_X_DATAY(i, j)); 2203 } 2204 2205 intel_lt_phy_transaction_end(encoder, wakeref); 2206 } 2207 2208 void intel_lt_phy_pll_state_verify(struct intel_atomic_state *state, 2209 struct intel_crtc *crtc) 2210 { 2211 struct intel_display *display = to_intel_display(state); 2212 struct intel_digital_port *dig_port; 2213 const struct intel_crtc_state *new_crtc_state = 2214 intel_atomic_get_new_crtc_state(state, crtc); 2215 struct intel_encoder *encoder; 2216 struct intel_lt_phy_pll_state pll_hw_state = {}; 2217 const struct intel_lt_phy_pll_state *pll_sw_state = &new_crtc_state->dpll_hw_state.ltpll; 2218 2219 if (DISPLAY_VER(display) < 35) 2220 return; 2221 2222 if (!new_crtc_state->hw.active) 2223 return; 2224 2225 /* intel_get_crtc_new_encoder() only works for modeset/fastset commits */ 2226 if (!intel_crtc_needs_modeset(new_crtc_state) && 2227 !intel_crtc_needs_fastset(new_crtc_state)) 2228 return; 2229 2230 encoder = intel_get_crtc_new_encoder(state, new_crtc_state); 2231 intel_lt_phy_pll_readout_hw_state(encoder, new_crtc_state, &pll_hw_state); 2232 2233 dig_port = enc_to_dig_port(encoder); 2234 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2235 return; 2236 2237 INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[0] != pll_sw_state->config[0], 2238 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 0: (expected 0x%04x, found 0x%04x)", 2239 crtc->base.base.id, crtc->base.name, 2240 pll_sw_state->config[0], pll_hw_state.config[0]); 2241 INTEL_DISPLAY_STATE_WARN(display, pll_hw_state.config[2] != pll_sw_state->config[2], 2242 "[CRTC:%d:%s] mismatch in LT PHY PLL CONFIG 2: (expected 0x%04x, found 0x%04x)", 2243 crtc->base.base.id, crtc->base.name, 2244 pll_sw_state->config[2], pll_hw_state.config[2]); 2245 } 2246 2247 void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, 2248 const struct intel_crtc_state *crtc_state) 2249 { 2250 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2251 2252 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2253 intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->port_clock); 2254 else 2255 intel_lt_phy_pll_enable(encoder, crtc_state); 2256 } 2257 2258 void intel_xe3plpd_pll_disable(struct intel_encoder *encoder) 2259 { 2260 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2261 2262 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 2263 intel_mtl_tbt_pll_disable_clock(encoder); 2264 else 2265 intel_lt_phy_pll_disable(encoder); 2266 2267 } 2268 2269 static void intel_lt_phy_pll_verify_clock(struct intel_display *display, 2270 int precomputed_clock, 2271 const char *pll_state_name, 2272 const struct intel_lt_phy_pll_state *pll_state, 2273 bool is_precomputed_state) 2274 { 2275 struct drm_printer p; 2276 int clock; 2277 2278 clock = intel_lt_phy_calc_port_clock(display, pll_state); 2279 2280 if (intel_dpll_clock_matches(clock, precomputed_clock)) 2281 return; 2282 2283 drm_warn(display->drm, 2284 "PLL state %s (%s): clock difference too high: computed %d, pre-computed %d\n", 2285 pll_state_name, 2286 is_precomputed_state ? "precomputed" : "computed", 2287 clock, precomputed_clock); 2288 2289 if (!drm_debug_enabled(DRM_UT_KMS)) 2290 return; 2291 2292 p = drm_dbg_printer(display->drm, DRM_UT_KMS, NULL); 2293 2294 drm_printf(&p, "PLL state %s (%s):\n", 2295 pll_state_name, 2296 is_precomputed_state ? "precomputed" : "computed"); 2297 intel_lt_phy_dump_hw_state(display, pll_state); 2298 } 2299 2300 static void intel_lt_phy_pll_verify_params(struct intel_display *display, 2301 const struct intel_lt_phy_pll_params *pll_params) 2302 { 2303 struct intel_lt_phy_pll_state pll_state; 2304 2305 intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->state, true); 2306 2307 if (!pll_params->is_hdmi) 2308 return; 2309 2310 if (intel_lt_phy_calculate_hdmi_state(&pll_state, pll_params->clock_rate) != 0) 2311 return; 2312 2313 intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false); 2314 } 2315 2316 static void intel_lt_phy_pll_verify_tables(struct intel_display *display, 2317 const struct intel_lt_phy_pll_params *tables) 2318 { 2319 int i; 2320 2321 for (i = 0; tables[i].name; i++) 2322 intel_lt_phy_pll_verify_params(display, &tables[i]); 2323 } 2324 2325 void intel_lt_phy_verify_plls(struct intel_display *display) 2326 { 2327 intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_dp_tables); 2328 intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables); 2329 intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); 2330 } 2331