1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "i915_reg.h" 9 #include "i915_utils.h" 10 #include "intel_de.h" 11 #include "intel_display_irq.h" 12 #include "intel_display_types.h" 13 #include "intel_dp_aux.h" 14 #include "intel_gmbus.h" 15 #include "intel_hotplug.h" 16 #include "intel_hotplug_irq.h" 17 18 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 19 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder); 20 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin); 21 22 static const u32 hpd_ilk[HPD_NUM_PINS] = { 23 [HPD_PORT_A] = DE_DP_A_HOTPLUG, 24 }; 25 26 static const u32 hpd_ivb[HPD_NUM_PINS] = { 27 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 28 }; 29 30 static const u32 hpd_bdw[HPD_NUM_PINS] = { 31 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 32 }; 33 34 static const u32 hpd_ibx[HPD_NUM_PINS] = { 35 [HPD_CRT] = SDE_CRT_HOTPLUG, 36 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 37 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 38 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 39 [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 40 }; 41 42 static const u32 hpd_cpt[HPD_NUM_PINS] = { 43 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 44 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 45 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 46 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 47 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 48 }; 49 50 static const u32 hpd_spt[HPD_NUM_PINS] = { 51 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 52 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 53 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 54 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 55 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 56 }; 57 58 static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 59 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 60 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 61 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 62 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 63 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 64 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 65 }; 66 67 static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 68 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 69 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 70 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 71 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 72 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 73 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 74 }; 75 76 static const u32 hpd_status_i915[HPD_NUM_PINS] = { 77 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 78 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 79 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 80 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 81 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 82 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 83 }; 84 85 static const u32 hpd_bxt[HPD_NUM_PINS] = { 86 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 87 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 88 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 89 }; 90 91 static const u32 hpd_gen11[HPD_NUM_PINS] = { 92 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 93 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 94 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 95 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 96 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 97 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 98 }; 99 100 static const u32 hpd_xelpdp[HPD_NUM_PINS] = { 101 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1), 102 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2), 103 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3), 104 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4), 105 }; 106 107 static const u32 hpd_icp[HPD_NUM_PINS] = { 108 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 109 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 110 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 111 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 112 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 113 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 114 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 115 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 116 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 117 }; 118 119 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 120 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 121 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 122 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 123 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 124 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1), 125 }; 126 127 static const u32 hpd_mtp[HPD_NUM_PINS] = { 128 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 129 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 130 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 131 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 132 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 133 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 134 }; 135 136 static void intel_hpd_init_pins(struct intel_display *display) 137 { 138 struct intel_hotplug *hpd = &display->hotplug; 139 140 if (HAS_GMCH(display)) { 141 if (display->platform.g4x || display->platform.valleyview || 142 display->platform.cherryview) 143 hpd->hpd = hpd_status_g4x; 144 else 145 hpd->hpd = hpd_status_i915; 146 return; 147 } 148 149 if (DISPLAY_VER(display) >= 14) 150 hpd->hpd = hpd_xelpdp; 151 else if (DISPLAY_VER(display) >= 11) 152 hpd->hpd = hpd_gen11; 153 else if (display->platform.geminilake || display->platform.broxton) 154 hpd->hpd = hpd_bxt; 155 else if (DISPLAY_VER(display) == 9) 156 hpd->hpd = NULL; /* no north HPD on SKL */ 157 else if (DISPLAY_VER(display) >= 8) 158 hpd->hpd = hpd_bdw; 159 else if (DISPLAY_VER(display) >= 7) 160 hpd->hpd = hpd_ivb; 161 else 162 hpd->hpd = hpd_ilk; 163 164 if ((INTEL_PCH_TYPE(display) < PCH_DG1) && 165 (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display))) 166 return; 167 168 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 169 hpd->pch_hpd = hpd_mtp; 170 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 171 hpd->pch_hpd = hpd_sde_dg1; 172 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 173 hpd->pch_hpd = hpd_icp; 174 else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display)) 175 hpd->pch_hpd = hpd_spt; 176 else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display)) 177 hpd->pch_hpd = hpd_cpt; 178 else if (HAS_PCH_IBX(display)) 179 hpd->pch_hpd = hpd_ibx; 180 else 181 MISSING_CASE(INTEL_PCH_TYPE(display)); 182 } 183 184 /* For display hotplug interrupt */ 185 void i915_hotplug_interrupt_update_locked(struct intel_display *display, 186 u32 mask, u32 bits) 187 { 188 lockdep_assert_held(&display->irq.lock); 189 drm_WARN_ON(display->drm, bits & ~mask); 190 191 intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); 192 } 193 194 /** 195 * i915_hotplug_interrupt_update - update hotplug interrupt enable 196 * @display: display device 197 * @mask: bits to update 198 * @bits: bits to enable 199 * NOTE: the HPD enable bits are modified both inside and outside 200 * of an interrupt context. To avoid that read-modify-write cycles 201 * interfere, these bits are protected by a spinlock. Since this 202 * function is usually not called from a context where the lock is 203 * held already, this function acquires the lock itself. A non-locking 204 * version is also available. 205 */ 206 void i915_hotplug_interrupt_update(struct intel_display *display, 207 u32 mask, 208 u32 bits) 209 { 210 spin_lock_irq(&display->irq.lock); 211 i915_hotplug_interrupt_update_locked(display, mask, bits); 212 spin_unlock_irq(&display->irq.lock); 213 } 214 215 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 216 { 217 switch (pin) { 218 case HPD_PORT_TC1: 219 case HPD_PORT_TC2: 220 case HPD_PORT_TC3: 221 case HPD_PORT_TC4: 222 case HPD_PORT_TC5: 223 case HPD_PORT_TC6: 224 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 225 default: 226 return false; 227 } 228 } 229 230 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 231 { 232 switch (pin) { 233 case HPD_PORT_A: 234 return val & PORTA_HOTPLUG_LONG_DETECT; 235 case HPD_PORT_B: 236 return val & PORTB_HOTPLUG_LONG_DETECT; 237 case HPD_PORT_C: 238 return val & PORTC_HOTPLUG_LONG_DETECT; 239 default: 240 return false; 241 } 242 } 243 244 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 245 { 246 switch (pin) { 247 case HPD_PORT_A: 248 case HPD_PORT_B: 249 case HPD_PORT_C: 250 case HPD_PORT_D: 251 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 252 default: 253 return false; 254 } 255 } 256 257 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 258 { 259 switch (pin) { 260 case HPD_PORT_TC1: 261 case HPD_PORT_TC2: 262 case HPD_PORT_TC3: 263 case HPD_PORT_TC4: 264 case HPD_PORT_TC5: 265 case HPD_PORT_TC6: 266 return val & ICP_TC_HPD_LONG_DETECT(pin); 267 default: 268 return false; 269 } 270 } 271 272 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 273 { 274 switch (pin) { 275 case HPD_PORT_E: 276 return val & PORTE_HOTPLUG_LONG_DETECT; 277 default: 278 return false; 279 } 280 } 281 282 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 283 { 284 switch (pin) { 285 case HPD_PORT_A: 286 return val & PORTA_HOTPLUG_LONG_DETECT; 287 case HPD_PORT_B: 288 return val & PORTB_HOTPLUG_LONG_DETECT; 289 case HPD_PORT_C: 290 return val & PORTC_HOTPLUG_LONG_DETECT; 291 case HPD_PORT_D: 292 return val & PORTD_HOTPLUG_LONG_DETECT; 293 default: 294 return false; 295 } 296 } 297 298 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 299 { 300 switch (pin) { 301 case HPD_PORT_A: 302 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 303 default: 304 return false; 305 } 306 } 307 308 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 309 { 310 switch (pin) { 311 case HPD_PORT_B: 312 return val & PORTB_HOTPLUG_LONG_DETECT; 313 case HPD_PORT_C: 314 return val & PORTC_HOTPLUG_LONG_DETECT; 315 case HPD_PORT_D: 316 return val & PORTD_HOTPLUG_LONG_DETECT; 317 default: 318 return false; 319 } 320 } 321 322 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 323 { 324 switch (pin) { 325 case HPD_PORT_B: 326 return val & PORTB_HOTPLUG_INT_LONG_PULSE; 327 case HPD_PORT_C: 328 return val & PORTC_HOTPLUG_INT_LONG_PULSE; 329 case HPD_PORT_D: 330 return val & PORTD_HOTPLUG_INT_LONG_PULSE; 331 default: 332 return false; 333 } 334 } 335 336 /* 337 * Get a bit mask of pins that have triggered, and which ones may be long. 338 * This can be called multiple times with the same masks to accumulate 339 * hotplug detection results from several registers. 340 * 341 * Note that the caller is expected to zero out the masks initially. 342 */ 343 static void intel_get_hpd_pins(struct intel_display *display, 344 u32 *pin_mask, u32 *long_mask, 345 u32 hotplug_trigger, u32 dig_hotplug_reg, 346 const u32 hpd[HPD_NUM_PINS], 347 bool long_pulse_detect(enum hpd_pin pin, u32 val)) 348 { 349 enum hpd_pin pin; 350 351 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 352 353 for_each_hpd_pin(pin) { 354 if ((hpd[pin] & hotplug_trigger) == 0) 355 continue; 356 357 *pin_mask |= BIT(pin); 358 359 if (long_pulse_detect(pin, dig_hotplug_reg)) 360 *long_mask |= BIT(pin); 361 } 362 363 drm_dbg_kms(display->drm, 364 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 365 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 366 } 367 368 static u32 intel_hpd_enabled_irqs(struct intel_display *display, 369 const u32 hpd[HPD_NUM_PINS]) 370 { 371 struct intel_encoder *encoder; 372 u32 enabled_irqs = 0; 373 374 for_each_intel_encoder(display->drm, encoder) 375 if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 376 enabled_irqs |= hpd[encoder->hpd_pin]; 377 378 return enabled_irqs; 379 } 380 381 static u32 intel_hpd_hotplug_irqs(struct intel_display *display, 382 const u32 hpd[HPD_NUM_PINS]) 383 { 384 struct intel_encoder *encoder; 385 u32 hotplug_irqs = 0; 386 387 for_each_intel_encoder(display->drm, encoder) 388 hotplug_irqs |= hpd[encoder->hpd_pin]; 389 390 return hotplug_irqs; 391 } 392 393 static u32 intel_hpd_hotplug_mask(struct intel_display *display, 394 hotplug_mask_func hotplug_mask) 395 { 396 enum hpd_pin pin; 397 u32 hotplug = 0; 398 399 for_each_hpd_pin(pin) 400 hotplug |= hotplug_mask(pin); 401 402 return hotplug; 403 } 404 405 static u32 intel_hpd_hotplug_enables(struct intel_display *display, 406 hotplug_enables_func hotplug_enables) 407 { 408 struct intel_encoder *encoder; 409 u32 hotplug = 0; 410 411 for_each_intel_encoder(display->drm, encoder) 412 hotplug |= hotplug_enables(encoder); 413 414 return hotplug; 415 } 416 417 u32 i9xx_hpd_irq_ack(struct intel_display *display) 418 { 419 u32 hotplug_status = 0, hotplug_status_mask; 420 int i; 421 422 if (display->platform.g4x || 423 display->platform.valleyview || display->platform.cherryview) 424 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 425 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 426 else 427 hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 428 429 /* 430 * We absolutely have to clear all the pending interrupt 431 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 432 * interrupt bit won't have an edge, and the i965/g4x 433 * edge triggered IIR will not notice that an interrupt 434 * is still pending. We can't use PORT_HOTPLUG_EN to 435 * guarantee the edge as the act of toggling the enable 436 * bits can itself generate a new hotplug interrupt :( 437 */ 438 for (i = 0; i < 10; i++) { 439 u32 tmp = intel_de_read(display, 440 PORT_HOTPLUG_STAT(display)) & hotplug_status_mask; 441 442 if (tmp == 0) 443 return hotplug_status; 444 445 hotplug_status |= tmp; 446 intel_de_write(display, PORT_HOTPLUG_STAT(display), 447 hotplug_status); 448 } 449 450 drm_WARN_ONCE(display->drm, 1, 451 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 452 intel_de_read(display, PORT_HOTPLUG_STAT(display))); 453 454 return hotplug_status; 455 } 456 457 void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status) 458 { 459 u32 pin_mask = 0, long_mask = 0; 460 u32 hotplug_trigger; 461 462 if (display->platform.g4x || 463 display->platform.valleyview || display->platform.cherryview) 464 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 465 else 466 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 467 468 if (hotplug_trigger) { 469 intel_get_hpd_pins(display, &pin_mask, &long_mask, 470 hotplug_trigger, hotplug_trigger, 471 display->hotplug.hpd, 472 i9xx_port_hotplug_long_detect); 473 474 intel_hpd_irq_handler(display, pin_mask, long_mask); 475 } 476 477 if ((display->platform.g4x || 478 display->platform.valleyview || display->platform.cherryview) && 479 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 480 intel_dp_aux_irq_handler(display); 481 } 482 483 void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 484 { 485 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 486 487 /* 488 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 489 * unless we touch the hotplug register, even if hotplug_trigger is 490 * zero. Not acking leads to "The master control interrupt lied (SDE)!" 491 * errors. 492 */ 493 dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG); 494 if (!hotplug_trigger) { 495 u32 mask = PORTA_HOTPLUG_STATUS_MASK | 496 PORTD_HOTPLUG_STATUS_MASK | 497 PORTC_HOTPLUG_STATUS_MASK | 498 PORTB_HOTPLUG_STATUS_MASK; 499 dig_hotplug_reg &= ~mask; 500 } 501 502 intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg); 503 if (!hotplug_trigger) 504 return; 505 506 intel_get_hpd_pins(display, &pin_mask, &long_mask, 507 hotplug_trigger, dig_hotplug_reg, 508 display->hotplug.pch_hpd, 509 pch_port_hotplug_long_detect); 510 511 intel_hpd_irq_handler(display, pin_mask, long_mask); 512 } 513 514 void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) 515 { 516 enum hpd_pin pin; 517 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 518 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 519 u32 pin_mask = 0, long_mask = 0; 520 521 if (DISPLAY_VER(display) >= 20) 522 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; 523 524 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 525 u32 val; 526 527 if (!(display->hotplug.hpd[pin] & hotplug_trigger)) 528 continue; 529 530 pin_mask |= BIT(pin); 531 532 val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin)); 533 intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val); 534 535 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT)) 536 long_mask |= BIT(pin); 537 } 538 539 if (pin_mask) { 540 drm_dbg_kms(display->drm, 541 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 542 hotplug_trigger, pin_mask, long_mask); 543 544 intel_hpd_irq_handler(display, pin_mask, long_mask); 545 } 546 547 if (trigger_aux) 548 intel_dp_aux_irq_handler(display); 549 550 if (!pin_mask && !trigger_aux) 551 drm_err(display->drm, 552 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir); 553 } 554 555 void icp_irq_handler(struct intel_display *display, u32 pch_iir) 556 { 557 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 558 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 559 u32 pin_mask = 0, long_mask = 0; 560 561 if (ddi_hotplug_trigger) { 562 u32 dig_hotplug_reg; 563 564 /* Locking due to DSI native GPIO sequences */ 565 spin_lock(&display->irq.lock); 566 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0); 567 spin_unlock(&display->irq.lock); 568 569 intel_get_hpd_pins(display, &pin_mask, &long_mask, 570 ddi_hotplug_trigger, dig_hotplug_reg, 571 display->hotplug.pch_hpd, 572 icp_ddi_port_hotplug_long_detect); 573 } 574 575 if (tc_hotplug_trigger) { 576 u32 dig_hotplug_reg; 577 578 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0); 579 580 intel_get_hpd_pins(display, &pin_mask, &long_mask, 581 tc_hotplug_trigger, dig_hotplug_reg, 582 display->hotplug.pch_hpd, 583 icp_tc_port_hotplug_long_detect); 584 } 585 586 if (pin_mask) 587 intel_hpd_irq_handler(display, pin_mask, long_mask); 588 589 if (pch_iir & SDE_GMBUS_ICP) 590 intel_gmbus_irq_handler(display); 591 } 592 593 void spt_irq_handler(struct intel_display *display, u32 pch_iir) 594 { 595 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 596 ~SDE_PORTE_HOTPLUG_SPT; 597 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 598 u32 pin_mask = 0, long_mask = 0; 599 600 if (hotplug_trigger) { 601 u32 dig_hotplug_reg; 602 603 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 604 605 intel_get_hpd_pins(display, &pin_mask, &long_mask, 606 hotplug_trigger, dig_hotplug_reg, 607 display->hotplug.pch_hpd, 608 spt_port_hotplug_long_detect); 609 } 610 611 if (hotplug2_trigger) { 612 u32 dig_hotplug_reg; 613 614 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0); 615 616 intel_get_hpd_pins(display, &pin_mask, &long_mask, 617 hotplug2_trigger, dig_hotplug_reg, 618 display->hotplug.pch_hpd, 619 spt_port_hotplug2_long_detect); 620 } 621 622 if (pin_mask) 623 intel_hpd_irq_handler(display, pin_mask, long_mask); 624 625 if (pch_iir & SDE_GMBUS_CPT) 626 intel_gmbus_irq_handler(display); 627 } 628 629 void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 630 { 631 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 632 633 dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0); 634 635 intel_get_hpd_pins(display, &pin_mask, &long_mask, 636 hotplug_trigger, dig_hotplug_reg, 637 display->hotplug.hpd, 638 ilk_port_hotplug_long_detect); 639 640 intel_hpd_irq_handler(display, pin_mask, long_mask); 641 } 642 643 void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 644 { 645 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 646 647 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 648 649 intel_get_hpd_pins(display, &pin_mask, &long_mask, 650 hotplug_trigger, dig_hotplug_reg, 651 display->hotplug.hpd, 652 bxt_port_hotplug_long_detect); 653 654 intel_hpd_irq_handler(display, pin_mask, long_mask); 655 } 656 657 void gen11_hpd_irq_handler(struct intel_display *display, u32 iir) 658 { 659 u32 pin_mask = 0, long_mask = 0; 660 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 661 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 662 663 if (trigger_tc) { 664 u32 dig_hotplug_reg; 665 666 dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0); 667 668 intel_get_hpd_pins(display, &pin_mask, &long_mask, 669 trigger_tc, dig_hotplug_reg, 670 display->hotplug.hpd, 671 gen11_port_hotplug_long_detect); 672 } 673 674 if (trigger_tbt) { 675 u32 dig_hotplug_reg; 676 677 dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0); 678 679 intel_get_hpd_pins(display, &pin_mask, &long_mask, 680 trigger_tbt, dig_hotplug_reg, 681 display->hotplug.hpd, 682 gen11_port_hotplug_long_detect); 683 } 684 685 if (pin_mask) 686 intel_hpd_irq_handler(display, pin_mask, long_mask); 687 else 688 drm_err(display->drm, 689 "Unexpected DE HPD interrupt 0x%08x\n", iir); 690 } 691 692 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin) 693 { 694 switch (hpd_pin) { 695 case HPD_PORT_A: 696 return PORTA_HOTPLUG_ENABLE; 697 case HPD_PORT_B: 698 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK; 699 case HPD_PORT_C: 700 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK; 701 case HPD_PORT_D: 702 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK; 703 default: 704 return 0; 705 } 706 } 707 708 static u32 ibx_hotplug_enables(struct intel_encoder *encoder) 709 { 710 struct intel_display *display = to_intel_display(encoder); 711 712 switch (encoder->hpd_pin) { 713 case HPD_PORT_A: 714 /* 715 * When CPU and PCH are on the same package, port A 716 * HPD must be enabled in both north and south. 717 */ 718 return HAS_PCH_LPT_LP(display) ? 719 PORTA_HOTPLUG_ENABLE : 0; 720 case HPD_PORT_B: 721 return PORTB_HOTPLUG_ENABLE | 722 PORTB_PULSE_DURATION_2ms; 723 case HPD_PORT_C: 724 return PORTC_HOTPLUG_ENABLE | 725 PORTC_PULSE_DURATION_2ms; 726 case HPD_PORT_D: 727 return PORTD_HOTPLUG_ENABLE | 728 PORTD_PULSE_DURATION_2ms; 729 default: 730 return 0; 731 } 732 } 733 734 static void ibx_hpd_detection_setup(struct intel_display *display) 735 { 736 /* 737 * Enable digital hotplug on the PCH, and configure the DP short pulse 738 * duration to 2ms (which is the minimum in the Display Port spec). 739 * The pulse duration bits are reserved on LPT+. 740 */ 741 intel_de_rmw(display, PCH_PORT_HOTPLUG, 742 intel_hpd_hotplug_mask(display, ibx_hotplug_mask), 743 intel_hpd_hotplug_enables(display, ibx_hotplug_enables)); 744 } 745 746 static void ibx_hpd_enable_detection(struct intel_encoder *encoder) 747 { 748 struct intel_display *display = to_intel_display(encoder); 749 750 intel_de_rmw(display, PCH_PORT_HOTPLUG, 751 ibx_hotplug_mask(encoder->hpd_pin), 752 ibx_hotplug_enables(encoder)); 753 } 754 755 static void ibx_hpd_irq_setup(struct intel_display *display) 756 { 757 u32 hotplug_irqs, enabled_irqs; 758 759 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 760 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 761 762 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 763 764 ibx_hpd_detection_setup(display); 765 } 766 767 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 768 { 769 switch (hpd_pin) { 770 case HPD_PORT_A: 771 case HPD_PORT_B: 772 case HPD_PORT_C: 773 case HPD_PORT_D: 774 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 775 default: 776 return 0; 777 } 778 } 779 780 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder) 781 { 782 return icp_ddi_hotplug_mask(encoder->hpd_pin); 783 } 784 785 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin) 786 { 787 switch (hpd_pin) { 788 case HPD_PORT_TC1: 789 case HPD_PORT_TC2: 790 case HPD_PORT_TC3: 791 case HPD_PORT_TC4: 792 case HPD_PORT_TC5: 793 case HPD_PORT_TC6: 794 return ICP_TC_HPD_ENABLE(hpd_pin); 795 default: 796 return 0; 797 } 798 } 799 800 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder) 801 { 802 return icp_tc_hotplug_mask(encoder->hpd_pin); 803 } 804 805 static void icp_ddi_hpd_detection_setup(struct intel_display *display) 806 { 807 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 808 intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask), 809 intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables)); 810 } 811 812 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 813 { 814 struct intel_display *display = to_intel_display(encoder); 815 816 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 817 icp_ddi_hotplug_mask(encoder->hpd_pin), 818 icp_ddi_hotplug_enables(encoder)); 819 } 820 821 static void icp_tc_hpd_detection_setup(struct intel_display *display) 822 { 823 intel_de_rmw(display, SHOTPLUG_CTL_TC, 824 intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask), 825 intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables)); 826 } 827 828 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) 829 { 830 struct intel_display *display = to_intel_display(encoder); 831 832 intel_de_rmw(display, SHOTPLUG_CTL_TC, 833 icp_tc_hotplug_mask(encoder->hpd_pin), 834 icp_tc_hotplug_enables(encoder)); 835 } 836 837 static void icp_hpd_enable_detection(struct intel_encoder *encoder) 838 { 839 icp_ddi_hpd_enable_detection(encoder); 840 icp_tc_hpd_enable_detection(encoder); 841 } 842 843 static void icp_hpd_irq_setup(struct intel_display *display) 844 { 845 u32 hotplug_irqs, enabled_irqs; 846 847 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 848 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 849 850 /* 851 * We reduce the value to 250us to be able to detect SHPD when an external display 852 * is connected. This is also expected of us as stated in DP1.4a Table 3-4. 853 */ 854 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 855 856 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 857 858 icp_ddi_hpd_detection_setup(display); 859 icp_tc_hpd_detection_setup(display); 860 } 861 862 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin) 863 { 864 switch (hpd_pin) { 865 case HPD_PORT_TC1: 866 case HPD_PORT_TC2: 867 case HPD_PORT_TC3: 868 case HPD_PORT_TC4: 869 case HPD_PORT_TC5: 870 case HPD_PORT_TC6: 871 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin); 872 default: 873 return 0; 874 } 875 } 876 877 static u32 gen11_hotplug_enables(struct intel_encoder *encoder) 878 { 879 return gen11_hotplug_mask(encoder->hpd_pin); 880 } 881 882 static void dg1_hpd_invert(struct intel_display *display) 883 { 884 u32 val = (INVERT_DDIA_HPD | 885 INVERT_DDIB_HPD | 886 INVERT_DDIC_HPD | 887 INVERT_DDID_HPD); 888 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 889 } 890 891 static void dg1_hpd_enable_detection(struct intel_encoder *encoder) 892 { 893 struct intel_display *display = to_intel_display(encoder); 894 895 dg1_hpd_invert(display); 896 icp_hpd_enable_detection(encoder); 897 } 898 899 static void dg1_hpd_irq_setup(struct intel_display *display) 900 { 901 dg1_hpd_invert(display); 902 icp_hpd_irq_setup(display); 903 } 904 905 static void gen11_tc_hpd_detection_setup(struct intel_display *display) 906 { 907 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 908 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 909 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 910 } 911 912 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) 913 { 914 struct intel_display *display = to_intel_display(encoder); 915 916 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 917 gen11_hotplug_mask(encoder->hpd_pin), 918 gen11_hotplug_enables(encoder)); 919 } 920 921 static void gen11_tbt_hpd_detection_setup(struct intel_display *display) 922 { 923 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 924 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 925 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 926 } 927 928 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) 929 { 930 struct intel_display *display = to_intel_display(encoder); 931 932 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 933 gen11_hotplug_mask(encoder->hpd_pin), 934 gen11_hotplug_enables(encoder)); 935 } 936 937 static void gen11_hpd_enable_detection(struct intel_encoder *encoder) 938 { 939 struct intel_display *display = to_intel_display(encoder); 940 941 gen11_tc_hpd_enable_detection(encoder); 942 gen11_tbt_hpd_enable_detection(encoder); 943 944 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 945 icp_hpd_enable_detection(encoder); 946 } 947 948 static void gen11_hpd_irq_setup(struct intel_display *display) 949 { 950 u32 hotplug_irqs, enabled_irqs; 951 952 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 953 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 954 955 intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs, 956 ~enabled_irqs & hotplug_irqs); 957 intel_de_posting_read(display, GEN11_DE_HPD_IMR); 958 959 gen11_tc_hpd_detection_setup(display); 960 gen11_tbt_hpd_detection_setup(display); 961 962 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 963 icp_hpd_irq_setup(display); 964 } 965 966 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 967 { 968 switch (hpd_pin) { 969 case HPD_PORT_A: 970 case HPD_PORT_B: 971 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 972 default: 973 return 0; 974 } 975 } 976 977 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder) 978 { 979 return mtp_ddi_hotplug_mask(encoder->hpd_pin); 980 } 981 982 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin) 983 { 984 switch (hpd_pin) { 985 case HPD_PORT_TC1: 986 case HPD_PORT_TC2: 987 case HPD_PORT_TC3: 988 case HPD_PORT_TC4: 989 return ICP_TC_HPD_ENABLE(hpd_pin); 990 default: 991 return 0; 992 } 993 } 994 995 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder) 996 { 997 return mtp_tc_hotplug_mask(encoder->hpd_pin); 998 } 999 1000 static void mtp_ddi_hpd_detection_setup(struct intel_display *display) 1001 { 1002 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1003 intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask), 1004 intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables)); 1005 } 1006 1007 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 1008 { 1009 struct intel_display *display = to_intel_display(encoder); 1010 1011 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1012 mtp_ddi_hotplug_mask(encoder->hpd_pin), 1013 mtp_ddi_hotplug_enables(encoder)); 1014 } 1015 1016 static void mtp_tc_hpd_detection_setup(struct intel_display *display) 1017 { 1018 intel_de_rmw(display, SHOTPLUG_CTL_TC, 1019 intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask), 1020 intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables)); 1021 } 1022 1023 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder) 1024 { 1025 struct intel_display *display = to_intel_display(encoder); 1026 1027 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1028 mtp_tc_hotplug_mask(encoder->hpd_pin), 1029 mtp_tc_hotplug_enables(encoder)); 1030 } 1031 1032 static void mtp_hpd_invert(struct intel_display *display) 1033 { 1034 u32 val = (INVERT_DDIA_HPD | 1035 INVERT_DDIB_HPD | 1036 INVERT_DDIC_HPD | 1037 INVERT_TC1_HPD | 1038 INVERT_TC2_HPD | 1039 INVERT_TC3_HPD | 1040 INVERT_TC4_HPD | 1041 INVERT_DDID_HPD_MTP | 1042 INVERT_DDIE_HPD); 1043 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 1044 } 1045 1046 static void mtp_hpd_enable_detection(struct intel_encoder *encoder) 1047 { 1048 struct intel_display *display = to_intel_display(encoder); 1049 1050 mtp_hpd_invert(display); 1051 mtp_ddi_hpd_enable_detection(encoder); 1052 mtp_tc_hpd_enable_detection(encoder); 1053 } 1054 1055 static void mtp_hpd_irq_setup(struct intel_display *display) 1056 { 1057 u32 hotplug_irqs, enabled_irqs; 1058 1059 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1060 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1061 1062 /* 1063 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the 1064 * SHPD_FILTER_CNT value should be. 1065 */ 1066 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 1067 1068 mtp_hpd_invert(display); 1069 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1070 1071 mtp_ddi_hpd_detection_setup(display); 1072 mtp_tc_hpd_detection_setup(display); 1073 } 1074 1075 static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display) 1076 { 1077 u32 hotplug_irqs, enabled_irqs; 1078 1079 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1080 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1081 1082 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1083 1084 mtp_ddi_hpd_detection_setup(display); 1085 mtp_tc_hpd_detection_setup(display); 1086 } 1087 1088 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin) 1089 { 1090 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4; 1091 } 1092 1093 static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display, 1094 enum hpd_pin hpd_pin, bool enable) 1095 { 1096 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE | 1097 XELPDP_DP_ALT_HOTPLUG_ENABLE; 1098 1099 if (!is_xelpdp_pica_hpd_pin(hpd_pin)) 1100 return; 1101 1102 intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1103 mask, enable ? mask : 0); 1104 } 1105 1106 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder) 1107 { 1108 struct intel_display *display = to_intel_display(encoder); 1109 1110 _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true); 1111 } 1112 1113 static void xelpdp_pica_hpd_detection_setup(struct intel_display *display) 1114 { 1115 struct intel_encoder *encoder; 1116 u32 available_pins = 0; 1117 enum hpd_pin pin; 1118 1119 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS); 1120 1121 for_each_intel_encoder(display->drm, encoder) 1122 available_pins |= BIT(encoder->hpd_pin); 1123 1124 for_each_hpd_pin(pin) 1125 _xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin)); 1126 } 1127 1128 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) 1129 { 1130 xelpdp_pica_hpd_enable_detection(encoder); 1131 mtp_hpd_enable_detection(encoder); 1132 } 1133 1134 static void xelpdp_hpd_irq_setup(struct intel_display *display) 1135 { 1136 u32 hotplug_irqs, enabled_irqs; 1137 1138 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1139 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1140 1141 intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs, 1142 ~enabled_irqs & hotplug_irqs); 1143 intel_de_posting_read(display, PICAINTERRUPT_IMR); 1144 1145 xelpdp_pica_hpd_detection_setup(display); 1146 1147 if (INTEL_PCH_TYPE(display) >= PCH_LNL) 1148 xe2lpd_sde_hpd_irq_setup(display); 1149 else if (INTEL_PCH_TYPE(display) >= PCH_MTL) 1150 mtp_hpd_irq_setup(display); 1151 } 1152 1153 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin) 1154 { 1155 switch (hpd_pin) { 1156 case HPD_PORT_A: 1157 return PORTA_HOTPLUG_ENABLE; 1158 case HPD_PORT_B: 1159 return PORTB_HOTPLUG_ENABLE; 1160 case HPD_PORT_C: 1161 return PORTC_HOTPLUG_ENABLE; 1162 case HPD_PORT_D: 1163 return PORTD_HOTPLUG_ENABLE; 1164 default: 1165 return 0; 1166 } 1167 } 1168 1169 static u32 spt_hotplug_enables(struct intel_encoder *encoder) 1170 { 1171 return spt_hotplug_mask(encoder->hpd_pin); 1172 } 1173 1174 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin) 1175 { 1176 switch (hpd_pin) { 1177 case HPD_PORT_E: 1178 return PORTE_HOTPLUG_ENABLE; 1179 default: 1180 return 0; 1181 } 1182 } 1183 1184 static u32 spt_hotplug2_enables(struct intel_encoder *encoder) 1185 { 1186 return spt_hotplug2_mask(encoder->hpd_pin); 1187 } 1188 1189 static void spt_hpd_detection_setup(struct intel_display *display) 1190 { 1191 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1192 if (HAS_PCH_CNP(display)) { 1193 intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, 1194 CHASSIS_CLK_REQ_DURATION(0xf)); 1195 } 1196 1197 /* Enable digital hotplug on the PCH */ 1198 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1199 intel_hpd_hotplug_mask(display, spt_hotplug_mask), 1200 intel_hpd_hotplug_enables(display, spt_hotplug_enables)); 1201 1202 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1203 intel_hpd_hotplug_mask(display, spt_hotplug2_mask), 1204 intel_hpd_hotplug_enables(display, spt_hotplug2_enables)); 1205 } 1206 1207 static void spt_hpd_enable_detection(struct intel_encoder *encoder) 1208 { 1209 struct intel_display *display = to_intel_display(encoder); 1210 1211 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1212 if (HAS_PCH_CNP(display)) { 1213 intel_de_rmw(display, SOUTH_CHICKEN1, 1214 CHASSIS_CLK_REQ_DURATION_MASK, 1215 CHASSIS_CLK_REQ_DURATION(0xf)); 1216 } 1217 1218 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1219 spt_hotplug_mask(encoder->hpd_pin), 1220 spt_hotplug_enables(encoder)); 1221 1222 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1223 spt_hotplug2_mask(encoder->hpd_pin), 1224 spt_hotplug2_enables(encoder)); 1225 } 1226 1227 static void spt_hpd_irq_setup(struct intel_display *display) 1228 { 1229 u32 hotplug_irqs, enabled_irqs; 1230 1231 if (INTEL_PCH_TYPE(display) >= PCH_CNP) 1232 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1233 1234 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1235 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1236 1237 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1238 1239 spt_hpd_detection_setup(display); 1240 } 1241 1242 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin) 1243 { 1244 switch (hpd_pin) { 1245 case HPD_PORT_A: 1246 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1247 DIGITAL_PORTA_PULSE_DURATION_MASK; 1248 default: 1249 return 0; 1250 } 1251 } 1252 1253 static u32 ilk_hotplug_enables(struct intel_encoder *encoder) 1254 { 1255 switch (encoder->hpd_pin) { 1256 case HPD_PORT_A: 1257 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1258 DIGITAL_PORTA_PULSE_DURATION_2ms; 1259 default: 1260 return 0; 1261 } 1262 } 1263 1264 static void ilk_hpd_detection_setup(struct intel_display *display) 1265 { 1266 /* 1267 * Enable digital hotplug on the CPU, and configure the DP short pulse 1268 * duration to 2ms (which is the minimum in the Display Port spec) 1269 * The pulse duration bits are reserved on HSW+. 1270 */ 1271 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1272 intel_hpd_hotplug_mask(display, ilk_hotplug_mask), 1273 intel_hpd_hotplug_enables(display, ilk_hotplug_enables)); 1274 } 1275 1276 static void ilk_hpd_enable_detection(struct intel_encoder *encoder) 1277 { 1278 struct intel_display *display = to_intel_display(encoder); 1279 1280 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1281 ilk_hotplug_mask(encoder->hpd_pin), 1282 ilk_hotplug_enables(encoder)); 1283 1284 ibx_hpd_enable_detection(encoder); 1285 } 1286 1287 static void ilk_hpd_irq_setup(struct intel_display *display) 1288 { 1289 u32 hotplug_irqs, enabled_irqs; 1290 1291 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1292 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1293 1294 if (DISPLAY_VER(display) >= 8) 1295 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1296 else 1297 ilk_update_display_irq(display, hotplug_irqs, enabled_irqs); 1298 1299 ilk_hpd_detection_setup(display); 1300 1301 ibx_hpd_irq_setup(display); 1302 } 1303 1304 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin) 1305 { 1306 switch (hpd_pin) { 1307 case HPD_PORT_A: 1308 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT; 1309 case HPD_PORT_B: 1310 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT; 1311 case HPD_PORT_C: 1312 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT; 1313 default: 1314 return 0; 1315 } 1316 } 1317 1318 static u32 bxt_hotplug_enables(struct intel_encoder *encoder) 1319 { 1320 u32 hotplug; 1321 1322 switch (encoder->hpd_pin) { 1323 case HPD_PORT_A: 1324 hotplug = PORTA_HOTPLUG_ENABLE; 1325 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1326 hotplug |= BXT_DDIA_HPD_INVERT; 1327 return hotplug; 1328 case HPD_PORT_B: 1329 hotplug = PORTB_HOTPLUG_ENABLE; 1330 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1331 hotplug |= BXT_DDIB_HPD_INVERT; 1332 return hotplug; 1333 case HPD_PORT_C: 1334 hotplug = PORTC_HOTPLUG_ENABLE; 1335 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1336 hotplug |= BXT_DDIC_HPD_INVERT; 1337 return hotplug; 1338 default: 1339 return 0; 1340 } 1341 } 1342 1343 static void bxt_hpd_detection_setup(struct intel_display *display) 1344 { 1345 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1346 intel_hpd_hotplug_mask(display, bxt_hotplug_mask), 1347 intel_hpd_hotplug_enables(display, bxt_hotplug_enables)); 1348 } 1349 1350 static void bxt_hpd_enable_detection(struct intel_encoder *encoder) 1351 { 1352 struct intel_display *display = to_intel_display(encoder); 1353 1354 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1355 bxt_hotplug_mask(encoder->hpd_pin), 1356 bxt_hotplug_enables(encoder)); 1357 } 1358 1359 static void bxt_hpd_irq_setup(struct intel_display *display) 1360 { 1361 u32 hotplug_irqs, enabled_irqs; 1362 1363 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1364 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1365 1366 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1367 1368 bxt_hpd_detection_setup(display); 1369 } 1370 1371 static void g45_hpd_peg_band_gap_wa(struct intel_display *display) 1372 { 1373 /* 1374 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1375 * 0xd. Failure to do so will result in spurious interrupts being 1376 * generated on the port when a cable is not attached. 1377 */ 1378 intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd); 1379 } 1380 1381 static void i915_hpd_enable_detection(struct intel_encoder *encoder) 1382 { 1383 struct intel_display *display = to_intel_display(encoder); 1384 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin]; 1385 1386 if (display->platform.g45) 1387 g45_hpd_peg_band_gap_wa(display); 1388 1389 /* HPD sense and interrupt enable are one and the same */ 1390 i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en); 1391 } 1392 1393 static void i915_hpd_irq_setup(struct intel_display *display) 1394 { 1395 u32 hotplug_en; 1396 1397 lockdep_assert_held(&display->irq.lock); 1398 1399 /* 1400 * Note HDMI and DP share hotplug bits. Enable bits are the same for all 1401 * generations. 1402 */ 1403 hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915); 1404 /* 1405 * Programming the CRT detection parameters tends to generate a spurious 1406 * hotplug event about three seconds later. So just do it once. 1407 */ 1408 if (display->platform.g4x) 1409 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1410 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1411 1412 if (display->platform.g45) 1413 g45_hpd_peg_band_gap_wa(display); 1414 1415 /* Ignore TV since it's buggy */ 1416 i915_hotplug_interrupt_update_locked(display, 1417 HOTPLUG_INT_EN_MASK | 1418 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 1419 CRT_HOTPLUG_ACTIVATION_PERIOD_64, 1420 hotplug_en); 1421 } 1422 1423 struct intel_hotplug_funcs { 1424 /* Enable HPD sense and interrupts for all present encoders */ 1425 void (*hpd_irq_setup)(struct intel_display *display); 1426 /* Enable HPD sense for a single encoder */ 1427 void (*hpd_enable_detection)(struct intel_encoder *encoder); 1428 }; 1429 1430 #define HPD_FUNCS(platform) \ 1431 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \ 1432 .hpd_irq_setup = platform##_hpd_irq_setup, \ 1433 .hpd_enable_detection = platform##_hpd_enable_detection, \ 1434 } 1435 1436 HPD_FUNCS(i915); 1437 HPD_FUNCS(xelpdp); 1438 HPD_FUNCS(dg1); 1439 HPD_FUNCS(gen11); 1440 HPD_FUNCS(bxt); 1441 HPD_FUNCS(icp); 1442 HPD_FUNCS(spt); 1443 HPD_FUNCS(ilk); 1444 #undef HPD_FUNCS 1445 1446 void intel_hpd_enable_detection(struct intel_encoder *encoder) 1447 { 1448 struct intel_display *display = to_intel_display(encoder); 1449 1450 if (display->funcs.hotplug) 1451 display->funcs.hotplug->hpd_enable_detection(encoder); 1452 } 1453 1454 void intel_hpd_irq_setup(struct intel_display *display) 1455 { 1456 if ((display->platform.valleyview || display->platform.cherryview) && 1457 !display->irq.vlv_display_irqs_enabled) 1458 return; 1459 1460 if (display->funcs.hotplug) 1461 display->funcs.hotplug->hpd_irq_setup(display); 1462 } 1463 1464 void intel_hotplug_irq_init(struct intel_display *display) 1465 { 1466 intel_hpd_init_pins(display); 1467 1468 intel_hpd_init_early(display); 1469 1470 if (HAS_GMCH(display)) { 1471 if (HAS_HOTPLUG(display)) 1472 display->funcs.hotplug = &i915_hpd_funcs; 1473 } else { 1474 if (HAS_PCH_DG2(display)) 1475 display->funcs.hotplug = &icp_hpd_funcs; 1476 else if (HAS_PCH_DG1(display)) 1477 display->funcs.hotplug = &dg1_hpd_funcs; 1478 else if (DISPLAY_VER(display) >= 14) 1479 display->funcs.hotplug = &xelpdp_hpd_funcs; 1480 else if (DISPLAY_VER(display) >= 11) 1481 display->funcs.hotplug = &gen11_hpd_funcs; 1482 else if (display->platform.geminilake || display->platform.broxton) 1483 display->funcs.hotplug = &bxt_hpd_funcs; 1484 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 1485 display->funcs.hotplug = &icp_hpd_funcs; 1486 else if (INTEL_PCH_TYPE(display) >= PCH_SPT) 1487 display->funcs.hotplug = &spt_hpd_funcs; 1488 else 1489 display->funcs.hotplug = &ilk_hpd_funcs; 1490 } 1491 } 1492