1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_print.h> 7 8 #include "i915_reg.h" 9 #include "i915_utils.h" 10 #include "intel_de.h" 11 #include "intel_display_irq.h" 12 #include "intel_display_regs.h" 13 #include "intel_display_types.h" 14 #include "intel_dp_aux.h" 15 #include "intel_gmbus.h" 16 #include "intel_hotplug.h" 17 #include "intel_hotplug_irq.h" 18 19 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 20 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder); 21 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin); 22 23 static const u32 hpd_ilk[HPD_NUM_PINS] = { 24 [HPD_PORT_A] = DE_DP_A_HOTPLUG, 25 }; 26 27 static const u32 hpd_ivb[HPD_NUM_PINS] = { 28 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 29 }; 30 31 static const u32 hpd_bdw[HPD_NUM_PINS] = { 32 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 33 }; 34 35 static const u32 hpd_ibx[HPD_NUM_PINS] = { 36 [HPD_CRT] = SDE_CRT_HOTPLUG, 37 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 38 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 39 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 40 [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 41 }; 42 43 static const u32 hpd_cpt[HPD_NUM_PINS] = { 44 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 45 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 46 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 47 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 48 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 49 }; 50 51 static const u32 hpd_spt[HPD_NUM_PINS] = { 52 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 53 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 54 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 55 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 56 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 57 }; 58 59 static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 60 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 61 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 62 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 63 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 64 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 65 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 66 }; 67 68 static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 69 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 70 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 71 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 72 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 73 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 74 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 75 }; 76 77 static const u32 hpd_status_i915[HPD_NUM_PINS] = { 78 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 79 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 80 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 81 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 82 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 83 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 84 }; 85 86 static const u32 hpd_bxt[HPD_NUM_PINS] = { 87 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 88 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 89 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 90 }; 91 92 static const u32 hpd_gen11[HPD_NUM_PINS] = { 93 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 94 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 95 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 96 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 97 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 98 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 99 }; 100 101 static const u32 hpd_xelpdp[HPD_NUM_PINS] = { 102 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1), 103 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2), 104 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3), 105 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4), 106 }; 107 108 static const u32 hpd_icp[HPD_NUM_PINS] = { 109 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 110 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 111 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 112 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 113 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 114 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 115 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 116 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 117 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 118 }; 119 120 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 121 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 122 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 123 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 124 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 125 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1), 126 }; 127 128 static const u32 hpd_mtp[HPD_NUM_PINS] = { 129 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 130 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 131 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 132 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 133 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 134 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 135 }; 136 137 static void intel_hpd_init_pins(struct intel_display *display) 138 { 139 struct intel_hotplug *hpd = &display->hotplug; 140 141 if (HAS_GMCH(display)) { 142 if (display->platform.g4x || display->platform.valleyview || 143 display->platform.cherryview) 144 hpd->hpd = hpd_status_g4x; 145 else 146 hpd->hpd = hpd_status_i915; 147 return; 148 } 149 150 if (DISPLAY_VER(display) >= 14) 151 hpd->hpd = hpd_xelpdp; 152 else if (DISPLAY_VER(display) >= 11) 153 hpd->hpd = hpd_gen11; 154 else if (display->platform.geminilake || display->platform.broxton) 155 hpd->hpd = hpd_bxt; 156 else if (DISPLAY_VER(display) == 9) 157 hpd->hpd = NULL; /* no north HPD on SKL */ 158 else if (DISPLAY_VER(display) >= 8) 159 hpd->hpd = hpd_bdw; 160 else if (DISPLAY_VER(display) >= 7) 161 hpd->hpd = hpd_ivb; 162 else 163 hpd->hpd = hpd_ilk; 164 165 if ((INTEL_PCH_TYPE(display) < PCH_DG1) && 166 (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display))) 167 return; 168 169 if (INTEL_PCH_TYPE(display) >= PCH_MTL) 170 hpd->pch_hpd = hpd_mtp; 171 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 172 hpd->pch_hpd = hpd_sde_dg1; 173 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 174 hpd->pch_hpd = hpd_icp; 175 else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display)) 176 hpd->pch_hpd = hpd_spt; 177 else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display)) 178 hpd->pch_hpd = hpd_cpt; 179 else if (HAS_PCH_IBX(display)) 180 hpd->pch_hpd = hpd_ibx; 181 else 182 MISSING_CASE(INTEL_PCH_TYPE(display)); 183 } 184 185 /* For display hotplug interrupt */ 186 void i915_hotplug_interrupt_update_locked(struct intel_display *display, 187 u32 mask, u32 bits) 188 { 189 lockdep_assert_held(&display->irq.lock); 190 drm_WARN_ON(display->drm, bits & ~mask); 191 192 intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); 193 } 194 195 /** 196 * i915_hotplug_interrupt_update - update hotplug interrupt enable 197 * @display: display device 198 * @mask: bits to update 199 * @bits: bits to enable 200 * NOTE: the HPD enable bits are modified both inside and outside 201 * of an interrupt context. To avoid that read-modify-write cycles 202 * interfere, these bits are protected by a spinlock. Since this 203 * function is usually not called from a context where the lock is 204 * held already, this function acquires the lock itself. A non-locking 205 * version is also available. 206 */ 207 void i915_hotplug_interrupt_update(struct intel_display *display, 208 u32 mask, 209 u32 bits) 210 { 211 spin_lock_irq(&display->irq.lock); 212 i915_hotplug_interrupt_update_locked(display, mask, bits); 213 spin_unlock_irq(&display->irq.lock); 214 } 215 216 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 217 { 218 switch (pin) { 219 case HPD_PORT_TC1: 220 case HPD_PORT_TC2: 221 case HPD_PORT_TC3: 222 case HPD_PORT_TC4: 223 case HPD_PORT_TC5: 224 case HPD_PORT_TC6: 225 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 226 default: 227 return false; 228 } 229 } 230 231 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 232 { 233 switch (pin) { 234 case HPD_PORT_A: 235 return val & PORTA_HOTPLUG_LONG_DETECT; 236 case HPD_PORT_B: 237 return val & PORTB_HOTPLUG_LONG_DETECT; 238 case HPD_PORT_C: 239 return val & PORTC_HOTPLUG_LONG_DETECT; 240 default: 241 return false; 242 } 243 } 244 245 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 246 { 247 switch (pin) { 248 case HPD_PORT_A: 249 case HPD_PORT_B: 250 case HPD_PORT_C: 251 case HPD_PORT_D: 252 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 253 default: 254 return false; 255 } 256 } 257 258 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 259 { 260 switch (pin) { 261 case HPD_PORT_TC1: 262 case HPD_PORT_TC2: 263 case HPD_PORT_TC3: 264 case HPD_PORT_TC4: 265 case HPD_PORT_TC5: 266 case HPD_PORT_TC6: 267 return val & ICP_TC_HPD_LONG_DETECT(pin); 268 default: 269 return false; 270 } 271 } 272 273 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 274 { 275 switch (pin) { 276 case HPD_PORT_E: 277 return val & PORTE_HOTPLUG_LONG_DETECT; 278 default: 279 return false; 280 } 281 } 282 283 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 284 { 285 switch (pin) { 286 case HPD_PORT_A: 287 return val & PORTA_HOTPLUG_LONG_DETECT; 288 case HPD_PORT_B: 289 return val & PORTB_HOTPLUG_LONG_DETECT; 290 case HPD_PORT_C: 291 return val & PORTC_HOTPLUG_LONG_DETECT; 292 case HPD_PORT_D: 293 return val & PORTD_HOTPLUG_LONG_DETECT; 294 default: 295 return false; 296 } 297 } 298 299 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 300 { 301 switch (pin) { 302 case HPD_PORT_A: 303 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 304 default: 305 return false; 306 } 307 } 308 309 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 310 { 311 switch (pin) { 312 case HPD_PORT_B: 313 return val & PORTB_HOTPLUG_LONG_DETECT; 314 case HPD_PORT_C: 315 return val & PORTC_HOTPLUG_LONG_DETECT; 316 case HPD_PORT_D: 317 return val & PORTD_HOTPLUG_LONG_DETECT; 318 default: 319 return false; 320 } 321 } 322 323 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 324 { 325 switch (pin) { 326 case HPD_PORT_B: 327 return val & PORTB_HOTPLUG_INT_LONG_PULSE; 328 case HPD_PORT_C: 329 return val & PORTC_HOTPLUG_INT_LONG_PULSE; 330 case HPD_PORT_D: 331 return val & PORTD_HOTPLUG_INT_LONG_PULSE; 332 default: 333 return false; 334 } 335 } 336 337 /* 338 * Get a bit mask of pins that have triggered, and which ones may be long. 339 * This can be called multiple times with the same masks to accumulate 340 * hotplug detection results from several registers. 341 * 342 * Note that the caller is expected to zero out the masks initially. 343 */ 344 static void intel_get_hpd_pins(struct intel_display *display, 345 u32 *pin_mask, u32 *long_mask, 346 u32 hotplug_trigger, u32 dig_hotplug_reg, 347 const u32 hpd[HPD_NUM_PINS], 348 bool long_pulse_detect(enum hpd_pin pin, u32 val)) 349 { 350 enum hpd_pin pin; 351 352 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 353 354 for_each_hpd_pin(pin) { 355 if ((hpd[pin] & hotplug_trigger) == 0) 356 continue; 357 358 *pin_mask |= BIT(pin); 359 360 if (long_pulse_detect(pin, dig_hotplug_reg)) 361 *long_mask |= BIT(pin); 362 } 363 364 drm_dbg_kms(display->drm, 365 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 366 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 367 } 368 369 static u32 intel_hpd_enabled_irqs(struct intel_display *display, 370 const u32 hpd[HPD_NUM_PINS]) 371 { 372 struct intel_encoder *encoder; 373 u32 enabled_irqs = 0; 374 375 for_each_intel_encoder(display->drm, encoder) 376 if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 377 enabled_irqs |= hpd[encoder->hpd_pin]; 378 379 return enabled_irqs; 380 } 381 382 static u32 intel_hpd_hotplug_irqs(struct intel_display *display, 383 const u32 hpd[HPD_NUM_PINS]) 384 { 385 struct intel_encoder *encoder; 386 u32 hotplug_irqs = 0; 387 388 for_each_intel_encoder(display->drm, encoder) 389 hotplug_irqs |= hpd[encoder->hpd_pin]; 390 391 return hotplug_irqs; 392 } 393 394 static u32 intel_hpd_hotplug_mask(struct intel_display *display, 395 hotplug_mask_func hotplug_mask) 396 { 397 enum hpd_pin pin; 398 u32 hotplug = 0; 399 400 for_each_hpd_pin(pin) 401 hotplug |= hotplug_mask(pin); 402 403 return hotplug; 404 } 405 406 static u32 intel_hpd_hotplug_enables(struct intel_display *display, 407 hotplug_enables_func hotplug_enables) 408 { 409 struct intel_encoder *encoder; 410 u32 hotplug = 0; 411 412 for_each_intel_encoder(display->drm, encoder) 413 hotplug |= hotplug_enables(encoder); 414 415 return hotplug; 416 } 417 418 u32 i9xx_hpd_irq_ack(struct intel_display *display) 419 { 420 u32 hotplug_status = 0, hotplug_status_mask; 421 int i; 422 423 if (display->platform.g4x || 424 display->platform.valleyview || display->platform.cherryview) 425 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 426 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 427 else 428 hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 429 430 /* 431 * We absolutely have to clear all the pending interrupt 432 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 433 * interrupt bit won't have an edge, and the i965/g4x 434 * edge triggered IIR will not notice that an interrupt 435 * is still pending. We can't use PORT_HOTPLUG_EN to 436 * guarantee the edge as the act of toggling the enable 437 * bits can itself generate a new hotplug interrupt :( 438 */ 439 for (i = 0; i < 10; i++) { 440 u32 tmp = intel_de_read(display, 441 PORT_HOTPLUG_STAT(display)) & hotplug_status_mask; 442 443 if (tmp == 0) 444 return hotplug_status; 445 446 hotplug_status |= tmp; 447 intel_de_write(display, PORT_HOTPLUG_STAT(display), 448 hotplug_status); 449 } 450 451 drm_WARN_ONCE(display->drm, 1, 452 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 453 intel_de_read(display, PORT_HOTPLUG_STAT(display))); 454 455 return hotplug_status; 456 } 457 458 void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status) 459 { 460 u32 pin_mask = 0, long_mask = 0; 461 u32 hotplug_trigger; 462 463 if (display->platform.g4x || 464 display->platform.valleyview || display->platform.cherryview) 465 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 466 else 467 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 468 469 if (hotplug_trigger) { 470 intel_get_hpd_pins(display, &pin_mask, &long_mask, 471 hotplug_trigger, hotplug_trigger, 472 display->hotplug.hpd, 473 i9xx_port_hotplug_long_detect); 474 475 intel_hpd_irq_handler(display, pin_mask, long_mask); 476 } 477 478 if ((display->platform.g4x || 479 display->platform.valleyview || display->platform.cherryview) && 480 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 481 intel_dp_aux_irq_handler(display); 482 } 483 484 void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 485 { 486 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 487 488 /* 489 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 490 * unless we touch the hotplug register, even if hotplug_trigger is 491 * zero. Not acking leads to "The master control interrupt lied (SDE)!" 492 * errors. 493 */ 494 dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG); 495 if (!hotplug_trigger) { 496 u32 mask = PORTA_HOTPLUG_STATUS_MASK | 497 PORTD_HOTPLUG_STATUS_MASK | 498 PORTC_HOTPLUG_STATUS_MASK | 499 PORTB_HOTPLUG_STATUS_MASK; 500 dig_hotplug_reg &= ~mask; 501 } 502 503 intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg); 504 if (!hotplug_trigger) 505 return; 506 507 intel_get_hpd_pins(display, &pin_mask, &long_mask, 508 hotplug_trigger, dig_hotplug_reg, 509 display->hotplug.pch_hpd, 510 pch_port_hotplug_long_detect); 511 512 intel_hpd_irq_handler(display, pin_mask, long_mask); 513 } 514 515 void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) 516 { 517 enum hpd_pin pin; 518 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 519 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 520 u32 pin_mask = 0, long_mask = 0; 521 522 if (DISPLAY_VER(display) >= 20) 523 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; 524 525 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 526 u32 val; 527 528 if (!(display->hotplug.hpd[pin] & hotplug_trigger)) 529 continue; 530 531 pin_mask |= BIT(pin); 532 533 val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin)); 534 intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val); 535 536 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT)) 537 long_mask |= BIT(pin); 538 } 539 540 if (pin_mask) { 541 drm_dbg_kms(display->drm, 542 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 543 hotplug_trigger, pin_mask, long_mask); 544 545 intel_hpd_irq_handler(display, pin_mask, long_mask); 546 } 547 548 if (trigger_aux) 549 intel_dp_aux_irq_handler(display); 550 551 if (!pin_mask && !trigger_aux) 552 drm_err(display->drm, 553 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir); 554 } 555 556 void icp_irq_handler(struct intel_display *display, u32 pch_iir) 557 { 558 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 559 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 560 u32 pin_mask = 0, long_mask = 0; 561 562 if (ddi_hotplug_trigger) { 563 u32 dig_hotplug_reg; 564 565 /* Locking due to DSI native GPIO sequences */ 566 spin_lock(&display->irq.lock); 567 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0); 568 spin_unlock(&display->irq.lock); 569 570 intel_get_hpd_pins(display, &pin_mask, &long_mask, 571 ddi_hotplug_trigger, dig_hotplug_reg, 572 display->hotplug.pch_hpd, 573 icp_ddi_port_hotplug_long_detect); 574 } 575 576 if (tc_hotplug_trigger) { 577 u32 dig_hotplug_reg; 578 579 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0); 580 581 intel_get_hpd_pins(display, &pin_mask, &long_mask, 582 tc_hotplug_trigger, dig_hotplug_reg, 583 display->hotplug.pch_hpd, 584 icp_tc_port_hotplug_long_detect); 585 } 586 587 if (pin_mask) 588 intel_hpd_irq_handler(display, pin_mask, long_mask); 589 590 if (pch_iir & SDE_GMBUS_ICP) 591 intel_gmbus_irq_handler(display); 592 } 593 594 void spt_irq_handler(struct intel_display *display, u32 pch_iir) 595 { 596 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 597 ~SDE_PORTE_HOTPLUG_SPT; 598 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 599 u32 pin_mask = 0, long_mask = 0; 600 601 if (hotplug_trigger) { 602 u32 dig_hotplug_reg; 603 604 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 605 606 intel_get_hpd_pins(display, &pin_mask, &long_mask, 607 hotplug_trigger, dig_hotplug_reg, 608 display->hotplug.pch_hpd, 609 spt_port_hotplug_long_detect); 610 } 611 612 if (hotplug2_trigger) { 613 u32 dig_hotplug_reg; 614 615 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0); 616 617 intel_get_hpd_pins(display, &pin_mask, &long_mask, 618 hotplug2_trigger, dig_hotplug_reg, 619 display->hotplug.pch_hpd, 620 spt_port_hotplug2_long_detect); 621 } 622 623 if (pin_mask) 624 intel_hpd_irq_handler(display, pin_mask, long_mask); 625 626 if (pch_iir & SDE_GMBUS_CPT) 627 intel_gmbus_irq_handler(display); 628 } 629 630 void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 631 { 632 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 633 634 dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0); 635 636 intel_get_hpd_pins(display, &pin_mask, &long_mask, 637 hotplug_trigger, dig_hotplug_reg, 638 display->hotplug.hpd, 639 ilk_port_hotplug_long_detect); 640 641 intel_hpd_irq_handler(display, pin_mask, long_mask); 642 } 643 644 void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 645 { 646 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 647 648 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 649 650 intel_get_hpd_pins(display, &pin_mask, &long_mask, 651 hotplug_trigger, dig_hotplug_reg, 652 display->hotplug.hpd, 653 bxt_port_hotplug_long_detect); 654 655 intel_hpd_irq_handler(display, pin_mask, long_mask); 656 } 657 658 void gen11_hpd_irq_handler(struct intel_display *display, u32 iir) 659 { 660 u32 pin_mask = 0, long_mask = 0; 661 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 662 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 663 664 if (trigger_tc) { 665 u32 dig_hotplug_reg; 666 667 dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0); 668 669 intel_get_hpd_pins(display, &pin_mask, &long_mask, 670 trigger_tc, dig_hotplug_reg, 671 display->hotplug.hpd, 672 gen11_port_hotplug_long_detect); 673 } 674 675 if (trigger_tbt) { 676 u32 dig_hotplug_reg; 677 678 dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0); 679 680 intel_get_hpd_pins(display, &pin_mask, &long_mask, 681 trigger_tbt, dig_hotplug_reg, 682 display->hotplug.hpd, 683 gen11_port_hotplug_long_detect); 684 } 685 686 if (pin_mask) 687 intel_hpd_irq_handler(display, pin_mask, long_mask); 688 else 689 drm_err(display->drm, 690 "Unexpected DE HPD interrupt 0x%08x\n", iir); 691 } 692 693 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin) 694 { 695 switch (hpd_pin) { 696 case HPD_PORT_A: 697 return PORTA_HOTPLUG_ENABLE; 698 case HPD_PORT_B: 699 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK; 700 case HPD_PORT_C: 701 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK; 702 case HPD_PORT_D: 703 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK; 704 default: 705 return 0; 706 } 707 } 708 709 static u32 ibx_hotplug_enables(struct intel_encoder *encoder) 710 { 711 struct intel_display *display = to_intel_display(encoder); 712 713 switch (encoder->hpd_pin) { 714 case HPD_PORT_A: 715 /* 716 * When CPU and PCH are on the same package, port A 717 * HPD must be enabled in both north and south. 718 */ 719 return HAS_PCH_LPT_LP(display) ? 720 PORTA_HOTPLUG_ENABLE : 0; 721 case HPD_PORT_B: 722 return PORTB_HOTPLUG_ENABLE | 723 PORTB_PULSE_DURATION_2ms; 724 case HPD_PORT_C: 725 return PORTC_HOTPLUG_ENABLE | 726 PORTC_PULSE_DURATION_2ms; 727 case HPD_PORT_D: 728 return PORTD_HOTPLUG_ENABLE | 729 PORTD_PULSE_DURATION_2ms; 730 default: 731 return 0; 732 } 733 } 734 735 static void ibx_hpd_detection_setup(struct intel_display *display) 736 { 737 /* 738 * Enable digital hotplug on the PCH, and configure the DP short pulse 739 * duration to 2ms (which is the minimum in the Display Port spec). 740 * The pulse duration bits are reserved on LPT+. 741 */ 742 intel_de_rmw(display, PCH_PORT_HOTPLUG, 743 intel_hpd_hotplug_mask(display, ibx_hotplug_mask), 744 intel_hpd_hotplug_enables(display, ibx_hotplug_enables)); 745 } 746 747 static void ibx_hpd_enable_detection(struct intel_encoder *encoder) 748 { 749 struct intel_display *display = to_intel_display(encoder); 750 751 intel_de_rmw(display, PCH_PORT_HOTPLUG, 752 ibx_hotplug_mask(encoder->hpd_pin), 753 ibx_hotplug_enables(encoder)); 754 } 755 756 static void ibx_hpd_irq_setup(struct intel_display *display) 757 { 758 u32 hotplug_irqs, enabled_irqs; 759 760 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 761 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 762 763 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 764 765 ibx_hpd_detection_setup(display); 766 } 767 768 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 769 { 770 switch (hpd_pin) { 771 case HPD_PORT_A: 772 case HPD_PORT_B: 773 case HPD_PORT_C: 774 case HPD_PORT_D: 775 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 776 default: 777 return 0; 778 } 779 } 780 781 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder) 782 { 783 return icp_ddi_hotplug_mask(encoder->hpd_pin); 784 } 785 786 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin) 787 { 788 switch (hpd_pin) { 789 case HPD_PORT_TC1: 790 case HPD_PORT_TC2: 791 case HPD_PORT_TC3: 792 case HPD_PORT_TC4: 793 case HPD_PORT_TC5: 794 case HPD_PORT_TC6: 795 return ICP_TC_HPD_ENABLE(hpd_pin); 796 default: 797 return 0; 798 } 799 } 800 801 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder) 802 { 803 return icp_tc_hotplug_mask(encoder->hpd_pin); 804 } 805 806 static void icp_ddi_hpd_detection_setup(struct intel_display *display) 807 { 808 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 809 intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask), 810 intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables)); 811 } 812 813 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 814 { 815 struct intel_display *display = to_intel_display(encoder); 816 817 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 818 icp_ddi_hotplug_mask(encoder->hpd_pin), 819 icp_ddi_hotplug_enables(encoder)); 820 } 821 822 static void icp_tc_hpd_detection_setup(struct intel_display *display) 823 { 824 intel_de_rmw(display, SHOTPLUG_CTL_TC, 825 intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask), 826 intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables)); 827 } 828 829 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) 830 { 831 struct intel_display *display = to_intel_display(encoder); 832 833 intel_de_rmw(display, SHOTPLUG_CTL_TC, 834 icp_tc_hotplug_mask(encoder->hpd_pin), 835 icp_tc_hotplug_enables(encoder)); 836 } 837 838 static void icp_hpd_enable_detection(struct intel_encoder *encoder) 839 { 840 icp_ddi_hpd_enable_detection(encoder); 841 icp_tc_hpd_enable_detection(encoder); 842 } 843 844 static void icp_hpd_irq_setup(struct intel_display *display) 845 { 846 u32 hotplug_irqs, enabled_irqs; 847 848 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 849 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 850 851 /* 852 * We reduce the value to 250us to be able to detect SHPD when an external display 853 * is connected. This is also expected of us as stated in DP1.4a Table 3-4. 854 */ 855 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 856 857 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 858 859 icp_ddi_hpd_detection_setup(display); 860 icp_tc_hpd_detection_setup(display); 861 } 862 863 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin) 864 { 865 switch (hpd_pin) { 866 case HPD_PORT_TC1: 867 case HPD_PORT_TC2: 868 case HPD_PORT_TC3: 869 case HPD_PORT_TC4: 870 case HPD_PORT_TC5: 871 case HPD_PORT_TC6: 872 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin); 873 default: 874 return 0; 875 } 876 } 877 878 static u32 gen11_hotplug_enables(struct intel_encoder *encoder) 879 { 880 return gen11_hotplug_mask(encoder->hpd_pin); 881 } 882 883 static void dg1_hpd_invert(struct intel_display *display) 884 { 885 u32 val = (INVERT_DDIA_HPD | 886 INVERT_DDIB_HPD | 887 INVERT_DDIC_HPD | 888 INVERT_DDID_HPD); 889 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 890 } 891 892 static void dg1_hpd_enable_detection(struct intel_encoder *encoder) 893 { 894 struct intel_display *display = to_intel_display(encoder); 895 896 dg1_hpd_invert(display); 897 icp_hpd_enable_detection(encoder); 898 } 899 900 static void dg1_hpd_irq_setup(struct intel_display *display) 901 { 902 dg1_hpd_invert(display); 903 icp_hpd_irq_setup(display); 904 } 905 906 static void gen11_tc_hpd_detection_setup(struct intel_display *display) 907 { 908 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 909 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 910 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 911 } 912 913 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) 914 { 915 struct intel_display *display = to_intel_display(encoder); 916 917 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 918 gen11_hotplug_mask(encoder->hpd_pin), 919 gen11_hotplug_enables(encoder)); 920 } 921 922 static void gen11_tbt_hpd_detection_setup(struct intel_display *display) 923 { 924 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 925 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 926 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 927 } 928 929 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) 930 { 931 struct intel_display *display = to_intel_display(encoder); 932 933 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 934 gen11_hotplug_mask(encoder->hpd_pin), 935 gen11_hotplug_enables(encoder)); 936 } 937 938 static void gen11_hpd_enable_detection(struct intel_encoder *encoder) 939 { 940 struct intel_display *display = to_intel_display(encoder); 941 942 gen11_tc_hpd_enable_detection(encoder); 943 gen11_tbt_hpd_enable_detection(encoder); 944 945 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 946 icp_hpd_enable_detection(encoder); 947 } 948 949 static void gen11_hpd_irq_setup(struct intel_display *display) 950 { 951 u32 hotplug_irqs, enabled_irqs; 952 953 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 954 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 955 956 intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs, 957 ~enabled_irqs & hotplug_irqs); 958 intel_de_posting_read(display, GEN11_DE_HPD_IMR); 959 960 gen11_tc_hpd_detection_setup(display); 961 gen11_tbt_hpd_detection_setup(display); 962 963 if (INTEL_PCH_TYPE(display) >= PCH_ICP) 964 icp_hpd_irq_setup(display); 965 } 966 967 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 968 { 969 switch (hpd_pin) { 970 case HPD_PORT_A: 971 case HPD_PORT_B: 972 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 973 default: 974 return 0; 975 } 976 } 977 978 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder) 979 { 980 return mtp_ddi_hotplug_mask(encoder->hpd_pin); 981 } 982 983 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin) 984 { 985 switch (hpd_pin) { 986 case HPD_PORT_TC1: 987 case HPD_PORT_TC2: 988 case HPD_PORT_TC3: 989 case HPD_PORT_TC4: 990 return ICP_TC_HPD_ENABLE(hpd_pin); 991 default: 992 return 0; 993 } 994 } 995 996 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder) 997 { 998 return mtp_tc_hotplug_mask(encoder->hpd_pin); 999 } 1000 1001 static void mtp_ddi_hpd_detection_setup(struct intel_display *display) 1002 { 1003 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1004 intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask), 1005 intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables)); 1006 } 1007 1008 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 1009 { 1010 struct intel_display *display = to_intel_display(encoder); 1011 1012 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1013 mtp_ddi_hotplug_mask(encoder->hpd_pin), 1014 mtp_ddi_hotplug_enables(encoder)); 1015 } 1016 1017 static void mtp_tc_hpd_detection_setup(struct intel_display *display) 1018 { 1019 intel_de_rmw(display, SHOTPLUG_CTL_TC, 1020 intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask), 1021 intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables)); 1022 } 1023 1024 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder) 1025 { 1026 struct intel_display *display = to_intel_display(encoder); 1027 1028 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1029 mtp_tc_hotplug_mask(encoder->hpd_pin), 1030 mtp_tc_hotplug_enables(encoder)); 1031 } 1032 1033 static void mtp_hpd_invert(struct intel_display *display) 1034 { 1035 u32 val = (INVERT_DDIA_HPD | 1036 INVERT_DDIB_HPD | 1037 INVERT_DDIC_HPD | 1038 INVERT_TC1_HPD | 1039 INVERT_TC2_HPD | 1040 INVERT_TC3_HPD | 1041 INVERT_TC4_HPD | 1042 INVERT_DDID_HPD_MTP | 1043 INVERT_DDIE_HPD); 1044 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 1045 } 1046 1047 static void mtp_hpd_enable_detection(struct intel_encoder *encoder) 1048 { 1049 struct intel_display *display = to_intel_display(encoder); 1050 1051 mtp_hpd_invert(display); 1052 mtp_ddi_hpd_enable_detection(encoder); 1053 mtp_tc_hpd_enable_detection(encoder); 1054 } 1055 1056 static void mtp_hpd_irq_setup(struct intel_display *display) 1057 { 1058 u32 hotplug_irqs, enabled_irqs; 1059 1060 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1061 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1062 1063 /* 1064 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the 1065 * SHPD_FILTER_CNT value should be. 1066 */ 1067 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 1068 1069 mtp_hpd_invert(display); 1070 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1071 1072 mtp_ddi_hpd_detection_setup(display); 1073 mtp_tc_hpd_detection_setup(display); 1074 } 1075 1076 static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display) 1077 { 1078 u32 hotplug_irqs, enabled_irqs; 1079 1080 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1081 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1082 1083 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1084 1085 mtp_ddi_hpd_detection_setup(display); 1086 mtp_tc_hpd_detection_setup(display); 1087 } 1088 1089 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin) 1090 { 1091 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4; 1092 } 1093 1094 static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display, 1095 enum hpd_pin hpd_pin, bool enable) 1096 { 1097 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE | 1098 XELPDP_DP_ALT_HOTPLUG_ENABLE; 1099 1100 if (!is_xelpdp_pica_hpd_pin(hpd_pin)) 1101 return; 1102 1103 intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1104 mask, enable ? mask : 0); 1105 } 1106 1107 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder) 1108 { 1109 struct intel_display *display = to_intel_display(encoder); 1110 1111 _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true); 1112 } 1113 1114 static void xelpdp_pica_hpd_detection_setup(struct intel_display *display) 1115 { 1116 struct intel_encoder *encoder; 1117 u32 available_pins = 0; 1118 enum hpd_pin pin; 1119 1120 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS); 1121 1122 for_each_intel_encoder(display->drm, encoder) 1123 available_pins |= BIT(encoder->hpd_pin); 1124 1125 for_each_hpd_pin(pin) 1126 _xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin)); 1127 } 1128 1129 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) 1130 { 1131 xelpdp_pica_hpd_enable_detection(encoder); 1132 mtp_hpd_enable_detection(encoder); 1133 } 1134 1135 static void xelpdp_hpd_irq_setup(struct intel_display *display) 1136 { 1137 u32 hotplug_irqs, enabled_irqs; 1138 1139 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1140 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1141 1142 intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs, 1143 ~enabled_irqs & hotplug_irqs); 1144 intel_de_posting_read(display, PICAINTERRUPT_IMR); 1145 1146 xelpdp_pica_hpd_detection_setup(display); 1147 1148 if (INTEL_PCH_TYPE(display) >= PCH_LNL) 1149 xe2lpd_sde_hpd_irq_setup(display); 1150 else if (INTEL_PCH_TYPE(display) >= PCH_MTL) 1151 mtp_hpd_irq_setup(display); 1152 } 1153 1154 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin) 1155 { 1156 switch (hpd_pin) { 1157 case HPD_PORT_A: 1158 return PORTA_HOTPLUG_ENABLE; 1159 case HPD_PORT_B: 1160 return PORTB_HOTPLUG_ENABLE; 1161 case HPD_PORT_C: 1162 return PORTC_HOTPLUG_ENABLE; 1163 case HPD_PORT_D: 1164 return PORTD_HOTPLUG_ENABLE; 1165 default: 1166 return 0; 1167 } 1168 } 1169 1170 static u32 spt_hotplug_enables(struct intel_encoder *encoder) 1171 { 1172 return spt_hotplug_mask(encoder->hpd_pin); 1173 } 1174 1175 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin) 1176 { 1177 switch (hpd_pin) { 1178 case HPD_PORT_E: 1179 return PORTE_HOTPLUG_ENABLE; 1180 default: 1181 return 0; 1182 } 1183 } 1184 1185 static u32 spt_hotplug2_enables(struct intel_encoder *encoder) 1186 { 1187 return spt_hotplug2_mask(encoder->hpd_pin); 1188 } 1189 1190 static void spt_hpd_detection_setup(struct intel_display *display) 1191 { 1192 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1193 if (HAS_PCH_CNP(display)) { 1194 intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, 1195 CHASSIS_CLK_REQ_DURATION(0xf)); 1196 } 1197 1198 /* Enable digital hotplug on the PCH */ 1199 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1200 intel_hpd_hotplug_mask(display, spt_hotplug_mask), 1201 intel_hpd_hotplug_enables(display, spt_hotplug_enables)); 1202 1203 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1204 intel_hpd_hotplug_mask(display, spt_hotplug2_mask), 1205 intel_hpd_hotplug_enables(display, spt_hotplug2_enables)); 1206 } 1207 1208 static void spt_hpd_enable_detection(struct intel_encoder *encoder) 1209 { 1210 struct intel_display *display = to_intel_display(encoder); 1211 1212 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1213 if (HAS_PCH_CNP(display)) { 1214 intel_de_rmw(display, SOUTH_CHICKEN1, 1215 CHASSIS_CLK_REQ_DURATION_MASK, 1216 CHASSIS_CLK_REQ_DURATION(0xf)); 1217 } 1218 1219 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1220 spt_hotplug_mask(encoder->hpd_pin), 1221 spt_hotplug_enables(encoder)); 1222 1223 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1224 spt_hotplug2_mask(encoder->hpd_pin), 1225 spt_hotplug2_enables(encoder)); 1226 } 1227 1228 static void spt_hpd_irq_setup(struct intel_display *display) 1229 { 1230 u32 hotplug_irqs, enabled_irqs; 1231 1232 if (INTEL_PCH_TYPE(display) >= PCH_CNP) 1233 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1234 1235 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1236 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1237 1238 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1239 1240 spt_hpd_detection_setup(display); 1241 } 1242 1243 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin) 1244 { 1245 switch (hpd_pin) { 1246 case HPD_PORT_A: 1247 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1248 DIGITAL_PORTA_PULSE_DURATION_MASK; 1249 default: 1250 return 0; 1251 } 1252 } 1253 1254 static u32 ilk_hotplug_enables(struct intel_encoder *encoder) 1255 { 1256 switch (encoder->hpd_pin) { 1257 case HPD_PORT_A: 1258 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1259 DIGITAL_PORTA_PULSE_DURATION_2ms; 1260 default: 1261 return 0; 1262 } 1263 } 1264 1265 static void ilk_hpd_detection_setup(struct intel_display *display) 1266 { 1267 /* 1268 * Enable digital hotplug on the CPU, and configure the DP short pulse 1269 * duration to 2ms (which is the minimum in the Display Port spec) 1270 * The pulse duration bits are reserved on HSW+. 1271 */ 1272 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1273 intel_hpd_hotplug_mask(display, ilk_hotplug_mask), 1274 intel_hpd_hotplug_enables(display, ilk_hotplug_enables)); 1275 } 1276 1277 static void ilk_hpd_enable_detection(struct intel_encoder *encoder) 1278 { 1279 struct intel_display *display = to_intel_display(encoder); 1280 1281 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1282 ilk_hotplug_mask(encoder->hpd_pin), 1283 ilk_hotplug_enables(encoder)); 1284 1285 ibx_hpd_enable_detection(encoder); 1286 } 1287 1288 static void ilk_hpd_irq_setup(struct intel_display *display) 1289 { 1290 u32 hotplug_irqs, enabled_irqs; 1291 1292 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1293 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1294 1295 if (DISPLAY_VER(display) >= 8) 1296 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1297 else 1298 ilk_update_display_irq(display, hotplug_irqs, enabled_irqs); 1299 1300 ilk_hpd_detection_setup(display); 1301 1302 ibx_hpd_irq_setup(display); 1303 } 1304 1305 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin) 1306 { 1307 switch (hpd_pin) { 1308 case HPD_PORT_A: 1309 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT; 1310 case HPD_PORT_B: 1311 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT; 1312 case HPD_PORT_C: 1313 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT; 1314 default: 1315 return 0; 1316 } 1317 } 1318 1319 static u32 bxt_hotplug_enables(struct intel_encoder *encoder) 1320 { 1321 u32 hotplug; 1322 1323 switch (encoder->hpd_pin) { 1324 case HPD_PORT_A: 1325 hotplug = PORTA_HOTPLUG_ENABLE; 1326 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1327 hotplug |= BXT_DDIA_HPD_INVERT; 1328 return hotplug; 1329 case HPD_PORT_B: 1330 hotplug = PORTB_HOTPLUG_ENABLE; 1331 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1332 hotplug |= BXT_DDIB_HPD_INVERT; 1333 return hotplug; 1334 case HPD_PORT_C: 1335 hotplug = PORTC_HOTPLUG_ENABLE; 1336 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1337 hotplug |= BXT_DDIC_HPD_INVERT; 1338 return hotplug; 1339 default: 1340 return 0; 1341 } 1342 } 1343 1344 static void bxt_hpd_detection_setup(struct intel_display *display) 1345 { 1346 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1347 intel_hpd_hotplug_mask(display, bxt_hotplug_mask), 1348 intel_hpd_hotplug_enables(display, bxt_hotplug_enables)); 1349 } 1350 1351 static void bxt_hpd_enable_detection(struct intel_encoder *encoder) 1352 { 1353 struct intel_display *display = to_intel_display(encoder); 1354 1355 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1356 bxt_hotplug_mask(encoder->hpd_pin), 1357 bxt_hotplug_enables(encoder)); 1358 } 1359 1360 static void bxt_hpd_irq_setup(struct intel_display *display) 1361 { 1362 u32 hotplug_irqs, enabled_irqs; 1363 1364 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1365 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1366 1367 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1368 1369 bxt_hpd_detection_setup(display); 1370 } 1371 1372 static void g45_hpd_peg_band_gap_wa(struct intel_display *display) 1373 { 1374 /* 1375 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1376 * 0xd. Failure to do so will result in spurious interrupts being 1377 * generated on the port when a cable is not attached. 1378 */ 1379 intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd); 1380 } 1381 1382 static void i915_hpd_enable_detection(struct intel_encoder *encoder) 1383 { 1384 struct intel_display *display = to_intel_display(encoder); 1385 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin]; 1386 1387 if (display->platform.g45) 1388 g45_hpd_peg_band_gap_wa(display); 1389 1390 /* HPD sense and interrupt enable are one and the same */ 1391 i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en); 1392 } 1393 1394 static void i915_hpd_irq_setup(struct intel_display *display) 1395 { 1396 u32 hotplug_en; 1397 1398 lockdep_assert_held(&display->irq.lock); 1399 1400 /* 1401 * Note HDMI and DP share hotplug bits. Enable bits are the same for all 1402 * generations. 1403 */ 1404 hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915); 1405 /* 1406 * Programming the CRT detection parameters tends to generate a spurious 1407 * hotplug event about three seconds later. So just do it once. 1408 */ 1409 if (display->platform.g4x) 1410 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1411 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1412 1413 if (display->platform.g45) 1414 g45_hpd_peg_band_gap_wa(display); 1415 1416 /* Ignore TV since it's buggy */ 1417 i915_hotplug_interrupt_update_locked(display, 1418 HOTPLUG_INT_EN_MASK | 1419 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 1420 CRT_HOTPLUG_ACTIVATION_PERIOD_64, 1421 hotplug_en); 1422 } 1423 1424 struct intel_hotplug_funcs { 1425 /* Enable HPD sense and interrupts for all present encoders */ 1426 void (*hpd_irq_setup)(struct intel_display *display); 1427 /* Enable HPD sense for a single encoder */ 1428 void (*hpd_enable_detection)(struct intel_encoder *encoder); 1429 }; 1430 1431 #define HPD_FUNCS(platform) \ 1432 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \ 1433 .hpd_irq_setup = platform##_hpd_irq_setup, \ 1434 .hpd_enable_detection = platform##_hpd_enable_detection, \ 1435 } 1436 1437 HPD_FUNCS(i915); 1438 HPD_FUNCS(xelpdp); 1439 HPD_FUNCS(dg1); 1440 HPD_FUNCS(gen11); 1441 HPD_FUNCS(bxt); 1442 HPD_FUNCS(icp); 1443 HPD_FUNCS(spt); 1444 HPD_FUNCS(ilk); 1445 #undef HPD_FUNCS 1446 1447 void intel_hpd_enable_detection(struct intel_encoder *encoder) 1448 { 1449 struct intel_display *display = to_intel_display(encoder); 1450 1451 if (display->funcs.hotplug) 1452 display->funcs.hotplug->hpd_enable_detection(encoder); 1453 } 1454 1455 void intel_hpd_irq_setup(struct intel_display *display) 1456 { 1457 if ((display->platform.valleyview || display->platform.cherryview) && 1458 !display->irq.vlv_display_irqs_enabled) 1459 return; 1460 1461 if (display->funcs.hotplug) 1462 display->funcs.hotplug->hpd_irq_setup(display); 1463 } 1464 1465 void intel_hotplug_irq_init(struct intel_display *display) 1466 { 1467 intel_hpd_init_pins(display); 1468 1469 intel_hpd_init_early(display); 1470 1471 if (HAS_GMCH(display)) { 1472 if (HAS_HOTPLUG(display)) 1473 display->funcs.hotplug = &i915_hpd_funcs; 1474 } else { 1475 if (HAS_PCH_DG2(display)) 1476 display->funcs.hotplug = &icp_hpd_funcs; 1477 else if (HAS_PCH_DG1(display)) 1478 display->funcs.hotplug = &dg1_hpd_funcs; 1479 else if (DISPLAY_VER(display) >= 14) 1480 display->funcs.hotplug = &xelpdp_hpd_funcs; 1481 else if (DISPLAY_VER(display) >= 11) 1482 display->funcs.hotplug = &gen11_hpd_funcs; 1483 else if (display->platform.geminilake || display->platform.broxton) 1484 display->funcs.hotplug = &bxt_hpd_funcs; 1485 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 1486 display->funcs.hotplug = &icp_hpd_funcs; 1487 else if (INTEL_PCH_TYPE(display) >= PCH_SPT) 1488 display->funcs.hotplug = &spt_hpd_funcs; 1489 else 1490 display->funcs.hotplug = &ilk_hpd_funcs; 1491 } 1492 } 1493