1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "intel_de.h" 9 #include "intel_display_irq.h" 10 #include "intel_display_types.h" 11 #include "intel_dp_aux.h" 12 #include "intel_gmbus.h" 13 #include "intel_hotplug.h" 14 #include "intel_hotplug_irq.h" 15 16 typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val); 17 typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder); 18 typedef u32 (*hotplug_mask_func)(enum hpd_pin pin); 19 20 static const u32 hpd_ilk[HPD_NUM_PINS] = { 21 [HPD_PORT_A] = DE_DP_A_HOTPLUG, 22 }; 23 24 static const u32 hpd_ivb[HPD_NUM_PINS] = { 25 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, 26 }; 27 28 static const u32 hpd_bdw[HPD_NUM_PINS] = { 29 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 30 }; 31 32 static const u32 hpd_ibx[HPD_NUM_PINS] = { 33 [HPD_CRT] = SDE_CRT_HOTPLUG, 34 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 35 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 36 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 37 [HPD_PORT_D] = SDE_PORTD_HOTPLUG, 38 }; 39 40 static const u32 hpd_cpt[HPD_NUM_PINS] = { 41 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 46 }; 47 48 static const u32 hpd_spt[HPD_NUM_PINS] = { 49 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, 53 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT, 54 }; 55 56 static const u32 hpd_mask_i915[HPD_NUM_PINS] = { 57 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN, 63 }; 64 65 static const u32 hpd_status_g4x[HPD_NUM_PINS] = { 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 72 }; 73 74 static const u32 hpd_status_i915[HPD_NUM_PINS] = { 75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS, 81 }; 82 83 static const u32 hpd_bxt[HPD_NUM_PINS] = { 84 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A), 85 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B), 86 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C), 87 }; 88 89 static const u32 hpd_gen11[HPD_NUM_PINS] = { 90 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1), 91 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2), 92 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3), 93 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4), 94 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5), 95 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6), 96 }; 97 98 static const u32 hpd_xelpdp[HPD_NUM_PINS] = { 99 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1), 100 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2), 101 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3), 102 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4), 103 }; 104 105 static const u32 hpd_icp[HPD_NUM_PINS] = { 106 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 107 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 108 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 109 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 110 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 111 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 112 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 113 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5), 114 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6), 115 }; 116 117 static const u32 hpd_sde_dg1[HPD_NUM_PINS] = { 118 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 119 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 120 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C), 121 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D), 122 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1), 123 }; 124 125 static const u32 hpd_mtp[HPD_NUM_PINS] = { 126 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A), 127 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B), 128 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1), 129 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2), 130 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3), 131 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4), 132 }; 133 134 static void intel_hpd_init_pins(struct intel_display *display) 135 { 136 struct drm_i915_private *dev_priv = to_i915(display->drm); 137 struct intel_hotplug *hpd = &display->hotplug; 138 139 if (HAS_GMCH(display)) { 140 if (display->platform.g4x || display->platform.valleyview || 141 display->platform.cherryview) 142 hpd->hpd = hpd_status_g4x; 143 else 144 hpd->hpd = hpd_status_i915; 145 return; 146 } 147 148 if (DISPLAY_VER(display) >= 14) 149 hpd->hpd = hpd_xelpdp; 150 else if (DISPLAY_VER(display) >= 11) 151 hpd->hpd = hpd_gen11; 152 else if (display->platform.geminilake || display->platform.broxton) 153 hpd->hpd = hpd_bxt; 154 else if (DISPLAY_VER(display) == 9) 155 hpd->hpd = NULL; /* no north HPD on SKL */ 156 else if (DISPLAY_VER(display) >= 8) 157 hpd->hpd = hpd_bdw; 158 else if (DISPLAY_VER(display) >= 7) 159 hpd->hpd = hpd_ivb; 160 else 161 hpd->hpd = hpd_ilk; 162 163 if ((INTEL_PCH_TYPE(dev_priv) < PCH_DG1) && 164 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) 165 return; 166 167 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) 168 hpd->pch_hpd = hpd_mtp; 169 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 170 hpd->pch_hpd = hpd_sde_dg1; 171 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 172 hpd->pch_hpd = hpd_icp; 173 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) 174 hpd->pch_hpd = hpd_spt; 175 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) 176 hpd->pch_hpd = hpd_cpt; 177 else if (HAS_PCH_IBX(dev_priv)) 178 hpd->pch_hpd = hpd_ibx; 179 else 180 MISSING_CASE(INTEL_PCH_TYPE(dev_priv)); 181 } 182 183 /* For display hotplug interrupt */ 184 void i915_hotplug_interrupt_update_locked(struct intel_display *display, 185 u32 mask, u32 bits) 186 { 187 struct drm_i915_private *dev_priv = to_i915(display->drm); 188 189 lockdep_assert_held(&dev_priv->irq_lock); 190 drm_WARN_ON(display->drm, bits & ~mask); 191 192 intel_de_rmw(display, PORT_HOTPLUG_EN(display), mask, bits); 193 } 194 195 /** 196 * i915_hotplug_interrupt_update - update hotplug interrupt enable 197 * @display: display device 198 * @mask: bits to update 199 * @bits: bits to enable 200 * NOTE: the HPD enable bits are modified both inside and outside 201 * of an interrupt context. To avoid that read-modify-write cycles 202 * interfere, these bits are protected by a spinlock. Since this 203 * function is usually not called from a context where the lock is 204 * held already, this function acquires the lock itself. A non-locking 205 * version is also available. 206 */ 207 void i915_hotplug_interrupt_update(struct intel_display *display, 208 u32 mask, 209 u32 bits) 210 { 211 struct drm_i915_private *dev_priv = to_i915(display->drm); 212 213 spin_lock_irq(&dev_priv->irq_lock); 214 i915_hotplug_interrupt_update_locked(display, mask, bits); 215 spin_unlock_irq(&dev_priv->irq_lock); 216 } 217 218 static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 219 { 220 switch (pin) { 221 case HPD_PORT_TC1: 222 case HPD_PORT_TC2: 223 case HPD_PORT_TC3: 224 case HPD_PORT_TC4: 225 case HPD_PORT_TC5: 226 case HPD_PORT_TC6: 227 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin); 228 default: 229 return false; 230 } 231 } 232 233 static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 234 { 235 switch (pin) { 236 case HPD_PORT_A: 237 return val & PORTA_HOTPLUG_LONG_DETECT; 238 case HPD_PORT_B: 239 return val & PORTB_HOTPLUG_LONG_DETECT; 240 case HPD_PORT_C: 241 return val & PORTC_HOTPLUG_LONG_DETECT; 242 default: 243 return false; 244 } 245 } 246 247 static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 248 { 249 switch (pin) { 250 case HPD_PORT_A: 251 case HPD_PORT_B: 252 case HPD_PORT_C: 253 case HPD_PORT_D: 254 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin); 255 default: 256 return false; 257 } 258 } 259 260 static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 261 { 262 switch (pin) { 263 case HPD_PORT_TC1: 264 case HPD_PORT_TC2: 265 case HPD_PORT_TC3: 266 case HPD_PORT_TC4: 267 case HPD_PORT_TC5: 268 case HPD_PORT_TC6: 269 return val & ICP_TC_HPD_LONG_DETECT(pin); 270 default: 271 return false; 272 } 273 } 274 275 static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val) 276 { 277 switch (pin) { 278 case HPD_PORT_E: 279 return val & PORTE_HOTPLUG_LONG_DETECT; 280 default: 281 return false; 282 } 283 } 284 285 static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 286 { 287 switch (pin) { 288 case HPD_PORT_A: 289 return val & PORTA_HOTPLUG_LONG_DETECT; 290 case HPD_PORT_B: 291 return val & PORTB_HOTPLUG_LONG_DETECT; 292 case HPD_PORT_C: 293 return val & PORTC_HOTPLUG_LONG_DETECT; 294 case HPD_PORT_D: 295 return val & PORTD_HOTPLUG_LONG_DETECT; 296 default: 297 return false; 298 } 299 } 300 301 static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 302 { 303 switch (pin) { 304 case HPD_PORT_A: 305 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; 306 default: 307 return false; 308 } 309 } 310 311 static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 312 { 313 switch (pin) { 314 case HPD_PORT_B: 315 return val & PORTB_HOTPLUG_LONG_DETECT; 316 case HPD_PORT_C: 317 return val & PORTC_HOTPLUG_LONG_DETECT; 318 case HPD_PORT_D: 319 return val & PORTD_HOTPLUG_LONG_DETECT; 320 default: 321 return false; 322 } 323 } 324 325 static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val) 326 { 327 switch (pin) { 328 case HPD_PORT_B: 329 return val & PORTB_HOTPLUG_INT_LONG_PULSE; 330 case HPD_PORT_C: 331 return val & PORTC_HOTPLUG_INT_LONG_PULSE; 332 case HPD_PORT_D: 333 return val & PORTD_HOTPLUG_INT_LONG_PULSE; 334 default: 335 return false; 336 } 337 } 338 339 /* 340 * Get a bit mask of pins that have triggered, and which ones may be long. 341 * This can be called multiple times with the same masks to accumulate 342 * hotplug detection results from several registers. 343 * 344 * Note that the caller is expected to zero out the masks initially. 345 */ 346 static void intel_get_hpd_pins(struct intel_display *display, 347 u32 *pin_mask, u32 *long_mask, 348 u32 hotplug_trigger, u32 dig_hotplug_reg, 349 const u32 hpd[HPD_NUM_PINS], 350 bool long_pulse_detect(enum hpd_pin pin, u32 val)) 351 { 352 enum hpd_pin pin; 353 354 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS); 355 356 for_each_hpd_pin(pin) { 357 if ((hpd[pin] & hotplug_trigger) == 0) 358 continue; 359 360 *pin_mask |= BIT(pin); 361 362 if (long_pulse_detect(pin, dig_hotplug_reg)) 363 *long_mask |= BIT(pin); 364 } 365 366 drm_dbg_kms(display->drm, 367 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n", 368 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask); 369 } 370 371 static u32 intel_hpd_enabled_irqs(struct intel_display *display, 372 const u32 hpd[HPD_NUM_PINS]) 373 { 374 struct intel_encoder *encoder; 375 u32 enabled_irqs = 0; 376 377 for_each_intel_encoder(display->drm, encoder) 378 if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) 379 enabled_irqs |= hpd[encoder->hpd_pin]; 380 381 return enabled_irqs; 382 } 383 384 static u32 intel_hpd_hotplug_irqs(struct intel_display *display, 385 const u32 hpd[HPD_NUM_PINS]) 386 { 387 struct intel_encoder *encoder; 388 u32 hotplug_irqs = 0; 389 390 for_each_intel_encoder(display->drm, encoder) 391 hotplug_irqs |= hpd[encoder->hpd_pin]; 392 393 return hotplug_irqs; 394 } 395 396 static u32 intel_hpd_hotplug_mask(struct intel_display *display, 397 hotplug_mask_func hotplug_mask) 398 { 399 enum hpd_pin pin; 400 u32 hotplug = 0; 401 402 for_each_hpd_pin(pin) 403 hotplug |= hotplug_mask(pin); 404 405 return hotplug; 406 } 407 408 static u32 intel_hpd_hotplug_enables(struct intel_display *display, 409 hotplug_enables_func hotplug_enables) 410 { 411 struct intel_encoder *encoder; 412 u32 hotplug = 0; 413 414 for_each_intel_encoder(display->drm, encoder) 415 hotplug |= hotplug_enables(encoder); 416 417 return hotplug; 418 } 419 420 u32 i9xx_hpd_irq_ack(struct intel_display *display) 421 { 422 u32 hotplug_status = 0, hotplug_status_mask; 423 int i; 424 425 if (display->platform.g4x || 426 display->platform.valleyview || display->platform.cherryview) 427 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | 428 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; 429 else 430 hotplug_status_mask = HOTPLUG_INT_STATUS_I915; 431 432 /* 433 * We absolutely have to clear all the pending interrupt 434 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port 435 * interrupt bit won't have an edge, and the i965/g4x 436 * edge triggered IIR will not notice that an interrupt 437 * is still pending. We can't use PORT_HOTPLUG_EN to 438 * guarantee the edge as the act of toggling the enable 439 * bits can itself generate a new hotplug interrupt :( 440 */ 441 for (i = 0; i < 10; i++) { 442 u32 tmp = intel_de_read(display, 443 PORT_HOTPLUG_STAT(display)) & hotplug_status_mask; 444 445 if (tmp == 0) 446 return hotplug_status; 447 448 hotplug_status |= tmp; 449 intel_de_write(display, PORT_HOTPLUG_STAT(display), 450 hotplug_status); 451 } 452 453 drm_WARN_ONCE(display->drm, 1, 454 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", 455 intel_de_read(display, PORT_HOTPLUG_STAT(display))); 456 457 return hotplug_status; 458 } 459 460 void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status) 461 { 462 u32 pin_mask = 0, long_mask = 0; 463 u32 hotplug_trigger; 464 465 if (display->platform.g4x || 466 display->platform.valleyview || display->platform.cherryview) 467 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; 468 else 469 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 470 471 if (hotplug_trigger) { 472 intel_get_hpd_pins(display, &pin_mask, &long_mask, 473 hotplug_trigger, hotplug_trigger, 474 display->hotplug.hpd, 475 i9xx_port_hotplug_long_detect); 476 477 intel_hpd_irq_handler(display, pin_mask, long_mask); 478 } 479 480 if ((display->platform.g4x || 481 display->platform.valleyview || display->platform.cherryview) && 482 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 483 intel_dp_aux_irq_handler(display); 484 } 485 486 void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 487 { 488 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 489 490 /* 491 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU 492 * unless we touch the hotplug register, even if hotplug_trigger is 493 * zero. Not acking leads to "The master control interrupt lied (SDE)!" 494 * errors. 495 */ 496 dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG); 497 if (!hotplug_trigger) { 498 u32 mask = PORTA_HOTPLUG_STATUS_MASK | 499 PORTD_HOTPLUG_STATUS_MASK | 500 PORTC_HOTPLUG_STATUS_MASK | 501 PORTB_HOTPLUG_STATUS_MASK; 502 dig_hotplug_reg &= ~mask; 503 } 504 505 intel_de_write(display, PCH_PORT_HOTPLUG, dig_hotplug_reg); 506 if (!hotplug_trigger) 507 return; 508 509 intel_get_hpd_pins(display, &pin_mask, &long_mask, 510 hotplug_trigger, dig_hotplug_reg, 511 display->hotplug.pch_hpd, 512 pch_port_hotplug_long_detect); 513 514 intel_hpd_irq_handler(display, pin_mask, long_mask); 515 } 516 517 void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir) 518 { 519 enum hpd_pin pin; 520 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK); 521 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK; 522 u32 pin_mask = 0, long_mask = 0; 523 524 if (DISPLAY_VER(display) >= 20) 525 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK; 526 527 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) { 528 u32 val; 529 530 if (!(display->hotplug.hpd[pin] & hotplug_trigger)) 531 continue; 532 533 pin_mask |= BIT(pin); 534 535 val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin)); 536 intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val); 537 538 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT)) 539 long_mask |= BIT(pin); 540 } 541 542 if (pin_mask) { 543 drm_dbg_kms(display->drm, 544 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n", 545 hotplug_trigger, pin_mask, long_mask); 546 547 intel_hpd_irq_handler(display, pin_mask, long_mask); 548 } 549 550 if (trigger_aux) 551 intel_dp_aux_irq_handler(display); 552 553 if (!pin_mask && !trigger_aux) 554 drm_err(display->drm, 555 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir); 556 } 557 558 void icp_irq_handler(struct intel_display *display, u32 pch_iir) 559 { 560 struct drm_i915_private *dev_priv = to_i915(display->drm); 561 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP; 562 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP; 563 u32 pin_mask = 0, long_mask = 0; 564 565 if (ddi_hotplug_trigger) { 566 u32 dig_hotplug_reg; 567 568 /* Locking due to DSI native GPIO sequences */ 569 spin_lock(&dev_priv->irq_lock); 570 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, 0, 0); 571 spin_unlock(&dev_priv->irq_lock); 572 573 intel_get_hpd_pins(display, &pin_mask, &long_mask, 574 ddi_hotplug_trigger, dig_hotplug_reg, 575 display->hotplug.pch_hpd, 576 icp_ddi_port_hotplug_long_detect); 577 } 578 579 if (tc_hotplug_trigger) { 580 u32 dig_hotplug_reg; 581 582 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, 0, 0); 583 584 intel_get_hpd_pins(display, &pin_mask, &long_mask, 585 tc_hotplug_trigger, dig_hotplug_reg, 586 display->hotplug.pch_hpd, 587 icp_tc_port_hotplug_long_detect); 588 } 589 590 if (pin_mask) 591 intel_hpd_irq_handler(display, pin_mask, long_mask); 592 593 if (pch_iir & SDE_GMBUS_ICP) 594 intel_gmbus_irq_handler(display); 595 } 596 597 void spt_irq_handler(struct intel_display *display, u32 pch_iir) 598 { 599 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & 600 ~SDE_PORTE_HOTPLUG_SPT; 601 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; 602 u32 pin_mask = 0, long_mask = 0; 603 604 if (hotplug_trigger) { 605 u32 dig_hotplug_reg; 606 607 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 608 609 intel_get_hpd_pins(display, &pin_mask, &long_mask, 610 hotplug_trigger, dig_hotplug_reg, 611 display->hotplug.pch_hpd, 612 spt_port_hotplug_long_detect); 613 } 614 615 if (hotplug2_trigger) { 616 u32 dig_hotplug_reg; 617 618 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, 0, 0); 619 620 intel_get_hpd_pins(display, &pin_mask, &long_mask, 621 hotplug2_trigger, dig_hotplug_reg, 622 display->hotplug.pch_hpd, 623 spt_port_hotplug2_long_detect); 624 } 625 626 if (pin_mask) 627 intel_hpd_irq_handler(display, pin_mask, long_mask); 628 629 if (pch_iir & SDE_GMBUS_CPT) 630 intel_gmbus_irq_handler(display); 631 } 632 633 void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 634 { 635 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 636 637 dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 0, 0); 638 639 intel_get_hpd_pins(display, &pin_mask, &long_mask, 640 hotplug_trigger, dig_hotplug_reg, 641 display->hotplug.hpd, 642 ilk_port_hotplug_long_detect); 643 644 intel_hpd_irq_handler(display, pin_mask, long_mask); 645 } 646 647 void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger) 648 { 649 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; 650 651 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, 0, 0); 652 653 intel_get_hpd_pins(display, &pin_mask, &long_mask, 654 hotplug_trigger, dig_hotplug_reg, 655 display->hotplug.hpd, 656 bxt_port_hotplug_long_detect); 657 658 intel_hpd_irq_handler(display, pin_mask, long_mask); 659 } 660 661 void gen11_hpd_irq_handler(struct intel_display *display, u32 iir) 662 { 663 u32 pin_mask = 0, long_mask = 0; 664 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK; 665 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK; 666 667 if (trigger_tc) { 668 u32 dig_hotplug_reg; 669 670 dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 0, 0); 671 672 intel_get_hpd_pins(display, &pin_mask, &long_mask, 673 trigger_tc, dig_hotplug_reg, 674 display->hotplug.hpd, 675 gen11_port_hotplug_long_detect); 676 } 677 678 if (trigger_tbt) { 679 u32 dig_hotplug_reg; 680 681 dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 0, 0); 682 683 intel_get_hpd_pins(display, &pin_mask, &long_mask, 684 trigger_tbt, dig_hotplug_reg, 685 display->hotplug.hpd, 686 gen11_port_hotplug_long_detect); 687 } 688 689 if (pin_mask) 690 intel_hpd_irq_handler(display, pin_mask, long_mask); 691 else 692 drm_err(display->drm, 693 "Unexpected DE HPD interrupt 0x%08x\n", iir); 694 } 695 696 static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin) 697 { 698 switch (hpd_pin) { 699 case HPD_PORT_A: 700 return PORTA_HOTPLUG_ENABLE; 701 case HPD_PORT_B: 702 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK; 703 case HPD_PORT_C: 704 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK; 705 case HPD_PORT_D: 706 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK; 707 default: 708 return 0; 709 } 710 } 711 712 static u32 ibx_hotplug_enables(struct intel_encoder *encoder) 713 { 714 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 715 716 switch (encoder->hpd_pin) { 717 case HPD_PORT_A: 718 /* 719 * When CPU and PCH are on the same package, port A 720 * HPD must be enabled in both north and south. 721 */ 722 return HAS_PCH_LPT_LP(i915) ? 723 PORTA_HOTPLUG_ENABLE : 0; 724 case HPD_PORT_B: 725 return PORTB_HOTPLUG_ENABLE | 726 PORTB_PULSE_DURATION_2ms; 727 case HPD_PORT_C: 728 return PORTC_HOTPLUG_ENABLE | 729 PORTC_PULSE_DURATION_2ms; 730 case HPD_PORT_D: 731 return PORTD_HOTPLUG_ENABLE | 732 PORTD_PULSE_DURATION_2ms; 733 default: 734 return 0; 735 } 736 } 737 738 static void ibx_hpd_detection_setup(struct intel_display *display) 739 { 740 /* 741 * Enable digital hotplug on the PCH, and configure the DP short pulse 742 * duration to 2ms (which is the minimum in the Display Port spec). 743 * The pulse duration bits are reserved on LPT+. 744 */ 745 intel_de_rmw(display, PCH_PORT_HOTPLUG, 746 intel_hpd_hotplug_mask(display, ibx_hotplug_mask), 747 intel_hpd_hotplug_enables(display, ibx_hotplug_enables)); 748 } 749 750 static void ibx_hpd_enable_detection(struct intel_encoder *encoder) 751 { 752 struct intel_display *display = to_intel_display(encoder); 753 754 intel_de_rmw(display, PCH_PORT_HOTPLUG, 755 ibx_hotplug_mask(encoder->hpd_pin), 756 ibx_hotplug_enables(encoder)); 757 } 758 759 static void ibx_hpd_irq_setup(struct intel_display *display) 760 { 761 u32 hotplug_irqs, enabled_irqs; 762 763 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 764 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 765 766 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 767 768 ibx_hpd_detection_setup(display); 769 } 770 771 static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 772 { 773 switch (hpd_pin) { 774 case HPD_PORT_A: 775 case HPD_PORT_B: 776 case HPD_PORT_C: 777 case HPD_PORT_D: 778 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 779 default: 780 return 0; 781 } 782 } 783 784 static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder) 785 { 786 return icp_ddi_hotplug_mask(encoder->hpd_pin); 787 } 788 789 static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin) 790 { 791 switch (hpd_pin) { 792 case HPD_PORT_TC1: 793 case HPD_PORT_TC2: 794 case HPD_PORT_TC3: 795 case HPD_PORT_TC4: 796 case HPD_PORT_TC5: 797 case HPD_PORT_TC6: 798 return ICP_TC_HPD_ENABLE(hpd_pin); 799 default: 800 return 0; 801 } 802 } 803 804 static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder) 805 { 806 return icp_tc_hotplug_mask(encoder->hpd_pin); 807 } 808 809 static void icp_ddi_hpd_detection_setup(struct intel_display *display) 810 { 811 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 812 intel_hpd_hotplug_mask(display, icp_ddi_hotplug_mask), 813 intel_hpd_hotplug_enables(display, icp_ddi_hotplug_enables)); 814 } 815 816 static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 817 { 818 struct intel_display *display = to_intel_display(encoder); 819 820 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 821 icp_ddi_hotplug_mask(encoder->hpd_pin), 822 icp_ddi_hotplug_enables(encoder)); 823 } 824 825 static void icp_tc_hpd_detection_setup(struct intel_display *display) 826 { 827 intel_de_rmw(display, SHOTPLUG_CTL_TC, 828 intel_hpd_hotplug_mask(display, icp_tc_hotplug_mask), 829 intel_hpd_hotplug_enables(display, icp_tc_hotplug_enables)); 830 } 831 832 static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder) 833 { 834 struct intel_display *display = to_intel_display(encoder); 835 836 intel_de_rmw(display, SHOTPLUG_CTL_TC, 837 icp_tc_hotplug_mask(encoder->hpd_pin), 838 icp_tc_hotplug_enables(encoder)); 839 } 840 841 static void icp_hpd_enable_detection(struct intel_encoder *encoder) 842 { 843 icp_ddi_hpd_enable_detection(encoder); 844 icp_tc_hpd_enable_detection(encoder); 845 } 846 847 static void icp_hpd_irq_setup(struct intel_display *display) 848 { 849 u32 hotplug_irqs, enabled_irqs; 850 851 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 852 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 853 854 /* 855 * We reduce the value to 250us to be able to detect SHPD when an external display 856 * is connected. This is also expected of us as stated in DP1.4a Table 3-4. 857 */ 858 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 859 860 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 861 862 icp_ddi_hpd_detection_setup(display); 863 icp_tc_hpd_detection_setup(display); 864 } 865 866 static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin) 867 { 868 switch (hpd_pin) { 869 case HPD_PORT_TC1: 870 case HPD_PORT_TC2: 871 case HPD_PORT_TC3: 872 case HPD_PORT_TC4: 873 case HPD_PORT_TC5: 874 case HPD_PORT_TC6: 875 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin); 876 default: 877 return 0; 878 } 879 } 880 881 static u32 gen11_hotplug_enables(struct intel_encoder *encoder) 882 { 883 return gen11_hotplug_mask(encoder->hpd_pin); 884 } 885 886 static void dg1_hpd_invert(struct intel_display *display) 887 { 888 u32 val = (INVERT_DDIA_HPD | 889 INVERT_DDIB_HPD | 890 INVERT_DDIC_HPD | 891 INVERT_DDID_HPD); 892 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 893 } 894 895 static void dg1_hpd_enable_detection(struct intel_encoder *encoder) 896 { 897 struct intel_display *display = to_intel_display(encoder); 898 899 dg1_hpd_invert(display); 900 icp_hpd_enable_detection(encoder); 901 } 902 903 static void dg1_hpd_irq_setup(struct intel_display *display) 904 { 905 dg1_hpd_invert(display); 906 icp_hpd_irq_setup(display); 907 } 908 909 static void gen11_tc_hpd_detection_setup(struct intel_display *display) 910 { 911 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 912 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 913 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 914 } 915 916 static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder) 917 { 918 struct intel_display *display = to_intel_display(encoder); 919 920 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, 921 gen11_hotplug_mask(encoder->hpd_pin), 922 gen11_hotplug_enables(encoder)); 923 } 924 925 static void gen11_tbt_hpd_detection_setup(struct intel_display *display) 926 { 927 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 928 intel_hpd_hotplug_mask(display, gen11_hotplug_mask), 929 intel_hpd_hotplug_enables(display, gen11_hotplug_enables)); 930 } 931 932 static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder) 933 { 934 struct intel_display *display = to_intel_display(encoder); 935 936 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, 937 gen11_hotplug_mask(encoder->hpd_pin), 938 gen11_hotplug_enables(encoder)); 939 } 940 941 static void gen11_hpd_enable_detection(struct intel_encoder *encoder) 942 { 943 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 944 945 gen11_tc_hpd_enable_detection(encoder); 946 gen11_tbt_hpd_enable_detection(encoder); 947 948 if (INTEL_PCH_TYPE(i915) >= PCH_ICP) 949 icp_hpd_enable_detection(encoder); 950 } 951 952 static void gen11_hpd_irq_setup(struct intel_display *display) 953 { 954 struct drm_i915_private *dev_priv = to_i915(display->drm); 955 u32 hotplug_irqs, enabled_irqs; 956 957 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 958 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 959 960 intel_de_rmw(display, GEN11_DE_HPD_IMR, hotplug_irqs, 961 ~enabled_irqs & hotplug_irqs); 962 intel_de_posting_read(display, GEN11_DE_HPD_IMR); 963 964 gen11_tc_hpd_detection_setup(display); 965 gen11_tbt_hpd_detection_setup(display); 966 967 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 968 icp_hpd_irq_setup(display); 969 } 970 971 static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin) 972 { 973 switch (hpd_pin) { 974 case HPD_PORT_A: 975 case HPD_PORT_B: 976 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin); 977 default: 978 return 0; 979 } 980 } 981 982 static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder) 983 { 984 return mtp_ddi_hotplug_mask(encoder->hpd_pin); 985 } 986 987 static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin) 988 { 989 switch (hpd_pin) { 990 case HPD_PORT_TC1: 991 case HPD_PORT_TC2: 992 case HPD_PORT_TC3: 993 case HPD_PORT_TC4: 994 return ICP_TC_HPD_ENABLE(hpd_pin); 995 default: 996 return 0; 997 } 998 } 999 1000 static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder) 1001 { 1002 return mtp_tc_hotplug_mask(encoder->hpd_pin); 1003 } 1004 1005 static void mtp_ddi_hpd_detection_setup(struct intel_display *display) 1006 { 1007 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1008 intel_hpd_hotplug_mask(display, mtp_ddi_hotplug_mask), 1009 intel_hpd_hotplug_enables(display, mtp_ddi_hotplug_enables)); 1010 } 1011 1012 static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder) 1013 { 1014 struct intel_display *display = to_intel_display(encoder); 1015 1016 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1017 mtp_ddi_hotplug_mask(encoder->hpd_pin), 1018 mtp_ddi_hotplug_enables(encoder)); 1019 } 1020 1021 static void mtp_tc_hpd_detection_setup(struct intel_display *display) 1022 { 1023 intel_de_rmw(display, SHOTPLUG_CTL_TC, 1024 intel_hpd_hotplug_mask(display, mtp_tc_hotplug_mask), 1025 intel_hpd_hotplug_enables(display, mtp_tc_hotplug_enables)); 1026 } 1027 1028 static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder) 1029 { 1030 struct intel_display *display = to_intel_display(encoder); 1031 1032 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 1033 mtp_tc_hotplug_mask(encoder->hpd_pin), 1034 mtp_tc_hotplug_enables(encoder)); 1035 } 1036 1037 static void mtp_hpd_invert(struct intel_display *display) 1038 { 1039 u32 val = (INVERT_DDIA_HPD | 1040 INVERT_DDIB_HPD | 1041 INVERT_DDIC_HPD | 1042 INVERT_TC1_HPD | 1043 INVERT_TC2_HPD | 1044 INVERT_TC3_HPD | 1045 INVERT_TC4_HPD | 1046 INVERT_DDID_HPD_MTP | 1047 INVERT_DDIE_HPD); 1048 intel_de_rmw(display, SOUTH_CHICKEN1, 0, val); 1049 } 1050 1051 static void mtp_hpd_enable_detection(struct intel_encoder *encoder) 1052 { 1053 struct intel_display *display = to_intel_display(encoder); 1054 1055 mtp_hpd_invert(display); 1056 mtp_ddi_hpd_enable_detection(encoder); 1057 mtp_tc_hpd_enable_detection(encoder); 1058 } 1059 1060 static void mtp_hpd_irq_setup(struct intel_display *display) 1061 { 1062 u32 hotplug_irqs, enabled_irqs; 1063 1064 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1065 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1066 1067 /* 1068 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the 1069 * SHPD_FILTER_CNT value should be. 1070 */ 1071 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250); 1072 1073 mtp_hpd_invert(display); 1074 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1075 1076 mtp_ddi_hpd_detection_setup(display); 1077 mtp_tc_hpd_detection_setup(display); 1078 } 1079 1080 static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display) 1081 { 1082 u32 hotplug_irqs, enabled_irqs; 1083 1084 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1085 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1086 1087 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1088 1089 mtp_ddi_hpd_detection_setup(display); 1090 mtp_tc_hpd_detection_setup(display); 1091 } 1092 1093 static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin) 1094 { 1095 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4; 1096 } 1097 1098 static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display, 1099 enum hpd_pin hpd_pin, bool enable) 1100 { 1101 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE | 1102 XELPDP_DP_ALT_HOTPLUG_ENABLE; 1103 1104 if (!is_xelpdp_pica_hpd_pin(hpd_pin)) 1105 return; 1106 1107 intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), 1108 mask, enable ? mask : 0); 1109 } 1110 1111 static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder) 1112 { 1113 struct intel_display *display = to_intel_display(encoder); 1114 1115 _xelpdp_pica_hpd_detection_setup(display, encoder->hpd_pin, true); 1116 } 1117 1118 static void xelpdp_pica_hpd_detection_setup(struct intel_display *display) 1119 { 1120 struct intel_encoder *encoder; 1121 u32 available_pins = 0; 1122 enum hpd_pin pin; 1123 1124 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS); 1125 1126 for_each_intel_encoder(display->drm, encoder) 1127 available_pins |= BIT(encoder->hpd_pin); 1128 1129 for_each_hpd_pin(pin) 1130 _xelpdp_pica_hpd_detection_setup(display, pin, available_pins & BIT(pin)); 1131 } 1132 1133 static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder) 1134 { 1135 xelpdp_pica_hpd_enable_detection(encoder); 1136 mtp_hpd_enable_detection(encoder); 1137 } 1138 1139 static void xelpdp_hpd_irq_setup(struct intel_display *display) 1140 { 1141 struct drm_i915_private *i915 = to_i915(display->drm); 1142 u32 hotplug_irqs, enabled_irqs; 1143 1144 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1145 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1146 1147 intel_de_rmw(display, PICAINTERRUPT_IMR, hotplug_irqs, 1148 ~enabled_irqs & hotplug_irqs); 1149 intel_de_posting_read(display, PICAINTERRUPT_IMR); 1150 1151 xelpdp_pica_hpd_detection_setup(display); 1152 1153 if (INTEL_PCH_TYPE(i915) >= PCH_LNL) 1154 xe2lpd_sde_hpd_irq_setup(display); 1155 else if (INTEL_PCH_TYPE(i915) >= PCH_MTL) 1156 mtp_hpd_irq_setup(display); 1157 } 1158 1159 static u32 spt_hotplug_mask(enum hpd_pin hpd_pin) 1160 { 1161 switch (hpd_pin) { 1162 case HPD_PORT_A: 1163 return PORTA_HOTPLUG_ENABLE; 1164 case HPD_PORT_B: 1165 return PORTB_HOTPLUG_ENABLE; 1166 case HPD_PORT_C: 1167 return PORTC_HOTPLUG_ENABLE; 1168 case HPD_PORT_D: 1169 return PORTD_HOTPLUG_ENABLE; 1170 default: 1171 return 0; 1172 } 1173 } 1174 1175 static u32 spt_hotplug_enables(struct intel_encoder *encoder) 1176 { 1177 return spt_hotplug_mask(encoder->hpd_pin); 1178 } 1179 1180 static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin) 1181 { 1182 switch (hpd_pin) { 1183 case HPD_PORT_E: 1184 return PORTE_HOTPLUG_ENABLE; 1185 default: 1186 return 0; 1187 } 1188 } 1189 1190 static u32 spt_hotplug2_enables(struct intel_encoder *encoder) 1191 { 1192 return spt_hotplug2_mask(encoder->hpd_pin); 1193 } 1194 1195 static void spt_hpd_detection_setup(struct intel_display *display) 1196 { 1197 struct drm_i915_private *dev_priv = to_i915(display->drm); 1198 1199 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1200 if (HAS_PCH_CNP(dev_priv)) { 1201 intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK, 1202 CHASSIS_CLK_REQ_DURATION(0xf)); 1203 } 1204 1205 /* Enable digital hotplug on the PCH */ 1206 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1207 intel_hpd_hotplug_mask(display, spt_hotplug_mask), 1208 intel_hpd_hotplug_enables(display, spt_hotplug_enables)); 1209 1210 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1211 intel_hpd_hotplug_mask(display, spt_hotplug2_mask), 1212 intel_hpd_hotplug_enables(display, spt_hotplug2_enables)); 1213 } 1214 1215 static void spt_hpd_enable_detection(struct intel_encoder *encoder) 1216 { 1217 struct intel_display *display = to_intel_display(encoder); 1218 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1219 1220 /* Display WA #1179 WaHardHangonHotPlug: cnp */ 1221 if (HAS_PCH_CNP(i915)) { 1222 intel_de_rmw(display, SOUTH_CHICKEN1, 1223 CHASSIS_CLK_REQ_DURATION_MASK, 1224 CHASSIS_CLK_REQ_DURATION(0xf)); 1225 } 1226 1227 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1228 spt_hotplug_mask(encoder->hpd_pin), 1229 spt_hotplug_enables(encoder)); 1230 1231 intel_de_rmw(display, PCH_PORT_HOTPLUG2, 1232 spt_hotplug2_mask(encoder->hpd_pin), 1233 spt_hotplug2_enables(encoder)); 1234 } 1235 1236 static void spt_hpd_irq_setup(struct intel_display *display) 1237 { 1238 struct drm_i915_private *dev_priv = to_i915(display->drm); 1239 u32 hotplug_irqs, enabled_irqs; 1240 1241 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 1242 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ); 1243 1244 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.pch_hpd); 1245 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.pch_hpd); 1246 1247 ibx_display_interrupt_update(display, hotplug_irqs, enabled_irqs); 1248 1249 spt_hpd_detection_setup(display); 1250 } 1251 1252 static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin) 1253 { 1254 switch (hpd_pin) { 1255 case HPD_PORT_A: 1256 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1257 DIGITAL_PORTA_PULSE_DURATION_MASK; 1258 default: 1259 return 0; 1260 } 1261 } 1262 1263 static u32 ilk_hotplug_enables(struct intel_encoder *encoder) 1264 { 1265 switch (encoder->hpd_pin) { 1266 case HPD_PORT_A: 1267 return DIGITAL_PORTA_HOTPLUG_ENABLE | 1268 DIGITAL_PORTA_PULSE_DURATION_2ms; 1269 default: 1270 return 0; 1271 } 1272 } 1273 1274 static void ilk_hpd_detection_setup(struct intel_display *display) 1275 { 1276 /* 1277 * Enable digital hotplug on the CPU, and configure the DP short pulse 1278 * duration to 2ms (which is the minimum in the Display Port spec) 1279 * The pulse duration bits are reserved on HSW+. 1280 */ 1281 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1282 intel_hpd_hotplug_mask(display, ilk_hotplug_mask), 1283 intel_hpd_hotplug_enables(display, ilk_hotplug_enables)); 1284 } 1285 1286 static void ilk_hpd_enable_detection(struct intel_encoder *encoder) 1287 { 1288 struct intel_display *display = to_intel_display(encoder); 1289 1290 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, 1291 ilk_hotplug_mask(encoder->hpd_pin), 1292 ilk_hotplug_enables(encoder)); 1293 1294 ibx_hpd_enable_detection(encoder); 1295 } 1296 1297 static void ilk_hpd_irq_setup(struct intel_display *display) 1298 { 1299 u32 hotplug_irqs, enabled_irqs; 1300 1301 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1302 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1303 1304 if (DISPLAY_VER(display) >= 8) 1305 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1306 else 1307 ilk_update_display_irq(display, hotplug_irqs, enabled_irqs); 1308 1309 ilk_hpd_detection_setup(display); 1310 1311 ibx_hpd_irq_setup(display); 1312 } 1313 1314 static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin) 1315 { 1316 switch (hpd_pin) { 1317 case HPD_PORT_A: 1318 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT; 1319 case HPD_PORT_B: 1320 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT; 1321 case HPD_PORT_C: 1322 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT; 1323 default: 1324 return 0; 1325 } 1326 } 1327 1328 static u32 bxt_hotplug_enables(struct intel_encoder *encoder) 1329 { 1330 u32 hotplug; 1331 1332 switch (encoder->hpd_pin) { 1333 case HPD_PORT_A: 1334 hotplug = PORTA_HOTPLUG_ENABLE; 1335 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1336 hotplug |= BXT_DDIA_HPD_INVERT; 1337 return hotplug; 1338 case HPD_PORT_B: 1339 hotplug = PORTB_HOTPLUG_ENABLE; 1340 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1341 hotplug |= BXT_DDIB_HPD_INVERT; 1342 return hotplug; 1343 case HPD_PORT_C: 1344 hotplug = PORTC_HOTPLUG_ENABLE; 1345 if (intel_bios_encoder_hpd_invert(encoder->devdata)) 1346 hotplug |= BXT_DDIC_HPD_INVERT; 1347 return hotplug; 1348 default: 1349 return 0; 1350 } 1351 } 1352 1353 static void bxt_hpd_detection_setup(struct intel_display *display) 1354 { 1355 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1356 intel_hpd_hotplug_mask(display, bxt_hotplug_mask), 1357 intel_hpd_hotplug_enables(display, bxt_hotplug_enables)); 1358 } 1359 1360 static void bxt_hpd_enable_detection(struct intel_encoder *encoder) 1361 { 1362 struct intel_display *display = to_intel_display(encoder); 1363 1364 intel_de_rmw(display, PCH_PORT_HOTPLUG, 1365 bxt_hotplug_mask(encoder->hpd_pin), 1366 bxt_hotplug_enables(encoder)); 1367 } 1368 1369 static void bxt_hpd_irq_setup(struct intel_display *display) 1370 { 1371 u32 hotplug_irqs, enabled_irqs; 1372 1373 enabled_irqs = intel_hpd_enabled_irqs(display, display->hotplug.hpd); 1374 hotplug_irqs = intel_hpd_hotplug_irqs(display, display->hotplug.hpd); 1375 1376 bdw_update_port_irq(display, hotplug_irqs, enabled_irqs); 1377 1378 bxt_hpd_detection_setup(display); 1379 } 1380 1381 static void g45_hpd_peg_band_gap_wa(struct intel_display *display) 1382 { 1383 /* 1384 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 1385 * 0xd. Failure to do so will result in spurious interrupts being 1386 * generated on the port when a cable is not attached. 1387 */ 1388 intel_de_rmw(display, PEG_BAND_GAP_DATA, 0xf, 0xd); 1389 } 1390 1391 static void i915_hpd_enable_detection(struct intel_encoder *encoder) 1392 { 1393 struct intel_display *display = to_intel_display(encoder); 1394 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin]; 1395 1396 if (display->platform.g45) 1397 g45_hpd_peg_band_gap_wa(display); 1398 1399 /* HPD sense and interrupt enable are one and the same */ 1400 i915_hotplug_interrupt_update(display, hotplug_en, hotplug_en); 1401 } 1402 1403 static void i915_hpd_irq_setup(struct intel_display *display) 1404 { 1405 struct drm_i915_private *dev_priv = to_i915(display->drm); 1406 u32 hotplug_en; 1407 1408 lockdep_assert_held(&dev_priv->irq_lock); 1409 1410 /* 1411 * Note HDMI and DP share hotplug bits. Enable bits are the same for all 1412 * generations. 1413 */ 1414 hotplug_en = intel_hpd_enabled_irqs(display, hpd_mask_i915); 1415 /* 1416 * Programming the CRT detection parameters tends to generate a spurious 1417 * hotplug event about three seconds later. So just do it once. 1418 */ 1419 if (display->platform.g4x) 1420 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1421 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1422 1423 if (display->platform.g45) 1424 g45_hpd_peg_band_gap_wa(display); 1425 1426 /* Ignore TV since it's buggy */ 1427 i915_hotplug_interrupt_update_locked(display, 1428 HOTPLUG_INT_EN_MASK | 1429 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK | 1430 CRT_HOTPLUG_ACTIVATION_PERIOD_64, 1431 hotplug_en); 1432 } 1433 1434 struct intel_hotplug_funcs { 1435 /* Enable HPD sense and interrupts for all present encoders */ 1436 void (*hpd_irq_setup)(struct intel_display *display); 1437 /* Enable HPD sense for a single encoder */ 1438 void (*hpd_enable_detection)(struct intel_encoder *encoder); 1439 }; 1440 1441 #define HPD_FUNCS(platform) \ 1442 static const struct intel_hotplug_funcs platform##_hpd_funcs = { \ 1443 .hpd_irq_setup = platform##_hpd_irq_setup, \ 1444 .hpd_enable_detection = platform##_hpd_enable_detection, \ 1445 } 1446 1447 HPD_FUNCS(i915); 1448 HPD_FUNCS(xelpdp); 1449 HPD_FUNCS(dg1); 1450 HPD_FUNCS(gen11); 1451 HPD_FUNCS(bxt); 1452 HPD_FUNCS(icp); 1453 HPD_FUNCS(spt); 1454 HPD_FUNCS(ilk); 1455 #undef HPD_FUNCS 1456 1457 void intel_hpd_enable_detection(struct intel_encoder *encoder) 1458 { 1459 struct intel_display *display = to_intel_display(encoder); 1460 1461 if (display->funcs.hotplug) 1462 display->funcs.hotplug->hpd_enable_detection(encoder); 1463 } 1464 1465 void intel_hpd_irq_setup(struct intel_display *display) 1466 { 1467 if ((display->platform.valleyview || display->platform.cherryview) && 1468 !display->irq.vlv_display_irqs_enabled) 1469 return; 1470 1471 if (display->funcs.hotplug) 1472 display->funcs.hotplug->hpd_irq_setup(display); 1473 } 1474 1475 void intel_hotplug_irq_init(struct intel_display *display) 1476 { 1477 struct drm_i915_private *i915 = to_i915(display->drm); 1478 1479 intel_hpd_init_pins(display); 1480 1481 intel_hpd_init_early(display); 1482 1483 if (HAS_GMCH(display)) { 1484 if (HAS_HOTPLUG(display)) 1485 display->funcs.hotplug = &i915_hpd_funcs; 1486 } else { 1487 if (HAS_PCH_DG2(i915)) 1488 display->funcs.hotplug = &icp_hpd_funcs; 1489 else if (HAS_PCH_DG1(i915)) 1490 display->funcs.hotplug = &dg1_hpd_funcs; 1491 else if (DISPLAY_VER(display) >= 14) 1492 display->funcs.hotplug = &xelpdp_hpd_funcs; 1493 else if (DISPLAY_VER(display) >= 11) 1494 display->funcs.hotplug = &gen11_hpd_funcs; 1495 else if (display->platform.geminilake || display->platform.broxton) 1496 display->funcs.hotplug = &bxt_hpd_funcs; 1497 else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) 1498 display->funcs.hotplug = &icp_hpd_funcs; 1499 else if (INTEL_PCH_TYPE(i915) >= PCH_SPT) 1500 display->funcs.hotplug = &spt_hpd_funcs; 1501 else 1502 display->funcs.hotplug = &ilk_hpd_funcs; 1503 } 1504 } 1505