1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/intel/intel_lpe_audio.h> 42 43 #include "g4x_hdmi.h" 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_atomic.h" 47 #include "intel_audio.h" 48 #include "intel_connector.h" 49 #include "intel_cx0_phy.h" 50 #include "intel_ddi.h" 51 #include "intel_de.h" 52 #include "intel_display_driver.h" 53 #include "intel_display_types.h" 54 #include "intel_dp.h" 55 #include "intel_gmbus.h" 56 #include "intel_hdcp.h" 57 #include "intel_hdcp_regs.h" 58 #include "intel_hdmi.h" 59 #include "intel_lspcon.h" 60 #include "intel_panel.h" 61 #include "intel_snps_phy.h" 62 63 inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 64 { 65 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 66 } 67 68 static void 69 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 70 { 71 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 72 u32 enabled_bits; 73 74 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 75 76 drm_WARN(&dev_priv->drm, 77 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 78 "HDMI port enabled, expecting disabled\n"); 79 } 80 81 static void 82 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 83 enum transcoder cpu_transcoder) 84 { 85 drm_WARN(&dev_priv->drm, 86 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & 87 TRANS_DDI_FUNC_ENABLE, 88 "HDMI transcoder function enabled, expecting disabled\n"); 89 } 90 91 static u32 g4x_infoframe_index(unsigned int type) 92 { 93 switch (type) { 94 case HDMI_PACKET_TYPE_GAMUT_METADATA: 95 return VIDEO_DIP_SELECT_GAMUT; 96 case HDMI_INFOFRAME_TYPE_AVI: 97 return VIDEO_DIP_SELECT_AVI; 98 case HDMI_INFOFRAME_TYPE_SPD: 99 return VIDEO_DIP_SELECT_SPD; 100 case HDMI_INFOFRAME_TYPE_VENDOR: 101 return VIDEO_DIP_SELECT_VENDOR; 102 default: 103 MISSING_CASE(type); 104 return 0; 105 } 106 } 107 108 static u32 g4x_infoframe_enable(unsigned int type) 109 { 110 switch (type) { 111 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 112 return VIDEO_DIP_ENABLE_GCP; 113 case HDMI_PACKET_TYPE_GAMUT_METADATA: 114 return VIDEO_DIP_ENABLE_GAMUT; 115 case DP_SDP_VSC: 116 return 0; 117 case DP_SDP_ADAPTIVE_SYNC: 118 return 0; 119 case HDMI_INFOFRAME_TYPE_AVI: 120 return VIDEO_DIP_ENABLE_AVI; 121 case HDMI_INFOFRAME_TYPE_SPD: 122 return VIDEO_DIP_ENABLE_SPD; 123 case HDMI_INFOFRAME_TYPE_VENDOR: 124 return VIDEO_DIP_ENABLE_VENDOR; 125 case HDMI_INFOFRAME_TYPE_DRM: 126 return 0; 127 default: 128 MISSING_CASE(type); 129 return 0; 130 } 131 } 132 133 static u32 hsw_infoframe_enable(unsigned int type) 134 { 135 switch (type) { 136 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 137 return VIDEO_DIP_ENABLE_GCP_HSW; 138 case HDMI_PACKET_TYPE_GAMUT_METADATA: 139 return VIDEO_DIP_ENABLE_GMP_HSW; 140 case DP_SDP_VSC: 141 return VIDEO_DIP_ENABLE_VSC_HSW; 142 case DP_SDP_ADAPTIVE_SYNC: 143 return VIDEO_DIP_ENABLE_AS_ADL; 144 case DP_SDP_PPS: 145 return VDIP_ENABLE_PPS; 146 case HDMI_INFOFRAME_TYPE_AVI: 147 return VIDEO_DIP_ENABLE_AVI_HSW; 148 case HDMI_INFOFRAME_TYPE_SPD: 149 return VIDEO_DIP_ENABLE_SPD_HSW; 150 case HDMI_INFOFRAME_TYPE_VENDOR: 151 return VIDEO_DIP_ENABLE_VS_HSW; 152 case HDMI_INFOFRAME_TYPE_DRM: 153 return VIDEO_DIP_ENABLE_DRM_GLK; 154 default: 155 MISSING_CASE(type); 156 return 0; 157 } 158 } 159 160 static i915_reg_t 161 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 162 enum transcoder cpu_transcoder, 163 unsigned int type, 164 int i) 165 { 166 switch (type) { 167 case HDMI_PACKET_TYPE_GAMUT_METADATA: 168 return HSW_TVIDEO_DIP_GMP_DATA(dev_priv, cpu_transcoder, i); 169 case DP_SDP_VSC: 170 return HSW_TVIDEO_DIP_VSC_DATA(dev_priv, cpu_transcoder, i); 171 case DP_SDP_ADAPTIVE_SYNC: 172 return ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, cpu_transcoder, i); 173 case DP_SDP_PPS: 174 return ICL_VIDEO_DIP_PPS_DATA(dev_priv, cpu_transcoder, i); 175 case HDMI_INFOFRAME_TYPE_AVI: 176 return HSW_TVIDEO_DIP_AVI_DATA(dev_priv, cpu_transcoder, i); 177 case HDMI_INFOFRAME_TYPE_SPD: 178 return HSW_TVIDEO_DIP_SPD_DATA(dev_priv, cpu_transcoder, i); 179 case HDMI_INFOFRAME_TYPE_VENDOR: 180 return HSW_TVIDEO_DIP_VS_DATA(dev_priv, cpu_transcoder, i); 181 case HDMI_INFOFRAME_TYPE_DRM: 182 return GLK_TVIDEO_DIP_DRM_DATA(dev_priv, cpu_transcoder, i); 183 default: 184 MISSING_CASE(type); 185 return INVALID_MMIO_REG; 186 } 187 } 188 189 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 190 unsigned int type) 191 { 192 switch (type) { 193 case DP_SDP_VSC: 194 return VIDEO_DIP_VSC_DATA_SIZE; 195 case DP_SDP_ADAPTIVE_SYNC: 196 return VIDEO_DIP_ASYNC_DATA_SIZE; 197 case DP_SDP_PPS: 198 return VIDEO_DIP_PPS_DATA_SIZE; 199 case HDMI_PACKET_TYPE_GAMUT_METADATA: 200 if (DISPLAY_VER(dev_priv) >= 11) 201 return VIDEO_DIP_GMP_DATA_SIZE; 202 else 203 return VIDEO_DIP_DATA_SIZE; 204 default: 205 return VIDEO_DIP_DATA_SIZE; 206 } 207 } 208 209 static void g4x_write_infoframe(struct intel_encoder *encoder, 210 const struct intel_crtc_state *crtc_state, 211 unsigned int type, 212 const void *frame, ssize_t len) 213 { 214 const u32 *data = frame; 215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 216 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 217 int i; 218 219 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 220 "Writing DIP with CTL reg disabled\n"); 221 222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 223 val |= g4x_infoframe_index(type); 224 225 val &= ~g4x_infoframe_enable(type); 226 227 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 228 229 for (i = 0; i < len; i += 4) { 230 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 231 data++; 232 } 233 /* Write every possible data byte to force correct ECC calculation. */ 234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 235 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 236 237 val |= g4x_infoframe_enable(type); 238 val &= ~VIDEO_DIP_FREQ_MASK; 239 val |= VIDEO_DIP_FREQ_VSYNC; 240 241 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 242 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 243 } 244 245 static void g4x_read_infoframe(struct intel_encoder *encoder, 246 const struct intel_crtc_state *crtc_state, 247 unsigned int type, 248 void *frame, ssize_t len) 249 { 250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 251 u32 *data = frame; 252 int i; 253 254 intel_de_rmw(dev_priv, VIDEO_DIP_CTL, 255 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 256 257 for (i = 0; i < len; i += 4) 258 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 259 } 260 261 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 262 const struct intel_crtc_state *pipe_config) 263 { 264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 265 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 266 267 if ((val & VIDEO_DIP_ENABLE) == 0) 268 return 0; 269 270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 271 return 0; 272 273 return val & (VIDEO_DIP_ENABLE_AVI | 274 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 275 } 276 277 static void ibx_write_infoframe(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state, 279 unsigned int type, 280 const void *frame, ssize_t len) 281 { 282 const u32 *data = frame; 283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 286 u32 val = intel_de_read(dev_priv, reg); 287 int i; 288 289 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 290 "Writing DIP with CTL reg disabled\n"); 291 292 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 293 val |= g4x_infoframe_index(type); 294 295 val &= ~g4x_infoframe_enable(type); 296 297 intel_de_write(dev_priv, reg, val); 298 299 for (i = 0; i < len; i += 4) { 300 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 301 *data); 302 data++; 303 } 304 /* Write every possible data byte to force correct ECC calculation. */ 305 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 306 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 307 308 val |= g4x_infoframe_enable(type); 309 val &= ~VIDEO_DIP_FREQ_MASK; 310 val |= VIDEO_DIP_FREQ_VSYNC; 311 312 intel_de_write(dev_priv, reg, val); 313 intel_de_posting_read(dev_priv, reg); 314 } 315 316 static void ibx_read_infoframe(struct intel_encoder *encoder, 317 const struct intel_crtc_state *crtc_state, 318 unsigned int type, 319 void *frame, ssize_t len) 320 { 321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 u32 *data = frame; 324 int i; 325 326 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 327 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 328 329 for (i = 0; i < len; i += 4) 330 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 331 } 332 333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 334 const struct intel_crtc_state *pipe_config) 335 { 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 337 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 339 u32 val = intel_de_read(dev_priv, reg); 340 341 if ((val & VIDEO_DIP_ENABLE) == 0) 342 return 0; 343 344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 345 return 0; 346 347 return val & (VIDEO_DIP_ENABLE_AVI | 348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 350 } 351 352 static void cpt_write_infoframe(struct intel_encoder *encoder, 353 const struct intel_crtc_state *crtc_state, 354 unsigned int type, 355 const void *frame, ssize_t len) 356 { 357 const u32 *data = frame; 358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 361 u32 val = intel_de_read(dev_priv, reg); 362 int i; 363 364 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 365 "Writing DIP with CTL reg disabled\n"); 366 367 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 368 val |= g4x_infoframe_index(type); 369 370 /* The DIP control register spec says that we need to update the AVI 371 * infoframe without clearing its enable bit */ 372 if (type != HDMI_INFOFRAME_TYPE_AVI) 373 val &= ~g4x_infoframe_enable(type); 374 375 intel_de_write(dev_priv, reg, val); 376 377 for (i = 0; i < len; i += 4) { 378 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 379 *data); 380 data++; 381 } 382 /* Write every possible data byte to force correct ECC calculation. */ 383 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 384 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 385 386 val |= g4x_infoframe_enable(type); 387 val &= ~VIDEO_DIP_FREQ_MASK; 388 val |= VIDEO_DIP_FREQ_VSYNC; 389 390 intel_de_write(dev_priv, reg, val); 391 intel_de_posting_read(dev_priv, reg); 392 } 393 394 static void cpt_read_infoframe(struct intel_encoder *encoder, 395 const struct intel_crtc_state *crtc_state, 396 unsigned int type, 397 void *frame, ssize_t len) 398 { 399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 401 u32 *data = frame; 402 int i; 403 404 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 405 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 406 407 for (i = 0; i < len; i += 4) 408 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 409 } 410 411 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 412 const struct intel_crtc_state *pipe_config) 413 { 414 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 416 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 417 418 if ((val & VIDEO_DIP_ENABLE) == 0) 419 return 0; 420 421 return val & (VIDEO_DIP_ENABLE_AVI | 422 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 423 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 424 } 425 426 static void vlv_write_infoframe(struct intel_encoder *encoder, 427 const struct intel_crtc_state *crtc_state, 428 unsigned int type, 429 const void *frame, ssize_t len) 430 { 431 const u32 *data = frame; 432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 435 u32 val = intel_de_read(dev_priv, reg); 436 int i; 437 438 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 439 "Writing DIP with CTL reg disabled\n"); 440 441 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 442 val |= g4x_infoframe_index(type); 443 444 val &= ~g4x_infoframe_enable(type); 445 446 intel_de_write(dev_priv, reg, val); 447 448 for (i = 0; i < len; i += 4) { 449 intel_de_write(dev_priv, 450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 451 data++; 452 } 453 /* Write every possible data byte to force correct ECC calculation. */ 454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 455 intel_de_write(dev_priv, 456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 457 458 val |= g4x_infoframe_enable(type); 459 val &= ~VIDEO_DIP_FREQ_MASK; 460 val |= VIDEO_DIP_FREQ_VSYNC; 461 462 intel_de_write(dev_priv, reg, val); 463 intel_de_posting_read(dev_priv, reg); 464 } 465 466 static void vlv_read_infoframe(struct intel_encoder *encoder, 467 const struct intel_crtc_state *crtc_state, 468 unsigned int type, 469 void *frame, ssize_t len) 470 { 471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 473 u32 *data = frame; 474 int i; 475 476 intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), 477 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 478 479 for (i = 0; i < len; i += 4) 480 *data++ = intel_de_read(dev_priv, 481 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 482 } 483 484 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 485 const struct intel_crtc_state *pipe_config) 486 { 487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 488 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 489 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 490 491 if ((val & VIDEO_DIP_ENABLE) == 0) 492 return 0; 493 494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 495 return 0; 496 497 return val & (VIDEO_DIP_ENABLE_AVI | 498 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 499 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 500 } 501 502 void hsw_write_infoframe(struct intel_encoder *encoder, 503 const struct intel_crtc_state *crtc_state, 504 unsigned int type, 505 const void *frame, ssize_t len) 506 { 507 const u32 *data = frame; 508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 510 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(dev_priv, cpu_transcoder); 511 int data_size; 512 int i; 513 u32 val = intel_de_read(dev_priv, ctl_reg); 514 515 data_size = hsw_dip_data_size(dev_priv, type); 516 517 drm_WARN_ON(&dev_priv->drm, len > data_size); 518 519 val &= ~hsw_infoframe_enable(type); 520 intel_de_write(dev_priv, ctl_reg, val); 521 522 for (i = 0; i < len; i += 4) { 523 intel_de_write(dev_priv, 524 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 525 *data); 526 data++; 527 } 528 /* Write every possible data byte to force correct ECC calculation. */ 529 for (; i < data_size; i += 4) 530 intel_de_write(dev_priv, 531 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 532 0); 533 534 /* Wa_14013475917 */ 535 if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && 536 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 537 val |= hsw_infoframe_enable(type); 538 539 if (type == DP_SDP_VSC) 540 val |= VSC_DIP_HW_DATA_SW_HEA; 541 542 intel_de_write(dev_priv, ctl_reg, val); 543 intel_de_posting_read(dev_priv, ctl_reg); 544 } 545 546 void hsw_read_infoframe(struct intel_encoder *encoder, 547 const struct intel_crtc_state *crtc_state, 548 unsigned int type, void *frame, ssize_t len) 549 { 550 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 551 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 552 u32 *data = frame; 553 int i; 554 555 for (i = 0; i < len; i += 4) 556 *data++ = intel_de_read(dev_priv, 557 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 558 } 559 560 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 561 const struct intel_crtc_state *pipe_config) 562 { 563 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 564 u32 val = intel_de_read(dev_priv, 565 HSW_TVIDEO_DIP_CTL(dev_priv, pipe_config->cpu_transcoder)); 566 u32 mask; 567 568 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 569 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 570 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 571 572 if (DISPLAY_VER(dev_priv) >= 10) 573 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 574 575 if (HAS_AS_SDP(dev_priv)) 576 mask |= VIDEO_DIP_ENABLE_AS_ADL; 577 578 return val & mask; 579 } 580 581 static const u8 infoframe_type_to_idx[] = { 582 HDMI_PACKET_TYPE_GENERAL_CONTROL, 583 HDMI_PACKET_TYPE_GAMUT_METADATA, 584 DP_SDP_VSC, 585 DP_SDP_ADAPTIVE_SYNC, 586 HDMI_INFOFRAME_TYPE_AVI, 587 HDMI_INFOFRAME_TYPE_SPD, 588 HDMI_INFOFRAME_TYPE_VENDOR, 589 HDMI_INFOFRAME_TYPE_DRM, 590 }; 591 592 u32 intel_hdmi_infoframe_enable(unsigned int type) 593 { 594 int i; 595 596 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 597 if (infoframe_type_to_idx[i] == type) 598 return BIT(i); 599 } 600 601 return 0; 602 } 603 604 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 605 const struct intel_crtc_state *crtc_state) 606 { 607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 608 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 609 u32 val, ret = 0; 610 int i; 611 612 val = dig_port->infoframes_enabled(encoder, crtc_state); 613 614 /* map from hardware bits to dip idx */ 615 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 616 unsigned int type = infoframe_type_to_idx[i]; 617 618 if (HAS_DDI(dev_priv)) { 619 if (val & hsw_infoframe_enable(type)) 620 ret |= BIT(i); 621 } else { 622 if (val & g4x_infoframe_enable(type)) 623 ret |= BIT(i); 624 } 625 } 626 627 return ret; 628 } 629 630 /* 631 * The data we write to the DIP data buffer registers is 1 byte bigger than the 632 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 633 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 634 * used for both technologies. 635 * 636 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 637 * DW1: DB3 | DB2 | DB1 | DB0 638 * DW2: DB7 | DB6 | DB5 | DB4 639 * DW3: ... 640 * 641 * (HB is Header Byte, DB is Data Byte) 642 * 643 * The hdmi pack() functions don't know about that hardware specific hole so we 644 * trick them by giving an offset into the buffer and moving back the header 645 * bytes by one. 646 */ 647 static void intel_write_infoframe(struct intel_encoder *encoder, 648 const struct intel_crtc_state *crtc_state, 649 enum hdmi_infoframe_type type, 650 const union hdmi_infoframe *frame) 651 { 652 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 653 u8 buffer[VIDEO_DIP_DATA_SIZE]; 654 ssize_t len; 655 656 if ((crtc_state->infoframes.enable & 657 intel_hdmi_infoframe_enable(type)) == 0) 658 return; 659 660 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 661 return; 662 663 /* see comment above for the reason for this offset */ 664 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 665 if (drm_WARN_ON(encoder->base.dev, len < 0)) 666 return; 667 668 /* Insert the 'hole' (see big comment above) at position 3 */ 669 memmove(&buffer[0], &buffer[1], 3); 670 buffer[3] = 0; 671 len++; 672 673 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 674 } 675 676 void intel_read_infoframe(struct intel_encoder *encoder, 677 const struct intel_crtc_state *crtc_state, 678 enum hdmi_infoframe_type type, 679 union hdmi_infoframe *frame) 680 { 681 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 682 u8 buffer[VIDEO_DIP_DATA_SIZE]; 683 int ret; 684 685 if ((crtc_state->infoframes.enable & 686 intel_hdmi_infoframe_enable(type)) == 0) 687 return; 688 689 dig_port->read_infoframe(encoder, crtc_state, 690 type, buffer, sizeof(buffer)); 691 692 /* Fill the 'hole' (see big comment above) at position 3 */ 693 memmove(&buffer[1], &buffer[0], 3); 694 695 /* see comment above for the reason for this offset */ 696 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 697 if (ret) { 698 drm_dbg_kms(encoder->base.dev, 699 "Failed to unpack infoframe type 0x%02x\n", type); 700 return; 701 } 702 703 if (frame->any.type != type) 704 drm_dbg_kms(encoder->base.dev, 705 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 706 frame->any.type, type); 707 } 708 709 static bool 710 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 711 struct intel_crtc_state *crtc_state, 712 struct drm_connector_state *conn_state) 713 { 714 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 715 const struct drm_display_mode *adjusted_mode = 716 &crtc_state->hw.adjusted_mode; 717 struct drm_connector *connector = conn_state->connector; 718 int ret; 719 720 if (!crtc_state->has_infoframe) 721 return true; 722 723 crtc_state->infoframes.enable |= 724 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 725 726 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 727 adjusted_mode); 728 if (ret) 729 return false; 730 731 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 732 frame->colorspace = HDMI_COLORSPACE_YUV420; 733 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 734 frame->colorspace = HDMI_COLORSPACE_YUV444; 735 else 736 frame->colorspace = HDMI_COLORSPACE_RGB; 737 738 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 739 740 /* nonsense combination */ 741 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 742 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 743 744 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 745 drm_hdmi_avi_infoframe_quant_range(frame, connector, 746 adjusted_mode, 747 crtc_state->limited_color_range ? 748 HDMI_QUANTIZATION_RANGE_LIMITED : 749 HDMI_QUANTIZATION_RANGE_FULL); 750 } else { 751 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 752 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 753 } 754 755 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 756 757 /* TODO: handle pixel repetition for YCBCR420 outputs */ 758 759 ret = hdmi_avi_infoframe_check(frame); 760 if (drm_WARN_ON(encoder->base.dev, ret)) 761 return false; 762 763 return true; 764 } 765 766 static bool 767 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 768 struct intel_crtc_state *crtc_state, 769 struct drm_connector_state *conn_state) 770 { 771 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 772 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 773 int ret; 774 775 if (!crtc_state->has_infoframe) 776 return true; 777 778 crtc_state->infoframes.enable |= 779 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 780 781 if (IS_DGFX(i915)) 782 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 783 else 784 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 785 786 if (drm_WARN_ON(encoder->base.dev, ret)) 787 return false; 788 789 frame->sdi = HDMI_SPD_SDI_PC; 790 791 ret = hdmi_spd_infoframe_check(frame); 792 if (drm_WARN_ON(encoder->base.dev, ret)) 793 return false; 794 795 return true; 796 } 797 798 static bool 799 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 800 struct intel_crtc_state *crtc_state, 801 struct drm_connector_state *conn_state) 802 { 803 struct hdmi_vendor_infoframe *frame = 804 &crtc_state->infoframes.hdmi.vendor.hdmi; 805 const struct drm_display_info *info = 806 &conn_state->connector->display_info; 807 int ret; 808 809 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 810 return true; 811 812 crtc_state->infoframes.enable |= 813 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 814 815 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 816 conn_state->connector, 817 &crtc_state->hw.adjusted_mode); 818 if (drm_WARN_ON(encoder->base.dev, ret)) 819 return false; 820 821 ret = hdmi_vendor_infoframe_check(frame); 822 if (drm_WARN_ON(encoder->base.dev, ret)) 823 return false; 824 825 return true; 826 } 827 828 static bool 829 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 830 struct intel_crtc_state *crtc_state, 831 struct drm_connector_state *conn_state) 832 { 833 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 834 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 835 int ret; 836 837 if (DISPLAY_VER(dev_priv) < 10) 838 return true; 839 840 if (!crtc_state->has_infoframe) 841 return true; 842 843 if (!conn_state->hdr_output_metadata) 844 return true; 845 846 crtc_state->infoframes.enable |= 847 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 848 849 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 850 if (ret < 0) { 851 drm_dbg_kms(&dev_priv->drm, 852 "couldn't set HDR metadata in infoframe\n"); 853 return false; 854 } 855 856 ret = hdmi_drm_infoframe_check(frame); 857 if (drm_WARN_ON(&dev_priv->drm, ret)) 858 return false; 859 860 return true; 861 } 862 863 static void g4x_set_infoframes(struct intel_encoder *encoder, 864 bool enable, 865 const struct intel_crtc_state *crtc_state, 866 const struct drm_connector_state *conn_state) 867 { 868 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 869 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 870 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 871 i915_reg_t reg = VIDEO_DIP_CTL; 872 u32 val = intel_de_read(dev_priv, reg); 873 u32 port = VIDEO_DIP_PORT(encoder->port); 874 875 assert_hdmi_port_disabled(intel_hdmi); 876 877 /* If the registers were not initialized yet, they might be zeroes, 878 * which means we're selecting the AVI DIP and we're setting its 879 * frequency to once. This seems to really confuse the HW and make 880 * things stop working (the register spec says the AVI always needs to 881 * be sent every VSync). So here we avoid writing to the register more 882 * than we need and also explicitly select the AVI DIP and explicitly 883 * set its frequency to every VSync. Avoiding to write it twice seems to 884 * be enough to solve the problem, but being defensive shouldn't hurt us 885 * either. */ 886 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 887 888 if (!enable) { 889 if (!(val & VIDEO_DIP_ENABLE)) 890 return; 891 if (port != (val & VIDEO_DIP_PORT_MASK)) { 892 drm_dbg_kms(&dev_priv->drm, 893 "video DIP still enabled on port %c\n", 894 (val & VIDEO_DIP_PORT_MASK) >> 29); 895 return; 896 } 897 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 898 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 899 intel_de_write(dev_priv, reg, val); 900 intel_de_posting_read(dev_priv, reg); 901 return; 902 } 903 904 if (port != (val & VIDEO_DIP_PORT_MASK)) { 905 if (val & VIDEO_DIP_ENABLE) { 906 drm_dbg_kms(&dev_priv->drm, 907 "video DIP already enabled on port %c\n", 908 (val & VIDEO_DIP_PORT_MASK) >> 29); 909 return; 910 } 911 val &= ~VIDEO_DIP_PORT_MASK; 912 val |= port; 913 } 914 915 val |= VIDEO_DIP_ENABLE; 916 val &= ~(VIDEO_DIP_ENABLE_AVI | 917 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 918 919 intel_de_write(dev_priv, reg, val); 920 intel_de_posting_read(dev_priv, reg); 921 922 intel_write_infoframe(encoder, crtc_state, 923 HDMI_INFOFRAME_TYPE_AVI, 924 &crtc_state->infoframes.avi); 925 intel_write_infoframe(encoder, crtc_state, 926 HDMI_INFOFRAME_TYPE_SPD, 927 &crtc_state->infoframes.spd); 928 intel_write_infoframe(encoder, crtc_state, 929 HDMI_INFOFRAME_TYPE_VENDOR, 930 &crtc_state->infoframes.hdmi); 931 } 932 933 /* 934 * Determine if default_phase=1 can be indicated in the GCP infoframe. 935 * 936 * From HDMI specification 1.4a: 937 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 938 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 939 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 940 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 941 * phase of 0 942 */ 943 static bool gcp_default_phase_possible(int pipe_bpp, 944 const struct drm_display_mode *mode) 945 { 946 unsigned int pixels_per_group; 947 948 switch (pipe_bpp) { 949 case 30: 950 /* 4 pixels in 5 clocks */ 951 pixels_per_group = 4; 952 break; 953 case 36: 954 /* 2 pixels in 3 clocks */ 955 pixels_per_group = 2; 956 break; 957 case 48: 958 /* 1 pixel in 2 clocks */ 959 pixels_per_group = 1; 960 break; 961 default: 962 /* phase information not relevant for 8bpc */ 963 return false; 964 } 965 966 return mode->crtc_hdisplay % pixels_per_group == 0 && 967 mode->crtc_htotal % pixels_per_group == 0 && 968 mode->crtc_hblank_start % pixels_per_group == 0 && 969 mode->crtc_hblank_end % pixels_per_group == 0 && 970 mode->crtc_hsync_start % pixels_per_group == 0 && 971 mode->crtc_hsync_end % pixels_per_group == 0 && 972 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 973 mode->crtc_htotal/2 % pixels_per_group == 0); 974 } 975 976 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 977 const struct intel_crtc_state *crtc_state, 978 const struct drm_connector_state *conn_state) 979 { 980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 982 i915_reg_t reg; 983 984 if ((crtc_state->infoframes.enable & 985 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 986 return false; 987 988 if (HAS_DDI(dev_priv)) 989 reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder); 990 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 991 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 992 else if (HAS_PCH_SPLIT(dev_priv)) 993 reg = TVIDEO_DIP_GCP(crtc->pipe); 994 else 995 return false; 996 997 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 998 999 return true; 1000 } 1001 1002 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1003 struct intel_crtc_state *crtc_state) 1004 { 1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1007 i915_reg_t reg; 1008 1009 if ((crtc_state->infoframes.enable & 1010 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1011 return; 1012 1013 if (HAS_DDI(dev_priv)) 1014 reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder); 1015 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1016 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1017 else if (HAS_PCH_SPLIT(dev_priv)) 1018 reg = TVIDEO_DIP_GCP(crtc->pipe); 1019 else 1020 return; 1021 1022 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1023 } 1024 1025 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1026 struct intel_crtc_state *crtc_state, 1027 struct drm_connector_state *conn_state) 1028 { 1029 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1030 1031 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1032 return; 1033 1034 crtc_state->infoframes.enable |= 1035 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1036 1037 /* Indicate color indication for deep color mode */ 1038 if (crtc_state->pipe_bpp > 24) 1039 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1040 1041 /* Enable default_phase whenever the display mode is suitably aligned */ 1042 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1043 &crtc_state->hw.adjusted_mode)) 1044 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1045 } 1046 1047 static void ibx_set_infoframes(struct intel_encoder *encoder, 1048 bool enable, 1049 const struct intel_crtc_state *crtc_state, 1050 const struct drm_connector_state *conn_state) 1051 { 1052 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1053 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1054 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1055 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1056 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1057 u32 val = intel_de_read(dev_priv, reg); 1058 u32 port = VIDEO_DIP_PORT(encoder->port); 1059 1060 assert_hdmi_port_disabled(intel_hdmi); 1061 1062 /* See the big comment in g4x_set_infoframes() */ 1063 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1064 1065 if (!enable) { 1066 if (!(val & VIDEO_DIP_ENABLE)) 1067 return; 1068 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1069 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1070 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1071 intel_de_write(dev_priv, reg, val); 1072 intel_de_posting_read(dev_priv, reg); 1073 return; 1074 } 1075 1076 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1077 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1078 "DIP already enabled on port %c\n", 1079 (val & VIDEO_DIP_PORT_MASK) >> 29); 1080 val &= ~VIDEO_DIP_PORT_MASK; 1081 val |= port; 1082 } 1083 1084 val |= VIDEO_DIP_ENABLE; 1085 val &= ~(VIDEO_DIP_ENABLE_AVI | 1086 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1087 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1088 1089 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1090 val |= VIDEO_DIP_ENABLE_GCP; 1091 1092 intel_de_write(dev_priv, reg, val); 1093 intel_de_posting_read(dev_priv, reg); 1094 1095 intel_write_infoframe(encoder, crtc_state, 1096 HDMI_INFOFRAME_TYPE_AVI, 1097 &crtc_state->infoframes.avi); 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_SPD, 1100 &crtc_state->infoframes.spd); 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_VENDOR, 1103 &crtc_state->infoframes.hdmi); 1104 } 1105 1106 static void cpt_set_infoframes(struct intel_encoder *encoder, 1107 bool enable, 1108 const struct intel_crtc_state *crtc_state, 1109 const struct drm_connector_state *conn_state) 1110 { 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1113 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1114 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1115 u32 val = intel_de_read(dev_priv, reg); 1116 1117 assert_hdmi_port_disabled(intel_hdmi); 1118 1119 /* See the big comment in g4x_set_infoframes() */ 1120 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1121 1122 if (!enable) { 1123 if (!(val & VIDEO_DIP_ENABLE)) 1124 return; 1125 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1126 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1127 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1128 intel_de_write(dev_priv, reg, val); 1129 intel_de_posting_read(dev_priv, reg); 1130 return; 1131 } 1132 1133 /* Set both together, unset both together: see the spec. */ 1134 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1135 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1136 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1137 1138 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1139 val |= VIDEO_DIP_ENABLE_GCP; 1140 1141 intel_de_write(dev_priv, reg, val); 1142 intel_de_posting_read(dev_priv, reg); 1143 1144 intel_write_infoframe(encoder, crtc_state, 1145 HDMI_INFOFRAME_TYPE_AVI, 1146 &crtc_state->infoframes.avi); 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_SPD, 1149 &crtc_state->infoframes.spd); 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_VENDOR, 1152 &crtc_state->infoframes.hdmi); 1153 } 1154 1155 static void vlv_set_infoframes(struct intel_encoder *encoder, 1156 bool enable, 1157 const struct intel_crtc_state *crtc_state, 1158 const struct drm_connector_state *conn_state) 1159 { 1160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1161 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1162 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1163 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1164 u32 val = intel_de_read(dev_priv, reg); 1165 u32 port = VIDEO_DIP_PORT(encoder->port); 1166 1167 assert_hdmi_port_disabled(intel_hdmi); 1168 1169 /* See the big comment in g4x_set_infoframes() */ 1170 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1171 1172 if (!enable) { 1173 if (!(val & VIDEO_DIP_ENABLE)) 1174 return; 1175 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1176 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1177 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1178 intel_de_write(dev_priv, reg, val); 1179 intel_de_posting_read(dev_priv, reg); 1180 return; 1181 } 1182 1183 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1184 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1185 "DIP already enabled on port %c\n", 1186 (val & VIDEO_DIP_PORT_MASK) >> 29); 1187 val &= ~VIDEO_DIP_PORT_MASK; 1188 val |= port; 1189 } 1190 1191 val |= VIDEO_DIP_ENABLE; 1192 val &= ~(VIDEO_DIP_ENABLE_AVI | 1193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1194 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1195 1196 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1197 val |= VIDEO_DIP_ENABLE_GCP; 1198 1199 intel_de_write(dev_priv, reg, val); 1200 intel_de_posting_read(dev_priv, reg); 1201 1202 intel_write_infoframe(encoder, crtc_state, 1203 HDMI_INFOFRAME_TYPE_AVI, 1204 &crtc_state->infoframes.avi); 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_SPD, 1207 &crtc_state->infoframes.spd); 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_VENDOR, 1210 &crtc_state->infoframes.hdmi); 1211 } 1212 1213 static void hsw_set_infoframes(struct intel_encoder *encoder, 1214 bool enable, 1215 const struct intel_crtc_state *crtc_state, 1216 const struct drm_connector_state *conn_state) 1217 { 1218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1219 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv, 1220 crtc_state->cpu_transcoder); 1221 u32 val = intel_de_read(dev_priv, reg); 1222 1223 assert_hdmi_transcoder_func_disabled(dev_priv, 1224 crtc_state->cpu_transcoder); 1225 1226 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1227 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1228 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1229 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1230 1231 if (!enable) { 1232 intel_de_write(dev_priv, reg, val); 1233 intel_de_posting_read(dev_priv, reg); 1234 return; 1235 } 1236 1237 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1238 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1239 1240 intel_de_write(dev_priv, reg, val); 1241 intel_de_posting_read(dev_priv, reg); 1242 1243 intel_write_infoframe(encoder, crtc_state, 1244 HDMI_INFOFRAME_TYPE_AVI, 1245 &crtc_state->infoframes.avi); 1246 intel_write_infoframe(encoder, crtc_state, 1247 HDMI_INFOFRAME_TYPE_SPD, 1248 &crtc_state->infoframes.spd); 1249 intel_write_infoframe(encoder, crtc_state, 1250 HDMI_INFOFRAME_TYPE_VENDOR, 1251 &crtc_state->infoframes.hdmi); 1252 intel_write_infoframe(encoder, crtc_state, 1253 HDMI_INFOFRAME_TYPE_DRM, 1254 &crtc_state->infoframes.drm); 1255 } 1256 1257 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1258 { 1259 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1260 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1261 1262 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1263 return; 1264 1265 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1266 enable ? "Enabling" : "Disabling"); 1267 1268 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, 1269 hdmi->dp_dual_mode.type, ddc, enable); 1270 } 1271 1272 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1273 unsigned int offset, void *buffer, size_t size) 1274 { 1275 struct intel_hdmi *hdmi = &dig_port->hdmi; 1276 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1277 int ret; 1278 u8 start = offset & 0xff; 1279 struct i2c_msg msgs[] = { 1280 { 1281 .addr = DRM_HDCP_DDC_ADDR, 1282 .flags = 0, 1283 .len = 1, 1284 .buf = &start, 1285 }, 1286 { 1287 .addr = DRM_HDCP_DDC_ADDR, 1288 .flags = I2C_M_RD, 1289 .len = size, 1290 .buf = buffer 1291 } 1292 }; 1293 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1294 if (ret == ARRAY_SIZE(msgs)) 1295 return 0; 1296 return ret >= 0 ? -EIO : ret; 1297 } 1298 1299 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1300 unsigned int offset, void *buffer, size_t size) 1301 { 1302 struct intel_hdmi *hdmi = &dig_port->hdmi; 1303 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1304 int ret; 1305 u8 *write_buf; 1306 struct i2c_msg msg; 1307 1308 write_buf = kzalloc(size + 1, GFP_KERNEL); 1309 if (!write_buf) 1310 return -ENOMEM; 1311 1312 write_buf[0] = offset & 0xff; 1313 memcpy(&write_buf[1], buffer, size); 1314 1315 msg.addr = DRM_HDCP_DDC_ADDR; 1316 msg.flags = 0, 1317 msg.len = size + 1, 1318 msg.buf = write_buf; 1319 1320 ret = i2c_transfer(ddc, &msg, 1); 1321 if (ret == 1) 1322 ret = 0; 1323 else if (ret >= 0) 1324 ret = -EIO; 1325 1326 kfree(write_buf); 1327 return ret; 1328 } 1329 1330 static 1331 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1332 u8 *an) 1333 { 1334 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1335 struct intel_hdmi *hdmi = &dig_port->hdmi; 1336 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1337 int ret; 1338 1339 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1340 DRM_HDCP_AN_LEN); 1341 if (ret) { 1342 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1343 ret); 1344 return ret; 1345 } 1346 1347 ret = intel_gmbus_output_aksv(ddc); 1348 if (ret < 0) { 1349 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1350 return ret; 1351 } 1352 return 0; 1353 } 1354 1355 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1356 u8 *bksv) 1357 { 1358 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1359 1360 int ret; 1361 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1362 DRM_HDCP_KSV_LEN); 1363 if (ret) 1364 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1365 ret); 1366 return ret; 1367 } 1368 1369 static 1370 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1371 u8 *bstatus) 1372 { 1373 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1374 1375 int ret; 1376 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1377 bstatus, DRM_HDCP_BSTATUS_LEN); 1378 if (ret) 1379 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1380 ret); 1381 return ret; 1382 } 1383 1384 static 1385 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1386 bool *repeater_present) 1387 { 1388 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1389 int ret; 1390 u8 val; 1391 1392 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1393 if (ret) { 1394 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1395 ret); 1396 return ret; 1397 } 1398 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1399 return 0; 1400 } 1401 1402 static 1403 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1404 u8 *ri_prime) 1405 { 1406 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1407 1408 int ret; 1409 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1410 ri_prime, DRM_HDCP_RI_LEN); 1411 if (ret) 1412 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1413 ret); 1414 return ret; 1415 } 1416 1417 static 1418 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1419 bool *ksv_ready) 1420 { 1421 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1422 int ret; 1423 u8 val; 1424 1425 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1426 if (ret) { 1427 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1428 ret); 1429 return ret; 1430 } 1431 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1432 return 0; 1433 } 1434 1435 static 1436 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1437 int num_downstream, u8 *ksv_fifo) 1438 { 1439 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1440 int ret; 1441 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1442 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1443 if (ret) { 1444 drm_dbg_kms(&i915->drm, 1445 "Read ksv fifo over DDC failed (%d)\n", ret); 1446 return ret; 1447 } 1448 return 0; 1449 } 1450 1451 static 1452 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1453 int i, u32 *part) 1454 { 1455 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1456 int ret; 1457 1458 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1459 return -EINVAL; 1460 1461 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1462 part, DRM_HDCP_V_PRIME_PART_LEN); 1463 if (ret) 1464 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1465 i, ret); 1466 return ret; 1467 } 1468 1469 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1470 enum transcoder cpu_transcoder) 1471 { 1472 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1473 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1474 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1475 u32 scanline; 1476 int ret; 1477 1478 for (;;) { 1479 scanline = intel_de_read(dev_priv, 1480 PIPEDSL(dev_priv, crtc->pipe)); 1481 if (scanline > 100 && scanline < 200) 1482 break; 1483 usleep_range(25, 50); 1484 } 1485 1486 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1487 false, TRANS_DDI_HDCP_SIGNALLING); 1488 if (ret) { 1489 drm_err(&dev_priv->drm, 1490 "Disable HDCP signalling failed (%d)\n", ret); 1491 return ret; 1492 } 1493 1494 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1495 true, TRANS_DDI_HDCP_SIGNALLING); 1496 if (ret) { 1497 drm_err(&dev_priv->drm, 1498 "Enable HDCP signalling failed (%d)\n", ret); 1499 return ret; 1500 } 1501 1502 return 0; 1503 } 1504 1505 static 1506 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1507 enum transcoder cpu_transcoder, 1508 bool enable) 1509 { 1510 struct intel_hdmi *hdmi = &dig_port->hdmi; 1511 struct intel_connector *connector = hdmi->attached_connector; 1512 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1513 int ret; 1514 1515 if (!enable) 1516 usleep_range(6, 60); /* Bspec says >= 6us */ 1517 1518 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1519 cpu_transcoder, enable, 1520 TRANS_DDI_HDCP_SIGNALLING); 1521 if (ret) { 1522 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1523 enable ? "Enable" : "Disable", ret); 1524 return ret; 1525 } 1526 1527 /* 1528 * WA: To fix incorrect positioning of the window of 1529 * opportunity and enc_en signalling in KABYLAKE. 1530 */ 1531 if (IS_KABYLAKE(dev_priv) && enable) 1532 return kbl_repositioning_enc_en_signal(connector, 1533 cpu_transcoder); 1534 1535 return 0; 1536 } 1537 1538 static 1539 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1540 struct intel_connector *connector) 1541 { 1542 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1543 enum port port = dig_port->base.port; 1544 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1545 int ret; 1546 union { 1547 u32 reg; 1548 u8 shim[DRM_HDCP_RI_LEN]; 1549 } ri; 1550 1551 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1552 if (ret) 1553 return false; 1554 1555 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1556 1557 /* Wait for Ri prime match */ 1558 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1559 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1560 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1561 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1562 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1563 port))); 1564 return false; 1565 } 1566 return true; 1567 } 1568 1569 static 1570 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1571 struct intel_connector *connector) 1572 { 1573 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1574 int retry; 1575 1576 for (retry = 0; retry < 3; retry++) 1577 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1578 return true; 1579 1580 drm_err(&i915->drm, "Link check failed\n"); 1581 return false; 1582 } 1583 1584 struct hdcp2_hdmi_msg_timeout { 1585 u8 msg_id; 1586 u16 timeout; 1587 }; 1588 1589 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1590 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1591 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1592 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1593 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1594 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1595 }; 1596 1597 static 1598 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1599 u8 *rx_status) 1600 { 1601 return intel_hdmi_hdcp_read(dig_port, 1602 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1603 rx_status, 1604 HDCP_2_2_HDMI_RXSTATUS_LEN); 1605 } 1606 1607 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1608 { 1609 int i; 1610 1611 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1612 if (is_paired) 1613 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1614 else 1615 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1616 } 1617 1618 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1619 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1620 return hdcp2_msg_timeout[i].timeout; 1621 } 1622 1623 return -EINVAL; 1624 } 1625 1626 static int 1627 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1628 u8 msg_id, bool *msg_ready, 1629 ssize_t *msg_sz) 1630 { 1631 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1632 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1633 int ret; 1634 1635 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1636 if (ret < 0) { 1637 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1638 ret); 1639 return ret; 1640 } 1641 1642 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1643 rx_status[0]); 1644 1645 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1646 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1647 *msg_sz); 1648 else 1649 *msg_ready = *msg_sz; 1650 1651 return 0; 1652 } 1653 1654 static ssize_t 1655 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1656 u8 msg_id, bool paired) 1657 { 1658 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1659 bool msg_ready = false; 1660 int timeout, ret; 1661 ssize_t msg_sz = 0; 1662 1663 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1664 if (timeout < 0) 1665 return timeout; 1666 1667 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1668 msg_id, &msg_ready, 1669 &msg_sz), 1670 !ret && msg_ready && msg_sz, timeout * 1000, 1671 1000, 5 * 1000); 1672 if (ret) 1673 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1674 msg_id, ret, timeout); 1675 1676 return ret ? ret : msg_sz; 1677 } 1678 1679 static 1680 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1681 void *buf, size_t size) 1682 { 1683 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1684 unsigned int offset; 1685 1686 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1687 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1688 } 1689 1690 static 1691 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1692 u8 msg_id, void *buf, size_t size) 1693 { 1694 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1695 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1696 struct intel_hdmi *hdmi = &dig_port->hdmi; 1697 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1698 unsigned int offset; 1699 ssize_t ret; 1700 1701 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1702 hdcp->is_paired); 1703 if (ret < 0) 1704 return ret; 1705 1706 /* 1707 * Available msg size should be equal to or lesser than the 1708 * available buffer. 1709 */ 1710 if (ret > size) { 1711 drm_dbg_kms(&i915->drm, 1712 "msg_sz(%zd) is more than exp size(%zu)\n", 1713 ret, size); 1714 return -EINVAL; 1715 } 1716 1717 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1718 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1719 if (ret) 1720 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1721 msg_id, ret); 1722 1723 return ret; 1724 } 1725 1726 static 1727 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1728 struct intel_connector *connector) 1729 { 1730 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1731 int ret; 1732 1733 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1734 if (ret) 1735 return ret; 1736 1737 /* 1738 * Re-auth request and Link Integrity Failures are represented by 1739 * same bit. i.e reauth_req. 1740 */ 1741 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1742 ret = HDCP_REAUTH_REQUEST; 1743 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1744 ret = HDCP_TOPOLOGY_CHANGE; 1745 1746 return ret; 1747 } 1748 1749 static 1750 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1751 bool *capable) 1752 { 1753 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1754 u8 hdcp2_version; 1755 int ret; 1756 1757 *capable = false; 1758 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1759 &hdcp2_version, sizeof(hdcp2_version)); 1760 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1761 *capable = true; 1762 1763 return ret; 1764 } 1765 1766 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1767 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1768 .read_bksv = intel_hdmi_hdcp_read_bksv, 1769 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1770 .repeater_present = intel_hdmi_hdcp_repeater_present, 1771 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1772 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1773 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1774 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1775 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1776 .check_link = intel_hdmi_hdcp_check_link, 1777 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1778 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1779 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1780 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1781 .protocol = HDCP_PROTOCOL_HDMI, 1782 }; 1783 1784 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1785 { 1786 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1787 int max_tmds_clock, vbt_max_tmds_clock; 1788 1789 if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_S(dev_priv)) 1790 max_tmds_clock = 600000; 1791 else if (DISPLAY_VER(dev_priv) >= 10) 1792 max_tmds_clock = 594000; 1793 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1794 max_tmds_clock = 300000; 1795 else if (DISPLAY_VER(dev_priv) >= 5) 1796 max_tmds_clock = 225000; 1797 else 1798 max_tmds_clock = 165000; 1799 1800 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1801 if (vbt_max_tmds_clock) 1802 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1803 1804 return max_tmds_clock; 1805 } 1806 1807 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1808 const struct drm_connector_state *conn_state) 1809 { 1810 struct intel_connector *connector = hdmi->attached_connector; 1811 1812 return connector->base.display_info.is_hdmi && 1813 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1814 } 1815 1816 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1817 { 1818 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1819 } 1820 1821 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1822 bool respect_downstream_limits, 1823 bool has_hdmi_sink) 1824 { 1825 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1826 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1827 1828 if (respect_downstream_limits) { 1829 struct intel_connector *connector = hdmi->attached_connector; 1830 const struct drm_display_info *info = &connector->base.display_info; 1831 1832 if (hdmi->dp_dual_mode.max_tmds_clock) 1833 max_tmds_clock = min(max_tmds_clock, 1834 hdmi->dp_dual_mode.max_tmds_clock); 1835 1836 if (info->max_tmds_clock) 1837 max_tmds_clock = min(max_tmds_clock, 1838 info->max_tmds_clock); 1839 else if (!has_hdmi_sink) 1840 max_tmds_clock = min(max_tmds_clock, 165000); 1841 } 1842 1843 return max_tmds_clock; 1844 } 1845 1846 static enum drm_mode_status 1847 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1848 int clock, bool respect_downstream_limits, 1849 bool has_hdmi_sink) 1850 { 1851 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1852 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1853 1854 if (clock < 25000) 1855 return MODE_CLOCK_LOW; 1856 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1857 has_hdmi_sink)) 1858 return MODE_CLOCK_HIGH; 1859 1860 /* GLK DPLL can't generate 446-480 MHz */ 1861 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1862 return MODE_CLOCK_RANGE; 1863 1864 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1865 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1866 clock > 223333 && clock < 240000) 1867 return MODE_CLOCK_RANGE; 1868 1869 /* CHV DPLL can't generate 216-240 MHz */ 1870 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1871 return MODE_CLOCK_RANGE; 1872 1873 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1874 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1875 return MODE_CLOCK_RANGE; 1876 1877 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1878 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1879 return MODE_CLOCK_RANGE; 1880 1881 /* 1882 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1883 * set of link rates. 1884 * 1885 * FIXME: We will hopefully get an algorithmic way of programming 1886 * the MPLLB for HDMI in the future. 1887 */ 1888 if (DISPLAY_VER(dev_priv) >= 14) 1889 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); 1890 else if (IS_DG2(dev_priv)) 1891 return intel_snps_phy_check_hdmi_link_rate(clock); 1892 1893 return MODE_OK; 1894 } 1895 1896 int intel_hdmi_tmds_clock(int clock, int bpc, 1897 enum intel_output_format sink_format) 1898 { 1899 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1900 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1901 clock /= 2; 1902 1903 /* 1904 * Need to adjust the port link by: 1905 * 1.5x for 12bpc 1906 * 1.25x for 10bpc 1907 */ 1908 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1909 } 1910 1911 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1912 { 1913 switch (bpc) { 1914 case 12: 1915 return !HAS_GMCH(i915); 1916 case 10: 1917 return DISPLAY_VER(i915) >= 11; 1918 case 8: 1919 return true; 1920 default: 1921 MISSING_CASE(bpc); 1922 return false; 1923 } 1924 } 1925 1926 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1927 int bpc, bool has_hdmi_sink, 1928 enum intel_output_format sink_format) 1929 { 1930 const struct drm_display_info *info = &connector->display_info; 1931 const struct drm_hdmi_info *hdmi = &info->hdmi; 1932 1933 switch (bpc) { 1934 case 12: 1935 if (!has_hdmi_sink) 1936 return false; 1937 1938 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1939 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1940 else 1941 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1942 case 10: 1943 if (!has_hdmi_sink) 1944 return false; 1945 1946 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1947 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1948 else 1949 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1950 case 8: 1951 return true; 1952 default: 1953 MISSING_CASE(bpc); 1954 return false; 1955 } 1956 } 1957 1958 static enum drm_mode_status 1959 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1960 bool has_hdmi_sink, 1961 enum intel_output_format sink_format) 1962 { 1963 struct drm_i915_private *i915 = to_i915(connector->dev); 1964 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1965 enum drm_mode_status status = MODE_OK; 1966 int bpc; 1967 1968 /* 1969 * Try all color depths since valid port clock range 1970 * can have holes. Any mode that can be used with at 1971 * least one color depth is accepted. 1972 */ 1973 for (bpc = 12; bpc >= 8; bpc -= 2) { 1974 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1975 1976 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1977 continue; 1978 1979 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 1980 continue; 1981 1982 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1983 if (status == MODE_OK) 1984 return MODE_OK; 1985 } 1986 1987 /* can never happen */ 1988 drm_WARN_ON(&i915->drm, status == MODE_OK); 1989 1990 return status; 1991 } 1992 1993 static enum drm_mode_status 1994 intel_hdmi_mode_valid(struct drm_connector *connector, 1995 struct drm_display_mode *mode) 1996 { 1997 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1998 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1999 enum drm_mode_status status; 2000 int clock = mode->clock; 2001 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 2002 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2003 bool ycbcr_420_only; 2004 enum intel_output_format sink_format; 2005 2006 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 2007 if (status != MODE_OK) 2008 return status; 2009 2010 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2011 clock *= 2; 2012 2013 if (clock > max_dotclk) 2014 return MODE_CLOCK_HIGH; 2015 2016 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2017 if (!has_hdmi_sink) 2018 return MODE_CLOCK_LOW; 2019 clock *= 2; 2020 } 2021 2022 /* 2023 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2024 * enumerated only if FRL is supported. Current platforms do not support 2025 * FRL so prune the higher resolution modes that require doctclock more 2026 * than 600MHz. 2027 */ 2028 if (clock > 600000) 2029 return MODE_CLOCK_HIGH; 2030 2031 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2032 2033 if (ycbcr_420_only) 2034 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2035 else 2036 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2037 2038 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2039 if (status != MODE_OK) { 2040 if (ycbcr_420_only || 2041 !connector->ycbcr_420_allowed || 2042 !drm_mode_is_420_also(&connector->display_info, mode)) 2043 return status; 2044 2045 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2046 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2047 if (status != MODE_OK) 2048 return status; 2049 } 2050 2051 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2052 } 2053 2054 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2055 int bpc, bool has_hdmi_sink) 2056 { 2057 struct drm_atomic_state *state = crtc_state->uapi.state; 2058 struct drm_connector_state *connector_state; 2059 struct drm_connector *connector; 2060 int i; 2061 2062 for_each_new_connector_in_state(state, connector, connector_state, i) { 2063 if (connector_state->crtc != crtc_state->uapi.crtc) 2064 continue; 2065 2066 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2067 crtc_state->sink_format)) 2068 return false; 2069 } 2070 2071 return true; 2072 } 2073 2074 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2075 { 2076 struct drm_i915_private *dev_priv = 2077 to_i915(crtc_state->uapi.crtc->dev); 2078 const struct drm_display_mode *adjusted_mode = 2079 &crtc_state->hw.adjusted_mode; 2080 2081 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2082 return false; 2083 2084 /* Display Wa_1405510057:icl,ehl */ 2085 if (intel_hdmi_is_ycbcr420(crtc_state) && 2086 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2087 (adjusted_mode->crtc_hblank_end - 2088 adjusted_mode->crtc_hblank_start) % 8 == 2) 2089 return false; 2090 2091 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2092 } 2093 2094 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2095 struct intel_crtc_state *crtc_state, 2096 int clock, bool respect_downstream_limits) 2097 { 2098 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2099 int bpc; 2100 2101 /* 2102 * pipe_bpp could already be below 8bpc due to FDI 2103 * bandwidth constraints. HDMI minimum is 8bpc however. 2104 */ 2105 bpc = max(crtc_state->pipe_bpp / 3, 8); 2106 2107 /* 2108 * We will never exceed downstream TMDS clock limits while 2109 * attempting deep color. If the user insists on forcing an 2110 * out of spec mode they will have to be satisfied with 8bpc. 2111 */ 2112 if (!respect_downstream_limits) 2113 bpc = 8; 2114 2115 for (; bpc >= 8; bpc -= 2) { 2116 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2117 crtc_state->sink_format); 2118 2119 if (hdmi_bpc_possible(crtc_state, bpc) && 2120 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2121 respect_downstream_limits, 2122 crtc_state->has_hdmi_sink) == MODE_OK) 2123 return bpc; 2124 } 2125 2126 return -EINVAL; 2127 } 2128 2129 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2130 struct intel_crtc_state *crtc_state, 2131 bool respect_downstream_limits) 2132 { 2133 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2134 const struct drm_display_mode *adjusted_mode = 2135 &crtc_state->hw.adjusted_mode; 2136 int bpc, clock = adjusted_mode->crtc_clock; 2137 2138 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2139 clock *= 2; 2140 2141 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2142 respect_downstream_limits); 2143 if (bpc < 0) 2144 return bpc; 2145 2146 crtc_state->port_clock = 2147 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2148 2149 /* 2150 * pipe_bpp could already be below 8bpc due to 2151 * FDI bandwidth constraints. We shouldn't bump it 2152 * back up to the HDMI minimum 8bpc in that case. 2153 */ 2154 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2155 2156 drm_dbg_kms(&i915->drm, 2157 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2158 bpc, crtc_state->pipe_bpp); 2159 2160 return 0; 2161 } 2162 2163 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2164 const struct drm_connector_state *conn_state) 2165 { 2166 const struct intel_digital_connector_state *intel_conn_state = 2167 to_intel_digital_connector_state(conn_state); 2168 const struct drm_display_mode *adjusted_mode = 2169 &crtc_state->hw.adjusted_mode; 2170 2171 /* 2172 * Our YCbCr output is always limited range. 2173 * crtc_state->limited_color_range only applies to RGB, 2174 * and it must never be set for YCbCr or we risk setting 2175 * some conflicting bits in TRANSCONF which will mess up 2176 * the colors on the monitor. 2177 */ 2178 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2179 return false; 2180 2181 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2182 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2183 return crtc_state->has_hdmi_sink && 2184 drm_default_rgb_quant_range(adjusted_mode) == 2185 HDMI_QUANTIZATION_RANGE_LIMITED; 2186 } else { 2187 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2188 } 2189 } 2190 2191 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2192 const struct intel_crtc_state *crtc_state, 2193 const struct drm_connector_state *conn_state) 2194 { 2195 struct drm_connector *connector = conn_state->connector; 2196 const struct intel_digital_connector_state *intel_conn_state = 2197 to_intel_digital_connector_state(conn_state); 2198 2199 if (!crtc_state->has_hdmi_sink) 2200 return false; 2201 2202 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2203 return connector->display_info.has_audio; 2204 else 2205 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2206 } 2207 2208 static enum intel_output_format 2209 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2210 struct intel_connector *connector, 2211 bool ycbcr_420_output) 2212 { 2213 if (!crtc_state->has_hdmi_sink) 2214 return INTEL_OUTPUT_FORMAT_RGB; 2215 2216 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2217 return INTEL_OUTPUT_FORMAT_YCBCR420; 2218 else 2219 return INTEL_OUTPUT_FORMAT_RGB; 2220 } 2221 2222 static enum intel_output_format 2223 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2224 { 2225 return crtc_state->sink_format; 2226 } 2227 2228 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2229 struct intel_crtc_state *crtc_state, 2230 const struct drm_connector_state *conn_state, 2231 bool respect_downstream_limits) 2232 { 2233 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2234 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2235 const struct drm_display_info *info = &connector->base.display_info; 2236 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2237 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2238 int ret; 2239 2240 crtc_state->sink_format = 2241 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2242 2243 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2244 drm_dbg_kms(&i915->drm, 2245 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2246 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2247 } 2248 2249 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2250 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2251 if (ret) { 2252 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2253 !crtc_state->has_hdmi_sink || 2254 !connector->base.ycbcr_420_allowed || 2255 !drm_mode_is_420_also(info, adjusted_mode)) 2256 return ret; 2257 2258 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2259 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2260 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2261 } 2262 2263 return ret; 2264 } 2265 2266 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2267 { 2268 return crtc_state->uapi.encoder_mask && 2269 !is_power_of_2(crtc_state->uapi.encoder_mask); 2270 } 2271 2272 static bool source_supports_scrambling(struct intel_encoder *encoder) 2273 { 2274 /* 2275 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2276 * scrambling is supported. 2277 * But there seem to be cases where certain platforms that support 2278 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2279 * capped by VBT to less than 340MHz. 2280 * 2281 * In such cases when an HDMI2.0 sink is connected, it creates a 2282 * problem : the platform and the sink both support scrambling but the 2283 * HDMI 1.4 retimer chip doesn't. 2284 * 2285 * So go for scrambling, based on the max tmds clock taking into account, 2286 * restrictions coming from VBT. 2287 */ 2288 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2289 } 2290 2291 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2292 const struct intel_crtc_state *crtc_state, 2293 const struct drm_connector_state *conn_state) 2294 { 2295 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2296 2297 return intel_has_hdmi_sink(hdmi, conn_state) && 2298 !intel_hdmi_is_cloned(crtc_state); 2299 } 2300 2301 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2302 struct intel_crtc_state *pipe_config, 2303 struct drm_connector_state *conn_state) 2304 { 2305 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2306 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2307 struct drm_connector *connector = conn_state->connector; 2308 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2309 int ret; 2310 2311 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2312 return -EINVAL; 2313 2314 if (!connector->interlace_allowed && 2315 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2316 return -EINVAL; 2317 2318 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2319 2320 if (pipe_config->has_hdmi_sink) 2321 pipe_config->has_infoframe = true; 2322 2323 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2324 pipe_config->pixel_multiplier = 2; 2325 2326 pipe_config->has_audio = 2327 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2328 intel_audio_compute_config(encoder, pipe_config, conn_state); 2329 2330 /* 2331 * Try to respect downstream TMDS clock limits first, if 2332 * that fails assume the user might know something we don't. 2333 */ 2334 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2335 if (ret) 2336 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2337 if (ret) { 2338 drm_dbg_kms(&dev_priv->drm, 2339 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2340 pipe_config->hw.adjusted_mode.crtc_clock); 2341 return ret; 2342 } 2343 2344 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2345 ret = intel_panel_fitting(pipe_config, conn_state); 2346 if (ret) 2347 return ret; 2348 } 2349 2350 pipe_config->limited_color_range = 2351 intel_hdmi_limited_color_range(pipe_config, conn_state); 2352 2353 if (conn_state->picture_aspect_ratio) 2354 adjusted_mode->picture_aspect_ratio = 2355 conn_state->picture_aspect_ratio; 2356 2357 pipe_config->lane_count = 4; 2358 2359 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2360 if (scdc->scrambling.low_rates) 2361 pipe_config->hdmi_scrambling = true; 2362 2363 if (pipe_config->port_clock > 340000) { 2364 pipe_config->hdmi_scrambling = true; 2365 pipe_config->hdmi_high_tmds_clock_ratio = true; 2366 } 2367 } 2368 2369 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2370 conn_state); 2371 2372 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2373 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2374 return -EINVAL; 2375 } 2376 2377 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2378 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2379 return -EINVAL; 2380 } 2381 2382 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2383 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2384 return -EINVAL; 2385 } 2386 2387 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2388 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2389 return -EINVAL; 2390 } 2391 2392 return 0; 2393 } 2394 2395 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2396 { 2397 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2398 2399 /* 2400 * Give a hand to buggy BIOSen which forget to turn 2401 * the TMDS output buffers back on after a reboot. 2402 */ 2403 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2404 } 2405 2406 static void 2407 intel_hdmi_unset_edid(struct drm_connector *connector) 2408 { 2409 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2410 2411 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2412 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2413 2414 drm_edid_free(to_intel_connector(connector)->detect_edid); 2415 to_intel_connector(connector)->detect_edid = NULL; 2416 } 2417 2418 static void 2419 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2420 { 2421 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2422 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2423 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2424 struct i2c_adapter *ddc = connector->ddc; 2425 enum drm_dp_dual_mode_type type; 2426 2427 type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc); 2428 2429 /* 2430 * Type 1 DVI adaptors are not required to implement any 2431 * registers, so we can't always detect their presence. 2432 * Ideally we should be able to check the state of the 2433 * CONFIG1 pin, but no such luck on our hardware. 2434 * 2435 * The only method left to us is to check the VBT to see 2436 * if the port is a dual mode capable DP port. 2437 */ 2438 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2439 if (!connector->force && 2440 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2441 drm_dbg_kms(&dev_priv->drm, 2442 "Assuming DP dual mode adaptor presence based on VBT\n"); 2443 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2444 } else { 2445 type = DRM_DP_DUAL_MODE_NONE; 2446 } 2447 } 2448 2449 if (type == DRM_DP_DUAL_MODE_NONE) 2450 return; 2451 2452 hdmi->dp_dual_mode.type = type; 2453 hdmi->dp_dual_mode.max_tmds_clock = 2454 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc); 2455 2456 drm_dbg_kms(&dev_priv->drm, 2457 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2458 drm_dp_get_dual_mode_type_name(type), 2459 hdmi->dp_dual_mode.max_tmds_clock); 2460 2461 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2462 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2463 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2464 drm_dbg_kms(&dev_priv->drm, 2465 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2466 hdmi->dp_dual_mode.max_tmds_clock = 0; 2467 } 2468 } 2469 2470 static bool 2471 intel_hdmi_set_edid(struct drm_connector *connector) 2472 { 2473 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2474 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2475 struct i2c_adapter *ddc = connector->ddc; 2476 intel_wakeref_t wakeref; 2477 const struct drm_edid *drm_edid; 2478 bool connected = false; 2479 2480 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2481 2482 drm_edid = drm_edid_read_ddc(connector, ddc); 2483 2484 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2485 drm_dbg_kms(&dev_priv->drm, 2486 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2487 intel_gmbus_force_bit(ddc, true); 2488 drm_edid = drm_edid_read_ddc(connector, ddc); 2489 intel_gmbus_force_bit(ddc, false); 2490 } 2491 2492 /* Below we depend on display info having been updated */ 2493 drm_edid_connector_update(connector, drm_edid); 2494 2495 to_intel_connector(connector)->detect_edid = drm_edid; 2496 2497 if (drm_edid_is_digital(drm_edid)) { 2498 intel_hdmi_dp_dual_mode_detect(connector); 2499 2500 connected = true; 2501 } 2502 2503 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2504 2505 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2506 connector->display_info.source_physical_address); 2507 2508 return connected; 2509 } 2510 2511 static enum drm_connector_status 2512 intel_hdmi_detect(struct drm_connector *connector, bool force) 2513 { 2514 enum drm_connector_status status = connector_status_disconnected; 2515 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2516 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2517 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2518 intel_wakeref_t wakeref; 2519 2520 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2521 connector->base.id, connector->name); 2522 2523 if (!intel_display_device_enabled(dev_priv)) 2524 return connector_status_disconnected; 2525 2526 if (!intel_display_driver_check_access(dev_priv)) 2527 return connector->status; 2528 2529 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2530 2531 if (DISPLAY_VER(dev_priv) >= 11 && 2532 !intel_digital_port_connected(encoder)) 2533 goto out; 2534 2535 intel_hdmi_unset_edid(connector); 2536 2537 if (intel_hdmi_set_edid(connector)) 2538 status = connector_status_connected; 2539 2540 out: 2541 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2542 2543 if (status != connector_status_connected) 2544 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2545 2546 return status; 2547 } 2548 2549 static void 2550 intel_hdmi_force(struct drm_connector *connector) 2551 { 2552 struct drm_i915_private *i915 = to_i915(connector->dev); 2553 2554 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2555 connector->base.id, connector->name); 2556 2557 if (!intel_display_driver_check_access(i915)) 2558 return; 2559 2560 intel_hdmi_unset_edid(connector); 2561 2562 if (connector->status != connector_status_connected) 2563 return; 2564 2565 intel_hdmi_set_edid(connector); 2566 } 2567 2568 static int intel_hdmi_get_modes(struct drm_connector *connector) 2569 { 2570 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2571 return drm_edid_connector_add_modes(connector); 2572 } 2573 2574 static int 2575 intel_hdmi_connector_register(struct drm_connector *connector) 2576 { 2577 int ret; 2578 2579 ret = intel_connector_register(connector); 2580 if (ret) 2581 return ret; 2582 2583 return ret; 2584 } 2585 2586 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2587 { 2588 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2589 2590 cec_notifier_conn_unregister(n); 2591 2592 intel_connector_unregister(connector); 2593 } 2594 2595 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2596 .detect = intel_hdmi_detect, 2597 .force = intel_hdmi_force, 2598 .fill_modes = drm_helper_probe_single_connector_modes, 2599 .atomic_get_property = intel_digital_connector_atomic_get_property, 2600 .atomic_set_property = intel_digital_connector_atomic_set_property, 2601 .late_register = intel_hdmi_connector_register, 2602 .early_unregister = intel_hdmi_connector_unregister, 2603 .destroy = intel_connector_destroy, 2604 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2605 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2606 }; 2607 2608 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2609 struct drm_atomic_state *state) 2610 { 2611 struct drm_i915_private *i915 = to_i915(state->dev); 2612 2613 if (HAS_DDI(i915)) 2614 return intel_digital_connector_atomic_check(connector, state); 2615 else 2616 return g4x_hdmi_connector_atomic_check(connector, state); 2617 } 2618 2619 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2620 .get_modes = intel_hdmi_get_modes, 2621 .mode_valid = intel_hdmi_mode_valid, 2622 .atomic_check = intel_hdmi_connector_atomic_check, 2623 }; 2624 2625 static void 2626 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2627 { 2628 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2629 2630 intel_attach_force_audio_property(connector); 2631 intel_attach_broadcast_rgb_property(connector); 2632 intel_attach_aspect_ratio_property(connector); 2633 2634 intel_attach_hdmi_colorspace_property(connector); 2635 drm_connector_attach_content_type_property(connector); 2636 2637 if (DISPLAY_VER(dev_priv) >= 10) 2638 drm_connector_attach_hdr_output_metadata_property(connector); 2639 2640 if (!HAS_GMCH(dev_priv)) 2641 drm_connector_attach_max_bpc_property(connector, 8, 12); 2642 } 2643 2644 /* 2645 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2646 * @encoder: intel_encoder 2647 * @connector: drm_connector 2648 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2649 * or reset the high tmds clock ratio for scrambling 2650 * @scrambling: bool to Indicate if the function needs to set or reset 2651 * sink scrambling 2652 * 2653 * This function handles scrambling on HDMI 2.0 capable sinks. 2654 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2655 * it enables scrambling. This should be called before enabling the HDMI 2656 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2657 * detect a scrambled clock within 100 ms. 2658 * 2659 * Returns: 2660 * True on success, false on failure. 2661 */ 2662 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2663 struct drm_connector *connector, 2664 bool high_tmds_clock_ratio, 2665 bool scrambling) 2666 { 2667 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2668 struct drm_scrambling *sink_scrambling = 2669 &connector->display_info.hdmi.scdc.scrambling; 2670 2671 if (!sink_scrambling->supported) 2672 return true; 2673 2674 drm_dbg_kms(&dev_priv->drm, 2675 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2676 connector->base.id, connector->name, 2677 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2678 2679 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2680 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2681 drm_scdc_set_scrambling(connector, scrambling); 2682 } 2683 2684 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2685 { 2686 enum port port = encoder->port; 2687 u8 ddc_pin; 2688 2689 switch (port) { 2690 case PORT_B: 2691 ddc_pin = GMBUS_PIN_DPB; 2692 break; 2693 case PORT_C: 2694 ddc_pin = GMBUS_PIN_DPC; 2695 break; 2696 case PORT_D: 2697 ddc_pin = GMBUS_PIN_DPD_CHV; 2698 break; 2699 default: 2700 MISSING_CASE(port); 2701 ddc_pin = GMBUS_PIN_DPB; 2702 break; 2703 } 2704 return ddc_pin; 2705 } 2706 2707 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2708 { 2709 enum port port = encoder->port; 2710 u8 ddc_pin; 2711 2712 switch (port) { 2713 case PORT_B: 2714 ddc_pin = GMBUS_PIN_1_BXT; 2715 break; 2716 case PORT_C: 2717 ddc_pin = GMBUS_PIN_2_BXT; 2718 break; 2719 default: 2720 MISSING_CASE(port); 2721 ddc_pin = GMBUS_PIN_1_BXT; 2722 break; 2723 } 2724 return ddc_pin; 2725 } 2726 2727 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2728 { 2729 enum port port = encoder->port; 2730 u8 ddc_pin; 2731 2732 switch (port) { 2733 case PORT_B: 2734 ddc_pin = GMBUS_PIN_1_BXT; 2735 break; 2736 case PORT_C: 2737 ddc_pin = GMBUS_PIN_2_BXT; 2738 break; 2739 case PORT_D: 2740 ddc_pin = GMBUS_PIN_4_CNP; 2741 break; 2742 case PORT_F: 2743 ddc_pin = GMBUS_PIN_3_BXT; 2744 break; 2745 default: 2746 MISSING_CASE(port); 2747 ddc_pin = GMBUS_PIN_1_BXT; 2748 break; 2749 } 2750 return ddc_pin; 2751 } 2752 2753 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2754 { 2755 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2756 enum port port = encoder->port; 2757 2758 if (intel_encoder_is_combo(encoder)) 2759 return GMBUS_PIN_1_BXT + port; 2760 else if (intel_encoder_is_tc(encoder)) 2761 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2762 2763 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2764 return GMBUS_PIN_2_BXT; 2765 } 2766 2767 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2768 { 2769 enum phy phy = intel_encoder_to_phy(encoder); 2770 u8 ddc_pin; 2771 2772 switch (phy) { 2773 case PHY_A: 2774 ddc_pin = GMBUS_PIN_1_BXT; 2775 break; 2776 case PHY_B: 2777 ddc_pin = GMBUS_PIN_2_BXT; 2778 break; 2779 case PHY_C: 2780 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2781 break; 2782 default: 2783 MISSING_CASE(phy); 2784 ddc_pin = GMBUS_PIN_1_BXT; 2785 break; 2786 } 2787 return ddc_pin; 2788 } 2789 2790 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2791 { 2792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2793 enum phy phy = intel_encoder_to_phy(encoder); 2794 2795 WARN_ON(encoder->port == PORT_C); 2796 2797 /* 2798 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2799 * final two outputs use type-c pins, even though they're actually 2800 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2801 * all outputs. 2802 */ 2803 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2804 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2805 2806 return GMBUS_PIN_1_BXT + phy; 2807 } 2808 2809 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2810 { 2811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2812 enum phy phy = intel_encoder_to_phy(encoder); 2813 2814 drm_WARN_ON(&i915->drm, encoder->port == PORT_A); 2815 2816 /* 2817 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2818 * final two outputs use type-c pins, even though they're actually 2819 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2820 * all outputs. 2821 */ 2822 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2823 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2824 2825 return GMBUS_PIN_1_BXT + phy; 2826 } 2827 2828 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2829 { 2830 return intel_encoder_to_phy(encoder) + 1; 2831 } 2832 2833 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2834 { 2835 enum phy phy = intel_encoder_to_phy(encoder); 2836 2837 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2838 2839 /* 2840 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2841 * except first combo output. 2842 */ 2843 if (phy == PHY_A) 2844 return GMBUS_PIN_1_BXT; 2845 2846 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2847 } 2848 2849 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2850 { 2851 enum port port = encoder->port; 2852 u8 ddc_pin; 2853 2854 switch (port) { 2855 case PORT_B: 2856 ddc_pin = GMBUS_PIN_DPB; 2857 break; 2858 case PORT_C: 2859 ddc_pin = GMBUS_PIN_DPC; 2860 break; 2861 case PORT_D: 2862 ddc_pin = GMBUS_PIN_DPD; 2863 break; 2864 default: 2865 MISSING_CASE(port); 2866 ddc_pin = GMBUS_PIN_DPB; 2867 break; 2868 } 2869 return ddc_pin; 2870 } 2871 2872 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2873 { 2874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2875 u8 ddc_pin; 2876 2877 if (IS_ALDERLAKE_S(dev_priv)) 2878 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2879 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2880 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2881 else if (IS_ROCKETLAKE(dev_priv)) 2882 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2883 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2884 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2885 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2886 HAS_PCH_TGP(dev_priv)) 2887 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2888 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2889 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2890 else if (HAS_PCH_CNP(dev_priv)) 2891 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2892 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2893 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2894 else if (IS_CHERRYVIEW(dev_priv)) 2895 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2896 else 2897 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2898 2899 return ddc_pin; 2900 } 2901 2902 static struct intel_encoder * 2903 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2904 { 2905 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2906 struct intel_encoder *other; 2907 2908 for_each_intel_encoder(&i915->drm, other) { 2909 struct intel_connector *connector; 2910 2911 if (other == encoder) 2912 continue; 2913 2914 if (!intel_encoder_is_dig_port(other)) 2915 continue; 2916 2917 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2918 2919 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) 2920 return other; 2921 } 2922 2923 return NULL; 2924 } 2925 2926 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2927 { 2928 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2929 struct intel_encoder *other; 2930 const char *source; 2931 u8 ddc_pin; 2932 2933 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2934 source = "VBT"; 2935 2936 if (!ddc_pin) { 2937 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2938 source = "platform default"; 2939 } 2940 2941 if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) { 2942 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2943 encoder->base.base.id, encoder->base.name, ddc_pin); 2944 return 0; 2945 } 2946 2947 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2948 if (other) { 2949 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2950 encoder->base.base.id, encoder->base.name, ddc_pin, 2951 other->base.base.id, other->base.name); 2952 return 0; 2953 } 2954 2955 drm_dbg_kms(&i915->drm, 2956 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2957 encoder->base.base.id, encoder->base.name, 2958 ddc_pin, source); 2959 2960 return ddc_pin; 2961 } 2962 2963 void intel_infoframe_init(struct intel_digital_port *dig_port) 2964 { 2965 struct drm_i915_private *dev_priv = 2966 to_i915(dig_port->base.base.dev); 2967 2968 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2969 dig_port->write_infoframe = vlv_write_infoframe; 2970 dig_port->read_infoframe = vlv_read_infoframe; 2971 dig_port->set_infoframes = vlv_set_infoframes; 2972 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2973 } else if (IS_G4X(dev_priv)) { 2974 dig_port->write_infoframe = g4x_write_infoframe; 2975 dig_port->read_infoframe = g4x_read_infoframe; 2976 dig_port->set_infoframes = g4x_set_infoframes; 2977 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2978 } else if (HAS_DDI(dev_priv)) { 2979 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 2980 dig_port->write_infoframe = lspcon_write_infoframe; 2981 dig_port->read_infoframe = lspcon_read_infoframe; 2982 dig_port->set_infoframes = lspcon_set_infoframes; 2983 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2984 } else { 2985 dig_port->write_infoframe = hsw_write_infoframe; 2986 dig_port->read_infoframe = hsw_read_infoframe; 2987 dig_port->set_infoframes = hsw_set_infoframes; 2988 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2989 } 2990 } else if (HAS_PCH_IBX(dev_priv)) { 2991 dig_port->write_infoframe = ibx_write_infoframe; 2992 dig_port->read_infoframe = ibx_read_infoframe; 2993 dig_port->set_infoframes = ibx_set_infoframes; 2994 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2995 } else { 2996 dig_port->write_infoframe = cpt_write_infoframe; 2997 dig_port->read_infoframe = cpt_read_infoframe; 2998 dig_port->set_infoframes = cpt_set_infoframes; 2999 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3000 } 3001 } 3002 3003 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3004 struct intel_connector *intel_connector) 3005 { 3006 struct drm_connector *connector = &intel_connector->base; 3007 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3008 struct intel_encoder *intel_encoder = &dig_port->base; 3009 struct drm_device *dev = intel_encoder->base.dev; 3010 struct drm_i915_private *dev_priv = to_i915(dev); 3011 enum port port = intel_encoder->port; 3012 struct cec_connector_info conn_info; 3013 u8 ddc_pin; 3014 3015 drm_dbg_kms(&dev_priv->drm, 3016 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3017 intel_encoder->base.base.id, intel_encoder->base.name); 3018 3019 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3020 return; 3021 3022 if (drm_WARN(dev, dig_port->max_lanes < 4, 3023 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3024 dig_port->max_lanes, intel_encoder->base.base.id, 3025 intel_encoder->base.name)) 3026 return; 3027 3028 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3029 if (!ddc_pin) 3030 return; 3031 3032 drm_connector_init_with_ddc(dev, connector, 3033 &intel_hdmi_connector_funcs, 3034 DRM_MODE_CONNECTOR_HDMIA, 3035 intel_gmbus_get_adapter(dev_priv, ddc_pin)); 3036 3037 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3038 3039 if (DISPLAY_VER(dev_priv) < 12) 3040 connector->interlace_allowed = true; 3041 3042 connector->stereo_allowed = true; 3043 3044 if (DISPLAY_VER(dev_priv) >= 10) 3045 connector->ycbcr_420_allowed = true; 3046 3047 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3048 intel_connector->base.polled = intel_connector->polled; 3049 3050 if (HAS_DDI(dev_priv)) 3051 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3052 else 3053 intel_connector->get_hw_state = intel_connector_get_hw_state; 3054 3055 intel_hdmi_add_properties(intel_hdmi, connector); 3056 3057 intel_connector_attach_encoder(intel_connector, intel_encoder); 3058 intel_hdmi->attached_connector = intel_connector; 3059 3060 if (is_hdcp_supported(dev_priv, port)) { 3061 int ret = intel_hdcp_init(intel_connector, dig_port, 3062 &intel_hdmi_hdcp_shim); 3063 if (ret) 3064 drm_dbg_kms(&dev_priv->drm, 3065 "HDCP init failed, skipping.\n"); 3066 } 3067 3068 cec_fill_conn_info_from_drm(&conn_info, connector); 3069 3070 intel_hdmi->cec_notifier = 3071 cec_notifier_conn_register(dev->dev, port_identifier(port), 3072 &conn_info); 3073 if (!intel_hdmi->cec_notifier) 3074 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3075 } 3076 3077 /* 3078 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3079 * @vactive: Vactive of a display mode 3080 * 3081 * @return: appropriate dsc slice height for a given mode. 3082 */ 3083 int intel_hdmi_dsc_get_slice_height(int vactive) 3084 { 3085 int slice_height; 3086 3087 /* 3088 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3089 * Select smallest slice height >=96, that results in a valid PPS and 3090 * requires minimum padding lines required for final slice. 3091 * 3092 * Assumption : Vactive is even. 3093 */ 3094 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3095 if (vactive % slice_height == 0) 3096 return slice_height; 3097 3098 return 0; 3099 } 3100 3101 /* 3102 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3103 * and dsc decoder capabilities 3104 * 3105 * @crtc_state: intel crtc_state 3106 * @src_max_slices: maximum slices supported by the DSC encoder 3107 * @src_max_slice_width: maximum slice width supported by DSC encoder 3108 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3109 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3110 * 3111 * @return: num of dsc slices that can be supported by the dsc encoder 3112 * and decoder. 3113 */ 3114 int 3115 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3116 int src_max_slices, int src_max_slice_width, 3117 int hdmi_max_slices, int hdmi_throughput) 3118 { 3119 /* Pixel rates in KPixels/sec */ 3120 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3121 /* 3122 * Rates at which the source and sink are required to process pixels in each 3123 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3124 */ 3125 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3126 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3127 3128 /* Spec limits the slice width to 2720 pixels */ 3129 #define MAX_HDMI_SLICE_WIDTH 2720 3130 int kslice_adjust; 3131 int adjusted_clk_khz; 3132 int min_slices; 3133 int target_slices; 3134 int max_throughput; /* max clock freq. in khz per slice */ 3135 int max_slice_width; 3136 int slice_width; 3137 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3138 3139 if (!hdmi_throughput) 3140 return 0; 3141 3142 /* 3143 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3144 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3145 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3146 * dividing adjusted clock value by 10. 3147 */ 3148 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3149 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3150 kslice_adjust = 10; 3151 else 3152 kslice_adjust = 5; 3153 3154 /* 3155 * As per spec, the rate at which the source and the sink process 3156 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3157 * This depends upon the pixel clock rate and output formats 3158 * (kslice adjust). 3159 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3160 * at max 340MHz, otherwise they can be processed at max 400MHz. 3161 */ 3162 3163 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3164 3165 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3166 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3167 else 3168 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3169 3170 /* 3171 * Taking into account the sink's capability for maximum 3172 * clock per slice (in MHz) as read from HF-VSDB. 3173 */ 3174 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3175 3176 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3177 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3178 3179 /* 3180 * Keep on increasing the num of slices/line, starting from min_slices 3181 * per line till we get such a number, for which the slice_width is 3182 * just less than max_slice_width. The slices/line selected should be 3183 * less than or equal to the max horizontal slices that the combination 3184 * of PCON encoder and HDMI decoder can support. 3185 */ 3186 slice_width = max_slice_width; 3187 3188 do { 3189 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3190 target_slices = 1; 3191 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3192 target_slices = 2; 3193 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3194 target_slices = 4; 3195 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3196 target_slices = 8; 3197 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3198 target_slices = 12; 3199 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3200 target_slices = 16; 3201 else 3202 return 0; 3203 3204 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3205 if (slice_width >= max_slice_width) 3206 min_slices = target_slices + 1; 3207 } while (slice_width >= max_slice_width); 3208 3209 return target_slices; 3210 } 3211 3212 /* 3213 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3214 * source and sink capabilities. 3215 * 3216 * @src_fraction_bpp: fractional bpp supported by the source 3217 * @slice_width: dsc slice width supported by the source and sink 3218 * @num_slices: num of slices supported by the source and sink 3219 * @output_format: video output format 3220 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3221 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3222 * 3223 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3224 */ 3225 int 3226 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3227 int output_format, bool hdmi_all_bpp, 3228 int hdmi_max_chunk_bytes) 3229 { 3230 int max_dsc_bpp, min_dsc_bpp; 3231 int target_bytes; 3232 bool bpp_found = false; 3233 int bpp_decrement_x16; 3234 int bpp_target; 3235 int bpp_target_x16; 3236 3237 /* 3238 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3239 * Start with the max bpp and keep on decrementing with 3240 * fractional bpp, if supported by PCON DSC encoder 3241 * 3242 * for each bpp we check if no of bytes can be supported by HDMI sink 3243 */ 3244 3245 /* Assuming: bpc as 8*/ 3246 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3247 min_dsc_bpp = 6; 3248 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3249 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3250 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3251 min_dsc_bpp = 8; 3252 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3253 } else { 3254 /* Assuming 4:2:2 encoding */ 3255 min_dsc_bpp = 7; 3256 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3257 } 3258 3259 /* 3260 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3261 * Section 7.7.34 : Source shall not enable compressed Video 3262 * Transport with bpp_target settings above 12 bpp unless 3263 * DSC_all_bpp is set to 1. 3264 */ 3265 if (!hdmi_all_bpp) 3266 max_dsc_bpp = min(max_dsc_bpp, 12); 3267 3268 /* 3269 * The Sink has a limit of compressed data in bytes for a scanline, 3270 * as described in max_chunk_bytes field in HFVSDB block of edid. 3271 * The no. of bytes depend on the target bits per pixel that the 3272 * source configures. So we start with the max_bpp and calculate 3273 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3274 * till we get the target_chunk_bytes just less than what the sink's 3275 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3276 * 3277 * The decrement is according to the fractional support from PCON DSC 3278 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3279 * 3280 * bpp_target_x16 = bpp_target * 16 3281 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3282 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3283 */ 3284 3285 bpp_target = max_dsc_bpp; 3286 3287 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3288 if (!src_fractional_bpp) 3289 src_fractional_bpp = 1; 3290 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3291 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3292 3293 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3294 int bpp; 3295 3296 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3297 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3298 if (target_bytes <= hdmi_max_chunk_bytes) { 3299 bpp_found = true; 3300 break; 3301 } 3302 bpp_target_x16 -= bpp_decrement_x16; 3303 } 3304 if (bpp_found) 3305 return bpp_target_x16; 3306 3307 return 0; 3308 } 3309