1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/intel/intel_lpe_audio.h> 43 44 #include <media/cec-notifier.h> 45 46 #include "g4x_hdmi.h" 47 #include "i915_drv.h" 48 #include "i915_reg.h" 49 #include "intel_atomic.h" 50 #include "intel_audio.h" 51 #include "intel_connector.h" 52 #include "intel_cx0_phy.h" 53 #include "intel_ddi.h" 54 #include "intel_de.h" 55 #include "intel_display_driver.h" 56 #include "intel_display_types.h" 57 #include "intel_dp.h" 58 #include "intel_gmbus.h" 59 #include "intel_hdcp.h" 60 #include "intel_hdcp_regs.h" 61 #include "intel_hdcp_shim.h" 62 #include "intel_hdmi.h" 63 #include "intel_lspcon.h" 64 #include "intel_panel.h" 65 #include "intel_snps_phy.h" 66 67 static void 68 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 69 { 70 struct intel_display *display = to_intel_display(intel_hdmi); 71 u32 enabled_bits; 72 73 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 74 75 drm_WARN(display->drm, 76 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 77 "HDMI port enabled, expecting disabled\n"); 78 } 79 80 static void 81 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 82 enum transcoder cpu_transcoder) 83 { 84 drm_WARN(display->drm, 85 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 86 TRANS_DDI_FUNC_ENABLE, 87 "HDMI transcoder function enabled, expecting disabled\n"); 88 } 89 90 static u32 g4x_infoframe_index(unsigned int type) 91 { 92 switch (type) { 93 case HDMI_PACKET_TYPE_GAMUT_METADATA: 94 return VIDEO_DIP_SELECT_GAMUT; 95 case HDMI_INFOFRAME_TYPE_AVI: 96 return VIDEO_DIP_SELECT_AVI; 97 case HDMI_INFOFRAME_TYPE_SPD: 98 return VIDEO_DIP_SELECT_SPD; 99 case HDMI_INFOFRAME_TYPE_VENDOR: 100 return VIDEO_DIP_SELECT_VENDOR; 101 default: 102 MISSING_CASE(type); 103 return 0; 104 } 105 } 106 107 static u32 g4x_infoframe_enable(unsigned int type) 108 { 109 switch (type) { 110 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 111 return VIDEO_DIP_ENABLE_GCP; 112 case HDMI_PACKET_TYPE_GAMUT_METADATA: 113 return VIDEO_DIP_ENABLE_GAMUT; 114 case DP_SDP_VSC: 115 return 0; 116 case DP_SDP_ADAPTIVE_SYNC: 117 return 0; 118 case HDMI_INFOFRAME_TYPE_AVI: 119 return VIDEO_DIP_ENABLE_AVI; 120 case HDMI_INFOFRAME_TYPE_SPD: 121 return VIDEO_DIP_ENABLE_SPD; 122 case HDMI_INFOFRAME_TYPE_VENDOR: 123 return VIDEO_DIP_ENABLE_VENDOR; 124 case HDMI_INFOFRAME_TYPE_DRM: 125 return 0; 126 default: 127 MISSING_CASE(type); 128 return 0; 129 } 130 } 131 132 static u32 hsw_infoframe_enable(unsigned int type) 133 { 134 switch (type) { 135 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 136 return VIDEO_DIP_ENABLE_GCP_HSW; 137 case HDMI_PACKET_TYPE_GAMUT_METADATA: 138 return VIDEO_DIP_ENABLE_GMP_HSW; 139 case DP_SDP_VSC: 140 return VIDEO_DIP_ENABLE_VSC_HSW; 141 case DP_SDP_ADAPTIVE_SYNC: 142 return VIDEO_DIP_ENABLE_AS_ADL; 143 case DP_SDP_PPS: 144 return VDIP_ENABLE_PPS; 145 case HDMI_INFOFRAME_TYPE_AVI: 146 return VIDEO_DIP_ENABLE_AVI_HSW; 147 case HDMI_INFOFRAME_TYPE_SPD: 148 return VIDEO_DIP_ENABLE_SPD_HSW; 149 case HDMI_INFOFRAME_TYPE_VENDOR: 150 return VIDEO_DIP_ENABLE_VS_HSW; 151 case HDMI_INFOFRAME_TYPE_DRM: 152 return VIDEO_DIP_ENABLE_DRM_GLK; 153 default: 154 MISSING_CASE(type); 155 return 0; 156 } 157 } 158 159 static i915_reg_t 160 hsw_dip_data_reg(struct intel_display *display, 161 enum transcoder cpu_transcoder, 162 unsigned int type, 163 int i) 164 { 165 switch (type) { 166 case HDMI_PACKET_TYPE_GAMUT_METADATA: 167 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 168 case DP_SDP_VSC: 169 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 170 case DP_SDP_ADAPTIVE_SYNC: 171 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 172 case DP_SDP_PPS: 173 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 174 case HDMI_INFOFRAME_TYPE_AVI: 175 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 176 case HDMI_INFOFRAME_TYPE_SPD: 177 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 178 case HDMI_INFOFRAME_TYPE_VENDOR: 179 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_DRM: 181 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 182 default: 183 MISSING_CASE(type); 184 return INVALID_MMIO_REG; 185 } 186 } 187 188 static int hsw_dip_data_size(struct intel_display *display, 189 unsigned int type) 190 { 191 switch (type) { 192 case DP_SDP_VSC: 193 return VIDEO_DIP_VSC_DATA_SIZE; 194 case DP_SDP_ADAPTIVE_SYNC: 195 return VIDEO_DIP_ASYNC_DATA_SIZE; 196 case DP_SDP_PPS: 197 return VIDEO_DIP_PPS_DATA_SIZE; 198 case HDMI_PACKET_TYPE_GAMUT_METADATA: 199 if (DISPLAY_VER(display) >= 11) 200 return VIDEO_DIP_GMP_DATA_SIZE; 201 else 202 return VIDEO_DIP_DATA_SIZE; 203 default: 204 return VIDEO_DIP_DATA_SIZE; 205 } 206 } 207 208 static void g4x_write_infoframe(struct intel_encoder *encoder, 209 const struct intel_crtc_state *crtc_state, 210 unsigned int type, 211 const void *frame, ssize_t len) 212 { 213 struct intel_display *display = to_intel_display(encoder); 214 const u32 *data = frame; 215 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 216 int i; 217 218 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 219 "Writing DIP with CTL reg disabled\n"); 220 221 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 222 val |= g4x_infoframe_index(type); 223 224 val &= ~g4x_infoframe_enable(type); 225 226 intel_de_write(display, VIDEO_DIP_CTL, val); 227 228 for (i = 0; i < len; i += 4) { 229 intel_de_write(display, VIDEO_DIP_DATA, *data); 230 data++; 231 } 232 /* Write every possible data byte to force correct ECC calculation. */ 233 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 234 intel_de_write(display, VIDEO_DIP_DATA, 0); 235 236 val |= g4x_infoframe_enable(type); 237 val &= ~VIDEO_DIP_FREQ_MASK; 238 val |= VIDEO_DIP_FREQ_VSYNC; 239 240 intel_de_write(display, VIDEO_DIP_CTL, val); 241 intel_de_posting_read(display, VIDEO_DIP_CTL); 242 } 243 244 static void g4x_read_infoframe(struct intel_encoder *encoder, 245 const struct intel_crtc_state *crtc_state, 246 unsigned int type, 247 void *frame, ssize_t len) 248 { 249 struct intel_display *display = to_intel_display(encoder); 250 u32 *data = frame; 251 int i; 252 253 intel_de_rmw(display, VIDEO_DIP_CTL, 254 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 255 256 for (i = 0; i < len; i += 4) 257 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 258 } 259 260 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 261 const struct intel_crtc_state *pipe_config) 262 { 263 struct intel_display *display = to_intel_display(encoder); 264 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 265 266 if ((val & VIDEO_DIP_ENABLE) == 0) 267 return 0; 268 269 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 270 return 0; 271 272 return val & (VIDEO_DIP_ENABLE_AVI | 273 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 274 } 275 276 static void ibx_write_infoframe(struct intel_encoder *encoder, 277 const struct intel_crtc_state *crtc_state, 278 unsigned int type, 279 const void *frame, ssize_t len) 280 { 281 struct intel_display *display = to_intel_display(encoder); 282 const u32 *data = frame; 283 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 284 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 285 u32 val = intel_de_read(display, reg); 286 int i; 287 288 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 289 "Writing DIP with CTL reg disabled\n"); 290 291 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 292 val |= g4x_infoframe_index(type); 293 294 val &= ~g4x_infoframe_enable(type); 295 296 intel_de_write(display, reg, val); 297 298 for (i = 0; i < len; i += 4) { 299 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 300 *data); 301 data++; 302 } 303 /* Write every possible data byte to force correct ECC calculation. */ 304 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 305 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 306 307 val |= g4x_infoframe_enable(type); 308 val &= ~VIDEO_DIP_FREQ_MASK; 309 val |= VIDEO_DIP_FREQ_VSYNC; 310 311 intel_de_write(display, reg, val); 312 intel_de_posting_read(display, reg); 313 } 314 315 static void ibx_read_infoframe(struct intel_encoder *encoder, 316 const struct intel_crtc_state *crtc_state, 317 unsigned int type, 318 void *frame, ssize_t len) 319 { 320 struct intel_display *display = to_intel_display(encoder); 321 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 322 u32 *data = frame; 323 int i; 324 325 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 326 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 327 328 for (i = 0; i < len; i += 4) 329 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 330 } 331 332 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 333 const struct intel_crtc_state *pipe_config) 334 { 335 struct intel_display *display = to_intel_display(encoder); 336 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 337 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 338 u32 val = intel_de_read(display, reg); 339 340 if ((val & VIDEO_DIP_ENABLE) == 0) 341 return 0; 342 343 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 344 return 0; 345 346 return val & (VIDEO_DIP_ENABLE_AVI | 347 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 348 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 349 } 350 351 static void cpt_write_infoframe(struct intel_encoder *encoder, 352 const struct intel_crtc_state *crtc_state, 353 unsigned int type, 354 const void *frame, ssize_t len) 355 { 356 struct intel_display *display = to_intel_display(encoder); 357 const u32 *data = frame; 358 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 359 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 360 u32 val = intel_de_read(display, reg); 361 int i; 362 363 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 364 "Writing DIP with CTL reg disabled\n"); 365 366 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 367 val |= g4x_infoframe_index(type); 368 369 /* The DIP control register spec says that we need to update the AVI 370 * infoframe without clearing its enable bit */ 371 if (type != HDMI_INFOFRAME_TYPE_AVI) 372 val &= ~g4x_infoframe_enable(type); 373 374 intel_de_write(display, reg, val); 375 376 for (i = 0; i < len; i += 4) { 377 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 378 *data); 379 data++; 380 } 381 /* Write every possible data byte to force correct ECC calculation. */ 382 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 383 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 384 385 val |= g4x_infoframe_enable(type); 386 val &= ~VIDEO_DIP_FREQ_MASK; 387 val |= VIDEO_DIP_FREQ_VSYNC; 388 389 intel_de_write(display, reg, val); 390 intel_de_posting_read(display, reg); 391 } 392 393 static void cpt_read_infoframe(struct intel_encoder *encoder, 394 const struct intel_crtc_state *crtc_state, 395 unsigned int type, 396 void *frame, ssize_t len) 397 { 398 struct intel_display *display = to_intel_display(encoder); 399 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 400 u32 *data = frame; 401 int i; 402 403 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 404 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 405 406 for (i = 0; i < len; i += 4) 407 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 408 } 409 410 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 411 const struct intel_crtc_state *pipe_config) 412 { 413 struct intel_display *display = to_intel_display(encoder); 414 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 415 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 416 417 if ((val & VIDEO_DIP_ENABLE) == 0) 418 return 0; 419 420 return val & (VIDEO_DIP_ENABLE_AVI | 421 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 422 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 423 } 424 425 static void vlv_write_infoframe(struct intel_encoder *encoder, 426 const struct intel_crtc_state *crtc_state, 427 unsigned int type, 428 const void *frame, ssize_t len) 429 { 430 struct intel_display *display = to_intel_display(encoder); 431 const u32 *data = frame; 432 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 433 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 434 u32 val = intel_de_read(display, reg); 435 int i; 436 437 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 438 "Writing DIP with CTL reg disabled\n"); 439 440 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 441 val |= g4x_infoframe_index(type); 442 443 val &= ~g4x_infoframe_enable(type); 444 445 intel_de_write(display, reg, val); 446 447 for (i = 0; i < len; i += 4) { 448 intel_de_write(display, 449 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 450 data++; 451 } 452 /* Write every possible data byte to force correct ECC calculation. */ 453 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 454 intel_de_write(display, 455 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 456 457 val |= g4x_infoframe_enable(type); 458 val &= ~VIDEO_DIP_FREQ_MASK; 459 val |= VIDEO_DIP_FREQ_VSYNC; 460 461 intel_de_write(display, reg, val); 462 intel_de_posting_read(display, reg); 463 } 464 465 static void vlv_read_infoframe(struct intel_encoder *encoder, 466 const struct intel_crtc_state *crtc_state, 467 unsigned int type, 468 void *frame, ssize_t len) 469 { 470 struct intel_display *display = to_intel_display(encoder); 471 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 472 u32 *data = frame; 473 int i; 474 475 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 476 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 477 478 for (i = 0; i < len; i += 4) 479 *data++ = intel_de_read(display, 480 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 481 } 482 483 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 484 const struct intel_crtc_state *pipe_config) 485 { 486 struct intel_display *display = to_intel_display(encoder); 487 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 488 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 489 490 if ((val & VIDEO_DIP_ENABLE) == 0) 491 return 0; 492 493 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 494 return 0; 495 496 return val & (VIDEO_DIP_ENABLE_AVI | 497 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 498 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 499 } 500 501 void hsw_write_infoframe(struct intel_encoder *encoder, 502 const struct intel_crtc_state *crtc_state, 503 unsigned int type, 504 const void *frame, ssize_t len) 505 { 506 struct intel_display *display = to_intel_display(encoder); 507 const u32 *data = frame; 508 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 509 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 510 int data_size; 511 int i; 512 u32 val = intel_de_read(display, ctl_reg); 513 514 data_size = hsw_dip_data_size(display, type); 515 516 drm_WARN_ON(display->drm, len > data_size); 517 518 val &= ~hsw_infoframe_enable(type); 519 intel_de_write(display, ctl_reg, val); 520 521 for (i = 0; i < len; i += 4) { 522 intel_de_write(display, 523 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 524 *data); 525 data++; 526 } 527 /* Write every possible data byte to force correct ECC calculation. */ 528 for (; i < data_size; i += 4) 529 intel_de_write(display, 530 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 531 0); 532 533 /* Wa_14013475917 */ 534 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 535 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 536 val |= hsw_infoframe_enable(type); 537 538 if (type == DP_SDP_VSC) 539 val |= VSC_DIP_HW_DATA_SW_HEA; 540 541 intel_de_write(display, ctl_reg, val); 542 intel_de_posting_read(display, ctl_reg); 543 } 544 545 void hsw_read_infoframe(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state, 547 unsigned int type, void *frame, ssize_t len) 548 { 549 struct intel_display *display = to_intel_display(encoder); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 u32 *data = frame; 552 int i; 553 554 for (i = 0; i < len; i += 4) 555 *data++ = intel_de_read(display, 556 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 557 } 558 559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 560 const struct intel_crtc_state *pipe_config) 561 { 562 struct intel_display *display = to_intel_display(encoder); 563 u32 val = intel_de_read(display, 564 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 565 u32 mask; 566 567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 570 571 if (DISPLAY_VER(display) >= 10) 572 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 573 574 if (HAS_AS_SDP(display)) 575 mask |= VIDEO_DIP_ENABLE_AS_ADL; 576 577 return val & mask; 578 } 579 580 static const u8 infoframe_type_to_idx[] = { 581 HDMI_PACKET_TYPE_GENERAL_CONTROL, 582 HDMI_PACKET_TYPE_GAMUT_METADATA, 583 DP_SDP_VSC, 584 DP_SDP_ADAPTIVE_SYNC, 585 HDMI_INFOFRAME_TYPE_AVI, 586 HDMI_INFOFRAME_TYPE_SPD, 587 HDMI_INFOFRAME_TYPE_VENDOR, 588 HDMI_INFOFRAME_TYPE_DRM, 589 }; 590 591 u32 intel_hdmi_infoframe_enable(unsigned int type) 592 { 593 int i; 594 595 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 596 if (infoframe_type_to_idx[i] == type) 597 return BIT(i); 598 } 599 600 return 0; 601 } 602 603 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 604 const struct intel_crtc_state *crtc_state) 605 { 606 struct intel_display *display = to_intel_display(encoder); 607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 608 u32 val, ret = 0; 609 int i; 610 611 val = dig_port->infoframes_enabled(encoder, crtc_state); 612 613 /* map from hardware bits to dip idx */ 614 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 615 unsigned int type = infoframe_type_to_idx[i]; 616 617 if (HAS_DDI(display)) { 618 if (val & hsw_infoframe_enable(type)) 619 ret |= BIT(i); 620 } else { 621 if (val & g4x_infoframe_enable(type)) 622 ret |= BIT(i); 623 } 624 } 625 626 return ret; 627 } 628 629 /* 630 * The data we write to the DIP data buffer registers is 1 byte bigger than the 631 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 632 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 633 * used for both technologies. 634 * 635 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 636 * DW1: DB3 | DB2 | DB1 | DB0 637 * DW2: DB7 | DB6 | DB5 | DB4 638 * DW3: ... 639 * 640 * (HB is Header Byte, DB is Data Byte) 641 * 642 * The hdmi pack() functions don't know about that hardware specific hole so we 643 * trick them by giving an offset into the buffer and moving back the header 644 * bytes by one. 645 */ 646 static void intel_write_infoframe(struct intel_encoder *encoder, 647 const struct intel_crtc_state *crtc_state, 648 enum hdmi_infoframe_type type, 649 const union hdmi_infoframe *frame) 650 { 651 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 652 u8 buffer[VIDEO_DIP_DATA_SIZE]; 653 ssize_t len; 654 655 if ((crtc_state->infoframes.enable & 656 intel_hdmi_infoframe_enable(type)) == 0) 657 return; 658 659 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 660 return; 661 662 /* see comment above for the reason for this offset */ 663 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 664 if (drm_WARN_ON(encoder->base.dev, len < 0)) 665 return; 666 667 /* Insert the 'hole' (see big comment above) at position 3 */ 668 memmove(&buffer[0], &buffer[1], 3); 669 buffer[3] = 0; 670 len++; 671 672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 673 } 674 675 void intel_read_infoframe(struct intel_encoder *encoder, 676 const struct intel_crtc_state *crtc_state, 677 enum hdmi_infoframe_type type, 678 union hdmi_infoframe *frame) 679 { 680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 681 u8 buffer[VIDEO_DIP_DATA_SIZE]; 682 int ret; 683 684 if ((crtc_state->infoframes.enable & 685 intel_hdmi_infoframe_enable(type)) == 0) 686 return; 687 688 dig_port->read_infoframe(encoder, crtc_state, 689 type, buffer, sizeof(buffer)); 690 691 /* Fill the 'hole' (see big comment above) at position 3 */ 692 memmove(&buffer[1], &buffer[0], 3); 693 694 /* see comment above for the reason for this offset */ 695 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 696 if (ret) { 697 drm_dbg_kms(encoder->base.dev, 698 "Failed to unpack infoframe type 0x%02x\n", type); 699 return; 700 } 701 702 if (frame->any.type != type) 703 drm_dbg_kms(encoder->base.dev, 704 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 705 frame->any.type, type); 706 } 707 708 static bool 709 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 710 struct intel_crtc_state *crtc_state, 711 struct drm_connector_state *conn_state) 712 { 713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 714 const struct drm_display_mode *adjusted_mode = 715 &crtc_state->hw.adjusted_mode; 716 struct drm_connector *connector = conn_state->connector; 717 int ret; 718 719 if (!crtc_state->has_infoframe) 720 return true; 721 722 crtc_state->infoframes.enable |= 723 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 724 725 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 726 adjusted_mode); 727 if (ret) 728 return false; 729 730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 731 frame->colorspace = HDMI_COLORSPACE_YUV420; 732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 733 frame->colorspace = HDMI_COLORSPACE_YUV444; 734 else 735 frame->colorspace = HDMI_COLORSPACE_RGB; 736 737 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 738 739 /* nonsense combination */ 740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 742 743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 744 drm_hdmi_avi_infoframe_quant_range(frame, connector, 745 adjusted_mode, 746 crtc_state->limited_color_range ? 747 HDMI_QUANTIZATION_RANGE_LIMITED : 748 HDMI_QUANTIZATION_RANGE_FULL); 749 } else { 750 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 751 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 752 } 753 754 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 755 756 /* TODO: handle pixel repetition for YCBCR420 outputs */ 757 758 ret = hdmi_avi_infoframe_check(frame); 759 if (drm_WARN_ON(encoder->base.dev, ret)) 760 return false; 761 762 return true; 763 } 764 765 static bool 766 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 767 struct intel_crtc_state *crtc_state, 768 struct drm_connector_state *conn_state) 769 { 770 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 771 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 772 int ret; 773 774 if (!crtc_state->has_infoframe) 775 return true; 776 777 crtc_state->infoframes.enable |= 778 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 779 780 if (IS_DGFX(i915)) 781 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 782 else 783 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 784 785 if (drm_WARN_ON(encoder->base.dev, ret)) 786 return false; 787 788 frame->sdi = HDMI_SPD_SDI_PC; 789 790 ret = hdmi_spd_infoframe_check(frame); 791 if (drm_WARN_ON(encoder->base.dev, ret)) 792 return false; 793 794 return true; 795 } 796 797 static bool 798 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 799 struct intel_crtc_state *crtc_state, 800 struct drm_connector_state *conn_state) 801 { 802 struct hdmi_vendor_infoframe *frame = 803 &crtc_state->infoframes.hdmi.vendor.hdmi; 804 const struct drm_display_info *info = 805 &conn_state->connector->display_info; 806 int ret; 807 808 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 809 return true; 810 811 crtc_state->infoframes.enable |= 812 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 813 814 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 815 conn_state->connector, 816 &crtc_state->hw.adjusted_mode); 817 if (drm_WARN_ON(encoder->base.dev, ret)) 818 return false; 819 820 ret = hdmi_vendor_infoframe_check(frame); 821 if (drm_WARN_ON(encoder->base.dev, ret)) 822 return false; 823 824 return true; 825 } 826 827 static bool 828 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 829 struct intel_crtc_state *crtc_state, 830 struct drm_connector_state *conn_state) 831 { 832 struct intel_display *display = to_intel_display(encoder); 833 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 834 int ret; 835 836 if (DISPLAY_VER(display) < 10) 837 return true; 838 839 if (!crtc_state->has_infoframe) 840 return true; 841 842 if (!conn_state->hdr_output_metadata) 843 return true; 844 845 crtc_state->infoframes.enable |= 846 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 847 848 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 849 if (ret < 0) { 850 drm_dbg_kms(display->drm, 851 "couldn't set HDR metadata in infoframe\n"); 852 return false; 853 } 854 855 ret = hdmi_drm_infoframe_check(frame); 856 if (drm_WARN_ON(display->drm, ret)) 857 return false; 858 859 return true; 860 } 861 862 static void g4x_set_infoframes(struct intel_encoder *encoder, 863 bool enable, 864 const struct intel_crtc_state *crtc_state, 865 const struct drm_connector_state *conn_state) 866 { 867 struct intel_display *display = to_intel_display(encoder); 868 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 869 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 870 i915_reg_t reg = VIDEO_DIP_CTL; 871 u32 val = intel_de_read(display, reg); 872 u32 port = VIDEO_DIP_PORT(encoder->port); 873 874 assert_hdmi_port_disabled(intel_hdmi); 875 876 /* If the registers were not initialized yet, they might be zeroes, 877 * which means we're selecting the AVI DIP and we're setting its 878 * frequency to once. This seems to really confuse the HW and make 879 * things stop working (the register spec says the AVI always needs to 880 * be sent every VSync). So here we avoid writing to the register more 881 * than we need and also explicitly select the AVI DIP and explicitly 882 * set its frequency to every VSync. Avoiding to write it twice seems to 883 * be enough to solve the problem, but being defensive shouldn't hurt us 884 * either. */ 885 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 886 887 if (!enable) { 888 if (!(val & VIDEO_DIP_ENABLE)) 889 return; 890 if (port != (val & VIDEO_DIP_PORT_MASK)) { 891 drm_dbg_kms(display->drm, 892 "video DIP still enabled on port %c\n", 893 (val & VIDEO_DIP_PORT_MASK) >> 29); 894 return; 895 } 896 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 897 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 898 intel_de_write(display, reg, val); 899 intel_de_posting_read(display, reg); 900 return; 901 } 902 903 if (port != (val & VIDEO_DIP_PORT_MASK)) { 904 if (val & VIDEO_DIP_ENABLE) { 905 drm_dbg_kms(display->drm, 906 "video DIP already enabled on port %c\n", 907 (val & VIDEO_DIP_PORT_MASK) >> 29); 908 return; 909 } 910 val &= ~VIDEO_DIP_PORT_MASK; 911 val |= port; 912 } 913 914 val |= VIDEO_DIP_ENABLE; 915 val &= ~(VIDEO_DIP_ENABLE_AVI | 916 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 917 918 intel_de_write(display, reg, val); 919 intel_de_posting_read(display, reg); 920 921 intel_write_infoframe(encoder, crtc_state, 922 HDMI_INFOFRAME_TYPE_AVI, 923 &crtc_state->infoframes.avi); 924 intel_write_infoframe(encoder, crtc_state, 925 HDMI_INFOFRAME_TYPE_SPD, 926 &crtc_state->infoframes.spd); 927 intel_write_infoframe(encoder, crtc_state, 928 HDMI_INFOFRAME_TYPE_VENDOR, 929 &crtc_state->infoframes.hdmi); 930 } 931 932 /* 933 * Determine if default_phase=1 can be indicated in the GCP infoframe. 934 * 935 * From HDMI specification 1.4a: 936 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 937 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 938 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 939 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 940 * phase of 0 941 */ 942 static bool gcp_default_phase_possible(int pipe_bpp, 943 const struct drm_display_mode *mode) 944 { 945 unsigned int pixels_per_group; 946 947 switch (pipe_bpp) { 948 case 30: 949 /* 4 pixels in 5 clocks */ 950 pixels_per_group = 4; 951 break; 952 case 36: 953 /* 2 pixels in 3 clocks */ 954 pixels_per_group = 2; 955 break; 956 case 48: 957 /* 1 pixel in 2 clocks */ 958 pixels_per_group = 1; 959 break; 960 default: 961 /* phase information not relevant for 8bpc */ 962 return false; 963 } 964 965 return mode->crtc_hdisplay % pixels_per_group == 0 && 966 mode->crtc_htotal % pixels_per_group == 0 && 967 mode->crtc_hblank_start % pixels_per_group == 0 && 968 mode->crtc_hblank_end % pixels_per_group == 0 && 969 mode->crtc_hsync_start % pixels_per_group == 0 && 970 mode->crtc_hsync_end % pixels_per_group == 0 && 971 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 972 mode->crtc_htotal/2 % pixels_per_group == 0); 973 } 974 975 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 976 const struct intel_crtc_state *crtc_state, 977 const struct drm_connector_state *conn_state) 978 { 979 struct intel_display *display = to_intel_display(encoder); 980 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 981 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 982 i915_reg_t reg; 983 984 if ((crtc_state->infoframes.enable & 985 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 986 return false; 987 988 if (HAS_DDI(display)) 989 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 990 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 991 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 992 else if (HAS_PCH_SPLIT(dev_priv)) 993 reg = TVIDEO_DIP_GCP(crtc->pipe); 994 else 995 return false; 996 997 intel_de_write(display, reg, crtc_state->infoframes.gcp); 998 999 return true; 1000 } 1001 1002 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1003 struct intel_crtc_state *crtc_state) 1004 { 1005 struct intel_display *display = to_intel_display(encoder); 1006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1008 i915_reg_t reg; 1009 1010 if ((crtc_state->infoframes.enable & 1011 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1012 return; 1013 1014 if (HAS_DDI(display)) 1015 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1016 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1017 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1018 else if (HAS_PCH_SPLIT(dev_priv)) 1019 reg = TVIDEO_DIP_GCP(crtc->pipe); 1020 else 1021 return; 1022 1023 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1024 } 1025 1026 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1027 struct intel_crtc_state *crtc_state, 1028 struct drm_connector_state *conn_state) 1029 { 1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1031 1032 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1033 return; 1034 1035 crtc_state->infoframes.enable |= 1036 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1037 1038 /* Indicate color indication for deep color mode */ 1039 if (crtc_state->pipe_bpp > 24) 1040 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1041 1042 /* Enable default_phase whenever the display mode is suitably aligned */ 1043 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1044 &crtc_state->hw.adjusted_mode)) 1045 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1046 } 1047 1048 static void ibx_set_infoframes(struct intel_encoder *encoder, 1049 bool enable, 1050 const struct intel_crtc_state *crtc_state, 1051 const struct drm_connector_state *conn_state) 1052 { 1053 struct intel_display *display = to_intel_display(encoder); 1054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1055 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1056 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1057 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1058 u32 val = intel_de_read(display, reg); 1059 u32 port = VIDEO_DIP_PORT(encoder->port); 1060 1061 assert_hdmi_port_disabled(intel_hdmi); 1062 1063 /* See the big comment in g4x_set_infoframes() */ 1064 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1065 1066 if (!enable) { 1067 if (!(val & VIDEO_DIP_ENABLE)) 1068 return; 1069 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1070 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1071 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1072 intel_de_write(display, reg, val); 1073 intel_de_posting_read(display, reg); 1074 return; 1075 } 1076 1077 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1078 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1079 "DIP already enabled on port %c\n", 1080 (val & VIDEO_DIP_PORT_MASK) >> 29); 1081 val &= ~VIDEO_DIP_PORT_MASK; 1082 val |= port; 1083 } 1084 1085 val |= VIDEO_DIP_ENABLE; 1086 val &= ~(VIDEO_DIP_ENABLE_AVI | 1087 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1088 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1089 1090 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1091 val |= VIDEO_DIP_ENABLE_GCP; 1092 1093 intel_de_write(display, reg, val); 1094 intel_de_posting_read(display, reg); 1095 1096 intel_write_infoframe(encoder, crtc_state, 1097 HDMI_INFOFRAME_TYPE_AVI, 1098 &crtc_state->infoframes.avi); 1099 intel_write_infoframe(encoder, crtc_state, 1100 HDMI_INFOFRAME_TYPE_SPD, 1101 &crtc_state->infoframes.spd); 1102 intel_write_infoframe(encoder, crtc_state, 1103 HDMI_INFOFRAME_TYPE_VENDOR, 1104 &crtc_state->infoframes.hdmi); 1105 } 1106 1107 static void cpt_set_infoframes(struct intel_encoder *encoder, 1108 bool enable, 1109 const struct intel_crtc_state *crtc_state, 1110 const struct drm_connector_state *conn_state) 1111 { 1112 struct intel_display *display = to_intel_display(encoder); 1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1114 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1115 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1116 u32 val = intel_de_read(display, reg); 1117 1118 assert_hdmi_port_disabled(intel_hdmi); 1119 1120 /* See the big comment in g4x_set_infoframes() */ 1121 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1122 1123 if (!enable) { 1124 if (!(val & VIDEO_DIP_ENABLE)) 1125 return; 1126 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1127 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1128 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1129 intel_de_write(display, reg, val); 1130 intel_de_posting_read(display, reg); 1131 return; 1132 } 1133 1134 /* Set both together, unset both together: see the spec. */ 1135 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1136 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1137 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1138 1139 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1140 val |= VIDEO_DIP_ENABLE_GCP; 1141 1142 intel_de_write(display, reg, val); 1143 intel_de_posting_read(display, reg); 1144 1145 intel_write_infoframe(encoder, crtc_state, 1146 HDMI_INFOFRAME_TYPE_AVI, 1147 &crtc_state->infoframes.avi); 1148 intel_write_infoframe(encoder, crtc_state, 1149 HDMI_INFOFRAME_TYPE_SPD, 1150 &crtc_state->infoframes.spd); 1151 intel_write_infoframe(encoder, crtc_state, 1152 HDMI_INFOFRAME_TYPE_VENDOR, 1153 &crtc_state->infoframes.hdmi); 1154 } 1155 1156 static void vlv_set_infoframes(struct intel_encoder *encoder, 1157 bool enable, 1158 const struct intel_crtc_state *crtc_state, 1159 const struct drm_connector_state *conn_state) 1160 { 1161 struct intel_display *display = to_intel_display(encoder); 1162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1163 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1164 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1165 u32 val = intel_de_read(display, reg); 1166 u32 port = VIDEO_DIP_PORT(encoder->port); 1167 1168 assert_hdmi_port_disabled(intel_hdmi); 1169 1170 /* See the big comment in g4x_set_infoframes() */ 1171 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1172 1173 if (!enable) { 1174 if (!(val & VIDEO_DIP_ENABLE)) 1175 return; 1176 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1177 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1178 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1179 intel_de_write(display, reg, val); 1180 intel_de_posting_read(display, reg); 1181 return; 1182 } 1183 1184 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1185 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1186 "DIP already enabled on port %c\n", 1187 (val & VIDEO_DIP_PORT_MASK) >> 29); 1188 val &= ~VIDEO_DIP_PORT_MASK; 1189 val |= port; 1190 } 1191 1192 val |= VIDEO_DIP_ENABLE; 1193 val &= ~(VIDEO_DIP_ENABLE_AVI | 1194 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1195 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1196 1197 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1198 val |= VIDEO_DIP_ENABLE_GCP; 1199 1200 intel_de_write(display, reg, val); 1201 intel_de_posting_read(display, reg); 1202 1203 intel_write_infoframe(encoder, crtc_state, 1204 HDMI_INFOFRAME_TYPE_AVI, 1205 &crtc_state->infoframes.avi); 1206 intel_write_infoframe(encoder, crtc_state, 1207 HDMI_INFOFRAME_TYPE_SPD, 1208 &crtc_state->infoframes.spd); 1209 intel_write_infoframe(encoder, crtc_state, 1210 HDMI_INFOFRAME_TYPE_VENDOR, 1211 &crtc_state->infoframes.hdmi); 1212 } 1213 1214 static void hsw_set_infoframes(struct intel_encoder *encoder, 1215 bool enable, 1216 const struct intel_crtc_state *crtc_state, 1217 const struct drm_connector_state *conn_state) 1218 { 1219 struct intel_display *display = to_intel_display(encoder); 1220 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1221 crtc_state->cpu_transcoder); 1222 u32 val = intel_de_read(display, reg); 1223 1224 assert_hdmi_transcoder_func_disabled(display, 1225 crtc_state->cpu_transcoder); 1226 1227 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1228 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1229 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1230 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1231 1232 if (!enable) { 1233 intel_de_write(display, reg, val); 1234 intel_de_posting_read(display, reg); 1235 return; 1236 } 1237 1238 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1239 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1240 1241 intel_de_write(display, reg, val); 1242 intel_de_posting_read(display, reg); 1243 1244 intel_write_infoframe(encoder, crtc_state, 1245 HDMI_INFOFRAME_TYPE_AVI, 1246 &crtc_state->infoframes.avi); 1247 intel_write_infoframe(encoder, crtc_state, 1248 HDMI_INFOFRAME_TYPE_SPD, 1249 &crtc_state->infoframes.spd); 1250 intel_write_infoframe(encoder, crtc_state, 1251 HDMI_INFOFRAME_TYPE_VENDOR, 1252 &crtc_state->infoframes.hdmi); 1253 intel_write_infoframe(encoder, crtc_state, 1254 HDMI_INFOFRAME_TYPE_DRM, 1255 &crtc_state->infoframes.drm); 1256 } 1257 1258 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1259 { 1260 struct intel_display *display = to_intel_display(hdmi); 1261 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1262 1263 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1264 return; 1265 1266 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1267 enable ? "Enabling" : "Disabling"); 1268 1269 drm_dp_dual_mode_set_tmds_output(display->drm, 1270 hdmi->dp_dual_mode.type, ddc, enable); 1271 } 1272 1273 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1274 unsigned int offset, void *buffer, size_t size) 1275 { 1276 struct intel_hdmi *hdmi = &dig_port->hdmi; 1277 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1278 int ret; 1279 u8 start = offset & 0xff; 1280 struct i2c_msg msgs[] = { 1281 { 1282 .addr = DRM_HDCP_DDC_ADDR, 1283 .flags = 0, 1284 .len = 1, 1285 .buf = &start, 1286 }, 1287 { 1288 .addr = DRM_HDCP_DDC_ADDR, 1289 .flags = I2C_M_RD, 1290 .len = size, 1291 .buf = buffer 1292 } 1293 }; 1294 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1295 if (ret == ARRAY_SIZE(msgs)) 1296 return 0; 1297 return ret >= 0 ? -EIO : ret; 1298 } 1299 1300 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1301 unsigned int offset, void *buffer, size_t size) 1302 { 1303 struct intel_hdmi *hdmi = &dig_port->hdmi; 1304 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1305 int ret; 1306 u8 *write_buf; 1307 struct i2c_msg msg; 1308 1309 write_buf = kzalloc(size + 1, GFP_KERNEL); 1310 if (!write_buf) 1311 return -ENOMEM; 1312 1313 write_buf[0] = offset & 0xff; 1314 memcpy(&write_buf[1], buffer, size); 1315 1316 msg.addr = DRM_HDCP_DDC_ADDR; 1317 msg.flags = 0; 1318 msg.len = size + 1; 1319 msg.buf = write_buf; 1320 1321 ret = i2c_transfer(ddc, &msg, 1); 1322 if (ret == 1) 1323 ret = 0; 1324 else if (ret >= 0) 1325 ret = -EIO; 1326 1327 kfree(write_buf); 1328 return ret; 1329 } 1330 1331 static 1332 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1333 u8 *an) 1334 { 1335 struct intel_display *display = to_intel_display(dig_port); 1336 struct intel_hdmi *hdmi = &dig_port->hdmi; 1337 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1338 int ret; 1339 1340 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1341 DRM_HDCP_AN_LEN); 1342 if (ret) { 1343 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1344 ret); 1345 return ret; 1346 } 1347 1348 ret = intel_gmbus_output_aksv(ddc); 1349 if (ret < 0) { 1350 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1351 return ret; 1352 } 1353 return 0; 1354 } 1355 1356 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1357 u8 *bksv) 1358 { 1359 struct intel_display *display = to_intel_display(dig_port); 1360 1361 int ret; 1362 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1363 DRM_HDCP_KSV_LEN); 1364 if (ret) 1365 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1366 ret); 1367 return ret; 1368 } 1369 1370 static 1371 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1372 u8 *bstatus) 1373 { 1374 struct intel_display *display = to_intel_display(dig_port); 1375 1376 int ret; 1377 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1378 bstatus, DRM_HDCP_BSTATUS_LEN); 1379 if (ret) 1380 drm_dbg_kms(display->drm, 1381 "Read bstatus over DDC failed (%d)\n", 1382 ret); 1383 return ret; 1384 } 1385 1386 static 1387 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1388 bool *repeater_present) 1389 { 1390 struct intel_display *display = to_intel_display(dig_port); 1391 int ret; 1392 u8 val; 1393 1394 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1395 if (ret) { 1396 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1397 ret); 1398 return ret; 1399 } 1400 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1401 return 0; 1402 } 1403 1404 static 1405 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1406 u8 *ri_prime) 1407 { 1408 struct intel_display *display = to_intel_display(dig_port); 1409 1410 int ret; 1411 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1412 ri_prime, DRM_HDCP_RI_LEN); 1413 if (ret) 1414 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1415 ret); 1416 return ret; 1417 } 1418 1419 static 1420 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1421 bool *ksv_ready) 1422 { 1423 struct intel_display *display = to_intel_display(dig_port); 1424 int ret; 1425 u8 val; 1426 1427 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1428 if (ret) { 1429 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1430 ret); 1431 return ret; 1432 } 1433 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1434 return 0; 1435 } 1436 1437 static 1438 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1439 int num_downstream, u8 *ksv_fifo) 1440 { 1441 struct intel_display *display = to_intel_display(dig_port); 1442 int ret; 1443 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1444 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1445 if (ret) { 1446 drm_dbg_kms(display->drm, 1447 "Read ksv fifo over DDC failed (%d)\n", ret); 1448 return ret; 1449 } 1450 return 0; 1451 } 1452 1453 static 1454 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1455 int i, u32 *part) 1456 { 1457 struct intel_display *display = to_intel_display(dig_port); 1458 int ret; 1459 1460 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1461 return -EINVAL; 1462 1463 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1464 part, DRM_HDCP_V_PRIME_PART_LEN); 1465 if (ret) 1466 drm_dbg_kms(display->drm, 1467 "Read V'[%d] over DDC failed (%d)\n", 1468 i, ret); 1469 return ret; 1470 } 1471 1472 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1473 enum transcoder cpu_transcoder) 1474 { 1475 struct intel_display *display = to_intel_display(connector); 1476 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1477 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1478 u32 scanline; 1479 int ret; 1480 1481 for (;;) { 1482 scanline = intel_de_read(display, 1483 PIPEDSL(display, crtc->pipe)); 1484 if (scanline > 100 && scanline < 200) 1485 break; 1486 usleep_range(25, 50); 1487 } 1488 1489 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1490 false, TRANS_DDI_HDCP_SIGNALLING); 1491 if (ret) { 1492 drm_err(display->drm, 1493 "Disable HDCP signalling failed (%d)\n", ret); 1494 return ret; 1495 } 1496 1497 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1498 true, TRANS_DDI_HDCP_SIGNALLING); 1499 if (ret) { 1500 drm_err(display->drm, 1501 "Enable HDCP signalling failed (%d)\n", ret); 1502 return ret; 1503 } 1504 1505 return 0; 1506 } 1507 1508 static 1509 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1510 enum transcoder cpu_transcoder, 1511 bool enable) 1512 { 1513 struct intel_display *display = to_intel_display(dig_port); 1514 struct intel_hdmi *hdmi = &dig_port->hdmi; 1515 struct intel_connector *connector = hdmi->attached_connector; 1516 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1517 int ret; 1518 1519 if (!enable) 1520 usleep_range(6, 60); /* Bspec says >= 6us */ 1521 1522 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1523 cpu_transcoder, enable, 1524 TRANS_DDI_HDCP_SIGNALLING); 1525 if (ret) { 1526 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1527 enable ? "Enable" : "Disable", ret); 1528 return ret; 1529 } 1530 1531 /* 1532 * WA: To fix incorrect positioning of the window of 1533 * opportunity and enc_en signalling in KABYLAKE. 1534 */ 1535 if (IS_KABYLAKE(dev_priv) && enable) 1536 return kbl_repositioning_enc_en_signal(connector, 1537 cpu_transcoder); 1538 1539 return 0; 1540 } 1541 1542 static 1543 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1544 struct intel_connector *connector) 1545 { 1546 struct intel_display *display = to_intel_display(dig_port); 1547 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1548 enum port port = dig_port->base.port; 1549 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1550 int ret; 1551 union { 1552 u32 reg; 1553 u8 shim[DRM_HDCP_RI_LEN]; 1554 } ri; 1555 1556 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1557 if (ret) 1558 return false; 1559 1560 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1561 1562 /* Wait for Ri prime match */ 1563 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1564 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1565 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1566 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1567 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1568 port))); 1569 return false; 1570 } 1571 return true; 1572 } 1573 1574 static 1575 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1576 struct intel_connector *connector) 1577 { 1578 struct intel_display *display = to_intel_display(dig_port); 1579 int retry; 1580 1581 for (retry = 0; retry < 3; retry++) 1582 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1583 return true; 1584 1585 drm_err(display->drm, "Link check failed\n"); 1586 return false; 1587 } 1588 1589 struct hdcp2_hdmi_msg_timeout { 1590 u8 msg_id; 1591 u16 timeout; 1592 }; 1593 1594 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1595 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1596 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1597 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1598 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1599 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1600 }; 1601 1602 static 1603 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1604 u8 *rx_status) 1605 { 1606 return intel_hdmi_hdcp_read(dig_port, 1607 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1608 rx_status, 1609 HDCP_2_2_HDMI_RXSTATUS_LEN); 1610 } 1611 1612 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1613 { 1614 int i; 1615 1616 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1617 if (is_paired) 1618 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1619 else 1620 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1621 } 1622 1623 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1624 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1625 return hdcp2_msg_timeout[i].timeout; 1626 } 1627 1628 return -EINVAL; 1629 } 1630 1631 static int 1632 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1633 u8 msg_id, bool *msg_ready, 1634 ssize_t *msg_sz) 1635 { 1636 struct intel_display *display = to_intel_display(dig_port); 1637 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1638 int ret; 1639 1640 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1641 if (ret < 0) { 1642 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1643 ret); 1644 return ret; 1645 } 1646 1647 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1648 rx_status[0]); 1649 1650 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1651 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1652 *msg_sz); 1653 else 1654 *msg_ready = *msg_sz; 1655 1656 return 0; 1657 } 1658 1659 static ssize_t 1660 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1661 u8 msg_id, bool paired) 1662 { 1663 struct intel_display *display = to_intel_display(dig_port); 1664 bool msg_ready = false; 1665 int timeout, ret; 1666 ssize_t msg_sz = 0; 1667 1668 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1669 if (timeout < 0) 1670 return timeout; 1671 1672 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1673 msg_id, &msg_ready, 1674 &msg_sz), 1675 !ret && msg_ready && msg_sz, timeout * 1000, 1676 1000, 5 * 1000); 1677 if (ret) 1678 drm_dbg_kms(display->drm, 1679 "msg_id: %d, ret: %d, timeout: %d\n", 1680 msg_id, ret, timeout); 1681 1682 return ret ? ret : msg_sz; 1683 } 1684 1685 static 1686 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1687 void *buf, size_t size) 1688 { 1689 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1690 unsigned int offset; 1691 1692 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1693 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1694 } 1695 1696 static 1697 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1698 u8 msg_id, void *buf, size_t size) 1699 { 1700 struct intel_display *display = to_intel_display(connector); 1701 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1702 struct intel_hdmi *hdmi = &dig_port->hdmi; 1703 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1704 unsigned int offset; 1705 ssize_t ret; 1706 1707 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1708 hdcp->is_paired); 1709 if (ret < 0) 1710 return ret; 1711 1712 /* 1713 * Available msg size should be equal to or lesser than the 1714 * available buffer. 1715 */ 1716 if (ret > size) { 1717 drm_dbg_kms(display->drm, 1718 "msg_sz(%zd) is more than exp size(%zu)\n", 1719 ret, size); 1720 return -EINVAL; 1721 } 1722 1723 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1724 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1725 if (ret) 1726 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1727 msg_id, ret); 1728 1729 return ret; 1730 } 1731 1732 static 1733 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1734 struct intel_connector *connector) 1735 { 1736 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1737 int ret; 1738 1739 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1740 if (ret) 1741 return ret; 1742 1743 /* 1744 * Re-auth request and Link Integrity Failures are represented by 1745 * same bit. i.e reauth_req. 1746 */ 1747 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1748 ret = HDCP_REAUTH_REQUEST; 1749 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1750 ret = HDCP_TOPOLOGY_CHANGE; 1751 1752 return ret; 1753 } 1754 1755 static 1756 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1757 bool *capable) 1758 { 1759 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1760 u8 hdcp2_version; 1761 int ret; 1762 1763 *capable = false; 1764 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1765 &hdcp2_version, sizeof(hdcp2_version)); 1766 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1767 *capable = true; 1768 1769 return ret; 1770 } 1771 1772 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1773 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1774 .read_bksv = intel_hdmi_hdcp_read_bksv, 1775 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1776 .repeater_present = intel_hdmi_hdcp_repeater_present, 1777 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1778 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1779 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1780 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1781 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1782 .check_link = intel_hdmi_hdcp_check_link, 1783 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1784 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1785 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1786 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1787 .protocol = HDCP_PROTOCOL_HDMI, 1788 }; 1789 1790 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1791 { 1792 struct intel_display *display = to_intel_display(encoder); 1793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1794 int max_tmds_clock, vbt_max_tmds_clock; 1795 1796 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) 1797 max_tmds_clock = 600000; 1798 else if (DISPLAY_VER(display) >= 10) 1799 max_tmds_clock = 594000; 1800 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) 1801 max_tmds_clock = 300000; 1802 else if (DISPLAY_VER(display) >= 5) 1803 max_tmds_clock = 225000; 1804 else 1805 max_tmds_clock = 165000; 1806 1807 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1808 if (vbt_max_tmds_clock) 1809 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1810 1811 return max_tmds_clock; 1812 } 1813 1814 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1815 const struct drm_connector_state *conn_state) 1816 { 1817 struct intel_connector *connector = hdmi->attached_connector; 1818 1819 return connector->base.display_info.is_hdmi && 1820 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1821 } 1822 1823 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1824 { 1825 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1826 } 1827 1828 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1829 bool respect_downstream_limits, 1830 bool has_hdmi_sink) 1831 { 1832 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1833 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1834 1835 if (respect_downstream_limits) { 1836 struct intel_connector *connector = hdmi->attached_connector; 1837 const struct drm_display_info *info = &connector->base.display_info; 1838 1839 if (hdmi->dp_dual_mode.max_tmds_clock) 1840 max_tmds_clock = min(max_tmds_clock, 1841 hdmi->dp_dual_mode.max_tmds_clock); 1842 1843 if (info->max_tmds_clock) 1844 max_tmds_clock = min(max_tmds_clock, 1845 info->max_tmds_clock); 1846 else if (!has_hdmi_sink) 1847 max_tmds_clock = min(max_tmds_clock, 165000); 1848 } 1849 1850 return max_tmds_clock; 1851 } 1852 1853 static enum drm_mode_status 1854 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1855 int clock, bool respect_downstream_limits, 1856 bool has_hdmi_sink) 1857 { 1858 struct intel_display *display = to_intel_display(hdmi); 1859 struct drm_i915_private *dev_priv = to_i915(display->drm); 1860 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1861 1862 if (clock < 25000) 1863 return MODE_CLOCK_LOW; 1864 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1865 has_hdmi_sink)) 1866 return MODE_CLOCK_HIGH; 1867 1868 /* GLK DPLL can't generate 446-480 MHz */ 1869 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1870 return MODE_CLOCK_RANGE; 1871 1872 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1873 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1874 clock > 223333 && clock < 240000) 1875 return MODE_CLOCK_RANGE; 1876 1877 /* CHV DPLL can't generate 216-240 MHz */ 1878 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1879 return MODE_CLOCK_RANGE; 1880 1881 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1882 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1883 return MODE_CLOCK_RANGE; 1884 1885 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1886 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1887 return MODE_CLOCK_RANGE; 1888 1889 /* 1890 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1891 * set of link rates. 1892 * 1893 * FIXME: We will hopefully get an algorithmic way of programming 1894 * the MPLLB for HDMI in the future. 1895 */ 1896 if (DISPLAY_VER(display) >= 14) 1897 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); 1898 else if (IS_DG2(dev_priv)) 1899 return intel_snps_phy_check_hdmi_link_rate(clock); 1900 1901 return MODE_OK; 1902 } 1903 1904 int intel_hdmi_tmds_clock(int clock, int bpc, 1905 enum intel_output_format sink_format) 1906 { 1907 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1908 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1909 clock /= 2; 1910 1911 /* 1912 * Need to adjust the port link by: 1913 * 1.5x for 12bpc 1914 * 1.25x for 10bpc 1915 */ 1916 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1917 } 1918 1919 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1920 { 1921 switch (bpc) { 1922 case 12: 1923 return !HAS_GMCH(display); 1924 case 10: 1925 return DISPLAY_VER(display) >= 11; 1926 case 8: 1927 return true; 1928 default: 1929 MISSING_CASE(bpc); 1930 return false; 1931 } 1932 } 1933 1934 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1935 int bpc, bool has_hdmi_sink, 1936 enum intel_output_format sink_format) 1937 { 1938 const struct drm_display_info *info = &connector->display_info; 1939 const struct drm_hdmi_info *hdmi = &info->hdmi; 1940 1941 switch (bpc) { 1942 case 12: 1943 if (!has_hdmi_sink) 1944 return false; 1945 1946 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1947 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1948 else 1949 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1950 case 10: 1951 if (!has_hdmi_sink) 1952 return false; 1953 1954 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1955 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1956 else 1957 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1958 case 8: 1959 return true; 1960 default: 1961 MISSING_CASE(bpc); 1962 return false; 1963 } 1964 } 1965 1966 static enum drm_mode_status 1967 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1968 bool has_hdmi_sink, 1969 enum intel_output_format sink_format) 1970 { 1971 struct intel_display *display = to_intel_display(connector->dev); 1972 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1973 enum drm_mode_status status = MODE_OK; 1974 int bpc; 1975 1976 /* 1977 * Try all color depths since valid port clock range 1978 * can have holes. Any mode that can be used with at 1979 * least one color depth is accepted. 1980 */ 1981 for (bpc = 12; bpc >= 8; bpc -= 2) { 1982 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1983 1984 if (!intel_hdmi_source_bpc_possible(display, bpc)) 1985 continue; 1986 1987 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 1988 continue; 1989 1990 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1991 if (status == MODE_OK) 1992 return MODE_OK; 1993 } 1994 1995 /* can never happen */ 1996 drm_WARN_ON(display->drm, status == MODE_OK); 1997 1998 return status; 1999 } 2000 2001 static enum drm_mode_status 2002 intel_hdmi_mode_valid(struct drm_connector *connector, 2003 struct drm_display_mode *mode) 2004 { 2005 struct intel_display *display = to_intel_display(connector->dev); 2006 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2007 struct drm_i915_private *dev_priv = to_i915(display->drm); 2008 enum drm_mode_status status; 2009 int clock = mode->clock; 2010 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 2011 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2012 bool ycbcr_420_only; 2013 enum intel_output_format sink_format; 2014 2015 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 2016 if (status != MODE_OK) 2017 return status; 2018 2019 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2020 clock *= 2; 2021 2022 if (clock > max_dotclk) 2023 return MODE_CLOCK_HIGH; 2024 2025 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2026 if (!has_hdmi_sink) 2027 return MODE_CLOCK_LOW; 2028 clock *= 2; 2029 } 2030 2031 /* 2032 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2033 * enumerated only if FRL is supported. Current platforms do not support 2034 * FRL so prune the higher resolution modes that require doctclock more 2035 * than 600MHz. 2036 */ 2037 if (clock > 600000) 2038 return MODE_CLOCK_HIGH; 2039 2040 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2041 2042 if (ycbcr_420_only) 2043 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2044 else 2045 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2046 2047 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2048 if (status != MODE_OK) { 2049 if (ycbcr_420_only || 2050 !connector->ycbcr_420_allowed || 2051 !drm_mode_is_420_also(&connector->display_info, mode)) 2052 return status; 2053 2054 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2055 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2056 if (status != MODE_OK) 2057 return status; 2058 } 2059 2060 return intel_mode_valid_max_plane_size(dev_priv, mode, 1); 2061 } 2062 2063 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2064 int bpc, bool has_hdmi_sink) 2065 { 2066 struct drm_atomic_state *state = crtc_state->uapi.state; 2067 struct drm_connector_state *connector_state; 2068 struct drm_connector *connector; 2069 int i; 2070 2071 for_each_new_connector_in_state(state, connector, connector_state, i) { 2072 if (connector_state->crtc != crtc_state->uapi.crtc) 2073 continue; 2074 2075 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2076 crtc_state->sink_format)) 2077 return false; 2078 } 2079 2080 return true; 2081 } 2082 2083 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2084 { 2085 struct intel_display *display = to_intel_display(crtc_state); 2086 const struct drm_display_mode *adjusted_mode = 2087 &crtc_state->hw.adjusted_mode; 2088 2089 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2090 return false; 2091 2092 /* Display Wa_1405510057:icl,ehl */ 2093 if (intel_hdmi_is_ycbcr420(crtc_state) && 2094 bpc == 10 && DISPLAY_VER(display) == 11 && 2095 (adjusted_mode->crtc_hblank_end - 2096 adjusted_mode->crtc_hblank_start) % 8 == 2) 2097 return false; 2098 2099 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2100 } 2101 2102 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2103 struct intel_crtc_state *crtc_state, 2104 int clock, bool respect_downstream_limits) 2105 { 2106 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2107 int bpc; 2108 2109 /* 2110 * pipe_bpp could already be below 8bpc due to FDI 2111 * bandwidth constraints. HDMI minimum is 8bpc however. 2112 */ 2113 bpc = max(crtc_state->pipe_bpp / 3, 8); 2114 2115 /* 2116 * We will never exceed downstream TMDS clock limits while 2117 * attempting deep color. If the user insists on forcing an 2118 * out of spec mode they will have to be satisfied with 8bpc. 2119 */ 2120 if (!respect_downstream_limits) 2121 bpc = 8; 2122 2123 for (; bpc >= 8; bpc -= 2) { 2124 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2125 crtc_state->sink_format); 2126 2127 if (hdmi_bpc_possible(crtc_state, bpc) && 2128 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2129 respect_downstream_limits, 2130 crtc_state->has_hdmi_sink) == MODE_OK) 2131 return bpc; 2132 } 2133 2134 return -EINVAL; 2135 } 2136 2137 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2138 struct intel_crtc_state *crtc_state, 2139 bool respect_downstream_limits) 2140 { 2141 struct intel_display *display = to_intel_display(encoder); 2142 const struct drm_display_mode *adjusted_mode = 2143 &crtc_state->hw.adjusted_mode; 2144 int bpc, clock = adjusted_mode->crtc_clock; 2145 2146 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2147 clock *= 2; 2148 2149 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2150 respect_downstream_limits); 2151 if (bpc < 0) 2152 return bpc; 2153 2154 crtc_state->port_clock = 2155 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2156 2157 /* 2158 * pipe_bpp could already be below 8bpc due to 2159 * FDI bandwidth constraints. We shouldn't bump it 2160 * back up to the HDMI minimum 8bpc in that case. 2161 */ 2162 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2163 2164 drm_dbg_kms(display->drm, 2165 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2166 bpc, crtc_state->pipe_bpp); 2167 2168 return 0; 2169 } 2170 2171 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2172 const struct drm_connector_state *conn_state) 2173 { 2174 const struct intel_digital_connector_state *intel_conn_state = 2175 to_intel_digital_connector_state(conn_state); 2176 const struct drm_display_mode *adjusted_mode = 2177 &crtc_state->hw.adjusted_mode; 2178 2179 /* 2180 * Our YCbCr output is always limited range. 2181 * crtc_state->limited_color_range only applies to RGB, 2182 * and it must never be set for YCbCr or we risk setting 2183 * some conflicting bits in TRANSCONF which will mess up 2184 * the colors on the monitor. 2185 */ 2186 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2187 return false; 2188 2189 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2190 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2191 return crtc_state->has_hdmi_sink && 2192 drm_default_rgb_quant_range(adjusted_mode) == 2193 HDMI_QUANTIZATION_RANGE_LIMITED; 2194 } else { 2195 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2196 } 2197 } 2198 2199 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2200 const struct intel_crtc_state *crtc_state, 2201 const struct drm_connector_state *conn_state) 2202 { 2203 struct drm_connector *connector = conn_state->connector; 2204 const struct intel_digital_connector_state *intel_conn_state = 2205 to_intel_digital_connector_state(conn_state); 2206 2207 if (!crtc_state->has_hdmi_sink) 2208 return false; 2209 2210 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2211 return connector->display_info.has_audio; 2212 else 2213 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2214 } 2215 2216 static enum intel_output_format 2217 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2218 struct intel_connector *connector, 2219 bool ycbcr_420_output) 2220 { 2221 if (!crtc_state->has_hdmi_sink) 2222 return INTEL_OUTPUT_FORMAT_RGB; 2223 2224 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2225 return INTEL_OUTPUT_FORMAT_YCBCR420; 2226 else 2227 return INTEL_OUTPUT_FORMAT_RGB; 2228 } 2229 2230 static enum intel_output_format 2231 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2232 { 2233 return crtc_state->sink_format; 2234 } 2235 2236 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2237 struct intel_crtc_state *crtc_state, 2238 const struct drm_connector_state *conn_state, 2239 bool respect_downstream_limits) 2240 { 2241 struct intel_display *display = to_intel_display(encoder); 2242 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2243 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2244 const struct drm_display_info *info = &connector->base.display_info; 2245 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2246 int ret; 2247 2248 crtc_state->sink_format = 2249 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2250 2251 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2252 drm_dbg_kms(display->drm, 2253 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2254 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2255 } 2256 2257 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2258 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2259 if (ret) { 2260 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2261 !crtc_state->has_hdmi_sink || 2262 !connector->base.ycbcr_420_allowed || 2263 !drm_mode_is_420_also(info, adjusted_mode)) 2264 return ret; 2265 2266 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2267 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2268 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2269 } 2270 2271 return ret; 2272 } 2273 2274 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2275 { 2276 return crtc_state->uapi.encoder_mask && 2277 !is_power_of_2(crtc_state->uapi.encoder_mask); 2278 } 2279 2280 static bool source_supports_scrambling(struct intel_encoder *encoder) 2281 { 2282 /* 2283 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2284 * scrambling is supported. 2285 * But there seem to be cases where certain platforms that support 2286 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2287 * capped by VBT to less than 340MHz. 2288 * 2289 * In such cases when an HDMI2.0 sink is connected, it creates a 2290 * problem : the platform and the sink both support scrambling but the 2291 * HDMI 1.4 retimer chip doesn't. 2292 * 2293 * So go for scrambling, based on the max tmds clock taking into account, 2294 * restrictions coming from VBT. 2295 */ 2296 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2297 } 2298 2299 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2300 const struct intel_crtc_state *crtc_state, 2301 const struct drm_connector_state *conn_state) 2302 { 2303 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2304 2305 return intel_has_hdmi_sink(hdmi, conn_state) && 2306 !intel_hdmi_is_cloned(crtc_state); 2307 } 2308 2309 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2310 struct intel_crtc_state *pipe_config, 2311 struct drm_connector_state *conn_state) 2312 { 2313 struct intel_display *display = to_intel_display(encoder); 2314 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2315 struct drm_connector *connector = conn_state->connector; 2316 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2317 int ret; 2318 2319 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2320 return -EINVAL; 2321 2322 if (!connector->interlace_allowed && 2323 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2324 return -EINVAL; 2325 2326 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2327 2328 if (pipe_config->has_hdmi_sink) 2329 pipe_config->has_infoframe = true; 2330 2331 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2332 pipe_config->pixel_multiplier = 2; 2333 2334 pipe_config->has_audio = 2335 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2336 intel_audio_compute_config(encoder, pipe_config, conn_state); 2337 2338 /* 2339 * Try to respect downstream TMDS clock limits first, if 2340 * that fails assume the user might know something we don't. 2341 */ 2342 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2343 if (ret) 2344 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2345 if (ret) { 2346 drm_dbg_kms(display->drm, 2347 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2348 pipe_config->hw.adjusted_mode.crtc_clock); 2349 return ret; 2350 } 2351 2352 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2353 ret = intel_panel_fitting(pipe_config, conn_state); 2354 if (ret) 2355 return ret; 2356 } 2357 2358 pipe_config->limited_color_range = 2359 intel_hdmi_limited_color_range(pipe_config, conn_state); 2360 2361 if (conn_state->picture_aspect_ratio) 2362 adjusted_mode->picture_aspect_ratio = 2363 conn_state->picture_aspect_ratio; 2364 2365 pipe_config->lane_count = 4; 2366 2367 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2368 if (scdc->scrambling.low_rates) 2369 pipe_config->hdmi_scrambling = true; 2370 2371 if (pipe_config->port_clock > 340000) { 2372 pipe_config->hdmi_scrambling = true; 2373 pipe_config->hdmi_high_tmds_clock_ratio = true; 2374 } 2375 } 2376 2377 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2378 conn_state); 2379 2380 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2381 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2382 return -EINVAL; 2383 } 2384 2385 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2386 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2387 return -EINVAL; 2388 } 2389 2390 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2391 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2392 return -EINVAL; 2393 } 2394 2395 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2396 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2397 return -EINVAL; 2398 } 2399 2400 return 0; 2401 } 2402 2403 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2404 { 2405 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2406 2407 /* 2408 * Give a hand to buggy BIOSen which forget to turn 2409 * the TMDS output buffers back on after a reboot. 2410 */ 2411 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2412 } 2413 2414 static void 2415 intel_hdmi_unset_edid(struct drm_connector *connector) 2416 { 2417 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2418 2419 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2420 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2421 2422 drm_edid_free(to_intel_connector(connector)->detect_edid); 2423 to_intel_connector(connector)->detect_edid = NULL; 2424 } 2425 2426 static void 2427 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2428 { 2429 struct intel_display *display = to_intel_display(connector->dev); 2430 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2431 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2432 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2433 struct i2c_adapter *ddc = connector->ddc; 2434 enum drm_dp_dual_mode_type type; 2435 2436 type = drm_dp_dual_mode_detect(display->drm, ddc); 2437 2438 /* 2439 * Type 1 DVI adaptors are not required to implement any 2440 * registers, so we can't always detect their presence. 2441 * Ideally we should be able to check the state of the 2442 * CONFIG1 pin, but no such luck on our hardware. 2443 * 2444 * The only method left to us is to check the VBT to see 2445 * if the port is a dual mode capable DP port. 2446 */ 2447 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2448 if (!connector->force && 2449 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2450 drm_dbg_kms(display->drm, 2451 "Assuming DP dual mode adaptor presence based on VBT\n"); 2452 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2453 } else { 2454 type = DRM_DP_DUAL_MODE_NONE; 2455 } 2456 } 2457 2458 if (type == DRM_DP_DUAL_MODE_NONE) 2459 return; 2460 2461 hdmi->dp_dual_mode.type = type; 2462 hdmi->dp_dual_mode.max_tmds_clock = 2463 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2464 2465 drm_dbg_kms(display->drm, 2466 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2467 drm_dp_get_dual_mode_type_name(type), 2468 hdmi->dp_dual_mode.max_tmds_clock); 2469 2470 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2471 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && 2472 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2473 drm_dbg_kms(display->drm, 2474 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2475 hdmi->dp_dual_mode.max_tmds_clock = 0; 2476 } 2477 } 2478 2479 static bool 2480 intel_hdmi_set_edid(struct drm_connector *connector) 2481 { 2482 struct intel_display *display = to_intel_display(connector->dev); 2483 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2484 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2485 struct i2c_adapter *ddc = connector->ddc; 2486 intel_wakeref_t wakeref; 2487 const struct drm_edid *drm_edid; 2488 bool connected = false; 2489 2490 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2491 2492 drm_edid = drm_edid_read_ddc(connector, ddc); 2493 2494 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2495 drm_dbg_kms(display->drm, 2496 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2497 intel_gmbus_force_bit(ddc, true); 2498 drm_edid = drm_edid_read_ddc(connector, ddc); 2499 intel_gmbus_force_bit(ddc, false); 2500 } 2501 2502 /* Below we depend on display info having been updated */ 2503 drm_edid_connector_update(connector, drm_edid); 2504 2505 to_intel_connector(connector)->detect_edid = drm_edid; 2506 2507 if (drm_edid_is_digital(drm_edid)) { 2508 intel_hdmi_dp_dual_mode_detect(connector); 2509 2510 connected = true; 2511 } 2512 2513 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2514 2515 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2516 connector->display_info.source_physical_address); 2517 2518 return connected; 2519 } 2520 2521 static enum drm_connector_status 2522 intel_hdmi_detect(struct drm_connector *connector, bool force) 2523 { 2524 struct intel_display *display = to_intel_display(connector->dev); 2525 enum drm_connector_status status = connector_status_disconnected; 2526 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2527 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2528 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2529 intel_wakeref_t wakeref; 2530 2531 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2532 connector->base.id, connector->name); 2533 2534 if (!intel_display_device_enabled(dev_priv)) 2535 return connector_status_disconnected; 2536 2537 if (!intel_display_driver_check_access(dev_priv)) 2538 return connector->status; 2539 2540 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2541 2542 if (DISPLAY_VER(display) >= 11 && 2543 !intel_digital_port_connected(encoder)) 2544 goto out; 2545 2546 intel_hdmi_unset_edid(connector); 2547 2548 if (intel_hdmi_set_edid(connector)) 2549 status = connector_status_connected; 2550 2551 out: 2552 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2553 2554 if (status != connector_status_connected) 2555 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2556 2557 return status; 2558 } 2559 2560 static void 2561 intel_hdmi_force(struct drm_connector *connector) 2562 { 2563 struct intel_display *display = to_intel_display(connector->dev); 2564 struct drm_i915_private *i915 = to_i915(connector->dev); 2565 2566 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2567 connector->base.id, connector->name); 2568 2569 if (!intel_display_driver_check_access(i915)) 2570 return; 2571 2572 intel_hdmi_unset_edid(connector); 2573 2574 if (connector->status != connector_status_connected) 2575 return; 2576 2577 intel_hdmi_set_edid(connector); 2578 } 2579 2580 static int intel_hdmi_get_modes(struct drm_connector *connector) 2581 { 2582 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2583 return drm_edid_connector_add_modes(connector); 2584 } 2585 2586 static int 2587 intel_hdmi_connector_register(struct drm_connector *connector) 2588 { 2589 int ret; 2590 2591 ret = intel_connector_register(connector); 2592 if (ret) 2593 return ret; 2594 2595 return ret; 2596 } 2597 2598 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2599 { 2600 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2601 2602 cec_notifier_conn_unregister(n); 2603 2604 intel_connector_unregister(connector); 2605 } 2606 2607 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2608 .detect = intel_hdmi_detect, 2609 .force = intel_hdmi_force, 2610 .fill_modes = drm_helper_probe_single_connector_modes, 2611 .atomic_get_property = intel_digital_connector_atomic_get_property, 2612 .atomic_set_property = intel_digital_connector_atomic_set_property, 2613 .late_register = intel_hdmi_connector_register, 2614 .early_unregister = intel_hdmi_connector_unregister, 2615 .destroy = intel_connector_destroy, 2616 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2617 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2618 }; 2619 2620 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2621 struct drm_atomic_state *state) 2622 { 2623 struct intel_display *display = to_intel_display(connector->dev); 2624 2625 if (HAS_DDI(display)) 2626 return intel_digital_connector_atomic_check(connector, state); 2627 else 2628 return g4x_hdmi_connector_atomic_check(connector, state); 2629 } 2630 2631 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2632 .get_modes = intel_hdmi_get_modes, 2633 .mode_valid = intel_hdmi_mode_valid, 2634 .atomic_check = intel_hdmi_connector_atomic_check, 2635 }; 2636 2637 static void 2638 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2639 { 2640 struct intel_display *display = to_intel_display(intel_hdmi); 2641 2642 intel_attach_force_audio_property(connector); 2643 intel_attach_broadcast_rgb_property(connector); 2644 intel_attach_aspect_ratio_property(connector); 2645 2646 intel_attach_hdmi_colorspace_property(connector); 2647 drm_connector_attach_content_type_property(connector); 2648 2649 if (DISPLAY_VER(display) >= 10) 2650 drm_connector_attach_hdr_output_metadata_property(connector); 2651 2652 if (!HAS_GMCH(display)) 2653 drm_connector_attach_max_bpc_property(connector, 8, 12); 2654 } 2655 2656 /* 2657 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2658 * @encoder: intel_encoder 2659 * @connector: drm_connector 2660 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2661 * or reset the high tmds clock ratio for scrambling 2662 * @scrambling: bool to Indicate if the function needs to set or reset 2663 * sink scrambling 2664 * 2665 * This function handles scrambling on HDMI 2.0 capable sinks. 2666 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2667 * it enables scrambling. This should be called before enabling the HDMI 2668 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2669 * detect a scrambled clock within 100 ms. 2670 * 2671 * Returns: 2672 * True on success, false on failure. 2673 */ 2674 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2675 struct drm_connector *connector, 2676 bool high_tmds_clock_ratio, 2677 bool scrambling) 2678 { 2679 struct intel_display *display = to_intel_display(encoder); 2680 struct drm_scrambling *sink_scrambling = 2681 &connector->display_info.hdmi.scdc.scrambling; 2682 2683 if (!sink_scrambling->supported) 2684 return true; 2685 2686 drm_dbg_kms(display->drm, 2687 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2688 connector->base.id, connector->name, 2689 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2690 2691 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2692 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2693 drm_scdc_set_scrambling(connector, scrambling); 2694 } 2695 2696 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2697 { 2698 enum port port = encoder->port; 2699 u8 ddc_pin; 2700 2701 switch (port) { 2702 case PORT_B: 2703 ddc_pin = GMBUS_PIN_DPB; 2704 break; 2705 case PORT_C: 2706 ddc_pin = GMBUS_PIN_DPC; 2707 break; 2708 case PORT_D: 2709 ddc_pin = GMBUS_PIN_DPD_CHV; 2710 break; 2711 default: 2712 MISSING_CASE(port); 2713 ddc_pin = GMBUS_PIN_DPB; 2714 break; 2715 } 2716 return ddc_pin; 2717 } 2718 2719 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2720 { 2721 enum port port = encoder->port; 2722 u8 ddc_pin; 2723 2724 switch (port) { 2725 case PORT_B: 2726 ddc_pin = GMBUS_PIN_1_BXT; 2727 break; 2728 case PORT_C: 2729 ddc_pin = GMBUS_PIN_2_BXT; 2730 break; 2731 default: 2732 MISSING_CASE(port); 2733 ddc_pin = GMBUS_PIN_1_BXT; 2734 break; 2735 } 2736 return ddc_pin; 2737 } 2738 2739 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2740 { 2741 enum port port = encoder->port; 2742 u8 ddc_pin; 2743 2744 switch (port) { 2745 case PORT_B: 2746 ddc_pin = GMBUS_PIN_1_BXT; 2747 break; 2748 case PORT_C: 2749 ddc_pin = GMBUS_PIN_2_BXT; 2750 break; 2751 case PORT_D: 2752 ddc_pin = GMBUS_PIN_4_CNP; 2753 break; 2754 case PORT_F: 2755 ddc_pin = GMBUS_PIN_3_BXT; 2756 break; 2757 default: 2758 MISSING_CASE(port); 2759 ddc_pin = GMBUS_PIN_1_BXT; 2760 break; 2761 } 2762 return ddc_pin; 2763 } 2764 2765 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2766 { 2767 struct intel_display *display = to_intel_display(encoder); 2768 enum port port = encoder->port; 2769 2770 if (intel_encoder_is_combo(encoder)) 2771 return GMBUS_PIN_1_BXT + port; 2772 else if (intel_encoder_is_tc(encoder)) 2773 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2774 2775 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2776 return GMBUS_PIN_2_BXT; 2777 } 2778 2779 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2780 { 2781 enum phy phy = intel_encoder_to_phy(encoder); 2782 u8 ddc_pin; 2783 2784 switch (phy) { 2785 case PHY_A: 2786 ddc_pin = GMBUS_PIN_1_BXT; 2787 break; 2788 case PHY_B: 2789 ddc_pin = GMBUS_PIN_2_BXT; 2790 break; 2791 case PHY_C: 2792 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2793 break; 2794 default: 2795 MISSING_CASE(phy); 2796 ddc_pin = GMBUS_PIN_1_BXT; 2797 break; 2798 } 2799 return ddc_pin; 2800 } 2801 2802 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2803 { 2804 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2805 enum phy phy = intel_encoder_to_phy(encoder); 2806 2807 WARN_ON(encoder->port == PORT_C); 2808 2809 /* 2810 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2811 * final two outputs use type-c pins, even though they're actually 2812 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2813 * all outputs. 2814 */ 2815 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2816 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2817 2818 return GMBUS_PIN_1_BXT + phy; 2819 } 2820 2821 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2822 { 2823 struct intel_display *display = to_intel_display(encoder); 2824 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2825 enum phy phy = intel_encoder_to_phy(encoder); 2826 2827 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2828 2829 /* 2830 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2831 * final two outputs use type-c pins, even though they're actually 2832 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2833 * all outputs. 2834 */ 2835 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2836 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2837 2838 return GMBUS_PIN_1_BXT + phy; 2839 } 2840 2841 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2842 { 2843 return intel_encoder_to_phy(encoder) + 1; 2844 } 2845 2846 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2847 { 2848 enum phy phy = intel_encoder_to_phy(encoder); 2849 2850 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2851 2852 /* 2853 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2854 * except first combo output. 2855 */ 2856 if (phy == PHY_A) 2857 return GMBUS_PIN_1_BXT; 2858 2859 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2860 } 2861 2862 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2863 { 2864 enum port port = encoder->port; 2865 u8 ddc_pin; 2866 2867 switch (port) { 2868 case PORT_B: 2869 ddc_pin = GMBUS_PIN_DPB; 2870 break; 2871 case PORT_C: 2872 ddc_pin = GMBUS_PIN_DPC; 2873 break; 2874 case PORT_D: 2875 ddc_pin = GMBUS_PIN_DPD; 2876 break; 2877 default: 2878 MISSING_CASE(port); 2879 ddc_pin = GMBUS_PIN_DPB; 2880 break; 2881 } 2882 return ddc_pin; 2883 } 2884 2885 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2886 { 2887 struct intel_display *display = to_intel_display(encoder); 2888 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2889 u8 ddc_pin; 2890 2891 if (IS_ALDERLAKE_S(dev_priv)) 2892 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2893 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2894 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2895 else if (IS_ROCKETLAKE(dev_priv)) 2896 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2897 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) 2898 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2899 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2900 HAS_PCH_TGP(dev_priv)) 2901 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2902 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2903 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2904 else if (HAS_PCH_CNP(dev_priv)) 2905 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2906 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2907 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2908 else if (IS_CHERRYVIEW(dev_priv)) 2909 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2910 else 2911 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2912 2913 return ddc_pin; 2914 } 2915 2916 static struct intel_encoder * 2917 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2918 { 2919 struct intel_display *display = to_intel_display(encoder); 2920 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2921 struct intel_encoder *other; 2922 2923 for_each_intel_encoder(display->drm, other) { 2924 struct intel_connector *connector; 2925 2926 if (other == encoder) 2927 continue; 2928 2929 if (!intel_encoder_is_dig_port(other)) 2930 continue; 2931 2932 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2933 2934 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) 2935 return other; 2936 } 2937 2938 return NULL; 2939 } 2940 2941 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2942 { 2943 struct intel_display *display = to_intel_display(encoder); 2944 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2945 struct intel_encoder *other; 2946 const char *source; 2947 u8 ddc_pin; 2948 2949 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2950 source = "VBT"; 2951 2952 if (!ddc_pin) { 2953 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2954 source = "platform default"; 2955 } 2956 2957 if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) { 2958 drm_dbg_kms(display->drm, 2959 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2960 encoder->base.base.id, encoder->base.name, ddc_pin); 2961 return 0; 2962 } 2963 2964 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2965 if (other) { 2966 drm_dbg_kms(display->drm, 2967 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2968 encoder->base.base.id, encoder->base.name, ddc_pin, 2969 other->base.base.id, other->base.name); 2970 return 0; 2971 } 2972 2973 drm_dbg_kms(display->drm, 2974 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2975 encoder->base.base.id, encoder->base.name, 2976 ddc_pin, source); 2977 2978 return ddc_pin; 2979 } 2980 2981 void intel_infoframe_init(struct intel_digital_port *dig_port) 2982 { 2983 struct intel_display *display = to_intel_display(dig_port); 2984 struct drm_i915_private *dev_priv = 2985 to_i915(dig_port->base.base.dev); 2986 2987 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2988 dig_port->write_infoframe = vlv_write_infoframe; 2989 dig_port->read_infoframe = vlv_read_infoframe; 2990 dig_port->set_infoframes = vlv_set_infoframes; 2991 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2992 } else if (IS_G4X(dev_priv)) { 2993 dig_port->write_infoframe = g4x_write_infoframe; 2994 dig_port->read_infoframe = g4x_read_infoframe; 2995 dig_port->set_infoframes = g4x_set_infoframes; 2996 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2997 } else if (HAS_DDI(display)) { 2998 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 2999 dig_port->write_infoframe = lspcon_write_infoframe; 3000 dig_port->read_infoframe = lspcon_read_infoframe; 3001 dig_port->set_infoframes = lspcon_set_infoframes; 3002 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3003 } else { 3004 dig_port->write_infoframe = hsw_write_infoframe; 3005 dig_port->read_infoframe = hsw_read_infoframe; 3006 dig_port->set_infoframes = hsw_set_infoframes; 3007 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3008 } 3009 } else if (HAS_PCH_IBX(dev_priv)) { 3010 dig_port->write_infoframe = ibx_write_infoframe; 3011 dig_port->read_infoframe = ibx_read_infoframe; 3012 dig_port->set_infoframes = ibx_set_infoframes; 3013 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3014 } else { 3015 dig_port->write_infoframe = cpt_write_infoframe; 3016 dig_port->read_infoframe = cpt_read_infoframe; 3017 dig_port->set_infoframes = cpt_set_infoframes; 3018 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3019 } 3020 } 3021 3022 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3023 struct intel_connector *intel_connector) 3024 { 3025 struct intel_display *display = to_intel_display(dig_port); 3026 struct drm_connector *connector = &intel_connector->base; 3027 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3028 struct intel_encoder *intel_encoder = &dig_port->base; 3029 struct drm_device *dev = intel_encoder->base.dev; 3030 struct drm_i915_private *dev_priv = to_i915(dev); 3031 enum port port = intel_encoder->port; 3032 struct cec_connector_info conn_info; 3033 u8 ddc_pin; 3034 3035 drm_dbg_kms(display->drm, 3036 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3037 intel_encoder->base.base.id, intel_encoder->base.name); 3038 3039 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3040 return; 3041 3042 if (drm_WARN(dev, dig_port->max_lanes < 4, 3043 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3044 dig_port->max_lanes, intel_encoder->base.base.id, 3045 intel_encoder->base.name)) 3046 return; 3047 3048 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3049 if (!ddc_pin) 3050 return; 3051 3052 drm_connector_init_with_ddc(dev, connector, 3053 &intel_hdmi_connector_funcs, 3054 DRM_MODE_CONNECTOR_HDMIA, 3055 intel_gmbus_get_adapter(dev_priv, ddc_pin)); 3056 3057 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3058 3059 if (DISPLAY_VER(display) < 12) 3060 connector->interlace_allowed = true; 3061 3062 connector->stereo_allowed = true; 3063 3064 if (DISPLAY_VER(display) >= 10) 3065 connector->ycbcr_420_allowed = true; 3066 3067 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3068 intel_connector->base.polled = intel_connector->polled; 3069 3070 if (HAS_DDI(display)) 3071 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3072 else 3073 intel_connector->get_hw_state = intel_connector_get_hw_state; 3074 3075 intel_hdmi_add_properties(intel_hdmi, connector); 3076 3077 intel_connector_attach_encoder(intel_connector, intel_encoder); 3078 intel_hdmi->attached_connector = intel_connector; 3079 3080 if (is_hdcp_supported(dev_priv, port)) { 3081 int ret = intel_hdcp_init(intel_connector, dig_port, 3082 &intel_hdmi_hdcp_shim); 3083 if (ret) 3084 drm_dbg_kms(display->drm, 3085 "HDCP init failed, skipping.\n"); 3086 } 3087 3088 cec_fill_conn_info_from_drm(&conn_info, connector); 3089 3090 intel_hdmi->cec_notifier = 3091 cec_notifier_conn_register(dev->dev, port_identifier(port), 3092 &conn_info); 3093 if (!intel_hdmi->cec_notifier) 3094 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3095 } 3096 3097 /* 3098 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3099 * @vactive: Vactive of a display mode 3100 * 3101 * @return: appropriate dsc slice height for a given mode. 3102 */ 3103 int intel_hdmi_dsc_get_slice_height(int vactive) 3104 { 3105 int slice_height; 3106 3107 /* 3108 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3109 * Select smallest slice height >=96, that results in a valid PPS and 3110 * requires minimum padding lines required for final slice. 3111 * 3112 * Assumption : Vactive is even. 3113 */ 3114 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3115 if (vactive % slice_height == 0) 3116 return slice_height; 3117 3118 return 0; 3119 } 3120 3121 /* 3122 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3123 * and dsc decoder capabilities 3124 * 3125 * @crtc_state: intel crtc_state 3126 * @src_max_slices: maximum slices supported by the DSC encoder 3127 * @src_max_slice_width: maximum slice width supported by DSC encoder 3128 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3129 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3130 * 3131 * @return: num of dsc slices that can be supported by the dsc encoder 3132 * and decoder. 3133 */ 3134 int 3135 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3136 int src_max_slices, int src_max_slice_width, 3137 int hdmi_max_slices, int hdmi_throughput) 3138 { 3139 /* Pixel rates in KPixels/sec */ 3140 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3141 /* 3142 * Rates at which the source and sink are required to process pixels in each 3143 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3144 */ 3145 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3146 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3147 3148 /* Spec limits the slice width to 2720 pixels */ 3149 #define MAX_HDMI_SLICE_WIDTH 2720 3150 int kslice_adjust; 3151 int adjusted_clk_khz; 3152 int min_slices; 3153 int target_slices; 3154 int max_throughput; /* max clock freq. in khz per slice */ 3155 int max_slice_width; 3156 int slice_width; 3157 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3158 3159 if (!hdmi_throughput) 3160 return 0; 3161 3162 /* 3163 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3164 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3165 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3166 * dividing adjusted clock value by 10. 3167 */ 3168 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3169 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3170 kslice_adjust = 10; 3171 else 3172 kslice_adjust = 5; 3173 3174 /* 3175 * As per spec, the rate at which the source and the sink process 3176 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3177 * This depends upon the pixel clock rate and output formats 3178 * (kslice adjust). 3179 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3180 * at max 340MHz, otherwise they can be processed at max 400MHz. 3181 */ 3182 3183 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3184 3185 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3186 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3187 else 3188 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3189 3190 /* 3191 * Taking into account the sink's capability for maximum 3192 * clock per slice (in MHz) as read from HF-VSDB. 3193 */ 3194 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3195 3196 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3197 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3198 3199 /* 3200 * Keep on increasing the num of slices/line, starting from min_slices 3201 * per line till we get such a number, for which the slice_width is 3202 * just less than max_slice_width. The slices/line selected should be 3203 * less than or equal to the max horizontal slices that the combination 3204 * of PCON encoder and HDMI decoder can support. 3205 */ 3206 slice_width = max_slice_width; 3207 3208 do { 3209 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3210 target_slices = 1; 3211 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3212 target_slices = 2; 3213 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3214 target_slices = 4; 3215 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3216 target_slices = 8; 3217 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3218 target_slices = 12; 3219 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3220 target_slices = 16; 3221 else 3222 return 0; 3223 3224 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3225 if (slice_width >= max_slice_width) 3226 min_slices = target_slices + 1; 3227 } while (slice_width >= max_slice_width); 3228 3229 return target_slices; 3230 } 3231 3232 /* 3233 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3234 * source and sink capabilities. 3235 * 3236 * @src_fraction_bpp: fractional bpp supported by the source 3237 * @slice_width: dsc slice width supported by the source and sink 3238 * @num_slices: num of slices supported by the source and sink 3239 * @output_format: video output format 3240 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3241 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3242 * 3243 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3244 */ 3245 int 3246 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3247 int output_format, bool hdmi_all_bpp, 3248 int hdmi_max_chunk_bytes) 3249 { 3250 int max_dsc_bpp, min_dsc_bpp; 3251 int target_bytes; 3252 bool bpp_found = false; 3253 int bpp_decrement_x16; 3254 int bpp_target; 3255 int bpp_target_x16; 3256 3257 /* 3258 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3259 * Start with the max bpp and keep on decrementing with 3260 * fractional bpp, if supported by PCON DSC encoder 3261 * 3262 * for each bpp we check if no of bytes can be supported by HDMI sink 3263 */ 3264 3265 /* Assuming: bpc as 8*/ 3266 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3267 min_dsc_bpp = 6; 3268 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3269 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3270 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3271 min_dsc_bpp = 8; 3272 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3273 } else { 3274 /* Assuming 4:2:2 encoding */ 3275 min_dsc_bpp = 7; 3276 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3277 } 3278 3279 /* 3280 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3281 * Section 7.7.34 : Source shall not enable compressed Video 3282 * Transport with bpp_target settings above 12 bpp unless 3283 * DSC_all_bpp is set to 1. 3284 */ 3285 if (!hdmi_all_bpp) 3286 max_dsc_bpp = min(max_dsc_bpp, 12); 3287 3288 /* 3289 * The Sink has a limit of compressed data in bytes for a scanline, 3290 * as described in max_chunk_bytes field in HFVSDB block of edid. 3291 * The no. of bytes depend on the target bits per pixel that the 3292 * source configures. So we start with the max_bpp and calculate 3293 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3294 * till we get the target_chunk_bytes just less than what the sink's 3295 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3296 * 3297 * The decrement is according to the fractional support from PCON DSC 3298 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3299 * 3300 * bpp_target_x16 = bpp_target * 16 3301 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3302 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3303 */ 3304 3305 bpp_target = max_dsc_bpp; 3306 3307 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3308 if (!src_fractional_bpp) 3309 src_fractional_bpp = 1; 3310 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3311 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3312 3313 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3314 int bpp; 3315 3316 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3317 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3318 if (target_bytes <= hdmi_max_chunk_bytes) { 3319 bpp_found = true; 3320 break; 3321 } 3322 bpp_target_x16 -= bpp_decrement_x16; 3323 } 3324 if (bpp_found) 3325 return bpp_target_x16; 3326 3327 return 0; 3328 } 3329