1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_probe_helper.h> 42 #include <drm/intel/intel_lpe_audio.h> 43 44 #include <media/cec-notifier.h> 45 46 #include "g4x_hdmi.h" 47 #include "i915_drv.h" 48 #include "i915_reg.h" 49 #include "intel_atomic.h" 50 #include "intel_audio.h" 51 #include "intel_connector.h" 52 #include "intel_cx0_phy.h" 53 #include "intel_ddi.h" 54 #include "intel_de.h" 55 #include "intel_display_driver.h" 56 #include "intel_display_types.h" 57 #include "intel_dp.h" 58 #include "intel_gmbus.h" 59 #include "intel_hdcp.h" 60 #include "intel_hdcp_regs.h" 61 #include "intel_hdcp_shim.h" 62 #include "intel_hdmi.h" 63 #include "intel_lspcon.h" 64 #include "intel_panel.h" 65 #include "intel_pfit.h" 66 #include "intel_snps_phy.h" 67 #include "intel_vrr.h" 68 69 static void 70 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 71 { 72 struct intel_display *display = to_intel_display(intel_hdmi); 73 u32 enabled_bits; 74 75 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 76 77 drm_WARN(display->drm, 78 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 79 "HDMI port enabled, expecting disabled\n"); 80 } 81 82 static void 83 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 84 enum transcoder cpu_transcoder) 85 { 86 drm_WARN(display->drm, 87 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 88 TRANS_DDI_FUNC_ENABLE, 89 "HDMI transcoder function enabled, expecting disabled\n"); 90 } 91 92 static u32 g4x_infoframe_index(unsigned int type) 93 { 94 switch (type) { 95 case HDMI_PACKET_TYPE_GAMUT_METADATA: 96 return VIDEO_DIP_SELECT_GAMUT; 97 case HDMI_INFOFRAME_TYPE_AVI: 98 return VIDEO_DIP_SELECT_AVI; 99 case HDMI_INFOFRAME_TYPE_SPD: 100 return VIDEO_DIP_SELECT_SPD; 101 case HDMI_INFOFRAME_TYPE_VENDOR: 102 return VIDEO_DIP_SELECT_VENDOR; 103 default: 104 MISSING_CASE(type); 105 return 0; 106 } 107 } 108 109 static u32 g4x_infoframe_enable(unsigned int type) 110 { 111 switch (type) { 112 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 113 return VIDEO_DIP_ENABLE_GCP; 114 case HDMI_PACKET_TYPE_GAMUT_METADATA: 115 return VIDEO_DIP_ENABLE_GAMUT; 116 case DP_SDP_VSC: 117 return 0; 118 case DP_SDP_ADAPTIVE_SYNC: 119 return 0; 120 case HDMI_INFOFRAME_TYPE_AVI: 121 return VIDEO_DIP_ENABLE_AVI; 122 case HDMI_INFOFRAME_TYPE_SPD: 123 return VIDEO_DIP_ENABLE_SPD; 124 case HDMI_INFOFRAME_TYPE_VENDOR: 125 return VIDEO_DIP_ENABLE_VENDOR; 126 case HDMI_INFOFRAME_TYPE_DRM: 127 return 0; 128 default: 129 MISSING_CASE(type); 130 return 0; 131 } 132 } 133 134 static u32 hsw_infoframe_enable(unsigned int type) 135 { 136 switch (type) { 137 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 138 return VIDEO_DIP_ENABLE_GCP_HSW; 139 case HDMI_PACKET_TYPE_GAMUT_METADATA: 140 return VIDEO_DIP_ENABLE_GMP_HSW; 141 case DP_SDP_VSC: 142 return VIDEO_DIP_ENABLE_VSC_HSW; 143 case DP_SDP_ADAPTIVE_SYNC: 144 return VIDEO_DIP_ENABLE_AS_ADL; 145 case DP_SDP_PPS: 146 return VDIP_ENABLE_PPS; 147 case HDMI_INFOFRAME_TYPE_AVI: 148 return VIDEO_DIP_ENABLE_AVI_HSW; 149 case HDMI_INFOFRAME_TYPE_SPD: 150 return VIDEO_DIP_ENABLE_SPD_HSW; 151 case HDMI_INFOFRAME_TYPE_VENDOR: 152 return VIDEO_DIP_ENABLE_VS_HSW; 153 case HDMI_INFOFRAME_TYPE_DRM: 154 return VIDEO_DIP_ENABLE_DRM_GLK; 155 default: 156 MISSING_CASE(type); 157 return 0; 158 } 159 } 160 161 static i915_reg_t 162 hsw_dip_data_reg(struct intel_display *display, 163 enum transcoder cpu_transcoder, 164 unsigned int type, 165 int i) 166 { 167 switch (type) { 168 case HDMI_PACKET_TYPE_GAMUT_METADATA: 169 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 170 case DP_SDP_VSC: 171 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 172 case DP_SDP_ADAPTIVE_SYNC: 173 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 174 case DP_SDP_PPS: 175 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 176 case HDMI_INFOFRAME_TYPE_AVI: 177 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 178 case HDMI_INFOFRAME_TYPE_SPD: 179 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_VENDOR: 181 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_DRM: 183 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 184 default: 185 MISSING_CASE(type); 186 return INVALID_MMIO_REG; 187 } 188 } 189 190 static int hsw_dip_data_size(struct intel_display *display, 191 unsigned int type) 192 { 193 switch (type) { 194 case DP_SDP_VSC: 195 return VIDEO_DIP_VSC_DATA_SIZE; 196 case DP_SDP_ADAPTIVE_SYNC: 197 return VIDEO_DIP_ASYNC_DATA_SIZE; 198 case DP_SDP_PPS: 199 return VIDEO_DIP_PPS_DATA_SIZE; 200 case HDMI_PACKET_TYPE_GAMUT_METADATA: 201 if (DISPLAY_VER(display) >= 11) 202 return VIDEO_DIP_GMP_DATA_SIZE; 203 else 204 return VIDEO_DIP_DATA_SIZE; 205 default: 206 return VIDEO_DIP_DATA_SIZE; 207 } 208 } 209 210 static void g4x_write_infoframe(struct intel_encoder *encoder, 211 const struct intel_crtc_state *crtc_state, 212 unsigned int type, 213 const void *frame, ssize_t len) 214 { 215 struct intel_display *display = to_intel_display(encoder); 216 const u32 *data = frame; 217 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 218 int i; 219 220 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 221 "Writing DIP with CTL reg disabled\n"); 222 223 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 224 val |= g4x_infoframe_index(type); 225 226 val &= ~g4x_infoframe_enable(type); 227 228 intel_de_write(display, VIDEO_DIP_CTL, val); 229 230 for (i = 0; i < len; i += 4) { 231 intel_de_write(display, VIDEO_DIP_DATA, *data); 232 data++; 233 } 234 /* Write every possible data byte to force correct ECC calculation. */ 235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 236 intel_de_write(display, VIDEO_DIP_DATA, 0); 237 238 val |= g4x_infoframe_enable(type); 239 val &= ~VIDEO_DIP_FREQ_MASK; 240 val |= VIDEO_DIP_FREQ_VSYNC; 241 242 intel_de_write(display, VIDEO_DIP_CTL, val); 243 intel_de_posting_read(display, VIDEO_DIP_CTL); 244 } 245 246 static void g4x_read_infoframe(struct intel_encoder *encoder, 247 const struct intel_crtc_state *crtc_state, 248 unsigned int type, 249 void *frame, ssize_t len) 250 { 251 struct intel_display *display = to_intel_display(encoder); 252 u32 *data = frame; 253 int i; 254 255 intel_de_rmw(display, VIDEO_DIP_CTL, 256 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 257 258 for (i = 0; i < len; i += 4) 259 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 260 } 261 262 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 263 const struct intel_crtc_state *pipe_config) 264 { 265 struct intel_display *display = to_intel_display(encoder); 266 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 267 268 if ((val & VIDEO_DIP_ENABLE) == 0) 269 return 0; 270 271 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 272 return 0; 273 274 return val & (VIDEO_DIP_ENABLE_AVI | 275 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 276 } 277 278 static void ibx_write_infoframe(struct intel_encoder *encoder, 279 const struct intel_crtc_state *crtc_state, 280 unsigned int type, 281 const void *frame, ssize_t len) 282 { 283 struct intel_display *display = to_intel_display(encoder); 284 const u32 *data = frame; 285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 286 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 287 u32 val = intel_de_read(display, reg); 288 int i; 289 290 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 291 "Writing DIP with CTL reg disabled\n"); 292 293 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 294 val |= g4x_infoframe_index(type); 295 296 val &= ~g4x_infoframe_enable(type); 297 298 intel_de_write(display, reg, val); 299 300 for (i = 0; i < len; i += 4) { 301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 302 *data); 303 data++; 304 } 305 /* Write every possible data byte to force correct ECC calculation. */ 306 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 307 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 308 309 val |= g4x_infoframe_enable(type); 310 val &= ~VIDEO_DIP_FREQ_MASK; 311 val |= VIDEO_DIP_FREQ_VSYNC; 312 313 intel_de_write(display, reg, val); 314 intel_de_posting_read(display, reg); 315 } 316 317 static void ibx_read_infoframe(struct intel_encoder *encoder, 318 const struct intel_crtc_state *crtc_state, 319 unsigned int type, 320 void *frame, ssize_t len) 321 { 322 struct intel_display *display = to_intel_display(encoder); 323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 324 u32 *data = frame; 325 int i; 326 327 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 328 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 329 330 for (i = 0; i < len; i += 4) 331 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 332 } 333 334 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 335 const struct intel_crtc_state *pipe_config) 336 { 337 struct intel_display *display = to_intel_display(encoder); 338 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 339 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 340 u32 val = intel_de_read(display, reg); 341 342 if ((val & VIDEO_DIP_ENABLE) == 0) 343 return 0; 344 345 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 346 return 0; 347 348 return val & (VIDEO_DIP_ENABLE_AVI | 349 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 350 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 351 } 352 353 static void cpt_write_infoframe(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state, 355 unsigned int type, 356 const void *frame, ssize_t len) 357 { 358 struct intel_display *display = to_intel_display(encoder); 359 const u32 *data = frame; 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 362 u32 val = intel_de_read(display, reg); 363 int i; 364 365 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 366 "Writing DIP with CTL reg disabled\n"); 367 368 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 369 val |= g4x_infoframe_index(type); 370 371 /* The DIP control register spec says that we need to update the AVI 372 * infoframe without clearing its enable bit */ 373 if (type != HDMI_INFOFRAME_TYPE_AVI) 374 val &= ~g4x_infoframe_enable(type); 375 376 intel_de_write(display, reg, val); 377 378 for (i = 0; i < len; i += 4) { 379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 380 *data); 381 data++; 382 } 383 /* Write every possible data byte to force correct ECC calculation. */ 384 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 385 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 386 387 val |= g4x_infoframe_enable(type); 388 val &= ~VIDEO_DIP_FREQ_MASK; 389 val |= VIDEO_DIP_FREQ_VSYNC; 390 391 intel_de_write(display, reg, val); 392 intel_de_posting_read(display, reg); 393 } 394 395 static void cpt_read_infoframe(struct intel_encoder *encoder, 396 const struct intel_crtc_state *crtc_state, 397 unsigned int type, 398 void *frame, ssize_t len) 399 { 400 struct intel_display *display = to_intel_display(encoder); 401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 402 u32 *data = frame; 403 int i; 404 405 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 406 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 407 408 for (i = 0; i < len; i += 4) 409 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 410 } 411 412 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 413 const struct intel_crtc_state *pipe_config) 414 { 415 struct intel_display *display = to_intel_display(encoder); 416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 417 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 418 419 if ((val & VIDEO_DIP_ENABLE) == 0) 420 return 0; 421 422 return val & (VIDEO_DIP_ENABLE_AVI | 423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 425 } 426 427 static void vlv_write_infoframe(struct intel_encoder *encoder, 428 const struct intel_crtc_state *crtc_state, 429 unsigned int type, 430 const void *frame, ssize_t len) 431 { 432 struct intel_display *display = to_intel_display(encoder); 433 const u32 *data = frame; 434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 436 u32 val = intel_de_read(display, reg); 437 int i; 438 439 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 440 "Writing DIP with CTL reg disabled\n"); 441 442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 443 val |= g4x_infoframe_index(type); 444 445 val &= ~g4x_infoframe_enable(type); 446 447 intel_de_write(display, reg, val); 448 449 for (i = 0; i < len; i += 4) { 450 intel_de_write(display, 451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 452 data++; 453 } 454 /* Write every possible data byte to force correct ECC calculation. */ 455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 456 intel_de_write(display, 457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 458 459 val |= g4x_infoframe_enable(type); 460 val &= ~VIDEO_DIP_FREQ_MASK; 461 val |= VIDEO_DIP_FREQ_VSYNC; 462 463 intel_de_write(display, reg, val); 464 intel_de_posting_read(display, reg); 465 } 466 467 static void vlv_read_infoframe(struct intel_encoder *encoder, 468 const struct intel_crtc_state *crtc_state, 469 unsigned int type, 470 void *frame, ssize_t len) 471 { 472 struct intel_display *display = to_intel_display(encoder); 473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 474 u32 *data = frame; 475 int i; 476 477 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 478 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 479 480 for (i = 0; i < len; i += 4) 481 *data++ = intel_de_read(display, 482 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 483 } 484 485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 486 const struct intel_crtc_state *pipe_config) 487 { 488 struct intel_display *display = to_intel_display(encoder); 489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 490 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 491 492 if ((val & VIDEO_DIP_ENABLE) == 0) 493 return 0; 494 495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 496 return 0; 497 498 return val & (VIDEO_DIP_ENABLE_AVI | 499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 501 } 502 503 void hsw_write_infoframe(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 unsigned int type, 506 const void *frame, ssize_t len) 507 { 508 struct intel_display *display = to_intel_display(encoder); 509 const u32 *data = frame; 510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 512 int data_size; 513 int i; 514 u32 val = intel_de_read(display, ctl_reg); 515 516 data_size = hsw_dip_data_size(display, type); 517 518 drm_WARN_ON(display->drm, len > data_size); 519 520 val &= ~hsw_infoframe_enable(type); 521 intel_de_write(display, ctl_reg, val); 522 523 for (i = 0; i < len; i += 4) { 524 intel_de_write(display, 525 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 526 *data); 527 data++; 528 } 529 /* Write every possible data byte to force correct ECC calculation. */ 530 for (; i < data_size; i += 4) 531 intel_de_write(display, 532 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 533 0); 534 535 /* Wa_14013475917 */ 536 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 537 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 538 val |= hsw_infoframe_enable(type); 539 540 if (type == DP_SDP_VSC) 541 val |= VSC_DIP_HW_DATA_SW_HEA; 542 543 intel_de_write(display, ctl_reg, val); 544 intel_de_posting_read(display, ctl_reg); 545 } 546 547 void hsw_read_infoframe(struct intel_encoder *encoder, 548 const struct intel_crtc_state *crtc_state, 549 unsigned int type, void *frame, ssize_t len) 550 { 551 struct intel_display *display = to_intel_display(encoder); 552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 553 u32 *data = frame; 554 int i; 555 556 for (i = 0; i < len; i += 4) 557 *data++ = intel_de_read(display, 558 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 559 } 560 561 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 562 const struct intel_crtc_state *pipe_config) 563 { 564 struct intel_display *display = to_intel_display(encoder); 565 u32 val = intel_de_read(display, 566 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 567 u32 mask; 568 569 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 570 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 571 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 572 573 if (DISPLAY_VER(display) >= 10) 574 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 575 576 if (HAS_AS_SDP(display)) 577 mask |= VIDEO_DIP_ENABLE_AS_ADL; 578 579 return val & mask; 580 } 581 582 static const u8 infoframe_type_to_idx[] = { 583 HDMI_PACKET_TYPE_GENERAL_CONTROL, 584 HDMI_PACKET_TYPE_GAMUT_METADATA, 585 DP_SDP_VSC, 586 DP_SDP_ADAPTIVE_SYNC, 587 HDMI_INFOFRAME_TYPE_AVI, 588 HDMI_INFOFRAME_TYPE_SPD, 589 HDMI_INFOFRAME_TYPE_VENDOR, 590 HDMI_INFOFRAME_TYPE_DRM, 591 }; 592 593 u32 intel_hdmi_infoframe_enable(unsigned int type) 594 { 595 int i; 596 597 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 598 if (infoframe_type_to_idx[i] == type) 599 return BIT(i); 600 } 601 602 return 0; 603 } 604 605 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 606 const struct intel_crtc_state *crtc_state) 607 { 608 struct intel_display *display = to_intel_display(encoder); 609 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 610 u32 val, ret = 0; 611 int i; 612 613 val = dig_port->infoframes_enabled(encoder, crtc_state); 614 615 /* map from hardware bits to dip idx */ 616 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 617 unsigned int type = infoframe_type_to_idx[i]; 618 619 if (HAS_DDI(display)) { 620 if (val & hsw_infoframe_enable(type)) 621 ret |= BIT(i); 622 } else { 623 if (val & g4x_infoframe_enable(type)) 624 ret |= BIT(i); 625 } 626 } 627 628 return ret; 629 } 630 631 /* 632 * The data we write to the DIP data buffer registers is 1 byte bigger than the 633 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 634 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 635 * used for both technologies. 636 * 637 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 638 * DW1: DB3 | DB2 | DB1 | DB0 639 * DW2: DB7 | DB6 | DB5 | DB4 640 * DW3: ... 641 * 642 * (HB is Header Byte, DB is Data Byte) 643 * 644 * The hdmi pack() functions don't know about that hardware specific hole so we 645 * trick them by giving an offset into the buffer and moving back the header 646 * bytes by one. 647 */ 648 static void intel_write_infoframe(struct intel_encoder *encoder, 649 const struct intel_crtc_state *crtc_state, 650 enum hdmi_infoframe_type type, 651 const union hdmi_infoframe *frame) 652 { 653 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 654 u8 buffer[VIDEO_DIP_DATA_SIZE]; 655 ssize_t len; 656 657 if ((crtc_state->infoframes.enable & 658 intel_hdmi_infoframe_enable(type)) == 0) 659 return; 660 661 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 662 return; 663 664 /* see comment above for the reason for this offset */ 665 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 666 if (drm_WARN_ON(encoder->base.dev, len < 0)) 667 return; 668 669 /* Insert the 'hole' (see big comment above) at position 3 */ 670 memmove(&buffer[0], &buffer[1], 3); 671 buffer[3] = 0; 672 len++; 673 674 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 675 } 676 677 void intel_read_infoframe(struct intel_encoder *encoder, 678 const struct intel_crtc_state *crtc_state, 679 enum hdmi_infoframe_type type, 680 union hdmi_infoframe *frame) 681 { 682 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 683 u8 buffer[VIDEO_DIP_DATA_SIZE]; 684 int ret; 685 686 if ((crtc_state->infoframes.enable & 687 intel_hdmi_infoframe_enable(type)) == 0) 688 return; 689 690 dig_port->read_infoframe(encoder, crtc_state, 691 type, buffer, sizeof(buffer)); 692 693 /* Fill the 'hole' (see big comment above) at position 3 */ 694 memmove(&buffer[1], &buffer[0], 3); 695 696 /* see comment above for the reason for this offset */ 697 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 698 if (ret) { 699 drm_dbg_kms(encoder->base.dev, 700 "Failed to unpack infoframe type 0x%02x\n", type); 701 return; 702 } 703 704 if (frame->any.type != type) 705 drm_dbg_kms(encoder->base.dev, 706 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 707 frame->any.type, type); 708 } 709 710 static bool 711 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 712 struct intel_crtc_state *crtc_state, 713 struct drm_connector_state *conn_state) 714 { 715 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 716 const struct drm_display_mode *adjusted_mode = 717 &crtc_state->hw.adjusted_mode; 718 struct drm_connector *connector = conn_state->connector; 719 int ret; 720 721 if (!crtc_state->has_infoframe) 722 return true; 723 724 crtc_state->infoframes.enable |= 725 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 726 727 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 728 adjusted_mode); 729 if (ret) 730 return false; 731 732 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 733 frame->colorspace = HDMI_COLORSPACE_YUV420; 734 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 735 frame->colorspace = HDMI_COLORSPACE_YUV444; 736 else 737 frame->colorspace = HDMI_COLORSPACE_RGB; 738 739 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 740 741 /* nonsense combination */ 742 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 743 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 744 745 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 746 drm_hdmi_avi_infoframe_quant_range(frame, connector, 747 adjusted_mode, 748 crtc_state->limited_color_range ? 749 HDMI_QUANTIZATION_RANGE_LIMITED : 750 HDMI_QUANTIZATION_RANGE_FULL); 751 } else { 752 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 753 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 754 } 755 756 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 757 758 /* TODO: handle pixel repetition for YCBCR420 outputs */ 759 760 ret = hdmi_avi_infoframe_check(frame); 761 if (drm_WARN_ON(encoder->base.dev, ret)) 762 return false; 763 764 return true; 765 } 766 767 static bool 768 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 769 struct intel_crtc_state *crtc_state, 770 struct drm_connector_state *conn_state) 771 { 772 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 773 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 774 int ret; 775 776 if (!crtc_state->has_infoframe) 777 return true; 778 779 crtc_state->infoframes.enable |= 780 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 781 782 if (IS_DGFX(i915)) 783 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 784 else 785 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 786 787 if (drm_WARN_ON(encoder->base.dev, ret)) 788 return false; 789 790 frame->sdi = HDMI_SPD_SDI_PC; 791 792 ret = hdmi_spd_infoframe_check(frame); 793 if (drm_WARN_ON(encoder->base.dev, ret)) 794 return false; 795 796 return true; 797 } 798 799 static bool 800 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 801 struct intel_crtc_state *crtc_state, 802 struct drm_connector_state *conn_state) 803 { 804 struct hdmi_vendor_infoframe *frame = 805 &crtc_state->infoframes.hdmi.vendor.hdmi; 806 const struct drm_display_info *info = 807 &conn_state->connector->display_info; 808 int ret; 809 810 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 811 return true; 812 813 crtc_state->infoframes.enable |= 814 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 815 816 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 817 conn_state->connector, 818 &crtc_state->hw.adjusted_mode); 819 if (drm_WARN_ON(encoder->base.dev, ret)) 820 return false; 821 822 ret = hdmi_vendor_infoframe_check(frame); 823 if (drm_WARN_ON(encoder->base.dev, ret)) 824 return false; 825 826 return true; 827 } 828 829 static bool 830 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 831 struct intel_crtc_state *crtc_state, 832 struct drm_connector_state *conn_state) 833 { 834 struct intel_display *display = to_intel_display(encoder); 835 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 836 int ret; 837 838 if (DISPLAY_VER(display) < 10) 839 return true; 840 841 if (!crtc_state->has_infoframe) 842 return true; 843 844 if (!conn_state->hdr_output_metadata) 845 return true; 846 847 crtc_state->infoframes.enable |= 848 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 849 850 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 851 if (ret < 0) { 852 drm_dbg_kms(display->drm, 853 "couldn't set HDR metadata in infoframe\n"); 854 return false; 855 } 856 857 ret = hdmi_drm_infoframe_check(frame); 858 if (drm_WARN_ON(display->drm, ret)) 859 return false; 860 861 return true; 862 } 863 864 static void g4x_set_infoframes(struct intel_encoder *encoder, 865 bool enable, 866 const struct intel_crtc_state *crtc_state, 867 const struct drm_connector_state *conn_state) 868 { 869 struct intel_display *display = to_intel_display(encoder); 870 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 871 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 872 i915_reg_t reg = VIDEO_DIP_CTL; 873 u32 val = intel_de_read(display, reg); 874 u32 port = VIDEO_DIP_PORT(encoder->port); 875 876 assert_hdmi_port_disabled(intel_hdmi); 877 878 /* If the registers were not initialized yet, they might be zeroes, 879 * which means we're selecting the AVI DIP and we're setting its 880 * frequency to once. This seems to really confuse the HW and make 881 * things stop working (the register spec says the AVI always needs to 882 * be sent every VSync). So here we avoid writing to the register more 883 * than we need and also explicitly select the AVI DIP and explicitly 884 * set its frequency to every VSync. Avoiding to write it twice seems to 885 * be enough to solve the problem, but being defensive shouldn't hurt us 886 * either. */ 887 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 888 889 if (!enable) { 890 if (!(val & VIDEO_DIP_ENABLE)) 891 return; 892 if (port != (val & VIDEO_DIP_PORT_MASK)) { 893 drm_dbg_kms(display->drm, 894 "video DIP still enabled on port %c\n", 895 (val & VIDEO_DIP_PORT_MASK) >> 29); 896 return; 897 } 898 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 899 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 900 intel_de_write(display, reg, val); 901 intel_de_posting_read(display, reg); 902 return; 903 } 904 905 if (port != (val & VIDEO_DIP_PORT_MASK)) { 906 if (val & VIDEO_DIP_ENABLE) { 907 drm_dbg_kms(display->drm, 908 "video DIP already enabled on port %c\n", 909 (val & VIDEO_DIP_PORT_MASK) >> 29); 910 return; 911 } 912 val &= ~VIDEO_DIP_PORT_MASK; 913 val |= port; 914 } 915 916 val |= VIDEO_DIP_ENABLE; 917 val &= ~(VIDEO_DIP_ENABLE_AVI | 918 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 919 920 intel_de_write(display, reg, val); 921 intel_de_posting_read(display, reg); 922 923 intel_write_infoframe(encoder, crtc_state, 924 HDMI_INFOFRAME_TYPE_AVI, 925 &crtc_state->infoframes.avi); 926 intel_write_infoframe(encoder, crtc_state, 927 HDMI_INFOFRAME_TYPE_SPD, 928 &crtc_state->infoframes.spd); 929 intel_write_infoframe(encoder, crtc_state, 930 HDMI_INFOFRAME_TYPE_VENDOR, 931 &crtc_state->infoframes.hdmi); 932 } 933 934 /* 935 * Determine if default_phase=1 can be indicated in the GCP infoframe. 936 * 937 * From HDMI specification 1.4a: 938 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 939 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 940 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 941 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 942 * phase of 0 943 */ 944 static bool gcp_default_phase_possible(int pipe_bpp, 945 const struct drm_display_mode *mode) 946 { 947 unsigned int pixels_per_group; 948 949 switch (pipe_bpp) { 950 case 30: 951 /* 4 pixels in 5 clocks */ 952 pixels_per_group = 4; 953 break; 954 case 36: 955 /* 2 pixels in 3 clocks */ 956 pixels_per_group = 2; 957 break; 958 case 48: 959 /* 1 pixel in 2 clocks */ 960 pixels_per_group = 1; 961 break; 962 default: 963 /* phase information not relevant for 8bpc */ 964 return false; 965 } 966 967 return mode->crtc_hdisplay % pixels_per_group == 0 && 968 mode->crtc_htotal % pixels_per_group == 0 && 969 mode->crtc_hblank_start % pixels_per_group == 0 && 970 mode->crtc_hblank_end % pixels_per_group == 0 && 971 mode->crtc_hsync_start % pixels_per_group == 0 && 972 mode->crtc_hsync_end % pixels_per_group == 0 && 973 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 974 mode->crtc_htotal/2 % pixels_per_group == 0); 975 } 976 977 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 978 const struct intel_crtc_state *crtc_state, 979 const struct drm_connector_state *conn_state) 980 { 981 struct intel_display *display = to_intel_display(encoder); 982 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 983 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 984 i915_reg_t reg; 985 986 if ((crtc_state->infoframes.enable & 987 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 988 return false; 989 990 if (HAS_DDI(display)) 991 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 992 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 993 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 994 else if (HAS_PCH_SPLIT(dev_priv)) 995 reg = TVIDEO_DIP_GCP(crtc->pipe); 996 else 997 return false; 998 999 intel_de_write(display, reg, crtc_state->infoframes.gcp); 1000 1001 return true; 1002 } 1003 1004 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1005 struct intel_crtc_state *crtc_state) 1006 { 1007 struct intel_display *display = to_intel_display(encoder); 1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1010 i915_reg_t reg; 1011 1012 if ((crtc_state->infoframes.enable & 1013 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1014 return; 1015 1016 if (HAS_DDI(display)) 1017 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1018 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1019 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1020 else if (HAS_PCH_SPLIT(dev_priv)) 1021 reg = TVIDEO_DIP_GCP(crtc->pipe); 1022 else 1023 return; 1024 1025 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1026 } 1027 1028 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1029 struct intel_crtc_state *crtc_state, 1030 struct drm_connector_state *conn_state) 1031 { 1032 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1033 1034 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1035 return; 1036 1037 crtc_state->infoframes.enable |= 1038 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1039 1040 /* Indicate color indication for deep color mode */ 1041 if (crtc_state->pipe_bpp > 24) 1042 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1043 1044 /* Enable default_phase whenever the display mode is suitably aligned */ 1045 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1046 &crtc_state->hw.adjusted_mode)) 1047 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1048 } 1049 1050 static void ibx_set_infoframes(struct intel_encoder *encoder, 1051 bool enable, 1052 const struct intel_crtc_state *crtc_state, 1053 const struct drm_connector_state *conn_state) 1054 { 1055 struct intel_display *display = to_intel_display(encoder); 1056 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1057 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1058 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1059 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1060 u32 val = intel_de_read(display, reg); 1061 u32 port = VIDEO_DIP_PORT(encoder->port); 1062 1063 assert_hdmi_port_disabled(intel_hdmi); 1064 1065 /* See the big comment in g4x_set_infoframes() */ 1066 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1067 1068 if (!enable) { 1069 if (!(val & VIDEO_DIP_ENABLE)) 1070 return; 1071 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1072 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1073 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1074 intel_de_write(display, reg, val); 1075 intel_de_posting_read(display, reg); 1076 return; 1077 } 1078 1079 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1080 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1081 "DIP already enabled on port %c\n", 1082 (val & VIDEO_DIP_PORT_MASK) >> 29); 1083 val &= ~VIDEO_DIP_PORT_MASK; 1084 val |= port; 1085 } 1086 1087 val |= VIDEO_DIP_ENABLE; 1088 val &= ~(VIDEO_DIP_ENABLE_AVI | 1089 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1090 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1091 1092 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1093 val |= VIDEO_DIP_ENABLE_GCP; 1094 1095 intel_de_write(display, reg, val); 1096 intel_de_posting_read(display, reg); 1097 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_AVI, 1100 &crtc_state->infoframes.avi); 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_SPD, 1103 &crtc_state->infoframes.spd); 1104 intel_write_infoframe(encoder, crtc_state, 1105 HDMI_INFOFRAME_TYPE_VENDOR, 1106 &crtc_state->infoframes.hdmi); 1107 } 1108 1109 static void cpt_set_infoframes(struct intel_encoder *encoder, 1110 bool enable, 1111 const struct intel_crtc_state *crtc_state, 1112 const struct drm_connector_state *conn_state) 1113 { 1114 struct intel_display *display = to_intel_display(encoder); 1115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1116 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1117 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1118 u32 val = intel_de_read(display, reg); 1119 1120 assert_hdmi_port_disabled(intel_hdmi); 1121 1122 /* See the big comment in g4x_set_infoframes() */ 1123 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1124 1125 if (!enable) { 1126 if (!(val & VIDEO_DIP_ENABLE)) 1127 return; 1128 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1129 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1131 intel_de_write(display, reg, val); 1132 intel_de_posting_read(display, reg); 1133 return; 1134 } 1135 1136 /* Set both together, unset both together: see the spec. */ 1137 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1138 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1139 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1140 1141 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1142 val |= VIDEO_DIP_ENABLE_GCP; 1143 1144 intel_de_write(display, reg, val); 1145 intel_de_posting_read(display, reg); 1146 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_AVI, 1149 &crtc_state->infoframes.avi); 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_SPD, 1152 &crtc_state->infoframes.spd); 1153 intel_write_infoframe(encoder, crtc_state, 1154 HDMI_INFOFRAME_TYPE_VENDOR, 1155 &crtc_state->infoframes.hdmi); 1156 } 1157 1158 static void vlv_set_infoframes(struct intel_encoder *encoder, 1159 bool enable, 1160 const struct intel_crtc_state *crtc_state, 1161 const struct drm_connector_state *conn_state) 1162 { 1163 struct intel_display *display = to_intel_display(encoder); 1164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1165 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1166 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1167 u32 val = intel_de_read(display, reg); 1168 u32 port = VIDEO_DIP_PORT(encoder->port); 1169 1170 assert_hdmi_port_disabled(intel_hdmi); 1171 1172 /* See the big comment in g4x_set_infoframes() */ 1173 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1174 1175 if (!enable) { 1176 if (!(val & VIDEO_DIP_ENABLE)) 1177 return; 1178 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1179 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1180 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1181 intel_de_write(display, reg, val); 1182 intel_de_posting_read(display, reg); 1183 return; 1184 } 1185 1186 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1187 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1188 "DIP already enabled on port %c\n", 1189 (val & VIDEO_DIP_PORT_MASK) >> 29); 1190 val &= ~VIDEO_DIP_PORT_MASK; 1191 val |= port; 1192 } 1193 1194 val |= VIDEO_DIP_ENABLE; 1195 val &= ~(VIDEO_DIP_ENABLE_AVI | 1196 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1197 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1198 1199 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1200 val |= VIDEO_DIP_ENABLE_GCP; 1201 1202 intel_de_write(display, reg, val); 1203 intel_de_posting_read(display, reg); 1204 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_AVI, 1207 &crtc_state->infoframes.avi); 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_SPD, 1210 &crtc_state->infoframes.spd); 1211 intel_write_infoframe(encoder, crtc_state, 1212 HDMI_INFOFRAME_TYPE_VENDOR, 1213 &crtc_state->infoframes.hdmi); 1214 } 1215 1216 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, 1217 const struct intel_crtc_state *crtc_state, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct intel_display *display = to_intel_display(encoder); 1221 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1222 crtc_state->cpu_transcoder); 1223 u32 val = intel_de_read(display, reg); 1224 1225 if ((crtc_state->infoframes.enable & 1226 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 && 1227 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0) 1228 return; 1229 1230 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK); 1231 1232 intel_de_write(display, reg, val); 1233 intel_de_posting_read(display, reg); 1234 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_DRM, 1237 &crtc_state->infoframes.drm); 1238 } 1239 1240 static void hsw_set_infoframes(struct intel_encoder *encoder, 1241 bool enable, 1242 const struct intel_crtc_state *crtc_state, 1243 const struct drm_connector_state *conn_state) 1244 { 1245 struct intel_display *display = to_intel_display(encoder); 1246 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1247 crtc_state->cpu_transcoder); 1248 u32 val = intel_de_read(display, reg); 1249 1250 assert_hdmi_transcoder_func_disabled(display, 1251 crtc_state->cpu_transcoder); 1252 1253 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1254 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1255 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1256 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1257 1258 if (!enable) { 1259 intel_de_write(display, reg, val); 1260 intel_de_posting_read(display, reg); 1261 return; 1262 } 1263 1264 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1265 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1266 1267 intel_de_write(display, reg, val); 1268 intel_de_posting_read(display, reg); 1269 1270 intel_write_infoframe(encoder, crtc_state, 1271 HDMI_INFOFRAME_TYPE_AVI, 1272 &crtc_state->infoframes.avi); 1273 intel_write_infoframe(encoder, crtc_state, 1274 HDMI_INFOFRAME_TYPE_SPD, 1275 &crtc_state->infoframes.spd); 1276 intel_write_infoframe(encoder, crtc_state, 1277 HDMI_INFOFRAME_TYPE_VENDOR, 1278 &crtc_state->infoframes.hdmi); 1279 intel_write_infoframe(encoder, crtc_state, 1280 HDMI_INFOFRAME_TYPE_DRM, 1281 &crtc_state->infoframes.drm); 1282 } 1283 1284 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1285 { 1286 struct intel_display *display = to_intel_display(hdmi); 1287 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1288 1289 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1290 return; 1291 1292 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1293 enable ? "Enabling" : "Disabling"); 1294 1295 drm_dp_dual_mode_set_tmds_output(display->drm, 1296 hdmi->dp_dual_mode.type, ddc, enable); 1297 } 1298 1299 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1300 unsigned int offset, void *buffer, size_t size) 1301 { 1302 struct intel_hdmi *hdmi = &dig_port->hdmi; 1303 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1304 int ret; 1305 u8 start = offset & 0xff; 1306 struct i2c_msg msgs[] = { 1307 { 1308 .addr = DRM_HDCP_DDC_ADDR, 1309 .flags = 0, 1310 .len = 1, 1311 .buf = &start, 1312 }, 1313 { 1314 .addr = DRM_HDCP_DDC_ADDR, 1315 .flags = I2C_M_RD, 1316 .len = size, 1317 .buf = buffer 1318 } 1319 }; 1320 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1321 if (ret == ARRAY_SIZE(msgs)) 1322 return 0; 1323 return ret >= 0 ? -EIO : ret; 1324 } 1325 1326 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1327 unsigned int offset, void *buffer, size_t size) 1328 { 1329 struct intel_hdmi *hdmi = &dig_port->hdmi; 1330 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1331 int ret; 1332 u8 *write_buf; 1333 struct i2c_msg msg; 1334 1335 write_buf = kzalloc(size + 1, GFP_KERNEL); 1336 if (!write_buf) 1337 return -ENOMEM; 1338 1339 write_buf[0] = offset & 0xff; 1340 memcpy(&write_buf[1], buffer, size); 1341 1342 msg.addr = DRM_HDCP_DDC_ADDR; 1343 msg.flags = 0; 1344 msg.len = size + 1; 1345 msg.buf = write_buf; 1346 1347 ret = i2c_transfer(ddc, &msg, 1); 1348 if (ret == 1) 1349 ret = 0; 1350 else if (ret >= 0) 1351 ret = -EIO; 1352 1353 kfree(write_buf); 1354 return ret; 1355 } 1356 1357 static 1358 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1359 u8 *an) 1360 { 1361 struct intel_display *display = to_intel_display(dig_port); 1362 struct intel_hdmi *hdmi = &dig_port->hdmi; 1363 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1364 int ret; 1365 1366 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1367 DRM_HDCP_AN_LEN); 1368 if (ret) { 1369 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1370 ret); 1371 return ret; 1372 } 1373 1374 ret = intel_gmbus_output_aksv(ddc); 1375 if (ret < 0) { 1376 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1377 return ret; 1378 } 1379 return 0; 1380 } 1381 1382 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1383 u8 *bksv) 1384 { 1385 struct intel_display *display = to_intel_display(dig_port); 1386 1387 int ret; 1388 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1389 DRM_HDCP_KSV_LEN); 1390 if (ret) 1391 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1392 ret); 1393 return ret; 1394 } 1395 1396 static 1397 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1398 u8 *bstatus) 1399 { 1400 struct intel_display *display = to_intel_display(dig_port); 1401 1402 int ret; 1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1404 bstatus, DRM_HDCP_BSTATUS_LEN); 1405 if (ret) 1406 drm_dbg_kms(display->drm, 1407 "Read bstatus over DDC failed (%d)\n", 1408 ret); 1409 return ret; 1410 } 1411 1412 static 1413 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1414 bool *repeater_present) 1415 { 1416 struct intel_display *display = to_intel_display(dig_port); 1417 int ret; 1418 u8 val; 1419 1420 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1421 if (ret) { 1422 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1423 ret); 1424 return ret; 1425 } 1426 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1427 return 0; 1428 } 1429 1430 static 1431 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1432 u8 *ri_prime) 1433 { 1434 struct intel_display *display = to_intel_display(dig_port); 1435 1436 int ret; 1437 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1438 ri_prime, DRM_HDCP_RI_LEN); 1439 if (ret) 1440 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1441 ret); 1442 return ret; 1443 } 1444 1445 static 1446 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1447 bool *ksv_ready) 1448 { 1449 struct intel_display *display = to_intel_display(dig_port); 1450 int ret; 1451 u8 val; 1452 1453 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1454 if (ret) { 1455 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1456 ret); 1457 return ret; 1458 } 1459 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1460 return 0; 1461 } 1462 1463 static 1464 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1465 int num_downstream, u8 *ksv_fifo) 1466 { 1467 struct intel_display *display = to_intel_display(dig_port); 1468 int ret; 1469 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1470 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1471 if (ret) { 1472 drm_dbg_kms(display->drm, 1473 "Read ksv fifo over DDC failed (%d)\n", ret); 1474 return ret; 1475 } 1476 return 0; 1477 } 1478 1479 static 1480 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1481 int i, u32 *part) 1482 { 1483 struct intel_display *display = to_intel_display(dig_port); 1484 int ret; 1485 1486 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1487 return -EINVAL; 1488 1489 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1490 part, DRM_HDCP_V_PRIME_PART_LEN); 1491 if (ret) 1492 drm_dbg_kms(display->drm, 1493 "Read V'[%d] over DDC failed (%d)\n", 1494 i, ret); 1495 return ret; 1496 } 1497 1498 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1499 enum transcoder cpu_transcoder) 1500 { 1501 struct intel_display *display = to_intel_display(connector); 1502 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1503 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1504 u32 scanline; 1505 int ret; 1506 1507 for (;;) { 1508 scanline = intel_de_read(display, 1509 PIPEDSL(display, crtc->pipe)); 1510 if (scanline > 100 && scanline < 200) 1511 break; 1512 usleep_range(25, 50); 1513 } 1514 1515 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1516 false, TRANS_DDI_HDCP_SIGNALLING); 1517 if (ret) { 1518 drm_err(display->drm, 1519 "Disable HDCP signalling failed (%d)\n", ret); 1520 return ret; 1521 } 1522 1523 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1524 true, TRANS_DDI_HDCP_SIGNALLING); 1525 if (ret) { 1526 drm_err(display->drm, 1527 "Enable HDCP signalling failed (%d)\n", ret); 1528 return ret; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static 1535 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1536 enum transcoder cpu_transcoder, 1537 bool enable) 1538 { 1539 struct intel_display *display = to_intel_display(dig_port); 1540 struct intel_hdmi *hdmi = &dig_port->hdmi; 1541 struct intel_connector *connector = hdmi->attached_connector; 1542 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1543 int ret; 1544 1545 if (!enable) 1546 usleep_range(6, 60); /* Bspec says >= 6us */ 1547 1548 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1549 cpu_transcoder, enable, 1550 TRANS_DDI_HDCP_SIGNALLING); 1551 if (ret) { 1552 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1553 enable ? "Enable" : "Disable", ret); 1554 return ret; 1555 } 1556 1557 /* 1558 * WA: To fix incorrect positioning of the window of 1559 * opportunity and enc_en signalling in KABYLAKE. 1560 */ 1561 if (IS_KABYLAKE(dev_priv) && enable) 1562 return kbl_repositioning_enc_en_signal(connector, 1563 cpu_transcoder); 1564 1565 return 0; 1566 } 1567 1568 static 1569 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1570 struct intel_connector *connector) 1571 { 1572 struct intel_display *display = to_intel_display(dig_port); 1573 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1574 enum port port = dig_port->base.port; 1575 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1576 int ret; 1577 union { 1578 u32 reg; 1579 u8 shim[DRM_HDCP_RI_LEN]; 1580 } ri; 1581 1582 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1583 if (ret) 1584 return false; 1585 1586 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1587 1588 /* Wait for Ri prime match */ 1589 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1590 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1591 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1592 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1593 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1594 port))); 1595 return false; 1596 } 1597 return true; 1598 } 1599 1600 static 1601 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1602 struct intel_connector *connector) 1603 { 1604 int retry; 1605 1606 for (retry = 0; retry < 3; retry++) 1607 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1608 return true; 1609 1610 return false; 1611 } 1612 1613 struct hdcp2_hdmi_msg_timeout { 1614 u8 msg_id; 1615 u16 timeout; 1616 }; 1617 1618 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1619 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1620 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1621 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1622 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1623 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1624 }; 1625 1626 static 1627 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1628 u8 *rx_status) 1629 { 1630 return intel_hdmi_hdcp_read(dig_port, 1631 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1632 rx_status, 1633 HDCP_2_2_HDMI_RXSTATUS_LEN); 1634 } 1635 1636 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1637 { 1638 int i; 1639 1640 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1641 if (is_paired) 1642 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1643 else 1644 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1645 } 1646 1647 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1648 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1649 return hdcp2_msg_timeout[i].timeout; 1650 } 1651 1652 return -EINVAL; 1653 } 1654 1655 static int 1656 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1657 u8 msg_id, bool *msg_ready, 1658 ssize_t *msg_sz) 1659 { 1660 struct intel_display *display = to_intel_display(dig_port); 1661 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1662 int ret; 1663 1664 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1665 if (ret < 0) { 1666 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1667 ret); 1668 return ret; 1669 } 1670 1671 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1672 rx_status[0]); 1673 1674 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1675 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1676 *msg_sz); 1677 else 1678 *msg_ready = *msg_sz; 1679 1680 return 0; 1681 } 1682 1683 static ssize_t 1684 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1685 u8 msg_id, bool paired) 1686 { 1687 struct intel_display *display = to_intel_display(dig_port); 1688 bool msg_ready = false; 1689 int timeout, ret; 1690 ssize_t msg_sz = 0; 1691 1692 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1693 if (timeout < 0) 1694 return timeout; 1695 1696 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1697 msg_id, &msg_ready, 1698 &msg_sz), 1699 !ret && msg_ready && msg_sz, timeout * 1000, 1700 1000, 5 * 1000); 1701 if (ret) 1702 drm_dbg_kms(display->drm, 1703 "msg_id: %d, ret: %d, timeout: %d\n", 1704 msg_id, ret, timeout); 1705 1706 return ret ? ret : msg_sz; 1707 } 1708 1709 static 1710 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1711 void *buf, size_t size) 1712 { 1713 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1714 unsigned int offset; 1715 1716 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1717 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1718 } 1719 1720 static 1721 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1722 u8 msg_id, void *buf, size_t size) 1723 { 1724 struct intel_display *display = to_intel_display(connector); 1725 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1726 struct intel_hdmi *hdmi = &dig_port->hdmi; 1727 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1728 unsigned int offset; 1729 ssize_t ret; 1730 1731 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1732 hdcp->is_paired); 1733 if (ret < 0) 1734 return ret; 1735 1736 /* 1737 * Available msg size should be equal to or lesser than the 1738 * available buffer. 1739 */ 1740 if (ret > size) { 1741 drm_dbg_kms(display->drm, 1742 "msg_sz(%zd) is more than exp size(%zu)\n", 1743 ret, size); 1744 return -EINVAL; 1745 } 1746 1747 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1748 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1749 if (ret) 1750 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1751 msg_id, ret); 1752 1753 return ret; 1754 } 1755 1756 static 1757 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1758 struct intel_connector *connector) 1759 { 1760 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1761 int ret; 1762 1763 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1764 if (ret) 1765 return ret; 1766 1767 /* 1768 * Re-auth request and Link Integrity Failures are represented by 1769 * same bit. i.e reauth_req. 1770 */ 1771 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1772 ret = HDCP_REAUTH_REQUEST; 1773 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1774 ret = HDCP_TOPOLOGY_CHANGE; 1775 1776 return ret; 1777 } 1778 1779 static 1780 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1781 bool *capable) 1782 { 1783 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1784 u8 hdcp2_version; 1785 int ret; 1786 1787 *capable = false; 1788 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1789 &hdcp2_version, sizeof(hdcp2_version)); 1790 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1791 *capable = true; 1792 1793 return ret; 1794 } 1795 1796 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1797 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1798 .read_bksv = intel_hdmi_hdcp_read_bksv, 1799 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1800 .repeater_present = intel_hdmi_hdcp_repeater_present, 1801 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1802 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1803 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1804 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1805 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1806 .check_link = intel_hdmi_hdcp_check_link, 1807 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1808 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1809 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1810 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1811 .protocol = HDCP_PROTOCOL_HDMI, 1812 }; 1813 1814 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1815 { 1816 struct intel_display *display = to_intel_display(encoder); 1817 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1818 int max_tmds_clock, vbt_max_tmds_clock; 1819 1820 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) 1821 max_tmds_clock = 600000; 1822 else if (DISPLAY_VER(display) >= 10) 1823 max_tmds_clock = 594000; 1824 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) 1825 max_tmds_clock = 300000; 1826 else if (DISPLAY_VER(display) >= 5) 1827 max_tmds_clock = 225000; 1828 else 1829 max_tmds_clock = 165000; 1830 1831 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1832 if (vbt_max_tmds_clock) 1833 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1834 1835 return max_tmds_clock; 1836 } 1837 1838 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1839 const struct drm_connector_state *conn_state) 1840 { 1841 struct intel_connector *connector = hdmi->attached_connector; 1842 1843 return connector->base.display_info.is_hdmi && 1844 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1845 } 1846 1847 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1848 { 1849 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1850 } 1851 1852 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1853 bool respect_downstream_limits, 1854 bool has_hdmi_sink) 1855 { 1856 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1857 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1858 1859 if (respect_downstream_limits) { 1860 struct intel_connector *connector = hdmi->attached_connector; 1861 const struct drm_display_info *info = &connector->base.display_info; 1862 1863 if (hdmi->dp_dual_mode.max_tmds_clock) 1864 max_tmds_clock = min(max_tmds_clock, 1865 hdmi->dp_dual_mode.max_tmds_clock); 1866 1867 if (info->max_tmds_clock) 1868 max_tmds_clock = min(max_tmds_clock, 1869 info->max_tmds_clock); 1870 else if (!has_hdmi_sink) 1871 max_tmds_clock = min(max_tmds_clock, 165000); 1872 } 1873 1874 return max_tmds_clock; 1875 } 1876 1877 static enum drm_mode_status 1878 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1879 int clock, bool respect_downstream_limits, 1880 bool has_hdmi_sink) 1881 { 1882 struct intel_display *display = to_intel_display(hdmi); 1883 struct drm_i915_private *dev_priv = to_i915(display->drm); 1884 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1885 1886 if (clock < 25000) 1887 return MODE_CLOCK_LOW; 1888 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1889 has_hdmi_sink)) 1890 return MODE_CLOCK_HIGH; 1891 1892 /* GLK DPLL can't generate 446-480 MHz */ 1893 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1894 return MODE_CLOCK_RANGE; 1895 1896 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1897 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1898 clock > 223333 && clock < 240000) 1899 return MODE_CLOCK_RANGE; 1900 1901 /* CHV DPLL can't generate 216-240 MHz */ 1902 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1903 return MODE_CLOCK_RANGE; 1904 1905 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1906 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1907 return MODE_CLOCK_RANGE; 1908 1909 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1910 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1911 return MODE_CLOCK_RANGE; 1912 1913 return MODE_OK; 1914 } 1915 1916 int intel_hdmi_tmds_clock(int clock, int bpc, 1917 enum intel_output_format sink_format) 1918 { 1919 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1920 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1921 clock /= 2; 1922 1923 /* 1924 * Need to adjust the port link by: 1925 * 1.5x for 12bpc 1926 * 1.25x for 10bpc 1927 */ 1928 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1929 } 1930 1931 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1932 { 1933 switch (bpc) { 1934 case 12: 1935 return !HAS_GMCH(display); 1936 case 10: 1937 return DISPLAY_VER(display) >= 11; 1938 case 8: 1939 return true; 1940 default: 1941 MISSING_CASE(bpc); 1942 return false; 1943 } 1944 } 1945 1946 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1947 int bpc, bool has_hdmi_sink, 1948 enum intel_output_format sink_format) 1949 { 1950 const struct drm_display_info *info = &connector->display_info; 1951 const struct drm_hdmi_info *hdmi = &info->hdmi; 1952 1953 switch (bpc) { 1954 case 12: 1955 if (!has_hdmi_sink) 1956 return false; 1957 1958 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1959 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1960 else 1961 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1962 case 10: 1963 if (!has_hdmi_sink) 1964 return false; 1965 1966 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1967 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1968 else 1969 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1970 case 8: 1971 return true; 1972 default: 1973 MISSING_CASE(bpc); 1974 return false; 1975 } 1976 } 1977 1978 static enum drm_mode_status 1979 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1980 bool has_hdmi_sink, 1981 enum intel_output_format sink_format) 1982 { 1983 struct intel_display *display = to_intel_display(connector->dev); 1984 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1985 enum drm_mode_status status = MODE_OK; 1986 int bpc; 1987 1988 /* 1989 * Try all color depths since valid port clock range 1990 * can have holes. Any mode that can be used with at 1991 * least one color depth is accepted. 1992 */ 1993 for (bpc = 12; bpc >= 8; bpc -= 2) { 1994 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1995 1996 if (!intel_hdmi_source_bpc_possible(display, bpc)) 1997 continue; 1998 1999 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 2000 continue; 2001 2002 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 2003 if (status == MODE_OK) 2004 return MODE_OK; 2005 } 2006 2007 /* can never happen */ 2008 drm_WARN_ON(display->drm, status == MODE_OK); 2009 2010 return status; 2011 } 2012 2013 static enum drm_mode_status 2014 intel_hdmi_mode_valid(struct drm_connector *connector, 2015 const struct drm_display_mode *mode) 2016 { 2017 struct intel_display *display = to_intel_display(connector->dev); 2018 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2019 enum drm_mode_status status; 2020 int clock = mode->clock; 2021 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 2022 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2023 bool ycbcr_420_only; 2024 enum intel_output_format sink_format; 2025 2026 status = intel_cpu_transcoder_mode_valid(display, mode); 2027 if (status != MODE_OK) 2028 return status; 2029 2030 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2031 clock *= 2; 2032 2033 if (clock > max_dotclk) 2034 return MODE_CLOCK_HIGH; 2035 2036 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2037 if (!has_hdmi_sink) 2038 return MODE_CLOCK_LOW; 2039 clock *= 2; 2040 } 2041 2042 /* 2043 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2044 * enumerated only if FRL is supported. Current platforms do not support 2045 * FRL so prune the higher resolution modes that require doctclock more 2046 * than 600MHz. 2047 */ 2048 if (clock > 600000) 2049 return MODE_CLOCK_HIGH; 2050 2051 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2052 2053 if (ycbcr_420_only) 2054 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2055 else 2056 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2057 2058 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2059 if (status != MODE_OK) { 2060 if (ycbcr_420_only || 2061 !connector->ycbcr_420_allowed || 2062 !drm_mode_is_420_also(&connector->display_info, mode)) 2063 return status; 2064 2065 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2066 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2067 if (status != MODE_OK) 2068 return status; 2069 } 2070 2071 return intel_mode_valid_max_plane_size(display, mode, 1); 2072 } 2073 2074 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2075 int bpc, bool has_hdmi_sink) 2076 { 2077 struct drm_atomic_state *state = crtc_state->uapi.state; 2078 struct drm_connector_state *connector_state; 2079 struct drm_connector *connector; 2080 int i; 2081 2082 for_each_new_connector_in_state(state, connector, connector_state, i) { 2083 if (connector_state->crtc != crtc_state->uapi.crtc) 2084 continue; 2085 2086 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2087 crtc_state->sink_format)) 2088 return false; 2089 } 2090 2091 return true; 2092 } 2093 2094 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2095 { 2096 struct intel_display *display = to_intel_display(crtc_state); 2097 const struct drm_display_mode *adjusted_mode = 2098 &crtc_state->hw.adjusted_mode; 2099 2100 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2101 return false; 2102 2103 /* Display Wa_1405510057:icl,ehl */ 2104 if (intel_hdmi_is_ycbcr420(crtc_state) && 2105 bpc == 10 && DISPLAY_VER(display) == 11 && 2106 (adjusted_mode->crtc_hblank_end - 2107 adjusted_mode->crtc_hblank_start) % 8 == 2) 2108 return false; 2109 2110 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2111 } 2112 2113 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2114 struct intel_crtc_state *crtc_state, 2115 int clock, bool respect_downstream_limits) 2116 { 2117 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2118 int bpc; 2119 2120 /* 2121 * pipe_bpp could already be below 8bpc due to FDI 2122 * bandwidth constraints. HDMI minimum is 8bpc however. 2123 */ 2124 bpc = max(crtc_state->pipe_bpp / 3, 8); 2125 2126 /* 2127 * We will never exceed downstream TMDS clock limits while 2128 * attempting deep color. If the user insists on forcing an 2129 * out of spec mode they will have to be satisfied with 8bpc. 2130 */ 2131 if (!respect_downstream_limits) 2132 bpc = 8; 2133 2134 for (; bpc >= 8; bpc -= 2) { 2135 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2136 crtc_state->sink_format); 2137 2138 if (hdmi_bpc_possible(crtc_state, bpc) && 2139 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2140 respect_downstream_limits, 2141 crtc_state->has_hdmi_sink) == MODE_OK) 2142 return bpc; 2143 } 2144 2145 return -EINVAL; 2146 } 2147 2148 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2149 struct intel_crtc_state *crtc_state, 2150 bool respect_downstream_limits) 2151 { 2152 struct intel_display *display = to_intel_display(encoder); 2153 const struct drm_display_mode *adjusted_mode = 2154 &crtc_state->hw.adjusted_mode; 2155 int bpc, clock = adjusted_mode->crtc_clock; 2156 2157 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2158 clock *= 2; 2159 2160 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2161 respect_downstream_limits); 2162 if (bpc < 0) 2163 return bpc; 2164 2165 crtc_state->port_clock = 2166 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2167 2168 /* 2169 * pipe_bpp could already be below 8bpc due to 2170 * FDI bandwidth constraints. We shouldn't bump it 2171 * back up to the HDMI minimum 8bpc in that case. 2172 */ 2173 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2174 2175 drm_dbg_kms(display->drm, 2176 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2177 bpc, crtc_state->pipe_bpp); 2178 2179 return 0; 2180 } 2181 2182 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2183 const struct drm_connector_state *conn_state) 2184 { 2185 const struct intel_digital_connector_state *intel_conn_state = 2186 to_intel_digital_connector_state(conn_state); 2187 const struct drm_display_mode *adjusted_mode = 2188 &crtc_state->hw.adjusted_mode; 2189 2190 /* 2191 * Our YCbCr output is always limited range. 2192 * crtc_state->limited_color_range only applies to RGB, 2193 * and it must never be set for YCbCr or we risk setting 2194 * some conflicting bits in TRANSCONF which will mess up 2195 * the colors on the monitor. 2196 */ 2197 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2198 return false; 2199 2200 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2201 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2202 return crtc_state->has_hdmi_sink && 2203 drm_default_rgb_quant_range(adjusted_mode) == 2204 HDMI_QUANTIZATION_RANGE_LIMITED; 2205 } else { 2206 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2207 } 2208 } 2209 2210 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2211 const struct intel_crtc_state *crtc_state, 2212 const struct drm_connector_state *conn_state) 2213 { 2214 struct drm_connector *connector = conn_state->connector; 2215 const struct intel_digital_connector_state *intel_conn_state = 2216 to_intel_digital_connector_state(conn_state); 2217 2218 if (!crtc_state->has_hdmi_sink) 2219 return false; 2220 2221 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2222 return connector->display_info.has_audio; 2223 else 2224 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2225 } 2226 2227 static enum intel_output_format 2228 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2229 struct intel_connector *connector, 2230 bool ycbcr_420_output) 2231 { 2232 if (!crtc_state->has_hdmi_sink) 2233 return INTEL_OUTPUT_FORMAT_RGB; 2234 2235 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2236 return INTEL_OUTPUT_FORMAT_YCBCR420; 2237 else 2238 return INTEL_OUTPUT_FORMAT_RGB; 2239 } 2240 2241 static enum intel_output_format 2242 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2243 { 2244 return crtc_state->sink_format; 2245 } 2246 2247 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2248 struct intel_crtc_state *crtc_state, 2249 const struct drm_connector_state *conn_state, 2250 bool respect_downstream_limits) 2251 { 2252 struct intel_display *display = to_intel_display(encoder); 2253 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2254 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2255 const struct drm_display_info *info = &connector->base.display_info; 2256 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2257 int ret; 2258 2259 crtc_state->sink_format = 2260 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2261 2262 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2263 drm_dbg_kms(display->drm, 2264 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2265 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2266 } 2267 2268 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2269 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2270 if (ret) { 2271 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2272 !crtc_state->has_hdmi_sink || 2273 !connector->base.ycbcr_420_allowed || 2274 !drm_mode_is_420_also(info, adjusted_mode)) 2275 return ret; 2276 2277 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2278 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2279 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2280 } 2281 2282 return ret; 2283 } 2284 2285 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2286 { 2287 return crtc_state->uapi.encoder_mask && 2288 !is_power_of_2(crtc_state->uapi.encoder_mask); 2289 } 2290 2291 static bool source_supports_scrambling(struct intel_encoder *encoder) 2292 { 2293 /* 2294 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2295 * scrambling is supported. 2296 * But there seem to be cases where certain platforms that support 2297 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2298 * capped by VBT to less than 340MHz. 2299 * 2300 * In such cases when an HDMI2.0 sink is connected, it creates a 2301 * problem : the platform and the sink both support scrambling but the 2302 * HDMI 1.4 retimer chip doesn't. 2303 * 2304 * So go for scrambling, based on the max tmds clock taking into account, 2305 * restrictions coming from VBT. 2306 */ 2307 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2308 } 2309 2310 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2311 const struct intel_crtc_state *crtc_state, 2312 const struct drm_connector_state *conn_state) 2313 { 2314 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2315 2316 return intel_has_hdmi_sink(hdmi, conn_state) && 2317 !intel_hdmi_is_cloned(crtc_state); 2318 } 2319 2320 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2321 struct intel_crtc_state *pipe_config, 2322 struct drm_connector_state *conn_state) 2323 { 2324 struct intel_display *display = to_intel_display(encoder); 2325 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2326 struct drm_connector *connector = conn_state->connector; 2327 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2328 int ret; 2329 2330 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2331 return -EINVAL; 2332 2333 if (!connector->interlace_allowed && 2334 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2335 return -EINVAL; 2336 2337 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2338 2339 if (pipe_config->has_hdmi_sink) 2340 pipe_config->has_infoframe = true; 2341 2342 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2343 pipe_config->pixel_multiplier = 2; 2344 2345 pipe_config->has_audio = 2346 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2347 intel_audio_compute_config(encoder, pipe_config, conn_state); 2348 2349 /* 2350 * Try to respect downstream TMDS clock limits first, if 2351 * that fails assume the user might know something we don't. 2352 */ 2353 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2354 if (ret) 2355 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2356 if (ret) { 2357 drm_dbg_kms(display->drm, 2358 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2359 pipe_config->hw.adjusted_mode.crtc_clock); 2360 return ret; 2361 } 2362 2363 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2364 ret = intel_pfit_compute_config(pipe_config, conn_state); 2365 if (ret) 2366 return ret; 2367 } 2368 2369 pipe_config->limited_color_range = 2370 intel_hdmi_limited_color_range(pipe_config, conn_state); 2371 2372 if (conn_state->picture_aspect_ratio) 2373 adjusted_mode->picture_aspect_ratio = 2374 conn_state->picture_aspect_ratio; 2375 2376 pipe_config->lane_count = 4; 2377 2378 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2379 if (scdc->scrambling.low_rates) 2380 pipe_config->hdmi_scrambling = true; 2381 2382 if (pipe_config->port_clock > 340000) { 2383 pipe_config->hdmi_scrambling = true; 2384 pipe_config->hdmi_high_tmds_clock_ratio = true; 2385 } 2386 } 2387 2388 intel_vrr_compute_config(pipe_config, conn_state); 2389 2390 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2391 conn_state); 2392 2393 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2394 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2395 return -EINVAL; 2396 } 2397 2398 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2399 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2400 return -EINVAL; 2401 } 2402 2403 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2404 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2405 return -EINVAL; 2406 } 2407 2408 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2409 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2410 return -EINVAL; 2411 } 2412 2413 return 0; 2414 } 2415 2416 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2417 { 2418 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2419 2420 /* 2421 * Give a hand to buggy BIOSen which forget to turn 2422 * the TMDS output buffers back on after a reboot. 2423 */ 2424 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2425 } 2426 2427 static void 2428 intel_hdmi_unset_edid(struct drm_connector *connector) 2429 { 2430 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2431 2432 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2433 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2434 2435 drm_edid_free(to_intel_connector(connector)->detect_edid); 2436 to_intel_connector(connector)->detect_edid = NULL; 2437 } 2438 2439 static void 2440 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2441 { 2442 struct intel_display *display = to_intel_display(connector->dev); 2443 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2444 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2445 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2446 struct i2c_adapter *ddc = connector->ddc; 2447 enum drm_dp_dual_mode_type type; 2448 2449 type = drm_dp_dual_mode_detect(display->drm, ddc); 2450 2451 /* 2452 * Type 1 DVI adaptors are not required to implement any 2453 * registers, so we can't always detect their presence. 2454 * Ideally we should be able to check the state of the 2455 * CONFIG1 pin, but no such luck on our hardware. 2456 * 2457 * The only method left to us is to check the VBT to see 2458 * if the port is a dual mode capable DP port. 2459 */ 2460 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2461 if (!connector->force && 2462 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2463 drm_dbg_kms(display->drm, 2464 "Assuming DP dual mode adaptor presence based on VBT\n"); 2465 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2466 } else { 2467 type = DRM_DP_DUAL_MODE_NONE; 2468 } 2469 } 2470 2471 if (type == DRM_DP_DUAL_MODE_NONE) 2472 return; 2473 2474 hdmi->dp_dual_mode.type = type; 2475 hdmi->dp_dual_mode.max_tmds_clock = 2476 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2477 2478 drm_dbg_kms(display->drm, 2479 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2480 drm_dp_get_dual_mode_type_name(type), 2481 hdmi->dp_dual_mode.max_tmds_clock); 2482 2483 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2484 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && 2485 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2486 drm_dbg_kms(display->drm, 2487 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2488 hdmi->dp_dual_mode.max_tmds_clock = 0; 2489 } 2490 } 2491 2492 static bool 2493 intel_hdmi_set_edid(struct drm_connector *connector) 2494 { 2495 struct intel_display *display = to_intel_display(connector->dev); 2496 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2497 struct i2c_adapter *ddc = connector->ddc; 2498 intel_wakeref_t wakeref; 2499 const struct drm_edid *drm_edid; 2500 bool connected = false; 2501 2502 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2503 2504 drm_edid = drm_edid_read_ddc(connector, ddc); 2505 2506 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2507 drm_dbg_kms(display->drm, 2508 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2509 intel_gmbus_force_bit(ddc, true); 2510 drm_edid = drm_edid_read_ddc(connector, ddc); 2511 intel_gmbus_force_bit(ddc, false); 2512 } 2513 2514 /* Below we depend on display info having been updated */ 2515 drm_edid_connector_update(connector, drm_edid); 2516 2517 to_intel_connector(connector)->detect_edid = drm_edid; 2518 2519 if (drm_edid_is_digital(drm_edid)) { 2520 intel_hdmi_dp_dual_mode_detect(connector); 2521 2522 connected = true; 2523 } 2524 2525 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2526 2527 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2528 connector->display_info.source_physical_address); 2529 2530 return connected; 2531 } 2532 2533 static enum drm_connector_status 2534 intel_hdmi_detect(struct drm_connector *connector, bool force) 2535 { 2536 struct intel_display *display = to_intel_display(connector->dev); 2537 enum drm_connector_status status = connector_status_disconnected; 2538 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2539 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2540 intel_wakeref_t wakeref; 2541 2542 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2543 connector->base.id, connector->name); 2544 2545 if (!intel_display_device_enabled(display)) 2546 return connector_status_disconnected; 2547 2548 if (!intel_display_driver_check_access(display)) 2549 return connector->status; 2550 2551 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2552 2553 if (DISPLAY_VER(display) >= 11 && 2554 !intel_digital_port_connected(encoder)) 2555 goto out; 2556 2557 intel_hdmi_unset_edid(connector); 2558 2559 if (intel_hdmi_set_edid(connector)) 2560 status = connector_status_connected; 2561 2562 out: 2563 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2564 2565 if (status != connector_status_connected) 2566 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2567 2568 return status; 2569 } 2570 2571 static void 2572 intel_hdmi_force(struct drm_connector *connector) 2573 { 2574 struct intel_display *display = to_intel_display(connector->dev); 2575 2576 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2577 connector->base.id, connector->name); 2578 2579 if (!intel_display_driver_check_access(display)) 2580 return; 2581 2582 intel_hdmi_unset_edid(connector); 2583 2584 if (connector->status != connector_status_connected) 2585 return; 2586 2587 intel_hdmi_set_edid(connector); 2588 } 2589 2590 static int intel_hdmi_get_modes(struct drm_connector *connector) 2591 { 2592 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2593 return drm_edid_connector_add_modes(connector); 2594 } 2595 2596 static int 2597 intel_hdmi_connector_register(struct drm_connector *connector) 2598 { 2599 int ret; 2600 2601 ret = intel_connector_register(connector); 2602 if (ret) 2603 return ret; 2604 2605 return ret; 2606 } 2607 2608 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2609 { 2610 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2611 2612 cec_notifier_conn_unregister(n); 2613 2614 intel_connector_unregister(connector); 2615 } 2616 2617 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2618 .detect = intel_hdmi_detect, 2619 .force = intel_hdmi_force, 2620 .fill_modes = drm_helper_probe_single_connector_modes, 2621 .atomic_get_property = intel_digital_connector_atomic_get_property, 2622 .atomic_set_property = intel_digital_connector_atomic_set_property, 2623 .late_register = intel_hdmi_connector_register, 2624 .early_unregister = intel_hdmi_connector_unregister, 2625 .destroy = intel_connector_destroy, 2626 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2627 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2628 }; 2629 2630 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2631 struct drm_atomic_state *state) 2632 { 2633 struct intel_display *display = to_intel_display(connector->dev); 2634 2635 if (HAS_DDI(display)) 2636 return intel_digital_connector_atomic_check(connector, state); 2637 else 2638 return g4x_hdmi_connector_atomic_check(connector, state); 2639 } 2640 2641 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2642 .get_modes = intel_hdmi_get_modes, 2643 .mode_valid = intel_hdmi_mode_valid, 2644 .atomic_check = intel_hdmi_connector_atomic_check, 2645 }; 2646 2647 static void 2648 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2649 { 2650 struct intel_display *display = to_intel_display(intel_hdmi); 2651 2652 intel_attach_force_audio_property(connector); 2653 intel_attach_broadcast_rgb_property(connector); 2654 intel_attach_aspect_ratio_property(connector); 2655 2656 intel_attach_hdmi_colorspace_property(connector); 2657 drm_connector_attach_content_type_property(connector); 2658 2659 if (DISPLAY_VER(display) >= 10) 2660 drm_connector_attach_hdr_output_metadata_property(connector); 2661 2662 if (!HAS_GMCH(display)) 2663 drm_connector_attach_max_bpc_property(connector, 8, 12); 2664 } 2665 2666 /* 2667 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2668 * @encoder: intel_encoder 2669 * @connector: drm_connector 2670 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2671 * or reset the high tmds clock ratio for scrambling 2672 * @scrambling: bool to Indicate if the function needs to set or reset 2673 * sink scrambling 2674 * 2675 * This function handles scrambling on HDMI 2.0 capable sinks. 2676 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2677 * it enables scrambling. This should be called before enabling the HDMI 2678 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2679 * detect a scrambled clock within 100 ms. 2680 * 2681 * Returns: 2682 * True on success, false on failure. 2683 */ 2684 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2685 struct drm_connector *connector, 2686 bool high_tmds_clock_ratio, 2687 bool scrambling) 2688 { 2689 struct intel_display *display = to_intel_display(encoder); 2690 struct drm_scrambling *sink_scrambling = 2691 &connector->display_info.hdmi.scdc.scrambling; 2692 2693 if (!sink_scrambling->supported) 2694 return true; 2695 2696 drm_dbg_kms(display->drm, 2697 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2698 connector->base.id, connector->name, 2699 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2700 2701 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2702 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2703 drm_scdc_set_scrambling(connector, scrambling); 2704 } 2705 2706 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2707 { 2708 enum port port = encoder->port; 2709 u8 ddc_pin; 2710 2711 switch (port) { 2712 case PORT_B: 2713 ddc_pin = GMBUS_PIN_DPB; 2714 break; 2715 case PORT_C: 2716 ddc_pin = GMBUS_PIN_DPC; 2717 break; 2718 case PORT_D: 2719 ddc_pin = GMBUS_PIN_DPD_CHV; 2720 break; 2721 default: 2722 MISSING_CASE(port); 2723 ddc_pin = GMBUS_PIN_DPB; 2724 break; 2725 } 2726 return ddc_pin; 2727 } 2728 2729 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2730 { 2731 enum port port = encoder->port; 2732 u8 ddc_pin; 2733 2734 switch (port) { 2735 case PORT_B: 2736 ddc_pin = GMBUS_PIN_1_BXT; 2737 break; 2738 case PORT_C: 2739 ddc_pin = GMBUS_PIN_2_BXT; 2740 break; 2741 default: 2742 MISSING_CASE(port); 2743 ddc_pin = GMBUS_PIN_1_BXT; 2744 break; 2745 } 2746 return ddc_pin; 2747 } 2748 2749 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2750 { 2751 enum port port = encoder->port; 2752 u8 ddc_pin; 2753 2754 switch (port) { 2755 case PORT_B: 2756 ddc_pin = GMBUS_PIN_1_BXT; 2757 break; 2758 case PORT_C: 2759 ddc_pin = GMBUS_PIN_2_BXT; 2760 break; 2761 case PORT_D: 2762 ddc_pin = GMBUS_PIN_4_CNP; 2763 break; 2764 case PORT_F: 2765 ddc_pin = GMBUS_PIN_3_BXT; 2766 break; 2767 default: 2768 MISSING_CASE(port); 2769 ddc_pin = GMBUS_PIN_1_BXT; 2770 break; 2771 } 2772 return ddc_pin; 2773 } 2774 2775 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2776 { 2777 struct intel_display *display = to_intel_display(encoder); 2778 enum port port = encoder->port; 2779 2780 if (intel_encoder_is_combo(encoder)) 2781 return GMBUS_PIN_1_BXT + port; 2782 else if (intel_encoder_is_tc(encoder)) 2783 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2784 2785 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2786 return GMBUS_PIN_2_BXT; 2787 } 2788 2789 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2790 { 2791 enum phy phy = intel_encoder_to_phy(encoder); 2792 u8 ddc_pin; 2793 2794 switch (phy) { 2795 case PHY_A: 2796 ddc_pin = GMBUS_PIN_1_BXT; 2797 break; 2798 case PHY_B: 2799 ddc_pin = GMBUS_PIN_2_BXT; 2800 break; 2801 case PHY_C: 2802 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2803 break; 2804 default: 2805 MISSING_CASE(phy); 2806 ddc_pin = GMBUS_PIN_1_BXT; 2807 break; 2808 } 2809 return ddc_pin; 2810 } 2811 2812 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2813 { 2814 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2815 enum phy phy = intel_encoder_to_phy(encoder); 2816 2817 WARN_ON(encoder->port == PORT_C); 2818 2819 /* 2820 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2821 * final two outputs use type-c pins, even though they're actually 2822 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2823 * all outputs. 2824 */ 2825 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2826 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2827 2828 return GMBUS_PIN_1_BXT + phy; 2829 } 2830 2831 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2832 { 2833 struct intel_display *display = to_intel_display(encoder); 2834 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2835 enum phy phy = intel_encoder_to_phy(encoder); 2836 2837 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2838 2839 /* 2840 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2841 * final two outputs use type-c pins, even though they're actually 2842 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2843 * all outputs. 2844 */ 2845 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2846 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2847 2848 return GMBUS_PIN_1_BXT + phy; 2849 } 2850 2851 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2852 { 2853 return intel_encoder_to_phy(encoder) + 1; 2854 } 2855 2856 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2857 { 2858 enum phy phy = intel_encoder_to_phy(encoder); 2859 2860 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2861 2862 /* 2863 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2864 * except first combo output. 2865 */ 2866 if (phy == PHY_A) 2867 return GMBUS_PIN_1_BXT; 2868 2869 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2870 } 2871 2872 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2873 { 2874 enum port port = encoder->port; 2875 u8 ddc_pin; 2876 2877 switch (port) { 2878 case PORT_B: 2879 ddc_pin = GMBUS_PIN_DPB; 2880 break; 2881 case PORT_C: 2882 ddc_pin = GMBUS_PIN_DPC; 2883 break; 2884 case PORT_D: 2885 ddc_pin = GMBUS_PIN_DPD; 2886 break; 2887 default: 2888 MISSING_CASE(port); 2889 ddc_pin = GMBUS_PIN_DPB; 2890 break; 2891 } 2892 return ddc_pin; 2893 } 2894 2895 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2896 { 2897 struct intel_display *display = to_intel_display(encoder); 2898 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2899 u8 ddc_pin; 2900 2901 if (IS_ALDERLAKE_S(dev_priv)) 2902 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2903 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2904 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2905 else if (IS_ROCKETLAKE(dev_priv)) 2906 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2907 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) 2908 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2909 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2910 HAS_PCH_TGP(dev_priv)) 2911 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2912 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2913 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2914 else if (HAS_PCH_CNP(dev_priv)) 2915 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2916 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2917 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2918 else if (IS_CHERRYVIEW(dev_priv)) 2919 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2920 else 2921 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2922 2923 return ddc_pin; 2924 } 2925 2926 static struct intel_encoder * 2927 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2928 { 2929 struct intel_display *display = to_intel_display(encoder); 2930 struct intel_encoder *other; 2931 2932 for_each_intel_encoder(display->drm, other) { 2933 struct intel_connector *connector; 2934 2935 if (other == encoder) 2936 continue; 2937 2938 if (!intel_encoder_is_dig_port(other)) 2939 continue; 2940 2941 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2942 2943 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) 2944 return other; 2945 } 2946 2947 return NULL; 2948 } 2949 2950 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2951 { 2952 struct intel_display *display = to_intel_display(encoder); 2953 struct intel_encoder *other; 2954 const char *source; 2955 u8 ddc_pin; 2956 2957 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2958 source = "VBT"; 2959 2960 if (!ddc_pin) { 2961 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2962 source = "platform default"; 2963 } 2964 2965 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { 2966 drm_dbg_kms(display->drm, 2967 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2968 encoder->base.base.id, encoder->base.name, ddc_pin); 2969 return 0; 2970 } 2971 2972 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2973 if (other) { 2974 drm_dbg_kms(display->drm, 2975 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2976 encoder->base.base.id, encoder->base.name, ddc_pin, 2977 other->base.base.id, other->base.name); 2978 return 0; 2979 } 2980 2981 drm_dbg_kms(display->drm, 2982 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2983 encoder->base.base.id, encoder->base.name, 2984 ddc_pin, source); 2985 2986 return ddc_pin; 2987 } 2988 2989 void intel_infoframe_init(struct intel_digital_port *dig_port) 2990 { 2991 struct intel_display *display = to_intel_display(dig_port); 2992 struct drm_i915_private *dev_priv = 2993 to_i915(dig_port->base.base.dev); 2994 2995 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2996 dig_port->write_infoframe = vlv_write_infoframe; 2997 dig_port->read_infoframe = vlv_read_infoframe; 2998 dig_port->set_infoframes = vlv_set_infoframes; 2999 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3000 } else if (IS_G4X(dev_priv)) { 3001 dig_port->write_infoframe = g4x_write_infoframe; 3002 dig_port->read_infoframe = g4x_read_infoframe; 3003 dig_port->set_infoframes = g4x_set_infoframes; 3004 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3005 } else if (HAS_DDI(display)) { 3006 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 3007 dig_port->write_infoframe = lspcon_write_infoframe; 3008 dig_port->read_infoframe = lspcon_read_infoframe; 3009 dig_port->set_infoframes = lspcon_set_infoframes; 3010 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3011 } else { 3012 dig_port->write_infoframe = hsw_write_infoframe; 3013 dig_port->read_infoframe = hsw_read_infoframe; 3014 dig_port->set_infoframes = hsw_set_infoframes; 3015 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3016 } 3017 } else if (HAS_PCH_IBX(dev_priv)) { 3018 dig_port->write_infoframe = ibx_write_infoframe; 3019 dig_port->read_infoframe = ibx_read_infoframe; 3020 dig_port->set_infoframes = ibx_set_infoframes; 3021 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3022 } else { 3023 dig_port->write_infoframe = cpt_write_infoframe; 3024 dig_port->read_infoframe = cpt_read_infoframe; 3025 dig_port->set_infoframes = cpt_set_infoframes; 3026 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3027 } 3028 } 3029 3030 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3031 struct intel_connector *intel_connector) 3032 { 3033 struct intel_display *display = to_intel_display(dig_port); 3034 struct drm_connector *connector = &intel_connector->base; 3035 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3036 struct intel_encoder *intel_encoder = &dig_port->base; 3037 struct drm_device *dev = intel_encoder->base.dev; 3038 enum port port = intel_encoder->port; 3039 struct cec_connector_info conn_info; 3040 u8 ddc_pin; 3041 3042 drm_dbg_kms(display->drm, 3043 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3044 intel_encoder->base.base.id, intel_encoder->base.name); 3045 3046 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3047 return false; 3048 3049 if (drm_WARN(dev, dig_port->max_lanes < 4, 3050 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3051 dig_port->max_lanes, intel_encoder->base.base.id, 3052 intel_encoder->base.name)) 3053 return false; 3054 3055 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3056 if (!ddc_pin) 3057 return false; 3058 3059 drm_connector_init_with_ddc(dev, connector, 3060 &intel_hdmi_connector_funcs, 3061 DRM_MODE_CONNECTOR_HDMIA, 3062 intel_gmbus_get_adapter(display, ddc_pin)); 3063 3064 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3065 3066 if (DISPLAY_VER(display) < 12) 3067 connector->interlace_allowed = true; 3068 3069 connector->stereo_allowed = true; 3070 3071 if (DISPLAY_VER(display) >= 10) 3072 connector->ycbcr_420_allowed = true; 3073 3074 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3075 intel_connector->base.polled = intel_connector->polled; 3076 3077 if (HAS_DDI(display)) 3078 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3079 else 3080 intel_connector->get_hw_state = intel_connector_get_hw_state; 3081 3082 intel_hdmi_add_properties(intel_hdmi, connector); 3083 3084 intel_connector_attach_encoder(intel_connector, intel_encoder); 3085 intel_hdmi->attached_connector = intel_connector; 3086 3087 if (is_hdcp_supported(display, port)) { 3088 int ret = intel_hdcp_init(intel_connector, dig_port, 3089 &intel_hdmi_hdcp_shim); 3090 if (ret) 3091 drm_dbg_kms(display->drm, 3092 "HDCP init failed, skipping.\n"); 3093 } 3094 3095 cec_fill_conn_info_from_drm(&conn_info, connector); 3096 3097 intel_hdmi->cec_notifier = 3098 cec_notifier_conn_register(dev->dev, port_identifier(port), 3099 &conn_info); 3100 if (!intel_hdmi->cec_notifier) 3101 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3102 3103 return true; 3104 } 3105 3106 /* 3107 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3108 * @vactive: Vactive of a display mode 3109 * 3110 * @return: appropriate dsc slice height for a given mode. 3111 */ 3112 int intel_hdmi_dsc_get_slice_height(int vactive) 3113 { 3114 int slice_height; 3115 3116 /* 3117 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3118 * Select smallest slice height >=96, that results in a valid PPS and 3119 * requires minimum padding lines required for final slice. 3120 * 3121 * Assumption : Vactive is even. 3122 */ 3123 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3124 if (vactive % slice_height == 0) 3125 return slice_height; 3126 3127 return 0; 3128 } 3129 3130 /* 3131 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3132 * and dsc decoder capabilities 3133 * 3134 * @crtc_state: intel crtc_state 3135 * @src_max_slices: maximum slices supported by the DSC encoder 3136 * @src_max_slice_width: maximum slice width supported by DSC encoder 3137 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3138 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3139 * 3140 * @return: num of dsc slices that can be supported by the dsc encoder 3141 * and decoder. 3142 */ 3143 int 3144 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3145 int src_max_slices, int src_max_slice_width, 3146 int hdmi_max_slices, int hdmi_throughput) 3147 { 3148 /* Pixel rates in KPixels/sec */ 3149 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3150 /* 3151 * Rates at which the source and sink are required to process pixels in each 3152 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3153 */ 3154 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3155 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3156 3157 /* Spec limits the slice width to 2720 pixels */ 3158 #define MAX_HDMI_SLICE_WIDTH 2720 3159 int kslice_adjust; 3160 int adjusted_clk_khz; 3161 int min_slices; 3162 int target_slices; 3163 int max_throughput; /* max clock freq. in khz per slice */ 3164 int max_slice_width; 3165 int slice_width; 3166 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3167 3168 if (!hdmi_throughput) 3169 return 0; 3170 3171 /* 3172 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3173 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3174 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3175 * dividing adjusted clock value by 10. 3176 */ 3177 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3178 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3179 kslice_adjust = 10; 3180 else 3181 kslice_adjust = 5; 3182 3183 /* 3184 * As per spec, the rate at which the source and the sink process 3185 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3186 * This depends upon the pixel clock rate and output formats 3187 * (kslice adjust). 3188 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3189 * at max 340MHz, otherwise they can be processed at max 400MHz. 3190 */ 3191 3192 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3193 3194 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3195 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3196 else 3197 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3198 3199 /* 3200 * Taking into account the sink's capability for maximum 3201 * clock per slice (in MHz) as read from HF-VSDB. 3202 */ 3203 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3204 3205 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3206 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3207 3208 /* 3209 * Keep on increasing the num of slices/line, starting from min_slices 3210 * per line till we get such a number, for which the slice_width is 3211 * just less than max_slice_width. The slices/line selected should be 3212 * less than or equal to the max horizontal slices that the combination 3213 * of PCON encoder and HDMI decoder can support. 3214 */ 3215 slice_width = max_slice_width; 3216 3217 do { 3218 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3219 target_slices = 1; 3220 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3221 target_slices = 2; 3222 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3223 target_slices = 4; 3224 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3225 target_slices = 8; 3226 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3227 target_slices = 12; 3228 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3229 target_slices = 16; 3230 else 3231 return 0; 3232 3233 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3234 if (slice_width >= max_slice_width) 3235 min_slices = target_slices + 1; 3236 } while (slice_width >= max_slice_width); 3237 3238 return target_slices; 3239 } 3240 3241 /* 3242 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3243 * source and sink capabilities. 3244 * 3245 * @src_fraction_bpp: fractional bpp supported by the source 3246 * @slice_width: dsc slice width supported by the source and sink 3247 * @num_slices: num of slices supported by the source and sink 3248 * @output_format: video output format 3249 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3250 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3251 * 3252 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3253 */ 3254 int 3255 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3256 int output_format, bool hdmi_all_bpp, 3257 int hdmi_max_chunk_bytes) 3258 { 3259 int max_dsc_bpp, min_dsc_bpp; 3260 int target_bytes; 3261 bool bpp_found = false; 3262 int bpp_decrement_x16; 3263 int bpp_target; 3264 int bpp_target_x16; 3265 3266 /* 3267 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3268 * Start with the max bpp and keep on decrementing with 3269 * fractional bpp, if supported by PCON DSC encoder 3270 * 3271 * for each bpp we check if no of bytes can be supported by HDMI sink 3272 */ 3273 3274 /* Assuming: bpc as 8*/ 3275 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3276 min_dsc_bpp = 6; 3277 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3278 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3279 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3280 min_dsc_bpp = 8; 3281 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3282 } else { 3283 /* Assuming 4:2:2 encoding */ 3284 min_dsc_bpp = 7; 3285 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3286 } 3287 3288 /* 3289 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3290 * Section 7.7.34 : Source shall not enable compressed Video 3291 * Transport with bpp_target settings above 12 bpp unless 3292 * DSC_all_bpp is set to 1. 3293 */ 3294 if (!hdmi_all_bpp) 3295 max_dsc_bpp = min(max_dsc_bpp, 12); 3296 3297 /* 3298 * The Sink has a limit of compressed data in bytes for a scanline, 3299 * as described in max_chunk_bytes field in HFVSDB block of edid. 3300 * The no. of bytes depend on the target bits per pixel that the 3301 * source configures. So we start with the max_bpp and calculate 3302 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3303 * till we get the target_chunk_bytes just less than what the sink's 3304 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3305 * 3306 * The decrement is according to the fractional support from PCON DSC 3307 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3308 * 3309 * bpp_target_x16 = bpp_target * 16 3310 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3311 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3312 */ 3313 3314 bpp_target = max_dsc_bpp; 3315 3316 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3317 if (!src_fractional_bpp) 3318 src_fractional_bpp = 1; 3319 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3320 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3321 3322 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3323 int bpp; 3324 3325 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3326 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3327 if (target_bytes <= hdmi_max_chunk_bytes) { 3328 bpp_found = true; 3329 break; 3330 } 3331 bpp_target_x16 -= bpp_decrement_x16; 3332 } 3333 if (bpp_found) 3334 return bpp_target_x16; 3335 3336 return 0; 3337 } 3338