1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/iopoll.h> 33 #include <linux/slab.h> 34 #include <linux/string_helpers.h> 35 36 #include <drm/display/drm_hdcp_helper.h> 37 #include <drm/display/drm_hdmi_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_crtc.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/intel/intel_lpe_audio.h> 45 #include <media/cec-notifier.h> 46 47 #include "g4x_hdmi.h" 48 #include "intel_atomic.h" 49 #include "intel_audio.h" 50 #include "intel_connector.h" 51 #include "intel_cx0_phy.h" 52 #include "intel_ddi.h" 53 #include "intel_de.h" 54 #include "intel_display_driver.h" 55 #include "intel_display_regs.h" 56 #include "intel_display_types.h" 57 #include "intel_display_utils.h" 58 #include "intel_dp.h" 59 #include "intel_gmbus.h" 60 #include "intel_hdcp.h" 61 #include "intel_hdcp_regs.h" 62 #include "intel_hdcp_shim.h" 63 #include "intel_hdmi.h" 64 #include "intel_link_bw.h" 65 #include "intel_lspcon.h" 66 #include "intel_panel.h" 67 #include "intel_pfit.h" 68 #include "intel_snps_phy.h" 69 #include "intel_vrr.h" 70 71 bool intel_hdmi_is_frl(u32 clock) 72 { 73 switch (clock) { 74 case 300000: /* 3 Gbps */ 75 case 600000: /* 6 Gbps */ 76 case 800000: /* 8 Gbps */ 77 case 1000000: /* 10 Gbps */ 78 case 1200000: /* 12 Gbps */ 79 return true; 80 default: 81 return false; 82 } 83 } 84 85 static void 86 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 87 { 88 struct intel_display *display = to_intel_display(intel_hdmi); 89 u32 enabled_bits; 90 91 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 92 93 drm_WARN(display->drm, 94 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 95 "HDMI port enabled, expecting disabled\n"); 96 } 97 98 static void 99 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 100 enum transcoder cpu_transcoder) 101 { 102 drm_WARN(display->drm, 103 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 104 TRANS_DDI_FUNC_ENABLE, 105 "HDMI transcoder function enabled, expecting disabled\n"); 106 } 107 108 static u32 g4x_infoframe_index(unsigned int type) 109 { 110 switch (type) { 111 case HDMI_PACKET_TYPE_GAMUT_METADATA: 112 return VIDEO_DIP_SELECT_GAMUT; 113 case HDMI_INFOFRAME_TYPE_AVI: 114 return VIDEO_DIP_SELECT_AVI; 115 case HDMI_INFOFRAME_TYPE_SPD: 116 return VIDEO_DIP_SELECT_SPD; 117 case HDMI_INFOFRAME_TYPE_VENDOR: 118 return VIDEO_DIP_SELECT_VENDOR; 119 default: 120 MISSING_CASE(type); 121 return 0; 122 } 123 } 124 125 static u32 g4x_infoframe_enable(unsigned int type) 126 { 127 switch (type) { 128 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 129 return VIDEO_DIP_ENABLE_GCP; 130 case HDMI_PACKET_TYPE_GAMUT_METADATA: 131 return VIDEO_DIP_ENABLE_GAMUT; 132 case DP_SDP_VSC: 133 return 0; 134 case DP_SDP_ADAPTIVE_SYNC: 135 return 0; 136 case HDMI_INFOFRAME_TYPE_AVI: 137 return VIDEO_DIP_ENABLE_AVI; 138 case HDMI_INFOFRAME_TYPE_SPD: 139 return VIDEO_DIP_ENABLE_SPD; 140 case HDMI_INFOFRAME_TYPE_VENDOR: 141 return VIDEO_DIP_ENABLE_VENDOR; 142 case HDMI_INFOFRAME_TYPE_DRM: 143 return 0; 144 default: 145 MISSING_CASE(type); 146 return 0; 147 } 148 } 149 150 static u32 hsw_infoframe_enable(unsigned int type) 151 { 152 switch (type) { 153 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 154 return VIDEO_DIP_ENABLE_GCP_HSW; 155 case HDMI_PACKET_TYPE_GAMUT_METADATA: 156 return VIDEO_DIP_ENABLE_GMP_HSW; 157 case DP_SDP_VSC: 158 return VIDEO_DIP_ENABLE_VSC_HSW; 159 case DP_SDP_ADAPTIVE_SYNC: 160 return VIDEO_DIP_ENABLE_AS_ADL; 161 case DP_SDP_PPS: 162 return VDIP_ENABLE_PPS; 163 case HDMI_INFOFRAME_TYPE_AVI: 164 return VIDEO_DIP_ENABLE_AVI_HSW; 165 case HDMI_INFOFRAME_TYPE_SPD: 166 return VIDEO_DIP_ENABLE_SPD_HSW; 167 case HDMI_INFOFRAME_TYPE_VENDOR: 168 return VIDEO_DIP_ENABLE_VS_HSW; 169 case HDMI_INFOFRAME_TYPE_DRM: 170 return VIDEO_DIP_ENABLE_DRM_GLK; 171 default: 172 MISSING_CASE(type); 173 return 0; 174 } 175 } 176 177 static i915_reg_t 178 hsw_dip_data_reg(struct intel_display *display, 179 enum transcoder cpu_transcoder, 180 unsigned int type, 181 int i) 182 { 183 switch (type) { 184 case HDMI_PACKET_TYPE_GAMUT_METADATA: 185 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 186 case DP_SDP_VSC: 187 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 188 case DP_SDP_ADAPTIVE_SYNC: 189 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 190 case DP_SDP_PPS: 191 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 192 case HDMI_INFOFRAME_TYPE_AVI: 193 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 194 case HDMI_INFOFRAME_TYPE_SPD: 195 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 196 case HDMI_INFOFRAME_TYPE_VENDOR: 197 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 198 case HDMI_INFOFRAME_TYPE_DRM: 199 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 200 default: 201 MISSING_CASE(type); 202 return INVALID_MMIO_REG; 203 } 204 } 205 206 static int hsw_dip_data_size(struct intel_display *display, 207 unsigned int type) 208 { 209 switch (type) { 210 case DP_SDP_VSC: 211 return VIDEO_DIP_VSC_DATA_SIZE; 212 case DP_SDP_ADAPTIVE_SYNC: 213 return VIDEO_DIP_ASYNC_DATA_SIZE; 214 case DP_SDP_PPS: 215 return VIDEO_DIP_PPS_DATA_SIZE; 216 case HDMI_PACKET_TYPE_GAMUT_METADATA: 217 if (DISPLAY_VER(display) >= 11) 218 return VIDEO_DIP_GMP_DATA_SIZE; 219 else 220 return VIDEO_DIP_DATA_SIZE; 221 default: 222 return VIDEO_DIP_DATA_SIZE; 223 } 224 } 225 226 static void g4x_write_infoframe(struct intel_encoder *encoder, 227 const struct intel_crtc_state *crtc_state, 228 unsigned int type, 229 const void *frame, ssize_t len) 230 { 231 struct intel_display *display = to_intel_display(encoder); 232 const u32 *data = frame; 233 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 234 int i; 235 236 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 237 "Writing DIP with CTL reg disabled\n"); 238 239 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 240 val |= g4x_infoframe_index(type); 241 242 val &= ~g4x_infoframe_enable(type); 243 244 intel_de_write(display, VIDEO_DIP_CTL, val); 245 246 for (i = 0; i < len; i += 4) { 247 intel_de_write(display, VIDEO_DIP_DATA, *data); 248 data++; 249 } 250 /* Write every possible data byte to force correct ECC calculation. */ 251 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 252 intel_de_write(display, VIDEO_DIP_DATA, 0); 253 254 val |= g4x_infoframe_enable(type); 255 val &= ~VIDEO_DIP_FREQ_MASK; 256 val |= VIDEO_DIP_FREQ_VSYNC; 257 258 intel_de_write(display, VIDEO_DIP_CTL, val); 259 intel_de_posting_read(display, VIDEO_DIP_CTL); 260 } 261 262 static void g4x_read_infoframe(struct intel_encoder *encoder, 263 const struct intel_crtc_state *crtc_state, 264 unsigned int type, 265 void *frame, ssize_t len) 266 { 267 struct intel_display *display = to_intel_display(encoder); 268 u32 *data = frame; 269 int i; 270 271 intel_de_rmw(display, VIDEO_DIP_CTL, 272 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 273 274 for (i = 0; i < len; i += 4) 275 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 276 } 277 278 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 279 const struct intel_crtc_state *pipe_config) 280 { 281 struct intel_display *display = to_intel_display(encoder); 282 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 283 284 if ((val & VIDEO_DIP_ENABLE) == 0) 285 return 0; 286 287 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 288 return 0; 289 290 return val & (VIDEO_DIP_ENABLE_AVI | 291 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 292 } 293 294 static void ibx_write_infoframe(struct intel_encoder *encoder, 295 const struct intel_crtc_state *crtc_state, 296 unsigned int type, 297 const void *frame, ssize_t len) 298 { 299 struct intel_display *display = to_intel_display(encoder); 300 const u32 *data = frame; 301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 302 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 303 u32 val = intel_de_read(display, reg); 304 int i; 305 306 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 307 "Writing DIP with CTL reg disabled\n"); 308 309 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 310 val |= g4x_infoframe_index(type); 311 312 val &= ~g4x_infoframe_enable(type); 313 314 intel_de_write(display, reg, val); 315 316 for (i = 0; i < len; i += 4) { 317 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 318 *data); 319 data++; 320 } 321 /* Write every possible data byte to force correct ECC calculation. */ 322 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 323 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 324 325 val |= g4x_infoframe_enable(type); 326 val &= ~VIDEO_DIP_FREQ_MASK; 327 val |= VIDEO_DIP_FREQ_VSYNC; 328 329 intel_de_write(display, reg, val); 330 intel_de_posting_read(display, reg); 331 } 332 333 static void ibx_read_infoframe(struct intel_encoder *encoder, 334 const struct intel_crtc_state *crtc_state, 335 unsigned int type, 336 void *frame, ssize_t len) 337 { 338 struct intel_display *display = to_intel_display(encoder); 339 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 340 u32 *data = frame; 341 int i; 342 343 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 344 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 345 346 for (i = 0; i < len; i += 4) 347 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 348 } 349 350 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 351 const struct intel_crtc_state *pipe_config) 352 { 353 struct intel_display *display = to_intel_display(encoder); 354 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 355 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 356 u32 val = intel_de_read(display, reg); 357 358 if ((val & VIDEO_DIP_ENABLE) == 0) 359 return 0; 360 361 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 362 return 0; 363 364 return val & (VIDEO_DIP_ENABLE_AVI | 365 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 366 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 367 } 368 369 static void cpt_write_infoframe(struct intel_encoder *encoder, 370 const struct intel_crtc_state *crtc_state, 371 unsigned int type, 372 const void *frame, ssize_t len) 373 { 374 struct intel_display *display = to_intel_display(encoder); 375 const u32 *data = frame; 376 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 377 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 378 u32 val = intel_de_read(display, reg); 379 int i; 380 381 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 382 "Writing DIP with CTL reg disabled\n"); 383 384 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 385 val |= g4x_infoframe_index(type); 386 387 /* The DIP control register spec says that we need to update the AVI 388 * infoframe without clearing its enable bit */ 389 if (type != HDMI_INFOFRAME_TYPE_AVI) 390 val &= ~g4x_infoframe_enable(type); 391 392 intel_de_write(display, reg, val); 393 394 for (i = 0; i < len; i += 4) { 395 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 396 *data); 397 data++; 398 } 399 /* Write every possible data byte to force correct ECC calculation. */ 400 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 401 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 402 403 val |= g4x_infoframe_enable(type); 404 val &= ~VIDEO_DIP_FREQ_MASK; 405 val |= VIDEO_DIP_FREQ_VSYNC; 406 407 intel_de_write(display, reg, val); 408 intel_de_posting_read(display, reg); 409 } 410 411 static void cpt_read_infoframe(struct intel_encoder *encoder, 412 const struct intel_crtc_state *crtc_state, 413 unsigned int type, 414 void *frame, ssize_t len) 415 { 416 struct intel_display *display = to_intel_display(encoder); 417 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 418 u32 *data = frame; 419 int i; 420 421 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 422 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 423 424 for (i = 0; i < len; i += 4) 425 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 426 } 427 428 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 429 const struct intel_crtc_state *pipe_config) 430 { 431 struct intel_display *display = to_intel_display(encoder); 432 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 433 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 434 435 if ((val & VIDEO_DIP_ENABLE) == 0) 436 return 0; 437 438 return val & (VIDEO_DIP_ENABLE_AVI | 439 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 440 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 441 } 442 443 static void vlv_write_infoframe(struct intel_encoder *encoder, 444 const struct intel_crtc_state *crtc_state, 445 unsigned int type, 446 const void *frame, ssize_t len) 447 { 448 struct intel_display *display = to_intel_display(encoder); 449 const u32 *data = frame; 450 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 451 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 452 u32 val = intel_de_read(display, reg); 453 int i; 454 455 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 456 "Writing DIP with CTL reg disabled\n"); 457 458 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 459 val |= g4x_infoframe_index(type); 460 461 val &= ~g4x_infoframe_enable(type); 462 463 intel_de_write(display, reg, val); 464 465 for (i = 0; i < len; i += 4) { 466 intel_de_write(display, 467 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 468 data++; 469 } 470 /* Write every possible data byte to force correct ECC calculation. */ 471 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 472 intel_de_write(display, 473 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 474 475 val |= g4x_infoframe_enable(type); 476 val &= ~VIDEO_DIP_FREQ_MASK; 477 val |= VIDEO_DIP_FREQ_VSYNC; 478 479 intel_de_write(display, reg, val); 480 intel_de_posting_read(display, reg); 481 } 482 483 static void vlv_read_infoframe(struct intel_encoder *encoder, 484 const struct intel_crtc_state *crtc_state, 485 unsigned int type, 486 void *frame, ssize_t len) 487 { 488 struct intel_display *display = to_intel_display(encoder); 489 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 490 u32 *data = frame; 491 int i; 492 493 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 494 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 495 496 for (i = 0; i < len; i += 4) 497 *data++ = intel_de_read(display, 498 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 499 } 500 501 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 502 const struct intel_crtc_state *pipe_config) 503 { 504 struct intel_display *display = to_intel_display(encoder); 505 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 506 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 507 508 if ((val & VIDEO_DIP_ENABLE) == 0) 509 return 0; 510 511 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 512 return 0; 513 514 return val & (VIDEO_DIP_ENABLE_AVI | 515 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 516 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 517 } 518 519 void hsw_write_infoframe(struct intel_encoder *encoder, 520 const struct intel_crtc_state *crtc_state, 521 unsigned int type, 522 const void *frame, ssize_t len) 523 { 524 struct intel_display *display = to_intel_display(encoder); 525 const u32 *data = frame; 526 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 527 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 528 int data_size; 529 int i; 530 u32 val = intel_de_read(display, ctl_reg); 531 532 data_size = hsw_dip_data_size(display, type); 533 534 drm_WARN_ON(display->drm, len > data_size); 535 536 val &= ~hsw_infoframe_enable(type); 537 intel_de_write(display, ctl_reg, val); 538 539 for (i = 0; i < len; i += 4) { 540 intel_de_write(display, 541 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 542 *data); 543 data++; 544 } 545 /* Write every possible data byte to force correct ECC calculation. */ 546 for (; i < data_size; i += 4) 547 intel_de_write(display, 548 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 549 0); 550 551 /* Wa_14013475917 */ 552 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 553 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 554 val |= hsw_infoframe_enable(type); 555 556 if (type == DP_SDP_VSC) 557 val |= VSC_DIP_HW_DATA_SW_HEA; 558 559 intel_de_write(display, ctl_reg, val); 560 intel_de_posting_read(display, ctl_reg); 561 } 562 563 void hsw_read_infoframe(struct intel_encoder *encoder, 564 const struct intel_crtc_state *crtc_state, 565 unsigned int type, void *frame, ssize_t len) 566 { 567 struct intel_display *display = to_intel_display(encoder); 568 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 569 u32 *data = frame; 570 int i; 571 572 for (i = 0; i < len; i += 4) 573 *data++ = intel_de_read(display, 574 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 575 } 576 577 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 578 const struct intel_crtc_state *pipe_config) 579 { 580 struct intel_display *display = to_intel_display(encoder); 581 u32 val = intel_de_read(display, 582 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 583 u32 mask; 584 585 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 586 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 587 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 588 589 if (DISPLAY_VER(display) >= 10) 590 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 591 592 if (HAS_AS_SDP(display)) 593 mask |= VIDEO_DIP_ENABLE_AS_ADL; 594 595 return val & mask; 596 } 597 598 static const u8 infoframe_type_to_idx[] = { 599 HDMI_PACKET_TYPE_GENERAL_CONTROL, 600 HDMI_PACKET_TYPE_GAMUT_METADATA, 601 DP_SDP_VSC, 602 DP_SDP_ADAPTIVE_SYNC, 603 HDMI_INFOFRAME_TYPE_AVI, 604 HDMI_INFOFRAME_TYPE_SPD, 605 HDMI_INFOFRAME_TYPE_VENDOR, 606 HDMI_INFOFRAME_TYPE_DRM, 607 }; 608 609 u32 intel_hdmi_infoframe_enable(unsigned int type) 610 { 611 int i; 612 613 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 614 if (infoframe_type_to_idx[i] == type) 615 return BIT(i); 616 } 617 618 return 0; 619 } 620 621 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 622 const struct intel_crtc_state *crtc_state) 623 { 624 struct intel_display *display = to_intel_display(encoder); 625 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 626 u32 val, ret = 0; 627 int i; 628 629 val = dig_port->infoframes_enabled(encoder, crtc_state); 630 631 /* map from hardware bits to dip idx */ 632 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 633 unsigned int type = infoframe_type_to_idx[i]; 634 635 if (HAS_DDI(display)) { 636 if (val & hsw_infoframe_enable(type)) 637 ret |= BIT(i); 638 } else { 639 if (val & g4x_infoframe_enable(type)) 640 ret |= BIT(i); 641 } 642 } 643 644 return ret; 645 } 646 647 /* 648 * The data we write to the DIP data buffer registers is 1 byte bigger than the 649 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 650 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 651 * used for both technologies. 652 * 653 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 654 * DW1: DB3 | DB2 | DB1 | DB0 655 * DW2: DB7 | DB6 | DB5 | DB4 656 * DW3: ... 657 * 658 * (HB is Header Byte, DB is Data Byte) 659 * 660 * The hdmi pack() functions don't know about that hardware specific hole so we 661 * trick them by giving an offset into the buffer and moving back the header 662 * bytes by one. 663 */ 664 static void intel_write_infoframe(struct intel_encoder *encoder, 665 const struct intel_crtc_state *crtc_state, 666 enum hdmi_infoframe_type type, 667 const union hdmi_infoframe *frame) 668 { 669 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 670 u8 buffer[VIDEO_DIP_DATA_SIZE]; 671 ssize_t len; 672 673 if ((crtc_state->infoframes.enable & 674 intel_hdmi_infoframe_enable(type)) == 0) 675 return; 676 677 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 678 return; 679 680 /* see comment above for the reason for this offset */ 681 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 682 if (drm_WARN_ON(encoder->base.dev, len < 0)) 683 return; 684 685 /* Insert the 'hole' (see big comment above) at position 3 */ 686 memmove(&buffer[0], &buffer[1], 3); 687 buffer[3] = 0; 688 len++; 689 690 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 691 } 692 693 void intel_read_infoframe(struct intel_encoder *encoder, 694 const struct intel_crtc_state *crtc_state, 695 enum hdmi_infoframe_type type, 696 union hdmi_infoframe *frame) 697 { 698 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 699 u8 buffer[VIDEO_DIP_DATA_SIZE]; 700 int ret; 701 702 if ((crtc_state->infoframes.enable & 703 intel_hdmi_infoframe_enable(type)) == 0) 704 return; 705 706 dig_port->read_infoframe(encoder, crtc_state, 707 type, buffer, sizeof(buffer)); 708 709 /* Fill the 'hole' (see big comment above) at position 3 */ 710 memmove(&buffer[1], &buffer[0], 3); 711 712 /* see comment above for the reason for this offset */ 713 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 714 if (ret) { 715 drm_dbg_kms(encoder->base.dev, 716 "Failed to unpack infoframe type 0x%02x\n", type); 717 return; 718 } 719 720 if (frame->any.type != type) 721 drm_dbg_kms(encoder->base.dev, 722 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 723 frame->any.type, type); 724 } 725 726 static bool 727 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 728 struct intel_crtc_state *crtc_state, 729 struct drm_connector_state *conn_state) 730 { 731 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 732 const struct drm_display_mode *adjusted_mode = 733 &crtc_state->hw.adjusted_mode; 734 struct intel_connector *connector = to_intel_connector(conn_state->connector); 735 int ret; 736 737 if (!crtc_state->has_infoframe) 738 return true; 739 740 crtc_state->infoframes.enable |= 741 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 742 743 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base, 744 adjusted_mode); 745 if (ret) 746 return false; 747 748 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 749 frame->colorspace = HDMI_COLORSPACE_YUV420; 750 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 751 frame->colorspace = HDMI_COLORSPACE_YUV444; 752 else 753 frame->colorspace = HDMI_COLORSPACE_RGB; 754 755 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 756 757 /* nonsense combination */ 758 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 759 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 760 761 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 762 drm_hdmi_avi_infoframe_quant_range(frame, &connector->base, 763 adjusted_mode, 764 crtc_state->limited_color_range ? 765 HDMI_QUANTIZATION_RANGE_LIMITED : 766 HDMI_QUANTIZATION_RANGE_FULL); 767 } else { 768 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 769 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 770 } 771 772 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 773 774 /* TODO: handle pixel repetition for YCBCR420 outputs */ 775 776 ret = hdmi_avi_infoframe_check(frame); 777 if (drm_WARN_ON(encoder->base.dev, ret)) 778 return false; 779 780 return true; 781 } 782 783 static bool 784 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 785 struct intel_crtc_state *crtc_state, 786 struct drm_connector_state *conn_state) 787 { 788 struct intel_display *display = to_intel_display(crtc_state); 789 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 790 int ret; 791 792 if (!crtc_state->has_infoframe) 793 return true; 794 795 crtc_state->infoframes.enable |= 796 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 797 798 if (display->platform.dgfx) 799 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 800 else 801 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 802 803 if (drm_WARN_ON(encoder->base.dev, ret)) 804 return false; 805 806 frame->sdi = HDMI_SPD_SDI_PC; 807 808 ret = hdmi_spd_infoframe_check(frame); 809 if (drm_WARN_ON(encoder->base.dev, ret)) 810 return false; 811 812 return true; 813 } 814 815 static bool 816 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 817 struct intel_crtc_state *crtc_state, 818 struct drm_connector_state *conn_state) 819 { 820 struct hdmi_vendor_infoframe *frame = 821 &crtc_state->infoframes.hdmi.vendor.hdmi; 822 const struct drm_display_info *info = 823 &conn_state->connector->display_info; 824 int ret; 825 826 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 827 return true; 828 829 crtc_state->infoframes.enable |= 830 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 831 832 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 833 conn_state->connector, 834 &crtc_state->hw.adjusted_mode); 835 if (drm_WARN_ON(encoder->base.dev, ret)) 836 return false; 837 838 ret = hdmi_vendor_infoframe_check(frame); 839 if (drm_WARN_ON(encoder->base.dev, ret)) 840 return false; 841 842 return true; 843 } 844 845 static bool 846 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 847 struct intel_crtc_state *crtc_state, 848 struct drm_connector_state *conn_state) 849 { 850 struct intel_display *display = to_intel_display(encoder); 851 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 852 int ret; 853 854 if (DISPLAY_VER(display) < 10) 855 return true; 856 857 if (!crtc_state->has_infoframe) 858 return true; 859 860 if (!conn_state->hdr_output_metadata) 861 return true; 862 863 crtc_state->infoframes.enable |= 864 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 865 866 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 867 if (ret < 0) { 868 drm_dbg_kms(display->drm, 869 "couldn't set HDR metadata in infoframe\n"); 870 return false; 871 } 872 873 ret = hdmi_drm_infoframe_check(frame); 874 if (drm_WARN_ON(display->drm, ret)) 875 return false; 876 877 return true; 878 } 879 880 static void g4x_set_infoframes(struct intel_encoder *encoder, 881 bool enable, 882 const struct intel_crtc_state *crtc_state, 883 const struct drm_connector_state *conn_state) 884 { 885 struct intel_display *display = to_intel_display(encoder); 886 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 887 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 888 i915_reg_t reg = VIDEO_DIP_CTL; 889 u32 val = intel_de_read(display, reg); 890 u32 port = VIDEO_DIP_PORT(encoder->port); 891 892 assert_hdmi_port_disabled(intel_hdmi); 893 894 /* If the registers were not initialized yet, they might be zeroes, 895 * which means we're selecting the AVI DIP and we're setting its 896 * frequency to once. This seems to really confuse the HW and make 897 * things stop working (the register spec says the AVI always needs to 898 * be sent every VSync). So here we avoid writing to the register more 899 * than we need and also explicitly select the AVI DIP and explicitly 900 * set its frequency to every VSync. Avoiding to write it twice seems to 901 * be enough to solve the problem, but being defensive shouldn't hurt us 902 * either. */ 903 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 904 905 if (!enable) { 906 if (!(val & VIDEO_DIP_ENABLE)) 907 return; 908 if (port != (val & VIDEO_DIP_PORT_MASK)) { 909 drm_dbg_kms(display->drm, 910 "video DIP still enabled on port %c\n", 911 (val & VIDEO_DIP_PORT_MASK) >> 29); 912 return; 913 } 914 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 915 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 916 intel_de_write(display, reg, val); 917 intel_de_posting_read(display, reg); 918 return; 919 } 920 921 if (port != (val & VIDEO_DIP_PORT_MASK)) { 922 if (val & VIDEO_DIP_ENABLE) { 923 drm_dbg_kms(display->drm, 924 "video DIP already enabled on port %c\n", 925 (val & VIDEO_DIP_PORT_MASK) >> 29); 926 return; 927 } 928 val &= ~VIDEO_DIP_PORT_MASK; 929 val |= port; 930 } 931 932 val |= VIDEO_DIP_ENABLE; 933 val &= ~(VIDEO_DIP_ENABLE_AVI | 934 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 935 936 intel_de_write(display, reg, val); 937 intel_de_posting_read(display, reg); 938 939 intel_write_infoframe(encoder, crtc_state, 940 HDMI_INFOFRAME_TYPE_AVI, 941 &crtc_state->infoframes.avi); 942 intel_write_infoframe(encoder, crtc_state, 943 HDMI_INFOFRAME_TYPE_SPD, 944 &crtc_state->infoframes.spd); 945 intel_write_infoframe(encoder, crtc_state, 946 HDMI_INFOFRAME_TYPE_VENDOR, 947 &crtc_state->infoframes.hdmi); 948 } 949 950 /* 951 * Determine if default_phase=1 can be indicated in the GCP infoframe. 952 * 953 * From HDMI specification 1.4a: 954 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 955 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 956 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 957 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 958 * phase of 0 959 */ 960 static bool gcp_default_phase_possible(int pipe_bpp, 961 const struct drm_display_mode *mode) 962 { 963 unsigned int pixels_per_group; 964 965 switch (pipe_bpp) { 966 case 30: 967 /* 4 pixels in 5 clocks */ 968 pixels_per_group = 4; 969 break; 970 case 36: 971 /* 2 pixels in 3 clocks */ 972 pixels_per_group = 2; 973 break; 974 case 48: 975 /* 1 pixel in 2 clocks */ 976 pixels_per_group = 1; 977 break; 978 default: 979 /* phase information not relevant for 8bpc */ 980 return false; 981 } 982 983 return mode->crtc_hdisplay % pixels_per_group == 0 && 984 mode->crtc_htotal % pixels_per_group == 0 && 985 mode->crtc_hblank_start % pixels_per_group == 0 && 986 mode->crtc_hblank_end % pixels_per_group == 0 && 987 mode->crtc_hsync_start % pixels_per_group == 0 && 988 mode->crtc_hsync_end % pixels_per_group == 0 && 989 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 990 mode->crtc_htotal/2 % pixels_per_group == 0); 991 } 992 993 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 994 const struct intel_crtc_state *crtc_state, 995 const struct drm_connector_state *conn_state) 996 { 997 struct intel_display *display = to_intel_display(encoder); 998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 999 i915_reg_t reg; 1000 1001 if ((crtc_state->infoframes.enable & 1002 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1003 return false; 1004 1005 if (HAS_DDI(display)) 1006 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1007 else if (display->platform.valleyview || display->platform.cherryview) 1008 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1009 else if (HAS_PCH_SPLIT(display)) 1010 reg = TVIDEO_DIP_GCP(crtc->pipe); 1011 else 1012 return false; 1013 1014 intel_de_write(display, reg, crtc_state->infoframes.gcp); 1015 1016 return true; 1017 } 1018 1019 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1020 struct intel_crtc_state *crtc_state) 1021 { 1022 struct intel_display *display = to_intel_display(encoder); 1023 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1024 i915_reg_t reg; 1025 1026 if ((crtc_state->infoframes.enable & 1027 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1028 return; 1029 1030 if (HAS_DDI(display)) 1031 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1032 else if (display->platform.valleyview || display->platform.cherryview) 1033 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1034 else if (HAS_PCH_SPLIT(display)) 1035 reg = TVIDEO_DIP_GCP(crtc->pipe); 1036 else 1037 return; 1038 1039 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1040 } 1041 1042 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1043 struct intel_crtc_state *crtc_state, 1044 struct drm_connector_state *conn_state) 1045 { 1046 struct intel_display *display = to_intel_display(encoder); 1047 1048 if (display->platform.g4x || !crtc_state->has_infoframe) 1049 return; 1050 1051 crtc_state->infoframes.enable |= 1052 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1053 1054 /* Indicate color indication for deep color mode */ 1055 if (crtc_state->pipe_bpp > 24) 1056 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1057 1058 /* Enable default_phase whenever the display mode is suitably aligned */ 1059 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1060 &crtc_state->hw.adjusted_mode)) 1061 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1062 } 1063 1064 static void ibx_set_infoframes(struct intel_encoder *encoder, 1065 bool enable, 1066 const struct intel_crtc_state *crtc_state, 1067 const struct drm_connector_state *conn_state) 1068 { 1069 struct intel_display *display = to_intel_display(encoder); 1070 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1071 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1072 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1073 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1074 u32 val = intel_de_read(display, reg); 1075 u32 port = VIDEO_DIP_PORT(encoder->port); 1076 1077 assert_hdmi_port_disabled(intel_hdmi); 1078 1079 /* See the big comment in g4x_set_infoframes() */ 1080 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1081 1082 if (!enable) { 1083 if (!(val & VIDEO_DIP_ENABLE)) 1084 return; 1085 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1086 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1087 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1088 intel_de_write(display, reg, val); 1089 intel_de_posting_read(display, reg); 1090 return; 1091 } 1092 1093 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1094 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1095 "DIP already enabled on port %c\n", 1096 (val & VIDEO_DIP_PORT_MASK) >> 29); 1097 val &= ~VIDEO_DIP_PORT_MASK; 1098 val |= port; 1099 } 1100 1101 val |= VIDEO_DIP_ENABLE; 1102 val &= ~(VIDEO_DIP_ENABLE_AVI | 1103 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1104 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1105 1106 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1107 val |= VIDEO_DIP_ENABLE_GCP; 1108 1109 intel_de_write(display, reg, val); 1110 intel_de_posting_read(display, reg); 1111 1112 intel_write_infoframe(encoder, crtc_state, 1113 HDMI_INFOFRAME_TYPE_AVI, 1114 &crtc_state->infoframes.avi); 1115 intel_write_infoframe(encoder, crtc_state, 1116 HDMI_INFOFRAME_TYPE_SPD, 1117 &crtc_state->infoframes.spd); 1118 intel_write_infoframe(encoder, crtc_state, 1119 HDMI_INFOFRAME_TYPE_VENDOR, 1120 &crtc_state->infoframes.hdmi); 1121 } 1122 1123 static void cpt_set_infoframes(struct intel_encoder *encoder, 1124 bool enable, 1125 const struct intel_crtc_state *crtc_state, 1126 const struct drm_connector_state *conn_state) 1127 { 1128 struct intel_display *display = to_intel_display(encoder); 1129 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1130 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1131 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1132 u32 val = intel_de_read(display, reg); 1133 1134 assert_hdmi_port_disabled(intel_hdmi); 1135 1136 /* See the big comment in g4x_set_infoframes() */ 1137 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1138 1139 if (!enable) { 1140 if (!(val & VIDEO_DIP_ENABLE)) 1141 return; 1142 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1143 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1144 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1145 intel_de_write(display, reg, val); 1146 intel_de_posting_read(display, reg); 1147 return; 1148 } 1149 1150 /* Set both together, unset both together: see the spec. */ 1151 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1152 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1153 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1154 1155 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1156 val |= VIDEO_DIP_ENABLE_GCP; 1157 1158 intel_de_write(display, reg, val); 1159 intel_de_posting_read(display, reg); 1160 1161 intel_write_infoframe(encoder, crtc_state, 1162 HDMI_INFOFRAME_TYPE_AVI, 1163 &crtc_state->infoframes.avi); 1164 intel_write_infoframe(encoder, crtc_state, 1165 HDMI_INFOFRAME_TYPE_SPD, 1166 &crtc_state->infoframes.spd); 1167 intel_write_infoframe(encoder, crtc_state, 1168 HDMI_INFOFRAME_TYPE_VENDOR, 1169 &crtc_state->infoframes.hdmi); 1170 } 1171 1172 static void vlv_set_infoframes(struct intel_encoder *encoder, 1173 bool enable, 1174 const struct intel_crtc_state *crtc_state, 1175 const struct drm_connector_state *conn_state) 1176 { 1177 struct intel_display *display = to_intel_display(encoder); 1178 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1179 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1180 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1181 u32 val = intel_de_read(display, reg); 1182 u32 port = VIDEO_DIP_PORT(encoder->port); 1183 1184 assert_hdmi_port_disabled(intel_hdmi); 1185 1186 /* See the big comment in g4x_set_infoframes() */ 1187 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1188 1189 if (!enable) { 1190 if (!(val & VIDEO_DIP_ENABLE)) 1191 return; 1192 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1194 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1195 intel_de_write(display, reg, val); 1196 intel_de_posting_read(display, reg); 1197 return; 1198 } 1199 1200 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1201 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1202 "DIP already enabled on port %c\n", 1203 (val & VIDEO_DIP_PORT_MASK) >> 29); 1204 val &= ~VIDEO_DIP_PORT_MASK; 1205 val |= port; 1206 } 1207 1208 val |= VIDEO_DIP_ENABLE; 1209 val &= ~(VIDEO_DIP_ENABLE_AVI | 1210 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1211 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1212 1213 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1214 val |= VIDEO_DIP_ENABLE_GCP; 1215 1216 intel_de_write(display, reg, val); 1217 intel_de_posting_read(display, reg); 1218 1219 intel_write_infoframe(encoder, crtc_state, 1220 HDMI_INFOFRAME_TYPE_AVI, 1221 &crtc_state->infoframes.avi); 1222 intel_write_infoframe(encoder, crtc_state, 1223 HDMI_INFOFRAME_TYPE_SPD, 1224 &crtc_state->infoframes.spd); 1225 intel_write_infoframe(encoder, crtc_state, 1226 HDMI_INFOFRAME_TYPE_VENDOR, 1227 &crtc_state->infoframes.hdmi); 1228 } 1229 1230 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, 1231 const struct intel_crtc_state *crtc_state, 1232 const struct drm_connector_state *conn_state) 1233 { 1234 struct intel_display *display = to_intel_display(encoder); 1235 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1236 crtc_state->cpu_transcoder); 1237 u32 val = intel_de_read(display, reg); 1238 1239 if ((crtc_state->infoframes.enable & 1240 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 && 1241 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0) 1242 return; 1243 1244 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK); 1245 1246 intel_de_write(display, reg, val); 1247 intel_de_posting_read(display, reg); 1248 1249 intel_write_infoframe(encoder, crtc_state, 1250 HDMI_INFOFRAME_TYPE_DRM, 1251 &crtc_state->infoframes.drm); 1252 } 1253 1254 static void hsw_set_infoframes(struct intel_encoder *encoder, 1255 bool enable, 1256 const struct intel_crtc_state *crtc_state, 1257 const struct drm_connector_state *conn_state) 1258 { 1259 struct intel_display *display = to_intel_display(encoder); 1260 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1261 crtc_state->cpu_transcoder); 1262 u32 val = intel_de_read(display, reg); 1263 1264 assert_hdmi_transcoder_func_disabled(display, 1265 crtc_state->cpu_transcoder); 1266 1267 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1268 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1269 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1270 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1271 1272 if (!enable) { 1273 intel_de_write(display, reg, val); 1274 intel_de_posting_read(display, reg); 1275 return; 1276 } 1277 1278 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1279 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1280 1281 intel_de_write(display, reg, val); 1282 intel_de_posting_read(display, reg); 1283 1284 intel_write_infoframe(encoder, crtc_state, 1285 HDMI_INFOFRAME_TYPE_AVI, 1286 &crtc_state->infoframes.avi); 1287 intel_write_infoframe(encoder, crtc_state, 1288 HDMI_INFOFRAME_TYPE_SPD, 1289 &crtc_state->infoframes.spd); 1290 intel_write_infoframe(encoder, crtc_state, 1291 HDMI_INFOFRAME_TYPE_VENDOR, 1292 &crtc_state->infoframes.hdmi); 1293 intel_write_infoframe(encoder, crtc_state, 1294 HDMI_INFOFRAME_TYPE_DRM, 1295 &crtc_state->infoframes.drm); 1296 } 1297 1298 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1299 { 1300 struct intel_display *display = to_intel_display(hdmi); 1301 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1302 1303 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1304 return; 1305 1306 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1307 enable ? "Enabling" : "Disabling"); 1308 1309 drm_dp_dual_mode_set_tmds_output(display->drm, 1310 hdmi->dp_dual_mode.type, ddc, enable); 1311 } 1312 1313 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1314 unsigned int offset, void *buffer, size_t size) 1315 { 1316 struct intel_hdmi *hdmi = &dig_port->hdmi; 1317 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1318 int ret; 1319 u8 start = offset & 0xff; 1320 struct i2c_msg msgs[] = { 1321 { 1322 .addr = DRM_HDCP_DDC_ADDR, 1323 .flags = 0, 1324 .len = 1, 1325 .buf = &start, 1326 }, 1327 { 1328 .addr = DRM_HDCP_DDC_ADDR, 1329 .flags = I2C_M_RD, 1330 .len = size, 1331 .buf = buffer 1332 } 1333 }; 1334 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1335 if (ret == ARRAY_SIZE(msgs)) 1336 return 0; 1337 return ret >= 0 ? -EIO : ret; 1338 } 1339 1340 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1341 unsigned int offset, void *buffer, size_t size) 1342 { 1343 struct intel_hdmi *hdmi = &dig_port->hdmi; 1344 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1345 int ret; 1346 u8 *write_buf; 1347 struct i2c_msg msg; 1348 1349 write_buf = kzalloc(size + 1, GFP_KERNEL); 1350 if (!write_buf) 1351 return -ENOMEM; 1352 1353 write_buf[0] = offset & 0xff; 1354 memcpy(&write_buf[1], buffer, size); 1355 1356 msg.addr = DRM_HDCP_DDC_ADDR; 1357 msg.flags = 0; 1358 msg.len = size + 1; 1359 msg.buf = write_buf; 1360 1361 ret = i2c_transfer(ddc, &msg, 1); 1362 if (ret == 1) 1363 ret = 0; 1364 else if (ret >= 0) 1365 ret = -EIO; 1366 1367 kfree(write_buf); 1368 return ret; 1369 } 1370 1371 static 1372 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1373 u8 *an) 1374 { 1375 struct intel_display *display = to_intel_display(dig_port); 1376 struct intel_hdmi *hdmi = &dig_port->hdmi; 1377 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1378 int ret; 1379 1380 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1381 DRM_HDCP_AN_LEN); 1382 if (ret) { 1383 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1384 ret); 1385 return ret; 1386 } 1387 1388 ret = intel_gmbus_output_aksv(ddc); 1389 if (ret < 0) { 1390 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1391 return ret; 1392 } 1393 return 0; 1394 } 1395 1396 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1397 u8 *bksv) 1398 { 1399 struct intel_display *display = to_intel_display(dig_port); 1400 1401 int ret; 1402 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1403 DRM_HDCP_KSV_LEN); 1404 if (ret) 1405 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1406 ret); 1407 return ret; 1408 } 1409 1410 static 1411 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1412 u8 *bstatus) 1413 { 1414 struct intel_display *display = to_intel_display(dig_port); 1415 1416 int ret; 1417 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1418 bstatus, DRM_HDCP_BSTATUS_LEN); 1419 if (ret) 1420 drm_dbg_kms(display->drm, 1421 "Read bstatus over DDC failed (%d)\n", 1422 ret); 1423 return ret; 1424 } 1425 1426 static 1427 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1428 bool *repeater_present) 1429 { 1430 struct intel_display *display = to_intel_display(dig_port); 1431 int ret; 1432 u8 val; 1433 1434 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1435 if (ret) { 1436 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1437 ret); 1438 return ret; 1439 } 1440 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1441 return 0; 1442 } 1443 1444 static 1445 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1446 u8 *ri_prime) 1447 { 1448 struct intel_display *display = to_intel_display(dig_port); 1449 1450 int ret; 1451 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1452 ri_prime, DRM_HDCP_RI_LEN); 1453 if (ret) 1454 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1455 ret); 1456 return ret; 1457 } 1458 1459 static 1460 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1461 bool *ksv_ready) 1462 { 1463 struct intel_display *display = to_intel_display(dig_port); 1464 int ret; 1465 u8 val; 1466 1467 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1468 if (ret) { 1469 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1470 ret); 1471 return ret; 1472 } 1473 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1474 return 0; 1475 } 1476 1477 static 1478 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1479 int num_downstream, u8 *ksv_fifo) 1480 { 1481 struct intel_display *display = to_intel_display(dig_port); 1482 int ret; 1483 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1484 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1485 if (ret) { 1486 drm_dbg_kms(display->drm, 1487 "Read ksv fifo over DDC failed (%d)\n", ret); 1488 return ret; 1489 } 1490 return 0; 1491 } 1492 1493 static 1494 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1495 int i, u32 *part) 1496 { 1497 struct intel_display *display = to_intel_display(dig_port); 1498 int ret; 1499 1500 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1501 return -EINVAL; 1502 1503 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1504 part, DRM_HDCP_V_PRIME_PART_LEN); 1505 if (ret) 1506 drm_dbg_kms(display->drm, 1507 "Read V'[%d] over DDC failed (%d)\n", 1508 i, ret); 1509 return ret; 1510 } 1511 1512 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1513 enum transcoder cpu_transcoder) 1514 { 1515 struct intel_display *display = to_intel_display(connector); 1516 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1517 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1518 u32 scanline; 1519 int ret; 1520 1521 for (;;) { 1522 scanline = intel_de_read(display, 1523 PIPEDSL(display, crtc->pipe)); 1524 if (scanline > 100 && scanline < 200) 1525 break; 1526 usleep_range(25, 50); 1527 } 1528 1529 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1530 false, TRANS_DDI_HDCP_SIGNALLING); 1531 if (ret) { 1532 drm_err(display->drm, 1533 "Disable HDCP signalling failed (%d)\n", ret); 1534 return ret; 1535 } 1536 1537 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1538 true, TRANS_DDI_HDCP_SIGNALLING); 1539 if (ret) { 1540 drm_err(display->drm, 1541 "Enable HDCP signalling failed (%d)\n", ret); 1542 return ret; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static 1549 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1550 enum transcoder cpu_transcoder, 1551 bool enable) 1552 { 1553 struct intel_display *display = to_intel_display(dig_port); 1554 struct intel_hdmi *hdmi = &dig_port->hdmi; 1555 struct intel_connector *connector = hdmi->attached_connector; 1556 int ret; 1557 1558 if (!enable) 1559 usleep_range(6, 60); /* Bspec says >= 6us */ 1560 1561 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1562 cpu_transcoder, enable, 1563 TRANS_DDI_HDCP_SIGNALLING); 1564 if (ret) { 1565 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1566 enable ? "Enable" : "Disable", ret); 1567 return ret; 1568 } 1569 1570 /* 1571 * WA: To fix incorrect positioning of the window of 1572 * opportunity and enc_en signalling in KABYLAKE. 1573 */ 1574 if (display->platform.kabylake && enable) 1575 return kbl_repositioning_enc_en_signal(connector, 1576 cpu_transcoder); 1577 1578 return 0; 1579 } 1580 1581 static 1582 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1583 struct intel_connector *connector) 1584 { 1585 struct intel_display *display = to_intel_display(dig_port); 1586 enum port port = dig_port->base.port; 1587 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1588 int ret; 1589 union { 1590 u32 reg; 1591 u8 shim[DRM_HDCP_RI_LEN]; 1592 } ri; 1593 1594 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1595 if (ret) 1596 return false; 1597 1598 intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg); 1599 1600 /* Wait for Ri prime match */ 1601 ret = intel_de_wait_for_set(display, HDCP_STATUS(display, cpu_transcoder, port), 1602 HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1); 1603 if (ret) { 1604 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1605 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, 1606 port))); 1607 return false; 1608 } 1609 return true; 1610 } 1611 1612 static 1613 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1614 struct intel_connector *connector) 1615 { 1616 int retry; 1617 1618 for (retry = 0; retry < 3; retry++) 1619 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1620 return true; 1621 1622 return false; 1623 } 1624 1625 struct hdcp2_hdmi_msg_timeout { 1626 u8 msg_id; 1627 u16 timeout; 1628 }; 1629 1630 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1631 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1632 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1633 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1634 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1635 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1636 }; 1637 1638 static 1639 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1640 u8 *rx_status) 1641 { 1642 return intel_hdmi_hdcp_read(dig_port, 1643 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1644 rx_status, 1645 HDCP_2_2_HDMI_RXSTATUS_LEN); 1646 } 1647 1648 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1649 { 1650 int i; 1651 1652 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1653 if (is_paired) 1654 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1655 else 1656 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1657 } 1658 1659 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1660 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1661 return hdcp2_msg_timeout[i].timeout; 1662 } 1663 1664 return -EINVAL; 1665 } 1666 1667 static int 1668 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1669 u8 msg_id, bool *msg_ready, 1670 ssize_t *msg_sz) 1671 { 1672 struct intel_display *display = to_intel_display(dig_port); 1673 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1674 int ret; 1675 1676 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1677 if (ret < 0) { 1678 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1679 ret); 1680 return ret; 1681 } 1682 1683 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1684 rx_status[0]); 1685 1686 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1687 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1688 *msg_sz); 1689 else 1690 *msg_ready = *msg_sz; 1691 1692 return 0; 1693 } 1694 1695 static ssize_t 1696 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1697 u8 msg_id, bool paired) 1698 { 1699 struct intel_display *display = to_intel_display(dig_port); 1700 bool msg_ready = false; 1701 int timeout, ret; 1702 ssize_t msg_sz = 0; 1703 1704 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1705 if (timeout < 0) 1706 return timeout; 1707 1708 ret = poll_timeout_us(ret = hdcp2_detect_msg_availability(dig_port, msg_id, 1709 &msg_ready, &msg_sz), 1710 !ret && msg_ready && msg_sz, 1711 4000, timeout * 1000, false); 1712 if (ret) 1713 drm_dbg_kms(display->drm, 1714 "msg_id: %d, ret: %d, timeout: %d\n", 1715 msg_id, ret, timeout); 1716 1717 return ret ? ret : msg_sz; 1718 } 1719 1720 static 1721 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1722 void *buf, size_t size) 1723 { 1724 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1725 unsigned int offset; 1726 1727 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1728 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1729 } 1730 1731 static 1732 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1733 u8 msg_id, void *buf, size_t size) 1734 { 1735 struct intel_display *display = to_intel_display(connector); 1736 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1737 struct intel_hdmi *hdmi = &dig_port->hdmi; 1738 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1739 unsigned int offset; 1740 ssize_t ret; 1741 1742 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1743 hdcp->is_paired); 1744 if (ret < 0) 1745 return ret; 1746 1747 /* 1748 * Available msg size should be equal to or lesser than the 1749 * available buffer. 1750 */ 1751 if (ret > size) { 1752 drm_dbg_kms(display->drm, 1753 "msg_sz(%zd) is more than exp size(%zu)\n", 1754 ret, size); 1755 return -EINVAL; 1756 } 1757 1758 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1759 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1760 if (ret) 1761 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1762 msg_id, ret); 1763 1764 return ret; 1765 } 1766 1767 static 1768 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1769 struct intel_connector *connector) 1770 { 1771 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1772 int ret; 1773 1774 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1775 if (ret) 1776 return ret; 1777 1778 /* 1779 * Re-auth request and Link Integrity Failures are represented by 1780 * same bit. i.e reauth_req. 1781 */ 1782 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1783 ret = HDCP_REAUTH_REQUEST; 1784 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1785 ret = HDCP_TOPOLOGY_CHANGE; 1786 1787 return ret; 1788 } 1789 1790 static 1791 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1792 bool *capable) 1793 { 1794 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1795 u8 hdcp2_version; 1796 int ret; 1797 1798 *capable = false; 1799 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1800 &hdcp2_version, sizeof(hdcp2_version)); 1801 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1802 *capable = true; 1803 1804 return ret; 1805 } 1806 1807 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1808 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1809 .read_bksv = intel_hdmi_hdcp_read_bksv, 1810 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1811 .repeater_present = intel_hdmi_hdcp_repeater_present, 1812 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1813 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1814 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1815 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1816 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1817 .check_link = intel_hdmi_hdcp_check_link, 1818 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1819 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1820 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1821 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1822 .protocol = HDCP_PROTOCOL_HDMI, 1823 }; 1824 1825 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1826 { 1827 struct intel_display *display = to_intel_display(encoder); 1828 int max_tmds_clock, vbt_max_tmds_clock; 1829 1830 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s) 1831 max_tmds_clock = 600000; 1832 else if (DISPLAY_VER(display) >= 10) 1833 max_tmds_clock = 594000; 1834 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) 1835 max_tmds_clock = 300000; 1836 else if (DISPLAY_VER(display) >= 5) 1837 max_tmds_clock = 225000; 1838 else 1839 max_tmds_clock = 165000; 1840 1841 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1842 if (vbt_max_tmds_clock) 1843 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1844 1845 return max_tmds_clock; 1846 } 1847 1848 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1849 const struct drm_connector_state *conn_state) 1850 { 1851 struct intel_connector *connector = hdmi->attached_connector; 1852 1853 return connector->base.display_info.is_hdmi && 1854 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1855 } 1856 1857 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1858 { 1859 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1860 } 1861 1862 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1863 bool respect_downstream_limits, 1864 bool has_hdmi_sink) 1865 { 1866 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1867 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1868 1869 if (respect_downstream_limits) { 1870 struct intel_connector *connector = hdmi->attached_connector; 1871 const struct drm_display_info *info = &connector->base.display_info; 1872 1873 if (hdmi->dp_dual_mode.max_tmds_clock) 1874 max_tmds_clock = min(max_tmds_clock, 1875 hdmi->dp_dual_mode.max_tmds_clock); 1876 1877 if (info->max_tmds_clock) 1878 max_tmds_clock = min(max_tmds_clock, 1879 info->max_tmds_clock); 1880 else if (!has_hdmi_sink) 1881 max_tmds_clock = min(max_tmds_clock, 165000); 1882 } 1883 1884 return max_tmds_clock; 1885 } 1886 1887 static enum drm_mode_status 1888 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1889 int clock, bool respect_downstream_limits, 1890 bool has_hdmi_sink) 1891 { 1892 struct intel_display *display = to_intel_display(hdmi); 1893 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1894 1895 if (clock < 25000) 1896 return MODE_CLOCK_LOW; 1897 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1898 has_hdmi_sink)) 1899 return MODE_CLOCK_HIGH; 1900 1901 /* GLK DPLL can't generate 446-480 MHz */ 1902 if (display->platform.geminilake && clock > 446666 && clock < 480000) 1903 return MODE_CLOCK_RANGE; 1904 1905 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1906 if ((display->platform.geminilake || display->platform.broxton) && 1907 clock > 223333 && clock < 240000) 1908 return MODE_CLOCK_RANGE; 1909 1910 /* CHV DPLL can't generate 216-240 MHz */ 1911 if (display->platform.cherryview && clock > 216000 && clock < 240000) 1912 return MODE_CLOCK_RANGE; 1913 1914 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1915 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1916 return MODE_CLOCK_RANGE; 1917 1918 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1919 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1920 return MODE_CLOCK_RANGE; 1921 1922 return MODE_OK; 1923 } 1924 1925 int intel_hdmi_tmds_clock(int clock, int bpc, 1926 enum intel_output_format sink_format) 1927 { 1928 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1929 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1930 clock /= 2; 1931 1932 /* 1933 * Need to adjust the port link by: 1934 * 1.5x for 12bpc 1935 * 1.25x for 10bpc 1936 */ 1937 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1938 } 1939 1940 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1941 { 1942 switch (bpc) { 1943 case 12: 1944 return !HAS_GMCH(display); 1945 case 10: 1946 return DISPLAY_VER(display) >= 11; 1947 case 8: 1948 return true; 1949 default: 1950 MISSING_CASE(bpc); 1951 return false; 1952 } 1953 } 1954 1955 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector, 1956 int bpc, bool has_hdmi_sink, 1957 enum intel_output_format sink_format) 1958 { 1959 struct intel_connector *connector = to_intel_connector(_connector); 1960 const struct drm_display_info *info = &connector->base.display_info; 1961 const struct drm_hdmi_info *hdmi = &info->hdmi; 1962 1963 switch (bpc) { 1964 case 12: 1965 if (!has_hdmi_sink) 1966 return false; 1967 1968 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1969 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1970 else 1971 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1972 case 10: 1973 if (!has_hdmi_sink) 1974 return false; 1975 1976 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1977 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1978 else 1979 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1980 case 8: 1981 return true; 1982 default: 1983 MISSING_CASE(bpc); 1984 return false; 1985 } 1986 } 1987 1988 static enum drm_mode_status 1989 intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, 1990 bool has_hdmi_sink, 1991 enum intel_output_format sink_format) 1992 { 1993 struct intel_connector *connector = to_intel_connector(_connector); 1994 struct intel_display *display = to_intel_display(connector); 1995 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1996 enum drm_mode_status status = MODE_OK; 1997 int bpc; 1998 1999 /* 2000 * Try all color depths since valid port clock range 2001 * can have holes. Any mode that can be used with at 2002 * least one color depth is accepted. 2003 */ 2004 for (bpc = 12; bpc >= 8; bpc -= 2) { 2005 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 2006 2007 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2008 continue; 2009 2010 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2011 sink_format)) 2012 continue; 2013 2014 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 2015 if (status == MODE_OK) 2016 return MODE_OK; 2017 } 2018 2019 /* can never happen */ 2020 drm_WARN_ON(display->drm, status == MODE_OK); 2021 2022 return status; 2023 } 2024 2025 static enum drm_mode_status 2026 intel_hdmi_mode_valid(struct drm_connector *_connector, 2027 const struct drm_display_mode *mode) 2028 { 2029 struct intel_connector *connector = to_intel_connector(_connector); 2030 struct intel_display *display = to_intel_display(connector); 2031 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2032 enum drm_mode_status status; 2033 int clock = mode->clock; 2034 int max_dotclk = display->cdclk.max_dotclk_freq; 2035 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); 2036 bool ycbcr_420_only; 2037 enum intel_output_format sink_format; 2038 2039 status = intel_cpu_transcoder_mode_valid(display, mode); 2040 if (status != MODE_OK) 2041 return status; 2042 2043 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2044 clock *= 2; 2045 2046 if (clock > max_dotclk) 2047 return MODE_CLOCK_HIGH; 2048 2049 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2050 if (!has_hdmi_sink) 2051 return MODE_CLOCK_LOW; 2052 clock *= 2; 2053 } 2054 2055 /* 2056 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2057 * enumerated only if FRL is supported. Current platforms do not support 2058 * FRL so prune the higher resolution modes that require doctclock more 2059 * than 600MHz. 2060 */ 2061 if (clock > 600000) 2062 return MODE_CLOCK_HIGH; 2063 2064 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); 2065 2066 if (ycbcr_420_only) 2067 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2068 else 2069 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2070 2071 status = intel_pfit_mode_valid(display, mode, sink_format, 0); 2072 if (status != MODE_OK) 2073 return status; 2074 2075 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); 2076 if (status != MODE_OK) { 2077 if (ycbcr_420_only || 2078 !connector->base.ycbcr_420_allowed || 2079 !drm_mode_is_420_also(&connector->base.display_info, mode)) 2080 return status; 2081 2082 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2083 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, 2084 sink_format); 2085 if (status != MODE_OK) 2086 return status; 2087 } 2088 2089 return intel_mode_valid_max_plane_size(display, mode, 1); 2090 } 2091 2092 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2093 int bpc, bool has_hdmi_sink) 2094 { 2095 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 2096 struct intel_digital_connector_state *connector_state; 2097 struct intel_connector *connector; 2098 int i; 2099 2100 for_each_new_intel_connector_in_state(state, connector, connector_state, i) { 2101 if (connector_state->base.crtc != crtc_state->uapi.crtc) 2102 continue; 2103 2104 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2105 crtc_state->sink_format)) 2106 return false; 2107 } 2108 2109 return true; 2110 } 2111 2112 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2113 { 2114 struct intel_display *display = to_intel_display(crtc_state); 2115 const struct drm_display_mode *adjusted_mode = 2116 &crtc_state->hw.adjusted_mode; 2117 2118 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2119 return false; 2120 2121 /* Display Wa_1405510057:icl,ehl */ 2122 if (intel_hdmi_is_ycbcr420(crtc_state) && 2123 bpc == 10 && DISPLAY_VER(display) == 11 && 2124 (adjusted_mode->crtc_hblank_end - 2125 adjusted_mode->crtc_hblank_start) % 8 == 2) 2126 return false; 2127 2128 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2129 } 2130 2131 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2132 struct intel_crtc_state *crtc_state, 2133 int clock, bool respect_downstream_limits) 2134 { 2135 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2136 int bpc; 2137 2138 /* 2139 * pipe_bpp could already be below 8bpc due to FDI 2140 * bandwidth constraints. HDMI minimum is 8bpc however. 2141 */ 2142 bpc = max(crtc_state->pipe_bpp / 3, 8); 2143 2144 /* 2145 * We will never exceed downstream TMDS clock limits while 2146 * attempting deep color. If the user insists on forcing an 2147 * out of spec mode they will have to be satisfied with 8bpc. 2148 */ 2149 if (!respect_downstream_limits) 2150 bpc = 8; 2151 2152 for (; bpc >= 8; bpc -= 2) { 2153 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2154 crtc_state->sink_format); 2155 2156 if (hdmi_bpc_possible(crtc_state, bpc) && 2157 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2158 respect_downstream_limits, 2159 crtc_state->has_hdmi_sink) == MODE_OK) 2160 return bpc; 2161 } 2162 2163 return -EINVAL; 2164 } 2165 2166 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2167 struct intel_crtc_state *crtc_state, 2168 bool respect_downstream_limits) 2169 { 2170 struct intel_display *display = to_intel_display(encoder); 2171 const struct drm_display_mode *adjusted_mode = 2172 &crtc_state->hw.adjusted_mode; 2173 int bpc, clock = adjusted_mode->crtc_clock; 2174 2175 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2176 clock *= 2; 2177 2178 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2179 respect_downstream_limits); 2180 if (bpc < 0) 2181 return bpc; 2182 2183 crtc_state->port_clock = 2184 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2185 2186 /* 2187 * pipe_bpp could already be below 8bpc due to 2188 * FDI bandwidth constraints. We shouldn't bump it 2189 * back up to the HDMI minimum 8bpc in that case. 2190 */ 2191 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2192 2193 drm_dbg_kms(display->drm, 2194 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2195 bpc, crtc_state->pipe_bpp); 2196 2197 return 0; 2198 } 2199 2200 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2201 const struct drm_connector_state *conn_state) 2202 { 2203 const struct intel_digital_connector_state *intel_conn_state = 2204 to_intel_digital_connector_state(conn_state); 2205 const struct drm_display_mode *adjusted_mode = 2206 &crtc_state->hw.adjusted_mode; 2207 2208 /* 2209 * Our YCbCr output is always limited range. 2210 * crtc_state->limited_color_range only applies to RGB, 2211 * and it must never be set for YCbCr or we risk setting 2212 * some conflicting bits in TRANSCONF which will mess up 2213 * the colors on the monitor. 2214 */ 2215 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2216 return false; 2217 2218 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2219 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2220 return crtc_state->has_hdmi_sink && 2221 drm_default_rgb_quant_range(adjusted_mode) == 2222 HDMI_QUANTIZATION_RANGE_LIMITED; 2223 } else { 2224 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2225 } 2226 } 2227 2228 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2229 const struct intel_crtc_state *crtc_state, 2230 const struct drm_connector_state *conn_state) 2231 { 2232 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2233 const struct intel_digital_connector_state *intel_conn_state = 2234 to_intel_digital_connector_state(conn_state); 2235 2236 if (!crtc_state->has_hdmi_sink) 2237 return false; 2238 2239 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2240 return connector->base.display_info.has_audio; 2241 else 2242 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2243 } 2244 2245 static enum intel_output_format 2246 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2247 struct intel_connector *connector, 2248 bool ycbcr_420_output) 2249 { 2250 if (!crtc_state->has_hdmi_sink) 2251 return INTEL_OUTPUT_FORMAT_RGB; 2252 2253 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2254 return INTEL_OUTPUT_FORMAT_YCBCR420; 2255 else 2256 return INTEL_OUTPUT_FORMAT_RGB; 2257 } 2258 2259 static enum intel_output_format 2260 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2261 { 2262 return crtc_state->sink_format; 2263 } 2264 2265 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2266 struct intel_crtc_state *crtc_state, 2267 const struct drm_connector_state *conn_state, 2268 bool respect_downstream_limits) 2269 { 2270 struct intel_display *display = to_intel_display(encoder); 2271 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2272 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2273 const struct drm_display_info *info = &connector->base.display_info; 2274 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2275 int ret; 2276 2277 crtc_state->sink_format = 2278 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2279 2280 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2281 drm_dbg_kms(display->drm, 2282 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2283 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2284 } 2285 2286 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2287 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2288 if (ret) { 2289 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2290 !crtc_state->has_hdmi_sink || 2291 !connector->base.ycbcr_420_allowed || 2292 !drm_mode_is_420_also(info, adjusted_mode)) 2293 return ret; 2294 2295 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2296 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2297 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2298 } 2299 2300 return ret; 2301 } 2302 2303 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2304 { 2305 return crtc_state->uapi.encoder_mask && 2306 !is_power_of_2(crtc_state->uapi.encoder_mask); 2307 } 2308 2309 static bool source_supports_scrambling(struct intel_encoder *encoder) 2310 { 2311 /* 2312 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2313 * scrambling is supported. 2314 * But there seem to be cases where certain platforms that support 2315 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2316 * capped by VBT to less than 340MHz. 2317 * 2318 * In such cases when an HDMI2.0 sink is connected, it creates a 2319 * problem : the platform and the sink both support scrambling but the 2320 * HDMI 1.4 retimer chip doesn't. 2321 * 2322 * So go for scrambling, based on the max tmds clock taking into account, 2323 * restrictions coming from VBT. 2324 */ 2325 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2326 } 2327 2328 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2329 const struct intel_crtc_state *crtc_state, 2330 const struct drm_connector_state *conn_state) 2331 { 2332 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2333 2334 return intel_has_hdmi_sink(hdmi, conn_state) && 2335 !intel_hdmi_is_cloned(crtc_state); 2336 } 2337 2338 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2339 struct intel_crtc_state *pipe_config, 2340 struct drm_connector_state *conn_state) 2341 { 2342 struct intel_display *display = to_intel_display(encoder); 2343 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2344 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2345 struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc; 2346 int ret; 2347 2348 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2349 return -EINVAL; 2350 2351 if (!connector->base.interlace_allowed && 2352 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2353 return -EINVAL; 2354 2355 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2356 2357 if (pipe_config->has_hdmi_sink) 2358 pipe_config->has_infoframe = true; 2359 2360 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2361 pipe_config->pixel_multiplier = 2; 2362 2363 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) 2364 return -EINVAL; 2365 2366 pipe_config->has_audio = 2367 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2368 intel_audio_compute_config(encoder, pipe_config, conn_state); 2369 2370 /* 2371 * Try to respect downstream TMDS clock limits first, if 2372 * that fails assume the user might know something we don't. 2373 */ 2374 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2375 if (ret) 2376 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2377 if (ret) { 2378 drm_dbg_kms(display->drm, 2379 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2380 pipe_config->hw.adjusted_mode.crtc_clock); 2381 return ret; 2382 } 2383 2384 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2385 ret = intel_pfit_compute_config(pipe_config, conn_state); 2386 if (ret) 2387 return ret; 2388 } 2389 2390 pipe_config->limited_color_range = 2391 intel_hdmi_limited_color_range(pipe_config, conn_state); 2392 2393 if (conn_state->picture_aspect_ratio) 2394 adjusted_mode->picture_aspect_ratio = 2395 conn_state->picture_aspect_ratio; 2396 2397 pipe_config->lane_count = 4; 2398 2399 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2400 if (scdc->scrambling.low_rates) 2401 pipe_config->hdmi_scrambling = true; 2402 2403 if (pipe_config->port_clock > 340000) { 2404 pipe_config->hdmi_scrambling = true; 2405 pipe_config->hdmi_high_tmds_clock_ratio = true; 2406 } 2407 } 2408 2409 intel_vrr_compute_config(pipe_config, conn_state); 2410 2411 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2412 conn_state); 2413 2414 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2415 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2416 return -EINVAL; 2417 } 2418 2419 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2420 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2421 return -EINVAL; 2422 } 2423 2424 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2425 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2426 return -EINVAL; 2427 } 2428 2429 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2430 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2431 return -EINVAL; 2432 } 2433 2434 return 0; 2435 } 2436 2437 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2438 { 2439 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2440 2441 /* 2442 * Give a hand to buggy BIOSen which forget to turn 2443 * the TMDS output buffers back on after a reboot. 2444 */ 2445 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2446 } 2447 2448 static void 2449 intel_hdmi_unset_edid(struct drm_connector *_connector) 2450 { 2451 struct intel_connector *connector = to_intel_connector(_connector); 2452 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2453 2454 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2455 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2456 2457 drm_edid_free(connector->detect_edid); 2458 connector->detect_edid = NULL; 2459 } 2460 2461 static void 2462 intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector) 2463 { 2464 struct intel_connector *connector = to_intel_connector(_connector); 2465 struct intel_display *display = to_intel_display(connector); 2466 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2467 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2468 struct i2c_adapter *ddc = connector->base.ddc; 2469 enum drm_dp_dual_mode_type type; 2470 2471 type = drm_dp_dual_mode_detect(display->drm, ddc); 2472 2473 /* 2474 * Type 1 DVI adaptors are not required to implement any 2475 * registers, so we can't always detect their presence. 2476 * Ideally we should be able to check the state of the 2477 * CONFIG1 pin, but no such luck on our hardware. 2478 * 2479 * The only method left to us is to check the VBT to see 2480 * if the port is a dual mode capable DP port. 2481 */ 2482 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2483 if (!connector->base.force && 2484 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2485 drm_dbg_kms(display->drm, 2486 "Assuming DP dual mode adaptor presence based on VBT\n"); 2487 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2488 } else { 2489 type = DRM_DP_DUAL_MODE_NONE; 2490 } 2491 } 2492 2493 if (type == DRM_DP_DUAL_MODE_NONE) 2494 return; 2495 2496 hdmi->dp_dual_mode.type = type; 2497 hdmi->dp_dual_mode.max_tmds_clock = 2498 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2499 2500 drm_dbg_kms(display->drm, 2501 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2502 drm_dp_get_dual_mode_type_name(type), 2503 hdmi->dp_dual_mode.max_tmds_clock); 2504 2505 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2506 if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) && 2507 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2508 drm_dbg_kms(display->drm, 2509 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2510 hdmi->dp_dual_mode.max_tmds_clock = 0; 2511 } 2512 } 2513 2514 static bool 2515 intel_hdmi_set_edid(struct drm_connector *_connector) 2516 { 2517 struct intel_connector *connector = to_intel_connector(_connector); 2518 struct intel_display *display = to_intel_display(connector); 2519 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2520 struct i2c_adapter *ddc = connector->base.ddc; 2521 intel_wakeref_t wakeref; 2522 const struct drm_edid *drm_edid; 2523 bool connected = false; 2524 2525 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2526 2527 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2528 2529 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2530 drm_dbg_kms(display->drm, 2531 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2532 intel_gmbus_force_bit(ddc, true); 2533 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2534 intel_gmbus_force_bit(ddc, false); 2535 } 2536 2537 /* Below we depend on display info having been updated */ 2538 drm_edid_connector_update(&connector->base, drm_edid); 2539 2540 connector->detect_edid = drm_edid; 2541 2542 if (drm_edid_is_digital(drm_edid)) { 2543 intel_hdmi_dp_dual_mode_detect(&connector->base); 2544 2545 connected = true; 2546 } 2547 2548 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2549 2550 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2551 connector->base.display_info.source_physical_address); 2552 2553 return connected; 2554 } 2555 2556 static enum drm_connector_status 2557 intel_hdmi_detect(struct drm_connector *_connector, bool force) 2558 { 2559 struct intel_connector *connector = to_intel_connector(_connector); 2560 struct intel_display *display = to_intel_display(connector); 2561 enum drm_connector_status status = connector_status_disconnected; 2562 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2563 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2564 intel_wakeref_t wakeref; 2565 2566 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2567 connector->base.base.id, connector->base.name); 2568 2569 if (!intel_display_device_enabled(display)) 2570 return connector_status_disconnected; 2571 2572 if (!intel_display_driver_check_access(display)) 2573 return connector->base.status; 2574 2575 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2576 2577 if (DISPLAY_VER(display) >= 11 && 2578 !intel_digital_port_connected(encoder)) 2579 goto out; 2580 2581 intel_hdmi_unset_edid(&connector->base); 2582 2583 if (intel_hdmi_set_edid(&connector->base)) 2584 status = connector_status_connected; 2585 2586 out: 2587 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2588 2589 if (status != connector_status_connected) 2590 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2591 2592 return status; 2593 } 2594 2595 static void 2596 intel_hdmi_force(struct drm_connector *_connector) 2597 { 2598 struct intel_connector *connector = to_intel_connector(_connector); 2599 struct intel_display *display = to_intel_display(connector); 2600 2601 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2602 connector->base.base.id, connector->base.name); 2603 2604 if (!intel_display_driver_check_access(display)) 2605 return; 2606 2607 intel_hdmi_unset_edid(&connector->base); 2608 2609 if (connector->base.status != connector_status_connected) 2610 return; 2611 2612 intel_hdmi_set_edid(&connector->base); 2613 } 2614 2615 static int intel_hdmi_get_modes(struct drm_connector *_connector) 2616 { 2617 struct intel_connector *connector = to_intel_connector(_connector); 2618 2619 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2620 return drm_edid_connector_add_modes(&connector->base); 2621 } 2622 2623 static int 2624 intel_hdmi_connector_register(struct drm_connector *_connector) 2625 { 2626 struct intel_connector *connector = to_intel_connector(_connector); 2627 int ret; 2628 2629 ret = intel_connector_register(&connector->base); 2630 if (ret) 2631 return ret; 2632 2633 return ret; 2634 } 2635 2636 static void intel_hdmi_connector_unregister(struct drm_connector *_connector) 2637 { 2638 struct intel_connector *connector = to_intel_connector(_connector); 2639 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; 2640 2641 cec_notifier_conn_unregister(n); 2642 2643 intel_connector_unregister(&connector->base); 2644 } 2645 2646 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2647 .detect = intel_hdmi_detect, 2648 .force = intel_hdmi_force, 2649 .fill_modes = drm_helper_probe_single_connector_modes, 2650 .atomic_get_property = intel_digital_connector_atomic_get_property, 2651 .atomic_set_property = intel_digital_connector_atomic_set_property, 2652 .late_register = intel_hdmi_connector_register, 2653 .early_unregister = intel_hdmi_connector_unregister, 2654 .destroy = intel_connector_destroy, 2655 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2656 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2657 }; 2658 2659 static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, 2660 struct drm_atomic_state *state) 2661 { 2662 struct intel_connector *connector = to_intel_connector(_connector); 2663 struct intel_display *display = to_intel_display(connector); 2664 2665 if (HAS_DDI(display)) 2666 return intel_digital_connector_atomic_check(&connector->base, state); 2667 else 2668 return g4x_hdmi_connector_atomic_check(&connector->base, state); 2669 } 2670 2671 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2672 .get_modes = intel_hdmi_get_modes, 2673 .mode_valid = intel_hdmi_mode_valid, 2674 .atomic_check = intel_hdmi_connector_atomic_check, 2675 }; 2676 2677 static void 2678 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_connector) 2679 { 2680 struct intel_connector *connector = to_intel_connector(_connector); 2681 struct intel_display *display = to_intel_display(intel_hdmi); 2682 2683 intel_attach_force_audio_property(&connector->base); 2684 intel_attach_broadcast_rgb_property(&connector->base); 2685 intel_attach_aspect_ratio_property(&connector->base); 2686 2687 intel_attach_hdmi_colorspace_property(&connector->base); 2688 drm_connector_attach_content_type_property(&connector->base); 2689 2690 if (DISPLAY_VER(display) >= 10) 2691 drm_connector_attach_hdr_output_metadata_property(&connector->base); 2692 2693 if (!HAS_GMCH(display)) 2694 drm_connector_attach_max_bpc_property(&connector->base, 8, 12); 2695 } 2696 2697 /* 2698 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2699 * @encoder: intel_encoder 2700 * @connector: drm_connector 2701 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2702 * or reset the high tmds clock ratio for scrambling 2703 * @scrambling: bool to Indicate if the function needs to set or reset 2704 * sink scrambling 2705 * 2706 * This function handles scrambling on HDMI 2.0 capable sinks. 2707 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2708 * it enables scrambling. This should be called before enabling the HDMI 2709 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2710 * detect a scrambled clock within 100 ms. 2711 * 2712 * Returns: 2713 * True on success, false on failure. 2714 */ 2715 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2716 struct drm_connector *_connector, 2717 bool high_tmds_clock_ratio, 2718 bool scrambling) 2719 { 2720 struct intel_connector *connector = to_intel_connector(_connector); 2721 struct intel_display *display = to_intel_display(encoder); 2722 struct drm_scrambling *sink_scrambling = 2723 &connector->base.display_info.hdmi.scdc.scrambling; 2724 2725 if (!sink_scrambling->supported) 2726 return true; 2727 2728 drm_dbg_kms(display->drm, 2729 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2730 connector->base.base.id, connector->base.name, 2731 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2732 2733 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2734 return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) && 2735 drm_scdc_set_scrambling(&connector->base, scrambling); 2736 } 2737 2738 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2739 { 2740 enum port port = encoder->port; 2741 u8 ddc_pin; 2742 2743 switch (port) { 2744 case PORT_B: 2745 ddc_pin = GMBUS_PIN_DPB; 2746 break; 2747 case PORT_C: 2748 ddc_pin = GMBUS_PIN_DPC; 2749 break; 2750 case PORT_D: 2751 ddc_pin = GMBUS_PIN_DPD_CHV; 2752 break; 2753 default: 2754 MISSING_CASE(port); 2755 ddc_pin = GMBUS_PIN_DPB; 2756 break; 2757 } 2758 return ddc_pin; 2759 } 2760 2761 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2762 { 2763 enum port port = encoder->port; 2764 u8 ddc_pin; 2765 2766 switch (port) { 2767 case PORT_B: 2768 ddc_pin = GMBUS_PIN_1_BXT; 2769 break; 2770 case PORT_C: 2771 ddc_pin = GMBUS_PIN_2_BXT; 2772 break; 2773 default: 2774 MISSING_CASE(port); 2775 ddc_pin = GMBUS_PIN_1_BXT; 2776 break; 2777 } 2778 return ddc_pin; 2779 } 2780 2781 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2782 { 2783 enum port port = encoder->port; 2784 u8 ddc_pin; 2785 2786 switch (port) { 2787 case PORT_B: 2788 ddc_pin = GMBUS_PIN_1_BXT; 2789 break; 2790 case PORT_C: 2791 ddc_pin = GMBUS_PIN_2_BXT; 2792 break; 2793 case PORT_D: 2794 ddc_pin = GMBUS_PIN_4_CNP; 2795 break; 2796 case PORT_F: 2797 ddc_pin = GMBUS_PIN_3_BXT; 2798 break; 2799 default: 2800 MISSING_CASE(port); 2801 ddc_pin = GMBUS_PIN_1_BXT; 2802 break; 2803 } 2804 return ddc_pin; 2805 } 2806 2807 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2808 { 2809 struct intel_display *display = to_intel_display(encoder); 2810 enum port port = encoder->port; 2811 2812 if (intel_encoder_is_combo(encoder)) 2813 return GMBUS_PIN_1_BXT + port; 2814 else if (intel_encoder_is_tc(encoder)) 2815 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2816 2817 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2818 return GMBUS_PIN_2_BXT; 2819 } 2820 2821 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2822 { 2823 enum phy phy = intel_encoder_to_phy(encoder); 2824 u8 ddc_pin; 2825 2826 switch (phy) { 2827 case PHY_A: 2828 ddc_pin = GMBUS_PIN_1_BXT; 2829 break; 2830 case PHY_B: 2831 ddc_pin = GMBUS_PIN_2_BXT; 2832 break; 2833 case PHY_C: 2834 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2835 break; 2836 default: 2837 MISSING_CASE(phy); 2838 ddc_pin = GMBUS_PIN_1_BXT; 2839 break; 2840 } 2841 return ddc_pin; 2842 } 2843 2844 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2845 { 2846 struct intel_display *display = to_intel_display(encoder); 2847 enum phy phy = intel_encoder_to_phy(encoder); 2848 2849 WARN_ON(encoder->port == PORT_C); 2850 2851 /* 2852 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2853 * final two outputs use type-c pins, even though they're actually 2854 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2855 * all outputs. 2856 */ 2857 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2858 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2859 2860 return GMBUS_PIN_1_BXT + phy; 2861 } 2862 2863 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2864 { 2865 struct intel_display *display = to_intel_display(encoder); 2866 enum phy phy = intel_encoder_to_phy(encoder); 2867 2868 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2869 2870 /* 2871 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2872 * final two outputs use type-c pins, even though they're actually 2873 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2874 * all outputs. 2875 */ 2876 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2877 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2878 2879 return GMBUS_PIN_1_BXT + phy; 2880 } 2881 2882 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2883 { 2884 return intel_encoder_to_phy(encoder) + 1; 2885 } 2886 2887 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2888 { 2889 enum phy phy = intel_encoder_to_phy(encoder); 2890 2891 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2892 2893 /* 2894 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2895 * except first combo output. 2896 */ 2897 if (phy == PHY_A) 2898 return GMBUS_PIN_1_BXT; 2899 2900 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2901 } 2902 2903 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2904 { 2905 enum port port = encoder->port; 2906 u8 ddc_pin; 2907 2908 switch (port) { 2909 case PORT_B: 2910 ddc_pin = GMBUS_PIN_DPB; 2911 break; 2912 case PORT_C: 2913 ddc_pin = GMBUS_PIN_DPC; 2914 break; 2915 case PORT_D: 2916 ddc_pin = GMBUS_PIN_DPD; 2917 break; 2918 default: 2919 MISSING_CASE(port); 2920 ddc_pin = GMBUS_PIN_DPB; 2921 break; 2922 } 2923 return ddc_pin; 2924 } 2925 2926 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2927 { 2928 struct intel_display *display = to_intel_display(encoder); 2929 u8 ddc_pin; 2930 2931 if (display->platform.alderlake_s) 2932 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2933 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 2934 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2935 else if (display->platform.rocketlake) 2936 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2937 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display)) 2938 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2939 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 2940 HAS_PCH_TGP(display)) 2941 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2942 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2943 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2944 else if (HAS_PCH_CNP(display)) 2945 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2946 else if (display->platform.geminilake || display->platform.broxton) 2947 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2948 else if (display->platform.cherryview) 2949 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2950 else 2951 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2952 2953 return ddc_pin; 2954 } 2955 2956 static struct intel_encoder * 2957 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2958 { 2959 struct intel_display *display = to_intel_display(encoder); 2960 struct intel_encoder *other; 2961 2962 for_each_intel_encoder(display->drm, other) { 2963 struct intel_connector *connector; 2964 2965 if (other == encoder) 2966 continue; 2967 2968 if (!intel_encoder_is_dig_port(other)) 2969 continue; 2970 2971 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2972 2973 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) 2974 return other; 2975 } 2976 2977 return NULL; 2978 } 2979 2980 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2981 { 2982 struct intel_display *display = to_intel_display(encoder); 2983 struct intel_encoder *other; 2984 const char *source; 2985 u8 ddc_pin; 2986 2987 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2988 source = "VBT"; 2989 2990 if (!ddc_pin) { 2991 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2992 source = "platform default"; 2993 } 2994 2995 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { 2996 drm_dbg_kms(display->drm, 2997 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2998 encoder->base.base.id, encoder->base.name, ddc_pin); 2999 return 0; 3000 } 3001 3002 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 3003 if (other) { 3004 drm_dbg_kms(display->drm, 3005 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 3006 encoder->base.base.id, encoder->base.name, ddc_pin, 3007 other->base.base.id, other->base.name); 3008 return 0; 3009 } 3010 3011 drm_dbg_kms(display->drm, 3012 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 3013 encoder->base.base.id, encoder->base.name, 3014 ddc_pin, source); 3015 3016 return ddc_pin; 3017 } 3018 3019 void intel_infoframe_init(struct intel_digital_port *dig_port) 3020 { 3021 struct intel_display *display = to_intel_display(dig_port); 3022 3023 if (display->platform.valleyview || display->platform.cherryview) { 3024 dig_port->write_infoframe = vlv_write_infoframe; 3025 dig_port->read_infoframe = vlv_read_infoframe; 3026 dig_port->set_infoframes = vlv_set_infoframes; 3027 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3028 } else if (display->platform.g4x) { 3029 dig_port->write_infoframe = g4x_write_infoframe; 3030 dig_port->read_infoframe = g4x_read_infoframe; 3031 dig_port->set_infoframes = g4x_set_infoframes; 3032 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3033 } else if (HAS_DDI(display)) { 3034 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 3035 dig_port->write_infoframe = lspcon_write_infoframe; 3036 dig_port->read_infoframe = lspcon_read_infoframe; 3037 dig_port->set_infoframes = lspcon_set_infoframes; 3038 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3039 } else { 3040 dig_port->write_infoframe = hsw_write_infoframe; 3041 dig_port->read_infoframe = hsw_read_infoframe; 3042 dig_port->set_infoframes = hsw_set_infoframes; 3043 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3044 } 3045 } else if (HAS_PCH_IBX(display)) { 3046 dig_port->write_infoframe = ibx_write_infoframe; 3047 dig_port->read_infoframe = ibx_read_infoframe; 3048 dig_port->set_infoframes = ibx_set_infoframes; 3049 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3050 } else { 3051 dig_port->write_infoframe = cpt_write_infoframe; 3052 dig_port->read_infoframe = cpt_read_infoframe; 3053 dig_port->set_infoframes = cpt_set_infoframes; 3054 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3055 } 3056 } 3057 3058 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3059 struct intel_connector *intel_connector) 3060 { 3061 struct intel_display *display = to_intel_display(dig_port); 3062 struct drm_connector *connector = &intel_connector->base; 3063 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3064 struct intel_encoder *intel_encoder = &dig_port->base; 3065 struct drm_device *dev = intel_encoder->base.dev; 3066 enum port port = intel_encoder->port; 3067 struct cec_connector_info conn_info; 3068 u8 ddc_pin; 3069 3070 drm_dbg_kms(display->drm, 3071 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3072 intel_encoder->base.base.id, intel_encoder->base.name); 3073 3074 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3075 return false; 3076 3077 if (drm_WARN(dev, dig_port->max_lanes < 4, 3078 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3079 dig_port->max_lanes, intel_encoder->base.base.id, 3080 intel_encoder->base.name)) 3081 return false; 3082 3083 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3084 if (!ddc_pin) 3085 return false; 3086 3087 drm_connector_init_with_ddc(dev, connector, 3088 &intel_hdmi_connector_funcs, 3089 DRM_MODE_CONNECTOR_HDMIA, 3090 intel_gmbus_get_adapter(display, ddc_pin)); 3091 3092 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3093 3094 if (DISPLAY_VER(display) < 12) 3095 connector->interlace_allowed = true; 3096 3097 connector->stereo_allowed = true; 3098 3099 if (DISPLAY_VER(display) >= 10) 3100 connector->ycbcr_420_allowed = true; 3101 3102 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3103 intel_connector->base.polled = intel_connector->polled; 3104 3105 if (HAS_DDI(display)) 3106 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3107 else 3108 intel_connector->get_hw_state = intel_connector_get_hw_state; 3109 3110 intel_hdmi_add_properties(intel_hdmi, connector); 3111 3112 intel_connector_attach_encoder(intel_connector, intel_encoder); 3113 intel_hdmi->attached_connector = intel_connector; 3114 3115 if (is_hdcp_supported(display, port)) { 3116 int ret = intel_hdcp_init(intel_connector, dig_port, 3117 &intel_hdmi_hdcp_shim); 3118 if (ret) 3119 drm_dbg_kms(display->drm, 3120 "HDCP init failed, skipping.\n"); 3121 } 3122 3123 cec_fill_conn_info_from_drm(&conn_info, connector); 3124 3125 intel_hdmi->cec_notifier = 3126 cec_notifier_conn_register(dev->dev, port_identifier(port), 3127 &conn_info); 3128 if (!intel_hdmi->cec_notifier) 3129 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3130 3131 return true; 3132 } 3133 3134 /* 3135 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3136 * @vactive: Vactive of a display mode 3137 * 3138 * @return: appropriate dsc slice height for a given mode. 3139 */ 3140 int intel_hdmi_dsc_get_slice_height(int vactive) 3141 { 3142 int slice_height; 3143 3144 /* 3145 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3146 * Select smallest slice height >=96, that results in a valid PPS and 3147 * requires minimum padding lines required for final slice. 3148 * 3149 * Assumption : Vactive is even. 3150 */ 3151 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3152 if (vactive % slice_height == 0) 3153 return slice_height; 3154 3155 return 0; 3156 } 3157 3158 /* 3159 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3160 * and dsc decoder capabilities 3161 * 3162 * @crtc_state: intel crtc_state 3163 * @src_max_slices: maximum slices supported by the DSC encoder 3164 * @src_max_slice_width: maximum slice width supported by DSC encoder 3165 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3166 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3167 * 3168 * @return: num of dsc slices that can be supported by the dsc encoder 3169 * and decoder. 3170 */ 3171 int 3172 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3173 int src_max_slices, int src_max_slice_width, 3174 int hdmi_max_slices, int hdmi_throughput) 3175 { 3176 /* Pixel rates in KPixels/sec */ 3177 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3178 /* 3179 * Rates at which the source and sink are required to process pixels in each 3180 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3181 */ 3182 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3183 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3184 3185 /* Spec limits the slice width to 2720 pixels */ 3186 #define MAX_HDMI_SLICE_WIDTH 2720 3187 int kslice_adjust; 3188 int adjusted_clk_khz; 3189 int min_slices; 3190 int target_slices; 3191 int max_throughput; /* max clock freq. in khz per slice */ 3192 int max_slice_width; 3193 int slice_width; 3194 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3195 3196 if (!hdmi_throughput) 3197 return 0; 3198 3199 /* 3200 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3201 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3202 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3203 * dividing adjusted clock value by 10. 3204 */ 3205 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3206 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3207 kslice_adjust = 10; 3208 else 3209 kslice_adjust = 5; 3210 3211 /* 3212 * As per spec, the rate at which the source and the sink process 3213 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3214 * This depends upon the pixel clock rate and output formats 3215 * (kslice adjust). 3216 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3217 * at max 340MHz, otherwise they can be processed at max 400MHz. 3218 */ 3219 3220 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3221 3222 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3223 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3224 else 3225 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3226 3227 /* 3228 * Taking into account the sink's capability for maximum 3229 * clock per slice (in MHz) as read from HF-VSDB. 3230 */ 3231 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3232 3233 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3234 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3235 3236 /* 3237 * Keep on increasing the num of slices/line, starting from min_slices 3238 * per line till we get such a number, for which the slice_width is 3239 * just less than max_slice_width. The slices/line selected should be 3240 * less than or equal to the max horizontal slices that the combination 3241 * of PCON encoder and HDMI decoder can support. 3242 */ 3243 slice_width = max_slice_width; 3244 3245 do { 3246 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3247 target_slices = 1; 3248 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3249 target_slices = 2; 3250 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3251 target_slices = 4; 3252 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3253 target_slices = 8; 3254 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3255 target_slices = 12; 3256 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3257 target_slices = 16; 3258 else 3259 return 0; 3260 3261 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3262 if (slice_width >= max_slice_width) 3263 min_slices = target_slices + 1; 3264 } while (slice_width >= max_slice_width); 3265 3266 return target_slices; 3267 } 3268 3269 /* 3270 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3271 * source and sink capabilities. 3272 * 3273 * @src_fraction_bpp: fractional bpp supported by the source 3274 * @slice_width: dsc slice width supported by the source and sink 3275 * @num_slices: num of slices supported by the source and sink 3276 * @output_format: video output format 3277 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3278 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3279 * 3280 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3281 */ 3282 int 3283 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3284 int output_format, bool hdmi_all_bpp, 3285 int hdmi_max_chunk_bytes) 3286 { 3287 int max_dsc_bpp, min_dsc_bpp; 3288 int target_bytes; 3289 bool bpp_found = false; 3290 int bpp_decrement_x16; 3291 int bpp_target; 3292 int bpp_target_x16; 3293 3294 /* 3295 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3296 * Start with the max bpp and keep on decrementing with 3297 * fractional bpp, if supported by PCON DSC encoder 3298 * 3299 * for each bpp we check if no of bytes can be supported by HDMI sink 3300 */ 3301 3302 /* Assuming: bpc as 8*/ 3303 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3304 min_dsc_bpp = 6; 3305 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3306 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3307 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3308 min_dsc_bpp = 8; 3309 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3310 } else { 3311 /* Assuming 4:2:2 encoding */ 3312 min_dsc_bpp = 7; 3313 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3314 } 3315 3316 /* 3317 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3318 * Section 7.7.34 : Source shall not enable compressed Video 3319 * Transport with bpp_target settings above 12 bpp unless 3320 * DSC_all_bpp is set to 1. 3321 */ 3322 if (!hdmi_all_bpp) 3323 max_dsc_bpp = min(max_dsc_bpp, 12); 3324 3325 /* 3326 * The Sink has a limit of compressed data in bytes for a scanline, 3327 * as described in max_chunk_bytes field in HFVSDB block of edid. 3328 * The no. of bytes depend on the target bits per pixel that the 3329 * source configures. So we start with the max_bpp and calculate 3330 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3331 * till we get the target_chunk_bytes just less than what the sink's 3332 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3333 * 3334 * The decrement is according to the fractional support from PCON DSC 3335 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3336 * 3337 * bpp_target_x16 = bpp_target * 16 3338 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3339 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3340 */ 3341 3342 bpp_target = max_dsc_bpp; 3343 3344 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3345 if (!src_fractional_bpp) 3346 src_fractional_bpp = 1; 3347 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3348 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3349 3350 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3351 int bpp; 3352 3353 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3354 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3355 if (target_bytes <= hdmi_max_chunk_bytes) { 3356 bpp_found = true; 3357 break; 3358 } 3359 bpp_target_x16 -= bpp_decrement_x16; 3360 } 3361 if (bpp_found) 3362 return bpp_target_x16; 3363 3364 return 0; 3365 } 3366