1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/intel_lpe_audio.h> 42 43 #include "g4x_hdmi.h" 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_atomic.h" 47 #include "intel_audio.h" 48 #include "intel_connector.h" 49 #include "intel_cx0_phy.h" 50 #include "intel_ddi.h" 51 #include "intel_de.h" 52 #include "intel_display_driver.h" 53 #include "intel_display_types.h" 54 #include "intel_dp.h" 55 #include "intel_gmbus.h" 56 #include "intel_hdcp.h" 57 #include "intel_hdcp_regs.h" 58 #include "intel_hdmi.h" 59 #include "intel_lspcon.h" 60 #include "intel_panel.h" 61 #include "intel_snps_phy.h" 62 63 inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi) 64 { 65 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); 66 } 67 68 static void 69 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 70 { 71 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi); 72 u32 enabled_bits; 73 74 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 75 76 drm_WARN(&dev_priv->drm, 77 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 78 "HDMI port enabled, expecting disabled\n"); 79 } 80 81 static void 82 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 83 enum transcoder cpu_transcoder) 84 { 85 drm_WARN(&dev_priv->drm, 86 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 87 TRANS_DDI_FUNC_ENABLE, 88 "HDMI transcoder function enabled, expecting disabled\n"); 89 } 90 91 static u32 g4x_infoframe_index(unsigned int type) 92 { 93 switch (type) { 94 case HDMI_PACKET_TYPE_GAMUT_METADATA: 95 return VIDEO_DIP_SELECT_GAMUT; 96 case HDMI_INFOFRAME_TYPE_AVI: 97 return VIDEO_DIP_SELECT_AVI; 98 case HDMI_INFOFRAME_TYPE_SPD: 99 return VIDEO_DIP_SELECT_SPD; 100 case HDMI_INFOFRAME_TYPE_VENDOR: 101 return VIDEO_DIP_SELECT_VENDOR; 102 default: 103 MISSING_CASE(type); 104 return 0; 105 } 106 } 107 108 static u32 g4x_infoframe_enable(unsigned int type) 109 { 110 switch (type) { 111 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 112 return VIDEO_DIP_ENABLE_GCP; 113 case HDMI_PACKET_TYPE_GAMUT_METADATA: 114 return VIDEO_DIP_ENABLE_GAMUT; 115 case DP_SDP_VSC: 116 return 0; 117 case DP_SDP_ADAPTIVE_SYNC: 118 return 0; 119 case HDMI_INFOFRAME_TYPE_AVI: 120 return VIDEO_DIP_ENABLE_AVI; 121 case HDMI_INFOFRAME_TYPE_SPD: 122 return VIDEO_DIP_ENABLE_SPD; 123 case HDMI_INFOFRAME_TYPE_VENDOR: 124 return VIDEO_DIP_ENABLE_VENDOR; 125 case HDMI_INFOFRAME_TYPE_DRM: 126 return 0; 127 default: 128 MISSING_CASE(type); 129 return 0; 130 } 131 } 132 133 static u32 hsw_infoframe_enable(unsigned int type) 134 { 135 switch (type) { 136 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 137 return VIDEO_DIP_ENABLE_GCP_HSW; 138 case HDMI_PACKET_TYPE_GAMUT_METADATA: 139 return VIDEO_DIP_ENABLE_GMP_HSW; 140 case DP_SDP_VSC: 141 return VIDEO_DIP_ENABLE_VSC_HSW; 142 case DP_SDP_ADAPTIVE_SYNC: 143 return VIDEO_DIP_ENABLE_AS_ADL; 144 case DP_SDP_PPS: 145 return VDIP_ENABLE_PPS; 146 case HDMI_INFOFRAME_TYPE_AVI: 147 return VIDEO_DIP_ENABLE_AVI_HSW; 148 case HDMI_INFOFRAME_TYPE_SPD: 149 return VIDEO_DIP_ENABLE_SPD_HSW; 150 case HDMI_INFOFRAME_TYPE_VENDOR: 151 return VIDEO_DIP_ENABLE_VS_HSW; 152 case HDMI_INFOFRAME_TYPE_DRM: 153 return VIDEO_DIP_ENABLE_DRM_GLK; 154 default: 155 MISSING_CASE(type); 156 return 0; 157 } 158 } 159 160 static i915_reg_t 161 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 162 enum transcoder cpu_transcoder, 163 unsigned int type, 164 int i) 165 { 166 switch (type) { 167 case HDMI_PACKET_TYPE_GAMUT_METADATA: 168 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 169 case DP_SDP_VSC: 170 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 171 case DP_SDP_ADAPTIVE_SYNC: 172 return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); 173 case DP_SDP_PPS: 174 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 175 case HDMI_INFOFRAME_TYPE_AVI: 176 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 177 case HDMI_INFOFRAME_TYPE_SPD: 178 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 179 case HDMI_INFOFRAME_TYPE_VENDOR: 180 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 181 case HDMI_INFOFRAME_TYPE_DRM: 182 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 183 default: 184 MISSING_CASE(type); 185 return INVALID_MMIO_REG; 186 } 187 } 188 189 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 190 unsigned int type) 191 { 192 switch (type) { 193 case DP_SDP_VSC: 194 return VIDEO_DIP_VSC_DATA_SIZE; 195 case DP_SDP_ADAPTIVE_SYNC: 196 return VIDEO_DIP_ASYNC_DATA_SIZE; 197 case DP_SDP_PPS: 198 return VIDEO_DIP_PPS_DATA_SIZE; 199 case HDMI_PACKET_TYPE_GAMUT_METADATA: 200 if (DISPLAY_VER(dev_priv) >= 11) 201 return VIDEO_DIP_GMP_DATA_SIZE; 202 else 203 return VIDEO_DIP_DATA_SIZE; 204 default: 205 return VIDEO_DIP_DATA_SIZE; 206 } 207 } 208 209 static void g4x_write_infoframe(struct intel_encoder *encoder, 210 const struct intel_crtc_state *crtc_state, 211 unsigned int type, 212 const void *frame, ssize_t len) 213 { 214 const u32 *data = frame; 215 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 216 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 217 int i; 218 219 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 220 "Writing DIP with CTL reg disabled\n"); 221 222 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 223 val |= g4x_infoframe_index(type); 224 225 val &= ~g4x_infoframe_enable(type); 226 227 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 228 229 for (i = 0; i < len; i += 4) { 230 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 231 data++; 232 } 233 /* Write every possible data byte to force correct ECC calculation. */ 234 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 235 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 236 237 val |= g4x_infoframe_enable(type); 238 val &= ~VIDEO_DIP_FREQ_MASK; 239 val |= VIDEO_DIP_FREQ_VSYNC; 240 241 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 242 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 243 } 244 245 static void g4x_read_infoframe(struct intel_encoder *encoder, 246 const struct intel_crtc_state *crtc_state, 247 unsigned int type, 248 void *frame, ssize_t len) 249 { 250 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 251 u32 *data = frame; 252 int i; 253 254 intel_de_rmw(dev_priv, VIDEO_DIP_CTL, 255 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 256 257 for (i = 0; i < len; i += 4) 258 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 259 } 260 261 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 262 const struct intel_crtc_state *pipe_config) 263 { 264 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 265 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 266 267 if ((val & VIDEO_DIP_ENABLE) == 0) 268 return 0; 269 270 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 271 return 0; 272 273 return val & (VIDEO_DIP_ENABLE_AVI | 274 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 275 } 276 277 static void ibx_write_infoframe(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state, 279 unsigned int type, 280 const void *frame, ssize_t len) 281 { 282 const u32 *data = frame; 283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 284 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 285 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 286 u32 val = intel_de_read(dev_priv, reg); 287 int i; 288 289 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 290 "Writing DIP with CTL reg disabled\n"); 291 292 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 293 val |= g4x_infoframe_index(type); 294 295 val &= ~g4x_infoframe_enable(type); 296 297 intel_de_write(dev_priv, reg, val); 298 299 for (i = 0; i < len; i += 4) { 300 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 301 *data); 302 data++; 303 } 304 /* Write every possible data byte to force correct ECC calculation. */ 305 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 306 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 307 308 val |= g4x_infoframe_enable(type); 309 val &= ~VIDEO_DIP_FREQ_MASK; 310 val |= VIDEO_DIP_FREQ_VSYNC; 311 312 intel_de_write(dev_priv, reg, val); 313 intel_de_posting_read(dev_priv, reg); 314 } 315 316 static void ibx_read_infoframe(struct intel_encoder *encoder, 317 const struct intel_crtc_state *crtc_state, 318 unsigned int type, 319 void *frame, ssize_t len) 320 { 321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 322 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 323 u32 *data = frame; 324 int i; 325 326 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 327 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 328 329 for (i = 0; i < len; i += 4) 330 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 331 } 332 333 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 334 const struct intel_crtc_state *pipe_config) 335 { 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 337 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 338 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 339 u32 val = intel_de_read(dev_priv, reg); 340 341 if ((val & VIDEO_DIP_ENABLE) == 0) 342 return 0; 343 344 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 345 return 0; 346 347 return val & (VIDEO_DIP_ENABLE_AVI | 348 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 349 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 350 } 351 352 static void cpt_write_infoframe(struct intel_encoder *encoder, 353 const struct intel_crtc_state *crtc_state, 354 unsigned int type, 355 const void *frame, ssize_t len) 356 { 357 const u32 *data = frame; 358 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 359 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 360 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 361 u32 val = intel_de_read(dev_priv, reg); 362 int i; 363 364 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 365 "Writing DIP with CTL reg disabled\n"); 366 367 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 368 val |= g4x_infoframe_index(type); 369 370 /* The DIP control register spec says that we need to update the AVI 371 * infoframe without clearing its enable bit */ 372 if (type != HDMI_INFOFRAME_TYPE_AVI) 373 val &= ~g4x_infoframe_enable(type); 374 375 intel_de_write(dev_priv, reg, val); 376 377 for (i = 0; i < len; i += 4) { 378 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 379 *data); 380 data++; 381 } 382 /* Write every possible data byte to force correct ECC calculation. */ 383 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 384 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 385 386 val |= g4x_infoframe_enable(type); 387 val &= ~VIDEO_DIP_FREQ_MASK; 388 val |= VIDEO_DIP_FREQ_VSYNC; 389 390 intel_de_write(dev_priv, reg, val); 391 intel_de_posting_read(dev_priv, reg); 392 } 393 394 static void cpt_read_infoframe(struct intel_encoder *encoder, 395 const struct intel_crtc_state *crtc_state, 396 unsigned int type, 397 void *frame, ssize_t len) 398 { 399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 400 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 401 u32 *data = frame; 402 int i; 403 404 intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), 405 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 406 407 for (i = 0; i < len; i += 4) 408 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 409 } 410 411 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 412 const struct intel_crtc_state *pipe_config) 413 { 414 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 415 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 416 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 417 418 if ((val & VIDEO_DIP_ENABLE) == 0) 419 return 0; 420 421 return val & (VIDEO_DIP_ENABLE_AVI | 422 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 423 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 424 } 425 426 static void vlv_write_infoframe(struct intel_encoder *encoder, 427 const struct intel_crtc_state *crtc_state, 428 unsigned int type, 429 const void *frame, ssize_t len) 430 { 431 const u32 *data = frame; 432 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 433 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 434 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 435 u32 val = intel_de_read(dev_priv, reg); 436 int i; 437 438 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 439 "Writing DIP with CTL reg disabled\n"); 440 441 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 442 val |= g4x_infoframe_index(type); 443 444 val &= ~g4x_infoframe_enable(type); 445 446 intel_de_write(dev_priv, reg, val); 447 448 for (i = 0; i < len; i += 4) { 449 intel_de_write(dev_priv, 450 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 451 data++; 452 } 453 /* Write every possible data byte to force correct ECC calculation. */ 454 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 455 intel_de_write(dev_priv, 456 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 457 458 val |= g4x_infoframe_enable(type); 459 val &= ~VIDEO_DIP_FREQ_MASK; 460 val |= VIDEO_DIP_FREQ_VSYNC; 461 462 intel_de_write(dev_priv, reg, val); 463 intel_de_posting_read(dev_priv, reg); 464 } 465 466 static void vlv_read_infoframe(struct intel_encoder *encoder, 467 const struct intel_crtc_state *crtc_state, 468 unsigned int type, 469 void *frame, ssize_t len) 470 { 471 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 472 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 473 u32 *data = frame; 474 int i; 475 476 intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), 477 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 478 479 for (i = 0; i < len; i += 4) 480 *data++ = intel_de_read(dev_priv, 481 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 482 } 483 484 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 485 const struct intel_crtc_state *pipe_config) 486 { 487 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 488 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 489 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 490 491 if ((val & VIDEO_DIP_ENABLE) == 0) 492 return 0; 493 494 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 495 return 0; 496 497 return val & (VIDEO_DIP_ENABLE_AVI | 498 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 499 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 500 } 501 502 void hsw_write_infoframe(struct intel_encoder *encoder, 503 const struct intel_crtc_state *crtc_state, 504 unsigned int type, 505 const void *frame, ssize_t len) 506 { 507 const u32 *data = frame; 508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 509 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 510 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 511 int data_size; 512 int i; 513 u32 val = intel_de_read(dev_priv, ctl_reg); 514 515 data_size = hsw_dip_data_size(dev_priv, type); 516 517 drm_WARN_ON(&dev_priv->drm, len > data_size); 518 519 val &= ~hsw_infoframe_enable(type); 520 intel_de_write(dev_priv, ctl_reg, val); 521 522 for (i = 0; i < len; i += 4) { 523 intel_de_write(dev_priv, 524 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 525 *data); 526 data++; 527 } 528 /* Write every possible data byte to force correct ECC calculation. */ 529 for (; i < data_size; i += 4) 530 intel_de_write(dev_priv, 531 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 532 0); 533 534 /* Wa_14013475917 */ 535 if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)) 536 val |= hsw_infoframe_enable(type); 537 538 if (type == DP_SDP_VSC) 539 val |= VSC_DIP_HW_DATA_SW_HEA; 540 541 intel_de_write(dev_priv, ctl_reg, val); 542 intel_de_posting_read(dev_priv, ctl_reg); 543 } 544 545 void hsw_read_infoframe(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state, 547 unsigned int type, void *frame, ssize_t len) 548 { 549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 u32 *data = frame; 552 int i; 553 554 for (i = 0; i < len; i += 4) 555 *data++ = intel_de_read(dev_priv, 556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 557 } 558 559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 560 const struct intel_crtc_state *pipe_config) 561 { 562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 563 u32 val = intel_de_read(dev_priv, 564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 565 u32 mask; 566 567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 570 571 if (DISPLAY_VER(dev_priv) >= 10) 572 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 573 574 if (HAS_AS_SDP(dev_priv)) 575 mask |= VIDEO_DIP_ENABLE_AS_ADL; 576 577 return val & mask; 578 } 579 580 static const u8 infoframe_type_to_idx[] = { 581 HDMI_PACKET_TYPE_GENERAL_CONTROL, 582 HDMI_PACKET_TYPE_GAMUT_METADATA, 583 DP_SDP_VSC, 584 DP_SDP_ADAPTIVE_SYNC, 585 HDMI_INFOFRAME_TYPE_AVI, 586 HDMI_INFOFRAME_TYPE_SPD, 587 HDMI_INFOFRAME_TYPE_VENDOR, 588 HDMI_INFOFRAME_TYPE_DRM, 589 }; 590 591 u32 intel_hdmi_infoframe_enable(unsigned int type) 592 { 593 int i; 594 595 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 596 if (infoframe_type_to_idx[i] == type) 597 return BIT(i); 598 } 599 600 return 0; 601 } 602 603 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 604 const struct intel_crtc_state *crtc_state) 605 { 606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 607 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 608 u32 val, ret = 0; 609 int i; 610 611 val = dig_port->infoframes_enabled(encoder, crtc_state); 612 613 /* map from hardware bits to dip idx */ 614 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 615 unsigned int type = infoframe_type_to_idx[i]; 616 617 if (HAS_DDI(dev_priv)) { 618 if (val & hsw_infoframe_enable(type)) 619 ret |= BIT(i); 620 } else { 621 if (val & g4x_infoframe_enable(type)) 622 ret |= BIT(i); 623 } 624 } 625 626 return ret; 627 } 628 629 /* 630 * The data we write to the DIP data buffer registers is 1 byte bigger than the 631 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 632 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 633 * used for both technologies. 634 * 635 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 636 * DW1: DB3 | DB2 | DB1 | DB0 637 * DW2: DB7 | DB6 | DB5 | DB4 638 * DW3: ... 639 * 640 * (HB is Header Byte, DB is Data Byte) 641 * 642 * The hdmi pack() functions don't know about that hardware specific hole so we 643 * trick them by giving an offset into the buffer and moving back the header 644 * bytes by one. 645 */ 646 static void intel_write_infoframe(struct intel_encoder *encoder, 647 const struct intel_crtc_state *crtc_state, 648 enum hdmi_infoframe_type type, 649 const union hdmi_infoframe *frame) 650 { 651 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 652 u8 buffer[VIDEO_DIP_DATA_SIZE]; 653 ssize_t len; 654 655 if ((crtc_state->infoframes.enable & 656 intel_hdmi_infoframe_enable(type)) == 0) 657 return; 658 659 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 660 return; 661 662 /* see comment above for the reason for this offset */ 663 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 664 if (drm_WARN_ON(encoder->base.dev, len < 0)) 665 return; 666 667 /* Insert the 'hole' (see big comment above) at position 3 */ 668 memmove(&buffer[0], &buffer[1], 3); 669 buffer[3] = 0; 670 len++; 671 672 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 673 } 674 675 void intel_read_infoframe(struct intel_encoder *encoder, 676 const struct intel_crtc_state *crtc_state, 677 enum hdmi_infoframe_type type, 678 union hdmi_infoframe *frame) 679 { 680 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 681 u8 buffer[VIDEO_DIP_DATA_SIZE]; 682 int ret; 683 684 if ((crtc_state->infoframes.enable & 685 intel_hdmi_infoframe_enable(type)) == 0) 686 return; 687 688 dig_port->read_infoframe(encoder, crtc_state, 689 type, buffer, sizeof(buffer)); 690 691 /* Fill the 'hole' (see big comment above) at position 3 */ 692 memmove(&buffer[1], &buffer[0], 3); 693 694 /* see comment above for the reason for this offset */ 695 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 696 if (ret) { 697 drm_dbg_kms(encoder->base.dev, 698 "Failed to unpack infoframe type 0x%02x\n", type); 699 return; 700 } 701 702 if (frame->any.type != type) 703 drm_dbg_kms(encoder->base.dev, 704 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 705 frame->any.type, type); 706 } 707 708 static bool 709 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 710 struct intel_crtc_state *crtc_state, 711 struct drm_connector_state *conn_state) 712 { 713 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 714 const struct drm_display_mode *adjusted_mode = 715 &crtc_state->hw.adjusted_mode; 716 struct drm_connector *connector = conn_state->connector; 717 int ret; 718 719 if (!crtc_state->has_infoframe) 720 return true; 721 722 crtc_state->infoframes.enable |= 723 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 724 725 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 726 adjusted_mode); 727 if (ret) 728 return false; 729 730 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 731 frame->colorspace = HDMI_COLORSPACE_YUV420; 732 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 733 frame->colorspace = HDMI_COLORSPACE_YUV444; 734 else 735 frame->colorspace = HDMI_COLORSPACE_RGB; 736 737 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 738 739 /* nonsense combination */ 740 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 741 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 742 743 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 744 drm_hdmi_avi_infoframe_quant_range(frame, connector, 745 adjusted_mode, 746 crtc_state->limited_color_range ? 747 HDMI_QUANTIZATION_RANGE_LIMITED : 748 HDMI_QUANTIZATION_RANGE_FULL); 749 } else { 750 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 751 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 752 } 753 754 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 755 756 /* TODO: handle pixel repetition for YCBCR420 outputs */ 757 758 ret = hdmi_avi_infoframe_check(frame); 759 if (drm_WARN_ON(encoder->base.dev, ret)) 760 return false; 761 762 return true; 763 } 764 765 static bool 766 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 767 struct intel_crtc_state *crtc_state, 768 struct drm_connector_state *conn_state) 769 { 770 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 771 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 772 int ret; 773 774 if (!crtc_state->has_infoframe) 775 return true; 776 777 crtc_state->infoframes.enable |= 778 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 779 780 if (IS_DGFX(i915)) 781 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 782 else 783 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 784 785 if (drm_WARN_ON(encoder->base.dev, ret)) 786 return false; 787 788 frame->sdi = HDMI_SPD_SDI_PC; 789 790 ret = hdmi_spd_infoframe_check(frame); 791 if (drm_WARN_ON(encoder->base.dev, ret)) 792 return false; 793 794 return true; 795 } 796 797 static bool 798 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 799 struct intel_crtc_state *crtc_state, 800 struct drm_connector_state *conn_state) 801 { 802 struct hdmi_vendor_infoframe *frame = 803 &crtc_state->infoframes.hdmi.vendor.hdmi; 804 const struct drm_display_info *info = 805 &conn_state->connector->display_info; 806 int ret; 807 808 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 809 return true; 810 811 crtc_state->infoframes.enable |= 812 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 813 814 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 815 conn_state->connector, 816 &crtc_state->hw.adjusted_mode); 817 if (drm_WARN_ON(encoder->base.dev, ret)) 818 return false; 819 820 ret = hdmi_vendor_infoframe_check(frame); 821 if (drm_WARN_ON(encoder->base.dev, ret)) 822 return false; 823 824 return true; 825 } 826 827 static bool 828 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 829 struct intel_crtc_state *crtc_state, 830 struct drm_connector_state *conn_state) 831 { 832 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 833 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 834 int ret; 835 836 if (DISPLAY_VER(dev_priv) < 10) 837 return true; 838 839 if (!crtc_state->has_infoframe) 840 return true; 841 842 if (!conn_state->hdr_output_metadata) 843 return true; 844 845 crtc_state->infoframes.enable |= 846 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 847 848 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 849 if (ret < 0) { 850 drm_dbg_kms(&dev_priv->drm, 851 "couldn't set HDR metadata in infoframe\n"); 852 return false; 853 } 854 855 ret = hdmi_drm_infoframe_check(frame); 856 if (drm_WARN_ON(&dev_priv->drm, ret)) 857 return false; 858 859 return true; 860 } 861 862 static void g4x_set_infoframes(struct intel_encoder *encoder, 863 bool enable, 864 const struct intel_crtc_state *crtc_state, 865 const struct drm_connector_state *conn_state) 866 { 867 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 868 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 869 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 870 i915_reg_t reg = VIDEO_DIP_CTL; 871 u32 val = intel_de_read(dev_priv, reg); 872 u32 port = VIDEO_DIP_PORT(encoder->port); 873 874 assert_hdmi_port_disabled(intel_hdmi); 875 876 /* If the registers were not initialized yet, they might be zeroes, 877 * which means we're selecting the AVI DIP and we're setting its 878 * frequency to once. This seems to really confuse the HW and make 879 * things stop working (the register spec says the AVI always needs to 880 * be sent every VSync). So here we avoid writing to the register more 881 * than we need and also explicitly select the AVI DIP and explicitly 882 * set its frequency to every VSync. Avoiding to write it twice seems to 883 * be enough to solve the problem, but being defensive shouldn't hurt us 884 * either. */ 885 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 886 887 if (!enable) { 888 if (!(val & VIDEO_DIP_ENABLE)) 889 return; 890 if (port != (val & VIDEO_DIP_PORT_MASK)) { 891 drm_dbg_kms(&dev_priv->drm, 892 "video DIP still enabled on port %c\n", 893 (val & VIDEO_DIP_PORT_MASK) >> 29); 894 return; 895 } 896 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 897 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 898 intel_de_write(dev_priv, reg, val); 899 intel_de_posting_read(dev_priv, reg); 900 return; 901 } 902 903 if (port != (val & VIDEO_DIP_PORT_MASK)) { 904 if (val & VIDEO_DIP_ENABLE) { 905 drm_dbg_kms(&dev_priv->drm, 906 "video DIP already enabled on port %c\n", 907 (val & VIDEO_DIP_PORT_MASK) >> 29); 908 return; 909 } 910 val &= ~VIDEO_DIP_PORT_MASK; 911 val |= port; 912 } 913 914 val |= VIDEO_DIP_ENABLE; 915 val &= ~(VIDEO_DIP_ENABLE_AVI | 916 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 917 918 intel_de_write(dev_priv, reg, val); 919 intel_de_posting_read(dev_priv, reg); 920 921 intel_write_infoframe(encoder, crtc_state, 922 HDMI_INFOFRAME_TYPE_AVI, 923 &crtc_state->infoframes.avi); 924 intel_write_infoframe(encoder, crtc_state, 925 HDMI_INFOFRAME_TYPE_SPD, 926 &crtc_state->infoframes.spd); 927 intel_write_infoframe(encoder, crtc_state, 928 HDMI_INFOFRAME_TYPE_VENDOR, 929 &crtc_state->infoframes.hdmi); 930 } 931 932 /* 933 * Determine if default_phase=1 can be indicated in the GCP infoframe. 934 * 935 * From HDMI specification 1.4a: 936 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 937 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 938 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 939 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 940 * phase of 0 941 */ 942 static bool gcp_default_phase_possible(int pipe_bpp, 943 const struct drm_display_mode *mode) 944 { 945 unsigned int pixels_per_group; 946 947 switch (pipe_bpp) { 948 case 30: 949 /* 4 pixels in 5 clocks */ 950 pixels_per_group = 4; 951 break; 952 case 36: 953 /* 2 pixels in 3 clocks */ 954 pixels_per_group = 2; 955 break; 956 case 48: 957 /* 1 pixel in 2 clocks */ 958 pixels_per_group = 1; 959 break; 960 default: 961 /* phase information not relevant for 8bpc */ 962 return false; 963 } 964 965 return mode->crtc_hdisplay % pixels_per_group == 0 && 966 mode->crtc_htotal % pixels_per_group == 0 && 967 mode->crtc_hblank_start % pixels_per_group == 0 && 968 mode->crtc_hblank_end % pixels_per_group == 0 && 969 mode->crtc_hsync_start % pixels_per_group == 0 && 970 mode->crtc_hsync_end % pixels_per_group == 0 && 971 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 972 mode->crtc_htotal/2 % pixels_per_group == 0); 973 } 974 975 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 976 const struct intel_crtc_state *crtc_state, 977 const struct drm_connector_state *conn_state) 978 { 979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 980 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 981 i915_reg_t reg; 982 983 if ((crtc_state->infoframes.enable & 984 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 985 return false; 986 987 if (HAS_DDI(dev_priv)) 988 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 989 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 990 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 991 else if (HAS_PCH_SPLIT(dev_priv)) 992 reg = TVIDEO_DIP_GCP(crtc->pipe); 993 else 994 return false; 995 996 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 997 998 return true; 999 } 1000 1001 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1002 struct intel_crtc_state *crtc_state) 1003 { 1004 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1006 i915_reg_t reg; 1007 1008 if ((crtc_state->infoframes.enable & 1009 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1010 return; 1011 1012 if (HAS_DDI(dev_priv)) 1013 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1014 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1015 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1016 else if (HAS_PCH_SPLIT(dev_priv)) 1017 reg = TVIDEO_DIP_GCP(crtc->pipe); 1018 else 1019 return; 1020 1021 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1022 } 1023 1024 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1025 struct intel_crtc_state *crtc_state, 1026 struct drm_connector_state *conn_state) 1027 { 1028 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1029 1030 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1031 return; 1032 1033 crtc_state->infoframes.enable |= 1034 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1035 1036 /* Indicate color indication for deep color mode */ 1037 if (crtc_state->pipe_bpp > 24) 1038 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1039 1040 /* Enable default_phase whenever the display mode is suitably aligned */ 1041 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1042 &crtc_state->hw.adjusted_mode)) 1043 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1044 } 1045 1046 static void ibx_set_infoframes(struct intel_encoder *encoder, 1047 bool enable, 1048 const struct intel_crtc_state *crtc_state, 1049 const struct drm_connector_state *conn_state) 1050 { 1051 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1052 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1053 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1054 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1055 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1056 u32 val = intel_de_read(dev_priv, reg); 1057 u32 port = VIDEO_DIP_PORT(encoder->port); 1058 1059 assert_hdmi_port_disabled(intel_hdmi); 1060 1061 /* See the big comment in g4x_set_infoframes() */ 1062 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1063 1064 if (!enable) { 1065 if (!(val & VIDEO_DIP_ENABLE)) 1066 return; 1067 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1068 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1069 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1070 intel_de_write(dev_priv, reg, val); 1071 intel_de_posting_read(dev_priv, reg); 1072 return; 1073 } 1074 1075 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1076 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1077 "DIP already enabled on port %c\n", 1078 (val & VIDEO_DIP_PORT_MASK) >> 29); 1079 val &= ~VIDEO_DIP_PORT_MASK; 1080 val |= port; 1081 } 1082 1083 val |= VIDEO_DIP_ENABLE; 1084 val &= ~(VIDEO_DIP_ENABLE_AVI | 1085 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1086 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1087 1088 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1089 val |= VIDEO_DIP_ENABLE_GCP; 1090 1091 intel_de_write(dev_priv, reg, val); 1092 intel_de_posting_read(dev_priv, reg); 1093 1094 intel_write_infoframe(encoder, crtc_state, 1095 HDMI_INFOFRAME_TYPE_AVI, 1096 &crtc_state->infoframes.avi); 1097 intel_write_infoframe(encoder, crtc_state, 1098 HDMI_INFOFRAME_TYPE_SPD, 1099 &crtc_state->infoframes.spd); 1100 intel_write_infoframe(encoder, crtc_state, 1101 HDMI_INFOFRAME_TYPE_VENDOR, 1102 &crtc_state->infoframes.hdmi); 1103 } 1104 1105 static void cpt_set_infoframes(struct intel_encoder *encoder, 1106 bool enable, 1107 const struct intel_crtc_state *crtc_state, 1108 const struct drm_connector_state *conn_state) 1109 { 1110 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1111 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1112 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1113 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1114 u32 val = intel_de_read(dev_priv, reg); 1115 1116 assert_hdmi_port_disabled(intel_hdmi); 1117 1118 /* See the big comment in g4x_set_infoframes() */ 1119 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1120 1121 if (!enable) { 1122 if (!(val & VIDEO_DIP_ENABLE)) 1123 return; 1124 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1125 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1127 intel_de_write(dev_priv, reg, val); 1128 intel_de_posting_read(dev_priv, reg); 1129 return; 1130 } 1131 1132 /* Set both together, unset both together: see the spec. */ 1133 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1134 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1135 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1136 1137 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1138 val |= VIDEO_DIP_ENABLE_GCP; 1139 1140 intel_de_write(dev_priv, reg, val); 1141 intel_de_posting_read(dev_priv, reg); 1142 1143 intel_write_infoframe(encoder, crtc_state, 1144 HDMI_INFOFRAME_TYPE_AVI, 1145 &crtc_state->infoframes.avi); 1146 intel_write_infoframe(encoder, crtc_state, 1147 HDMI_INFOFRAME_TYPE_SPD, 1148 &crtc_state->infoframes.spd); 1149 intel_write_infoframe(encoder, crtc_state, 1150 HDMI_INFOFRAME_TYPE_VENDOR, 1151 &crtc_state->infoframes.hdmi); 1152 } 1153 1154 static void vlv_set_infoframes(struct intel_encoder *encoder, 1155 bool enable, 1156 const struct intel_crtc_state *crtc_state, 1157 const struct drm_connector_state *conn_state) 1158 { 1159 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1160 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1161 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1162 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1163 u32 val = intel_de_read(dev_priv, reg); 1164 u32 port = VIDEO_DIP_PORT(encoder->port); 1165 1166 assert_hdmi_port_disabled(intel_hdmi); 1167 1168 /* See the big comment in g4x_set_infoframes() */ 1169 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1170 1171 if (!enable) { 1172 if (!(val & VIDEO_DIP_ENABLE)) 1173 return; 1174 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1175 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1176 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1177 intel_de_write(dev_priv, reg, val); 1178 intel_de_posting_read(dev_priv, reg); 1179 return; 1180 } 1181 1182 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1183 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1184 "DIP already enabled on port %c\n", 1185 (val & VIDEO_DIP_PORT_MASK) >> 29); 1186 val &= ~VIDEO_DIP_PORT_MASK; 1187 val |= port; 1188 } 1189 1190 val |= VIDEO_DIP_ENABLE; 1191 val &= ~(VIDEO_DIP_ENABLE_AVI | 1192 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1193 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1194 1195 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1196 val |= VIDEO_DIP_ENABLE_GCP; 1197 1198 intel_de_write(dev_priv, reg, val); 1199 intel_de_posting_read(dev_priv, reg); 1200 1201 intel_write_infoframe(encoder, crtc_state, 1202 HDMI_INFOFRAME_TYPE_AVI, 1203 &crtc_state->infoframes.avi); 1204 intel_write_infoframe(encoder, crtc_state, 1205 HDMI_INFOFRAME_TYPE_SPD, 1206 &crtc_state->infoframes.spd); 1207 intel_write_infoframe(encoder, crtc_state, 1208 HDMI_INFOFRAME_TYPE_VENDOR, 1209 &crtc_state->infoframes.hdmi); 1210 } 1211 1212 static void hsw_set_infoframes(struct intel_encoder *encoder, 1213 bool enable, 1214 const struct intel_crtc_state *crtc_state, 1215 const struct drm_connector_state *conn_state) 1216 { 1217 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1218 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1219 u32 val = intel_de_read(dev_priv, reg); 1220 1221 assert_hdmi_transcoder_func_disabled(dev_priv, 1222 crtc_state->cpu_transcoder); 1223 1224 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1225 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1226 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1227 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1228 1229 if (!enable) { 1230 intel_de_write(dev_priv, reg, val); 1231 intel_de_posting_read(dev_priv, reg); 1232 return; 1233 } 1234 1235 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1236 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1237 1238 intel_de_write(dev_priv, reg, val); 1239 intel_de_posting_read(dev_priv, reg); 1240 1241 intel_write_infoframe(encoder, crtc_state, 1242 HDMI_INFOFRAME_TYPE_AVI, 1243 &crtc_state->infoframes.avi); 1244 intel_write_infoframe(encoder, crtc_state, 1245 HDMI_INFOFRAME_TYPE_SPD, 1246 &crtc_state->infoframes.spd); 1247 intel_write_infoframe(encoder, crtc_state, 1248 HDMI_INFOFRAME_TYPE_VENDOR, 1249 &crtc_state->infoframes.hdmi); 1250 intel_write_infoframe(encoder, crtc_state, 1251 HDMI_INFOFRAME_TYPE_DRM, 1252 &crtc_state->infoframes.drm); 1253 } 1254 1255 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1256 { 1257 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1258 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1259 1260 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1261 return; 1262 1263 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1264 enable ? "Enabling" : "Disabling"); 1265 1266 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, 1267 hdmi->dp_dual_mode.type, ddc, enable); 1268 } 1269 1270 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1271 unsigned int offset, void *buffer, size_t size) 1272 { 1273 struct intel_hdmi *hdmi = &dig_port->hdmi; 1274 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1275 int ret; 1276 u8 start = offset & 0xff; 1277 struct i2c_msg msgs[] = { 1278 { 1279 .addr = DRM_HDCP_DDC_ADDR, 1280 .flags = 0, 1281 .len = 1, 1282 .buf = &start, 1283 }, 1284 { 1285 .addr = DRM_HDCP_DDC_ADDR, 1286 .flags = I2C_M_RD, 1287 .len = size, 1288 .buf = buffer 1289 } 1290 }; 1291 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1292 if (ret == ARRAY_SIZE(msgs)) 1293 return 0; 1294 return ret >= 0 ? -EIO : ret; 1295 } 1296 1297 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1298 unsigned int offset, void *buffer, size_t size) 1299 { 1300 struct intel_hdmi *hdmi = &dig_port->hdmi; 1301 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1302 int ret; 1303 u8 *write_buf; 1304 struct i2c_msg msg; 1305 1306 write_buf = kzalloc(size + 1, GFP_KERNEL); 1307 if (!write_buf) 1308 return -ENOMEM; 1309 1310 write_buf[0] = offset & 0xff; 1311 memcpy(&write_buf[1], buffer, size); 1312 1313 msg.addr = DRM_HDCP_DDC_ADDR; 1314 msg.flags = 0, 1315 msg.len = size + 1, 1316 msg.buf = write_buf; 1317 1318 ret = i2c_transfer(ddc, &msg, 1); 1319 if (ret == 1) 1320 ret = 0; 1321 else if (ret >= 0) 1322 ret = -EIO; 1323 1324 kfree(write_buf); 1325 return ret; 1326 } 1327 1328 static 1329 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1330 u8 *an) 1331 { 1332 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1333 struct intel_hdmi *hdmi = &dig_port->hdmi; 1334 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1335 int ret; 1336 1337 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1338 DRM_HDCP_AN_LEN); 1339 if (ret) { 1340 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1341 ret); 1342 return ret; 1343 } 1344 1345 ret = intel_gmbus_output_aksv(ddc); 1346 if (ret < 0) { 1347 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1348 return ret; 1349 } 1350 return 0; 1351 } 1352 1353 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1354 u8 *bksv) 1355 { 1356 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1357 1358 int ret; 1359 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1360 DRM_HDCP_KSV_LEN); 1361 if (ret) 1362 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1363 ret); 1364 return ret; 1365 } 1366 1367 static 1368 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1369 u8 *bstatus) 1370 { 1371 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1372 1373 int ret; 1374 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1375 bstatus, DRM_HDCP_BSTATUS_LEN); 1376 if (ret) 1377 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1378 ret); 1379 return ret; 1380 } 1381 1382 static 1383 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1384 bool *repeater_present) 1385 { 1386 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1387 int ret; 1388 u8 val; 1389 1390 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1391 if (ret) { 1392 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1393 ret); 1394 return ret; 1395 } 1396 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1397 return 0; 1398 } 1399 1400 static 1401 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1402 u8 *ri_prime) 1403 { 1404 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1405 1406 int ret; 1407 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1408 ri_prime, DRM_HDCP_RI_LEN); 1409 if (ret) 1410 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1411 ret); 1412 return ret; 1413 } 1414 1415 static 1416 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1417 bool *ksv_ready) 1418 { 1419 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1420 int ret; 1421 u8 val; 1422 1423 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1424 if (ret) { 1425 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1426 ret); 1427 return ret; 1428 } 1429 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1430 return 0; 1431 } 1432 1433 static 1434 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1435 int num_downstream, u8 *ksv_fifo) 1436 { 1437 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1438 int ret; 1439 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1440 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1441 if (ret) { 1442 drm_dbg_kms(&i915->drm, 1443 "Read ksv fifo over DDC failed (%d)\n", ret); 1444 return ret; 1445 } 1446 return 0; 1447 } 1448 1449 static 1450 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1451 int i, u32 *part) 1452 { 1453 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1454 int ret; 1455 1456 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1457 return -EINVAL; 1458 1459 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1460 part, DRM_HDCP_V_PRIME_PART_LEN); 1461 if (ret) 1462 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1463 i, ret); 1464 return ret; 1465 } 1466 1467 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1468 enum transcoder cpu_transcoder) 1469 { 1470 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1471 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1472 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1473 u32 scanline; 1474 int ret; 1475 1476 for (;;) { 1477 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1478 if (scanline > 100 && scanline < 200) 1479 break; 1480 usleep_range(25, 50); 1481 } 1482 1483 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1484 false, TRANS_DDI_HDCP_SIGNALLING); 1485 if (ret) { 1486 drm_err(&dev_priv->drm, 1487 "Disable HDCP signalling failed (%d)\n", ret); 1488 return ret; 1489 } 1490 1491 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1492 true, TRANS_DDI_HDCP_SIGNALLING); 1493 if (ret) { 1494 drm_err(&dev_priv->drm, 1495 "Enable HDCP signalling failed (%d)\n", ret); 1496 return ret; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static 1503 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1504 enum transcoder cpu_transcoder, 1505 bool enable) 1506 { 1507 struct intel_hdmi *hdmi = &dig_port->hdmi; 1508 struct intel_connector *connector = hdmi->attached_connector; 1509 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1510 int ret; 1511 1512 if (!enable) 1513 usleep_range(6, 60); /* Bspec says >= 6us */ 1514 1515 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1516 cpu_transcoder, enable, 1517 TRANS_DDI_HDCP_SIGNALLING); 1518 if (ret) { 1519 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1520 enable ? "Enable" : "Disable", ret); 1521 return ret; 1522 } 1523 1524 /* 1525 * WA: To fix incorrect positioning of the window of 1526 * opportunity and enc_en signalling in KABYLAKE. 1527 */ 1528 if (IS_KABYLAKE(dev_priv) && enable) 1529 return kbl_repositioning_enc_en_signal(connector, 1530 cpu_transcoder); 1531 1532 return 0; 1533 } 1534 1535 static 1536 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1537 struct intel_connector *connector) 1538 { 1539 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1540 enum port port = dig_port->base.port; 1541 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1542 int ret; 1543 union { 1544 u32 reg; 1545 u8 shim[DRM_HDCP_RI_LEN]; 1546 } ri; 1547 1548 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1549 if (ret) 1550 return false; 1551 1552 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1553 1554 /* Wait for Ri prime match */ 1555 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1556 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1557 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1558 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1559 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1560 port))); 1561 return false; 1562 } 1563 return true; 1564 } 1565 1566 static 1567 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1568 struct intel_connector *connector) 1569 { 1570 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1571 int retry; 1572 1573 for (retry = 0; retry < 3; retry++) 1574 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1575 return true; 1576 1577 drm_err(&i915->drm, "Link check failed\n"); 1578 return false; 1579 } 1580 1581 struct hdcp2_hdmi_msg_timeout { 1582 u8 msg_id; 1583 u16 timeout; 1584 }; 1585 1586 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1587 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1588 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1589 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1590 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1591 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1592 }; 1593 1594 static 1595 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1596 u8 *rx_status) 1597 { 1598 return intel_hdmi_hdcp_read(dig_port, 1599 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1600 rx_status, 1601 HDCP_2_2_HDMI_RXSTATUS_LEN); 1602 } 1603 1604 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1605 { 1606 int i; 1607 1608 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1609 if (is_paired) 1610 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1611 else 1612 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1613 } 1614 1615 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1616 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1617 return hdcp2_msg_timeout[i].timeout; 1618 } 1619 1620 return -EINVAL; 1621 } 1622 1623 static int 1624 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1625 u8 msg_id, bool *msg_ready, 1626 ssize_t *msg_sz) 1627 { 1628 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1629 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1630 int ret; 1631 1632 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1633 if (ret < 0) { 1634 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1635 ret); 1636 return ret; 1637 } 1638 1639 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1640 rx_status[0]); 1641 1642 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1643 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1644 *msg_sz); 1645 else 1646 *msg_ready = *msg_sz; 1647 1648 return 0; 1649 } 1650 1651 static ssize_t 1652 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1653 u8 msg_id, bool paired) 1654 { 1655 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1656 bool msg_ready = false; 1657 int timeout, ret; 1658 ssize_t msg_sz = 0; 1659 1660 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1661 if (timeout < 0) 1662 return timeout; 1663 1664 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1665 msg_id, &msg_ready, 1666 &msg_sz), 1667 !ret && msg_ready && msg_sz, timeout * 1000, 1668 1000, 5 * 1000); 1669 if (ret) 1670 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1671 msg_id, ret, timeout); 1672 1673 return ret ? ret : msg_sz; 1674 } 1675 1676 static 1677 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1678 void *buf, size_t size) 1679 { 1680 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1681 unsigned int offset; 1682 1683 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1684 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1685 } 1686 1687 static 1688 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1689 u8 msg_id, void *buf, size_t size) 1690 { 1691 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1692 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1693 struct intel_hdmi *hdmi = &dig_port->hdmi; 1694 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1695 unsigned int offset; 1696 ssize_t ret; 1697 1698 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1699 hdcp->is_paired); 1700 if (ret < 0) 1701 return ret; 1702 1703 /* 1704 * Available msg size should be equal to or lesser than the 1705 * available buffer. 1706 */ 1707 if (ret > size) { 1708 drm_dbg_kms(&i915->drm, 1709 "msg_sz(%zd) is more than exp size(%zu)\n", 1710 ret, size); 1711 return -EINVAL; 1712 } 1713 1714 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1715 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1716 if (ret) 1717 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1718 msg_id, ret); 1719 1720 return ret; 1721 } 1722 1723 static 1724 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1725 struct intel_connector *connector) 1726 { 1727 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1728 int ret; 1729 1730 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1731 if (ret) 1732 return ret; 1733 1734 /* 1735 * Re-auth request and Link Integrity Failures are represented by 1736 * same bit. i.e reauth_req. 1737 */ 1738 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1739 ret = HDCP_REAUTH_REQUEST; 1740 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1741 ret = HDCP_TOPOLOGY_CHANGE; 1742 1743 return ret; 1744 } 1745 1746 static 1747 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1748 bool *capable) 1749 { 1750 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1751 u8 hdcp2_version; 1752 int ret; 1753 1754 *capable = false; 1755 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1756 &hdcp2_version, sizeof(hdcp2_version)); 1757 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1758 *capable = true; 1759 1760 return ret; 1761 } 1762 1763 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1764 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1765 .read_bksv = intel_hdmi_hdcp_read_bksv, 1766 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1767 .repeater_present = intel_hdmi_hdcp_repeater_present, 1768 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1769 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1770 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1771 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1772 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1773 .check_link = intel_hdmi_hdcp_check_link, 1774 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1775 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1776 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1777 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1778 .protocol = HDCP_PROTOCOL_HDMI, 1779 }; 1780 1781 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1782 { 1783 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1784 int max_tmds_clock, vbt_max_tmds_clock; 1785 1786 if (DISPLAY_VER(dev_priv) >= 10) 1787 max_tmds_clock = 594000; 1788 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1789 max_tmds_clock = 300000; 1790 else if (DISPLAY_VER(dev_priv) >= 5) 1791 max_tmds_clock = 225000; 1792 else 1793 max_tmds_clock = 165000; 1794 1795 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1796 if (vbt_max_tmds_clock) 1797 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1798 1799 return max_tmds_clock; 1800 } 1801 1802 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1803 const struct drm_connector_state *conn_state) 1804 { 1805 struct intel_connector *connector = hdmi->attached_connector; 1806 1807 return connector->base.display_info.is_hdmi && 1808 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1809 } 1810 1811 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1812 { 1813 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1814 } 1815 1816 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1817 bool respect_downstream_limits, 1818 bool has_hdmi_sink) 1819 { 1820 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1821 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1822 1823 if (respect_downstream_limits) { 1824 struct intel_connector *connector = hdmi->attached_connector; 1825 const struct drm_display_info *info = &connector->base.display_info; 1826 1827 if (hdmi->dp_dual_mode.max_tmds_clock) 1828 max_tmds_clock = min(max_tmds_clock, 1829 hdmi->dp_dual_mode.max_tmds_clock); 1830 1831 if (info->max_tmds_clock) 1832 max_tmds_clock = min(max_tmds_clock, 1833 info->max_tmds_clock); 1834 else if (!has_hdmi_sink) 1835 max_tmds_clock = min(max_tmds_clock, 165000); 1836 } 1837 1838 return max_tmds_clock; 1839 } 1840 1841 static enum drm_mode_status 1842 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1843 int clock, bool respect_downstream_limits, 1844 bool has_hdmi_sink) 1845 { 1846 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1847 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1848 1849 if (clock < 25000) 1850 return MODE_CLOCK_LOW; 1851 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1852 has_hdmi_sink)) 1853 return MODE_CLOCK_HIGH; 1854 1855 /* GLK DPLL can't generate 446-480 MHz */ 1856 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1857 return MODE_CLOCK_RANGE; 1858 1859 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1860 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1861 clock > 223333 && clock < 240000) 1862 return MODE_CLOCK_RANGE; 1863 1864 /* CHV DPLL can't generate 216-240 MHz */ 1865 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1866 return MODE_CLOCK_RANGE; 1867 1868 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1869 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1870 return MODE_CLOCK_RANGE; 1871 1872 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1873 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1874 return MODE_CLOCK_RANGE; 1875 1876 /* 1877 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1878 * set of link rates. 1879 * 1880 * FIXME: We will hopefully get an algorithmic way of programming 1881 * the MPLLB for HDMI in the future. 1882 */ 1883 if (DISPLAY_VER(dev_priv) >= 14) 1884 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); 1885 else if (IS_DG2(dev_priv)) 1886 return intel_snps_phy_check_hdmi_link_rate(clock); 1887 1888 return MODE_OK; 1889 } 1890 1891 int intel_hdmi_tmds_clock(int clock, int bpc, 1892 enum intel_output_format sink_format) 1893 { 1894 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1895 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1896 clock /= 2; 1897 1898 /* 1899 * Need to adjust the port link by: 1900 * 1.5x for 12bpc 1901 * 1.25x for 10bpc 1902 */ 1903 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1904 } 1905 1906 static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc) 1907 { 1908 switch (bpc) { 1909 case 12: 1910 return !HAS_GMCH(i915); 1911 case 10: 1912 return DISPLAY_VER(i915) >= 11; 1913 case 8: 1914 return true; 1915 default: 1916 MISSING_CASE(bpc); 1917 return false; 1918 } 1919 } 1920 1921 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1922 int bpc, bool has_hdmi_sink, 1923 enum intel_output_format sink_format) 1924 { 1925 const struct drm_display_info *info = &connector->display_info; 1926 const struct drm_hdmi_info *hdmi = &info->hdmi; 1927 1928 switch (bpc) { 1929 case 12: 1930 if (!has_hdmi_sink) 1931 return false; 1932 1933 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1934 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1935 else 1936 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1937 case 10: 1938 if (!has_hdmi_sink) 1939 return false; 1940 1941 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1942 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1943 else 1944 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1945 case 8: 1946 return true; 1947 default: 1948 MISSING_CASE(bpc); 1949 return false; 1950 } 1951 } 1952 1953 static enum drm_mode_status 1954 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1955 bool has_hdmi_sink, 1956 enum intel_output_format sink_format) 1957 { 1958 struct drm_i915_private *i915 = to_i915(connector->dev); 1959 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1960 enum drm_mode_status status = MODE_OK; 1961 int bpc; 1962 1963 /* 1964 * Try all color depths since valid port clock range 1965 * can have holes. Any mode that can be used with at 1966 * least one color depth is accepted. 1967 */ 1968 for (bpc = 12; bpc >= 8; bpc -= 2) { 1969 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1970 1971 if (!intel_hdmi_source_bpc_possible(i915, bpc)) 1972 continue; 1973 1974 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 1975 continue; 1976 1977 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1978 if (status == MODE_OK) 1979 return MODE_OK; 1980 } 1981 1982 /* can never happen */ 1983 drm_WARN_ON(&i915->drm, status == MODE_OK); 1984 1985 return status; 1986 } 1987 1988 static enum drm_mode_status 1989 intel_hdmi_mode_valid(struct drm_connector *connector, 1990 struct drm_display_mode *mode) 1991 { 1992 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1993 struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi); 1994 enum drm_mode_status status; 1995 int clock = mode->clock; 1996 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 1997 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1998 bool ycbcr_420_only; 1999 enum intel_output_format sink_format; 2000 2001 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 2002 if (status != MODE_OK) 2003 return status; 2004 2005 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2006 clock *= 2; 2007 2008 if (clock > max_dotclk) 2009 return MODE_CLOCK_HIGH; 2010 2011 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2012 if (!has_hdmi_sink) 2013 return MODE_CLOCK_LOW; 2014 clock *= 2; 2015 } 2016 2017 /* 2018 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2019 * enumerated only if FRL is supported. Current platforms do not support 2020 * FRL so prune the higher resolution modes that require doctclock more 2021 * than 600MHz. 2022 */ 2023 if (clock > 600000) 2024 return MODE_CLOCK_HIGH; 2025 2026 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2027 2028 if (ycbcr_420_only) 2029 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2030 else 2031 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2032 2033 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2034 if (status != MODE_OK) { 2035 if (ycbcr_420_only || 2036 !connector->ycbcr_420_allowed || 2037 !drm_mode_is_420_also(&connector->display_info, mode)) 2038 return status; 2039 2040 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2041 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2042 if (status != MODE_OK) 2043 return status; 2044 } 2045 2046 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2047 } 2048 2049 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2050 int bpc, bool has_hdmi_sink) 2051 { 2052 struct drm_atomic_state *state = crtc_state->uapi.state; 2053 struct drm_connector_state *connector_state; 2054 struct drm_connector *connector; 2055 int i; 2056 2057 for_each_new_connector_in_state(state, connector, connector_state, i) { 2058 if (connector_state->crtc != crtc_state->uapi.crtc) 2059 continue; 2060 2061 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2062 crtc_state->sink_format)) 2063 return false; 2064 } 2065 2066 return true; 2067 } 2068 2069 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2070 { 2071 struct drm_i915_private *dev_priv = 2072 to_i915(crtc_state->uapi.crtc->dev); 2073 const struct drm_display_mode *adjusted_mode = 2074 &crtc_state->hw.adjusted_mode; 2075 2076 if (!intel_hdmi_source_bpc_possible(dev_priv, bpc)) 2077 return false; 2078 2079 /* Display Wa_1405510057:icl,ehl */ 2080 if (intel_hdmi_is_ycbcr420(crtc_state) && 2081 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2082 (adjusted_mode->crtc_hblank_end - 2083 adjusted_mode->crtc_hblank_start) % 8 == 2) 2084 return false; 2085 2086 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2087 } 2088 2089 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2090 struct intel_crtc_state *crtc_state, 2091 int clock, bool respect_downstream_limits) 2092 { 2093 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2094 int bpc; 2095 2096 /* 2097 * pipe_bpp could already be below 8bpc due to FDI 2098 * bandwidth constraints. HDMI minimum is 8bpc however. 2099 */ 2100 bpc = max(crtc_state->pipe_bpp / 3, 8); 2101 2102 /* 2103 * We will never exceed downstream TMDS clock limits while 2104 * attempting deep color. If the user insists on forcing an 2105 * out of spec mode they will have to be satisfied with 8bpc. 2106 */ 2107 if (!respect_downstream_limits) 2108 bpc = 8; 2109 2110 for (; bpc >= 8; bpc -= 2) { 2111 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2112 crtc_state->sink_format); 2113 2114 if (hdmi_bpc_possible(crtc_state, bpc) && 2115 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2116 respect_downstream_limits, 2117 crtc_state->has_hdmi_sink) == MODE_OK) 2118 return bpc; 2119 } 2120 2121 return -EINVAL; 2122 } 2123 2124 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2125 struct intel_crtc_state *crtc_state, 2126 bool respect_downstream_limits) 2127 { 2128 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2129 const struct drm_display_mode *adjusted_mode = 2130 &crtc_state->hw.adjusted_mode; 2131 int bpc, clock = adjusted_mode->crtc_clock; 2132 2133 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2134 clock *= 2; 2135 2136 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2137 respect_downstream_limits); 2138 if (bpc < 0) 2139 return bpc; 2140 2141 crtc_state->port_clock = 2142 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2143 2144 /* 2145 * pipe_bpp could already be below 8bpc due to 2146 * FDI bandwidth constraints. We shouldn't bump it 2147 * back up to the HDMI minimum 8bpc in that case. 2148 */ 2149 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2150 2151 drm_dbg_kms(&i915->drm, 2152 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2153 bpc, crtc_state->pipe_bpp); 2154 2155 return 0; 2156 } 2157 2158 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2159 const struct drm_connector_state *conn_state) 2160 { 2161 const struct intel_digital_connector_state *intel_conn_state = 2162 to_intel_digital_connector_state(conn_state); 2163 const struct drm_display_mode *adjusted_mode = 2164 &crtc_state->hw.adjusted_mode; 2165 2166 /* 2167 * Our YCbCr output is always limited range. 2168 * crtc_state->limited_color_range only applies to RGB, 2169 * and it must never be set for YCbCr or we risk setting 2170 * some conflicting bits in TRANSCONF which will mess up 2171 * the colors on the monitor. 2172 */ 2173 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2174 return false; 2175 2176 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2177 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2178 return crtc_state->has_hdmi_sink && 2179 drm_default_rgb_quant_range(adjusted_mode) == 2180 HDMI_QUANTIZATION_RANGE_LIMITED; 2181 } else { 2182 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2183 } 2184 } 2185 2186 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2187 const struct intel_crtc_state *crtc_state, 2188 const struct drm_connector_state *conn_state) 2189 { 2190 struct drm_connector *connector = conn_state->connector; 2191 const struct intel_digital_connector_state *intel_conn_state = 2192 to_intel_digital_connector_state(conn_state); 2193 2194 if (!crtc_state->has_hdmi_sink) 2195 return false; 2196 2197 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2198 return connector->display_info.has_audio; 2199 else 2200 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2201 } 2202 2203 static enum intel_output_format 2204 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2205 struct intel_connector *connector, 2206 bool ycbcr_420_output) 2207 { 2208 if (!crtc_state->has_hdmi_sink) 2209 return INTEL_OUTPUT_FORMAT_RGB; 2210 2211 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2212 return INTEL_OUTPUT_FORMAT_YCBCR420; 2213 else 2214 return INTEL_OUTPUT_FORMAT_RGB; 2215 } 2216 2217 static enum intel_output_format 2218 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2219 { 2220 return crtc_state->sink_format; 2221 } 2222 2223 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2224 struct intel_crtc_state *crtc_state, 2225 const struct drm_connector_state *conn_state, 2226 bool respect_downstream_limits) 2227 { 2228 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2229 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2230 const struct drm_display_info *info = &connector->base.display_info; 2231 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2232 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2233 int ret; 2234 2235 crtc_state->sink_format = 2236 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2237 2238 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2239 drm_dbg_kms(&i915->drm, 2240 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2241 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2242 } 2243 2244 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2245 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2246 if (ret) { 2247 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2248 !crtc_state->has_hdmi_sink || 2249 !connector->base.ycbcr_420_allowed || 2250 !drm_mode_is_420_also(info, adjusted_mode)) 2251 return ret; 2252 2253 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2254 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2255 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2256 } 2257 2258 return ret; 2259 } 2260 2261 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2262 { 2263 return crtc_state->uapi.encoder_mask && 2264 !is_power_of_2(crtc_state->uapi.encoder_mask); 2265 } 2266 2267 static bool source_supports_scrambling(struct intel_encoder *encoder) 2268 { 2269 /* 2270 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2271 * scrambling is supported. 2272 * But there seem to be cases where certain platforms that support 2273 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2274 * capped by VBT to less than 340MHz. 2275 * 2276 * In such cases when an HDMI2.0 sink is connected, it creates a 2277 * problem : the platform and the sink both support scrambling but the 2278 * HDMI 1.4 retimer chip doesn't. 2279 * 2280 * So go for scrambling, based on the max tmds clock taking into account, 2281 * restrictions coming from VBT. 2282 */ 2283 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2284 } 2285 2286 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2287 const struct intel_crtc_state *crtc_state, 2288 const struct drm_connector_state *conn_state) 2289 { 2290 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2291 2292 return intel_has_hdmi_sink(hdmi, conn_state) && 2293 !intel_hdmi_is_cloned(crtc_state); 2294 } 2295 2296 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2297 struct intel_crtc_state *pipe_config, 2298 struct drm_connector_state *conn_state) 2299 { 2300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2301 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2302 struct drm_connector *connector = conn_state->connector; 2303 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2304 int ret; 2305 2306 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2307 return -EINVAL; 2308 2309 if (!connector->interlace_allowed && 2310 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2311 return -EINVAL; 2312 2313 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2314 2315 if (pipe_config->has_hdmi_sink) 2316 pipe_config->has_infoframe = true; 2317 2318 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2319 pipe_config->pixel_multiplier = 2; 2320 2321 pipe_config->has_audio = 2322 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2323 intel_audio_compute_config(encoder, pipe_config, conn_state); 2324 2325 /* 2326 * Try to respect downstream TMDS clock limits first, if 2327 * that fails assume the user might know something we don't. 2328 */ 2329 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2330 if (ret) 2331 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2332 if (ret) { 2333 drm_dbg_kms(&dev_priv->drm, 2334 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2335 pipe_config->hw.adjusted_mode.crtc_clock); 2336 return ret; 2337 } 2338 2339 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2340 ret = intel_panel_fitting(pipe_config, conn_state); 2341 if (ret) 2342 return ret; 2343 } 2344 2345 pipe_config->limited_color_range = 2346 intel_hdmi_limited_color_range(pipe_config, conn_state); 2347 2348 if (conn_state->picture_aspect_ratio) 2349 adjusted_mode->picture_aspect_ratio = 2350 conn_state->picture_aspect_ratio; 2351 2352 pipe_config->lane_count = 4; 2353 2354 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2355 if (scdc->scrambling.low_rates) 2356 pipe_config->hdmi_scrambling = true; 2357 2358 if (pipe_config->port_clock > 340000) { 2359 pipe_config->hdmi_scrambling = true; 2360 pipe_config->hdmi_high_tmds_clock_ratio = true; 2361 } 2362 } 2363 2364 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2365 conn_state); 2366 2367 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2368 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2369 return -EINVAL; 2370 } 2371 2372 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2373 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2374 return -EINVAL; 2375 } 2376 2377 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2378 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2379 return -EINVAL; 2380 } 2381 2382 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2383 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2384 return -EINVAL; 2385 } 2386 2387 return 0; 2388 } 2389 2390 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2391 { 2392 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2393 2394 /* 2395 * Give a hand to buggy BIOSen which forget to turn 2396 * the TMDS output buffers back on after a reboot. 2397 */ 2398 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2399 } 2400 2401 static void 2402 intel_hdmi_unset_edid(struct drm_connector *connector) 2403 { 2404 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2405 2406 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2407 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2408 2409 drm_edid_free(to_intel_connector(connector)->detect_edid); 2410 to_intel_connector(connector)->detect_edid = NULL; 2411 } 2412 2413 static void 2414 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2415 { 2416 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2417 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2418 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2419 struct i2c_adapter *ddc = connector->ddc; 2420 enum drm_dp_dual_mode_type type; 2421 2422 type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc); 2423 2424 /* 2425 * Type 1 DVI adaptors are not required to implement any 2426 * registers, so we can't always detect their presence. 2427 * Ideally we should be able to check the state of the 2428 * CONFIG1 pin, but no such luck on our hardware. 2429 * 2430 * The only method left to us is to check the VBT to see 2431 * if the port is a dual mode capable DP port. 2432 */ 2433 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2434 if (!connector->force && 2435 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2436 drm_dbg_kms(&dev_priv->drm, 2437 "Assuming DP dual mode adaptor presence based on VBT\n"); 2438 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2439 } else { 2440 type = DRM_DP_DUAL_MODE_NONE; 2441 } 2442 } 2443 2444 if (type == DRM_DP_DUAL_MODE_NONE) 2445 return; 2446 2447 hdmi->dp_dual_mode.type = type; 2448 hdmi->dp_dual_mode.max_tmds_clock = 2449 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc); 2450 2451 drm_dbg_kms(&dev_priv->drm, 2452 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2453 drm_dp_get_dual_mode_type_name(type), 2454 hdmi->dp_dual_mode.max_tmds_clock); 2455 2456 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2457 if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && 2458 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2459 drm_dbg_kms(&dev_priv->drm, 2460 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2461 hdmi->dp_dual_mode.max_tmds_clock = 0; 2462 } 2463 } 2464 2465 static bool 2466 intel_hdmi_set_edid(struct drm_connector *connector) 2467 { 2468 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2469 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2470 struct i2c_adapter *ddc = connector->ddc; 2471 intel_wakeref_t wakeref; 2472 const struct drm_edid *drm_edid; 2473 bool connected = false; 2474 2475 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2476 2477 drm_edid = drm_edid_read_ddc(connector, ddc); 2478 2479 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2480 drm_dbg_kms(&dev_priv->drm, 2481 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2482 intel_gmbus_force_bit(ddc, true); 2483 drm_edid = drm_edid_read_ddc(connector, ddc); 2484 intel_gmbus_force_bit(ddc, false); 2485 } 2486 2487 /* Below we depend on display info having been updated */ 2488 drm_edid_connector_update(connector, drm_edid); 2489 2490 to_intel_connector(connector)->detect_edid = drm_edid; 2491 2492 if (drm_edid_is_digital(drm_edid)) { 2493 intel_hdmi_dp_dual_mode_detect(connector); 2494 2495 connected = true; 2496 } 2497 2498 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2499 2500 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2501 connector->display_info.source_physical_address); 2502 2503 return connected; 2504 } 2505 2506 static enum drm_connector_status 2507 intel_hdmi_detect(struct drm_connector *connector, bool force) 2508 { 2509 enum drm_connector_status status = connector_status_disconnected; 2510 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2511 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2512 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2513 intel_wakeref_t wakeref; 2514 2515 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2516 connector->base.id, connector->name); 2517 2518 if (!intel_display_device_enabled(dev_priv)) 2519 return connector_status_disconnected; 2520 2521 if (!intel_display_driver_check_access(dev_priv)) 2522 return connector->status; 2523 2524 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2525 2526 if (DISPLAY_VER(dev_priv) >= 11 && 2527 !intel_digital_port_connected(encoder)) 2528 goto out; 2529 2530 intel_hdmi_unset_edid(connector); 2531 2532 if (intel_hdmi_set_edid(connector)) 2533 status = connector_status_connected; 2534 2535 out: 2536 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2537 2538 if (status != connector_status_connected) 2539 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2540 2541 return status; 2542 } 2543 2544 static void 2545 intel_hdmi_force(struct drm_connector *connector) 2546 { 2547 struct drm_i915_private *i915 = to_i915(connector->dev); 2548 2549 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2550 connector->base.id, connector->name); 2551 2552 if (!intel_display_driver_check_access(i915)) 2553 return; 2554 2555 intel_hdmi_unset_edid(connector); 2556 2557 if (connector->status != connector_status_connected) 2558 return; 2559 2560 intel_hdmi_set_edid(connector); 2561 } 2562 2563 static int intel_hdmi_get_modes(struct drm_connector *connector) 2564 { 2565 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2566 return drm_edid_connector_add_modes(connector); 2567 } 2568 2569 static int 2570 intel_hdmi_connector_register(struct drm_connector *connector) 2571 { 2572 int ret; 2573 2574 ret = intel_connector_register(connector); 2575 if (ret) 2576 return ret; 2577 2578 return ret; 2579 } 2580 2581 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2582 { 2583 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2584 2585 cec_notifier_conn_unregister(n); 2586 2587 intel_connector_unregister(connector); 2588 } 2589 2590 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2591 .detect = intel_hdmi_detect, 2592 .force = intel_hdmi_force, 2593 .fill_modes = drm_helper_probe_single_connector_modes, 2594 .atomic_get_property = intel_digital_connector_atomic_get_property, 2595 .atomic_set_property = intel_digital_connector_atomic_set_property, 2596 .late_register = intel_hdmi_connector_register, 2597 .early_unregister = intel_hdmi_connector_unregister, 2598 .destroy = intel_connector_destroy, 2599 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2600 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2601 }; 2602 2603 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2604 struct drm_atomic_state *state) 2605 { 2606 struct drm_i915_private *i915 = to_i915(state->dev); 2607 2608 if (HAS_DDI(i915)) 2609 return intel_digital_connector_atomic_check(connector, state); 2610 else 2611 return g4x_hdmi_connector_atomic_check(connector, state); 2612 } 2613 2614 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2615 .get_modes = intel_hdmi_get_modes, 2616 .mode_valid = intel_hdmi_mode_valid, 2617 .atomic_check = intel_hdmi_connector_atomic_check, 2618 }; 2619 2620 static void 2621 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2622 { 2623 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2624 2625 intel_attach_force_audio_property(connector); 2626 intel_attach_broadcast_rgb_property(connector); 2627 intel_attach_aspect_ratio_property(connector); 2628 2629 intel_attach_hdmi_colorspace_property(connector); 2630 drm_connector_attach_content_type_property(connector); 2631 2632 if (DISPLAY_VER(dev_priv) >= 10) 2633 drm_connector_attach_hdr_output_metadata_property(connector); 2634 2635 if (!HAS_GMCH(dev_priv)) 2636 drm_connector_attach_max_bpc_property(connector, 8, 12); 2637 } 2638 2639 /* 2640 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2641 * @encoder: intel_encoder 2642 * @connector: drm_connector 2643 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2644 * or reset the high tmds clock ratio for scrambling 2645 * @scrambling: bool to Indicate if the function needs to set or reset 2646 * sink scrambling 2647 * 2648 * This function handles scrambling on HDMI 2.0 capable sinks. 2649 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2650 * it enables scrambling. This should be called before enabling the HDMI 2651 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2652 * detect a scrambled clock within 100 ms. 2653 * 2654 * Returns: 2655 * True on success, false on failure. 2656 */ 2657 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2658 struct drm_connector *connector, 2659 bool high_tmds_clock_ratio, 2660 bool scrambling) 2661 { 2662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2663 struct drm_scrambling *sink_scrambling = 2664 &connector->display_info.hdmi.scdc.scrambling; 2665 2666 if (!sink_scrambling->supported) 2667 return true; 2668 2669 drm_dbg_kms(&dev_priv->drm, 2670 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2671 connector->base.id, connector->name, 2672 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2673 2674 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2675 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2676 drm_scdc_set_scrambling(connector, scrambling); 2677 } 2678 2679 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2680 { 2681 enum port port = encoder->port; 2682 u8 ddc_pin; 2683 2684 switch (port) { 2685 case PORT_B: 2686 ddc_pin = GMBUS_PIN_DPB; 2687 break; 2688 case PORT_C: 2689 ddc_pin = GMBUS_PIN_DPC; 2690 break; 2691 case PORT_D: 2692 ddc_pin = GMBUS_PIN_DPD_CHV; 2693 break; 2694 default: 2695 MISSING_CASE(port); 2696 ddc_pin = GMBUS_PIN_DPB; 2697 break; 2698 } 2699 return ddc_pin; 2700 } 2701 2702 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2703 { 2704 enum port port = encoder->port; 2705 u8 ddc_pin; 2706 2707 switch (port) { 2708 case PORT_B: 2709 ddc_pin = GMBUS_PIN_1_BXT; 2710 break; 2711 case PORT_C: 2712 ddc_pin = GMBUS_PIN_2_BXT; 2713 break; 2714 default: 2715 MISSING_CASE(port); 2716 ddc_pin = GMBUS_PIN_1_BXT; 2717 break; 2718 } 2719 return ddc_pin; 2720 } 2721 2722 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2723 { 2724 enum port port = encoder->port; 2725 u8 ddc_pin; 2726 2727 switch (port) { 2728 case PORT_B: 2729 ddc_pin = GMBUS_PIN_1_BXT; 2730 break; 2731 case PORT_C: 2732 ddc_pin = GMBUS_PIN_2_BXT; 2733 break; 2734 case PORT_D: 2735 ddc_pin = GMBUS_PIN_4_CNP; 2736 break; 2737 case PORT_F: 2738 ddc_pin = GMBUS_PIN_3_BXT; 2739 break; 2740 default: 2741 MISSING_CASE(port); 2742 ddc_pin = GMBUS_PIN_1_BXT; 2743 break; 2744 } 2745 return ddc_pin; 2746 } 2747 2748 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2749 { 2750 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2751 enum port port = encoder->port; 2752 2753 if (intel_encoder_is_combo(encoder)) 2754 return GMBUS_PIN_1_BXT + port; 2755 else if (intel_encoder_is_tc(encoder)) 2756 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2757 2758 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2759 return GMBUS_PIN_2_BXT; 2760 } 2761 2762 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2763 { 2764 enum phy phy = intel_encoder_to_phy(encoder); 2765 u8 ddc_pin; 2766 2767 switch (phy) { 2768 case PHY_A: 2769 ddc_pin = GMBUS_PIN_1_BXT; 2770 break; 2771 case PHY_B: 2772 ddc_pin = GMBUS_PIN_2_BXT; 2773 break; 2774 case PHY_C: 2775 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2776 break; 2777 default: 2778 MISSING_CASE(phy); 2779 ddc_pin = GMBUS_PIN_1_BXT; 2780 break; 2781 } 2782 return ddc_pin; 2783 } 2784 2785 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2786 { 2787 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2788 enum phy phy = intel_encoder_to_phy(encoder); 2789 2790 WARN_ON(encoder->port == PORT_C); 2791 2792 /* 2793 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2794 * final two outputs use type-c pins, even though they're actually 2795 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2796 * all outputs. 2797 */ 2798 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2799 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2800 2801 return GMBUS_PIN_1_BXT + phy; 2802 } 2803 2804 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2805 { 2806 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2807 enum phy phy = intel_encoder_to_phy(encoder); 2808 2809 drm_WARN_ON(&i915->drm, encoder->port == PORT_A); 2810 2811 /* 2812 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2813 * final two outputs use type-c pins, even though they're actually 2814 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2815 * all outputs. 2816 */ 2817 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2818 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2819 2820 return GMBUS_PIN_1_BXT + phy; 2821 } 2822 2823 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2824 { 2825 return intel_encoder_to_phy(encoder) + 1; 2826 } 2827 2828 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2829 { 2830 enum phy phy = intel_encoder_to_phy(encoder); 2831 2832 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2833 2834 /* 2835 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2836 * except first combo output. 2837 */ 2838 if (phy == PHY_A) 2839 return GMBUS_PIN_1_BXT; 2840 2841 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2842 } 2843 2844 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2845 { 2846 enum port port = encoder->port; 2847 u8 ddc_pin; 2848 2849 switch (port) { 2850 case PORT_B: 2851 ddc_pin = GMBUS_PIN_DPB; 2852 break; 2853 case PORT_C: 2854 ddc_pin = GMBUS_PIN_DPC; 2855 break; 2856 case PORT_D: 2857 ddc_pin = GMBUS_PIN_DPD; 2858 break; 2859 default: 2860 MISSING_CASE(port); 2861 ddc_pin = GMBUS_PIN_DPB; 2862 break; 2863 } 2864 return ddc_pin; 2865 } 2866 2867 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2868 { 2869 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2870 u8 ddc_pin; 2871 2872 if (IS_ALDERLAKE_S(dev_priv)) 2873 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2874 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2875 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2876 else if (IS_ROCKETLAKE(dev_priv)) 2877 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2878 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2879 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2880 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2881 HAS_PCH_TGP(dev_priv)) 2882 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2883 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2884 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2885 else if (HAS_PCH_CNP(dev_priv)) 2886 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2887 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2888 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2889 else if (IS_CHERRYVIEW(dev_priv)) 2890 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2891 else 2892 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2893 2894 return ddc_pin; 2895 } 2896 2897 static struct intel_encoder * 2898 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2899 { 2900 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2901 struct intel_encoder *other; 2902 2903 for_each_intel_encoder(&i915->drm, other) { 2904 struct intel_connector *connector; 2905 2906 if (other == encoder) 2907 continue; 2908 2909 if (!intel_encoder_is_dig_port(other)) 2910 continue; 2911 2912 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2913 2914 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) 2915 return other; 2916 } 2917 2918 return NULL; 2919 } 2920 2921 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2922 { 2923 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2924 struct intel_encoder *other; 2925 const char *source; 2926 u8 ddc_pin; 2927 2928 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2929 source = "VBT"; 2930 2931 if (!ddc_pin) { 2932 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2933 source = "platform default"; 2934 } 2935 2936 if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) { 2937 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2938 encoder->base.base.id, encoder->base.name, ddc_pin); 2939 return 0; 2940 } 2941 2942 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2943 if (other) { 2944 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2945 encoder->base.base.id, encoder->base.name, ddc_pin, 2946 other->base.base.id, other->base.name); 2947 return 0; 2948 } 2949 2950 drm_dbg_kms(&i915->drm, 2951 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2952 encoder->base.base.id, encoder->base.name, 2953 ddc_pin, source); 2954 2955 return ddc_pin; 2956 } 2957 2958 void intel_infoframe_init(struct intel_digital_port *dig_port) 2959 { 2960 struct drm_i915_private *dev_priv = 2961 to_i915(dig_port->base.base.dev); 2962 2963 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2964 dig_port->write_infoframe = vlv_write_infoframe; 2965 dig_port->read_infoframe = vlv_read_infoframe; 2966 dig_port->set_infoframes = vlv_set_infoframes; 2967 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2968 } else if (IS_G4X(dev_priv)) { 2969 dig_port->write_infoframe = g4x_write_infoframe; 2970 dig_port->read_infoframe = g4x_read_infoframe; 2971 dig_port->set_infoframes = g4x_set_infoframes; 2972 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2973 } else if (HAS_DDI(dev_priv)) { 2974 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 2975 dig_port->write_infoframe = lspcon_write_infoframe; 2976 dig_port->read_infoframe = lspcon_read_infoframe; 2977 dig_port->set_infoframes = lspcon_set_infoframes; 2978 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2979 } else { 2980 dig_port->write_infoframe = hsw_write_infoframe; 2981 dig_port->read_infoframe = hsw_read_infoframe; 2982 dig_port->set_infoframes = hsw_set_infoframes; 2983 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2984 } 2985 } else if (HAS_PCH_IBX(dev_priv)) { 2986 dig_port->write_infoframe = ibx_write_infoframe; 2987 dig_port->read_infoframe = ibx_read_infoframe; 2988 dig_port->set_infoframes = ibx_set_infoframes; 2989 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2990 } else { 2991 dig_port->write_infoframe = cpt_write_infoframe; 2992 dig_port->read_infoframe = cpt_read_infoframe; 2993 dig_port->set_infoframes = cpt_set_infoframes; 2994 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2995 } 2996 } 2997 2998 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2999 struct intel_connector *intel_connector) 3000 { 3001 struct drm_connector *connector = &intel_connector->base; 3002 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3003 struct intel_encoder *intel_encoder = &dig_port->base; 3004 struct drm_device *dev = intel_encoder->base.dev; 3005 struct drm_i915_private *dev_priv = to_i915(dev); 3006 enum port port = intel_encoder->port; 3007 struct cec_connector_info conn_info; 3008 u8 ddc_pin; 3009 3010 drm_dbg_kms(&dev_priv->drm, 3011 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3012 intel_encoder->base.base.id, intel_encoder->base.name); 3013 3014 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3015 return; 3016 3017 if (drm_WARN(dev, dig_port->max_lanes < 4, 3018 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3019 dig_port->max_lanes, intel_encoder->base.base.id, 3020 intel_encoder->base.name)) 3021 return; 3022 3023 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3024 if (!ddc_pin) 3025 return; 3026 3027 drm_connector_init_with_ddc(dev, connector, 3028 &intel_hdmi_connector_funcs, 3029 DRM_MODE_CONNECTOR_HDMIA, 3030 intel_gmbus_get_adapter(dev_priv, ddc_pin)); 3031 3032 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3033 3034 if (DISPLAY_VER(dev_priv) < 12) 3035 connector->interlace_allowed = true; 3036 3037 connector->stereo_allowed = true; 3038 3039 if (DISPLAY_VER(dev_priv) >= 10) 3040 connector->ycbcr_420_allowed = true; 3041 3042 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3043 intel_connector->base.polled = intel_connector->polled; 3044 3045 if (HAS_DDI(dev_priv)) 3046 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3047 else 3048 intel_connector->get_hw_state = intel_connector_get_hw_state; 3049 3050 intel_hdmi_add_properties(intel_hdmi, connector); 3051 3052 intel_connector_attach_encoder(intel_connector, intel_encoder); 3053 intel_hdmi->attached_connector = intel_connector; 3054 3055 if (is_hdcp_supported(dev_priv, port)) { 3056 int ret = intel_hdcp_init(intel_connector, dig_port, 3057 &intel_hdmi_hdcp_shim); 3058 if (ret) 3059 drm_dbg_kms(&dev_priv->drm, 3060 "HDCP init failed, skipping.\n"); 3061 } 3062 3063 cec_fill_conn_info_from_drm(&conn_info, connector); 3064 3065 intel_hdmi->cec_notifier = 3066 cec_notifier_conn_register(dev->dev, port_identifier(port), 3067 &conn_info); 3068 if (!intel_hdmi->cec_notifier) 3069 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 3070 } 3071 3072 /* 3073 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3074 * @vactive: Vactive of a display mode 3075 * 3076 * @return: appropriate dsc slice height for a given mode. 3077 */ 3078 int intel_hdmi_dsc_get_slice_height(int vactive) 3079 { 3080 int slice_height; 3081 3082 /* 3083 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3084 * Select smallest slice height >=96, that results in a valid PPS and 3085 * requires minimum padding lines required for final slice. 3086 * 3087 * Assumption : Vactive is even. 3088 */ 3089 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3090 if (vactive % slice_height == 0) 3091 return slice_height; 3092 3093 return 0; 3094 } 3095 3096 /* 3097 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3098 * and dsc decoder capabilities 3099 * 3100 * @crtc_state: intel crtc_state 3101 * @src_max_slices: maximum slices supported by the DSC encoder 3102 * @src_max_slice_width: maximum slice width supported by DSC encoder 3103 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3104 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3105 * 3106 * @return: num of dsc slices that can be supported by the dsc encoder 3107 * and decoder. 3108 */ 3109 int 3110 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3111 int src_max_slices, int src_max_slice_width, 3112 int hdmi_max_slices, int hdmi_throughput) 3113 { 3114 /* Pixel rates in KPixels/sec */ 3115 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3116 /* 3117 * Rates at which the source and sink are required to process pixels in each 3118 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3119 */ 3120 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3121 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3122 3123 /* Spec limits the slice width to 2720 pixels */ 3124 #define MAX_HDMI_SLICE_WIDTH 2720 3125 int kslice_adjust; 3126 int adjusted_clk_khz; 3127 int min_slices; 3128 int target_slices; 3129 int max_throughput; /* max clock freq. in khz per slice */ 3130 int max_slice_width; 3131 int slice_width; 3132 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3133 3134 if (!hdmi_throughput) 3135 return 0; 3136 3137 /* 3138 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3139 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3140 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3141 * dividing adjusted clock value by 10. 3142 */ 3143 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3144 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3145 kslice_adjust = 10; 3146 else 3147 kslice_adjust = 5; 3148 3149 /* 3150 * As per spec, the rate at which the source and the sink process 3151 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3152 * This depends upon the pixel clock rate and output formats 3153 * (kslice adjust). 3154 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3155 * at max 340MHz, otherwise they can be processed at max 400MHz. 3156 */ 3157 3158 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3159 3160 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3161 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3162 else 3163 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3164 3165 /* 3166 * Taking into account the sink's capability for maximum 3167 * clock per slice (in MHz) as read from HF-VSDB. 3168 */ 3169 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3170 3171 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3172 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3173 3174 /* 3175 * Keep on increasing the num of slices/line, starting from min_slices 3176 * per line till we get such a number, for which the slice_width is 3177 * just less than max_slice_width. The slices/line selected should be 3178 * less than or equal to the max horizontal slices that the combination 3179 * of PCON encoder and HDMI decoder can support. 3180 */ 3181 slice_width = max_slice_width; 3182 3183 do { 3184 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3185 target_slices = 1; 3186 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3187 target_slices = 2; 3188 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3189 target_slices = 4; 3190 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3191 target_slices = 8; 3192 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3193 target_slices = 12; 3194 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3195 target_slices = 16; 3196 else 3197 return 0; 3198 3199 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3200 if (slice_width >= max_slice_width) 3201 min_slices = target_slices + 1; 3202 } while (slice_width >= max_slice_width); 3203 3204 return target_slices; 3205 } 3206 3207 /* 3208 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3209 * source and sink capabilities. 3210 * 3211 * @src_fraction_bpp: fractional bpp supported by the source 3212 * @slice_width: dsc slice width supported by the source and sink 3213 * @num_slices: num of slices supported by the source and sink 3214 * @output_format: video output format 3215 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3216 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3217 * 3218 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3219 */ 3220 int 3221 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3222 int output_format, bool hdmi_all_bpp, 3223 int hdmi_max_chunk_bytes) 3224 { 3225 int max_dsc_bpp, min_dsc_bpp; 3226 int target_bytes; 3227 bool bpp_found = false; 3228 int bpp_decrement_x16; 3229 int bpp_target; 3230 int bpp_target_x16; 3231 3232 /* 3233 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3234 * Start with the max bpp and keep on decrementing with 3235 * fractional bpp, if supported by PCON DSC encoder 3236 * 3237 * for each bpp we check if no of bytes can be supported by HDMI sink 3238 */ 3239 3240 /* Assuming: bpc as 8*/ 3241 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3242 min_dsc_bpp = 6; 3243 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3244 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3245 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3246 min_dsc_bpp = 8; 3247 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3248 } else { 3249 /* Assuming 4:2:2 encoding */ 3250 min_dsc_bpp = 7; 3251 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3252 } 3253 3254 /* 3255 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3256 * Section 7.7.34 : Source shall not enable compressed Video 3257 * Transport with bpp_target settings above 12 bpp unless 3258 * DSC_all_bpp is set to 1. 3259 */ 3260 if (!hdmi_all_bpp) 3261 max_dsc_bpp = min(max_dsc_bpp, 12); 3262 3263 /* 3264 * The Sink has a limit of compressed data in bytes for a scanline, 3265 * as described in max_chunk_bytes field in HFVSDB block of edid. 3266 * The no. of bytes depend on the target bits per pixel that the 3267 * source configures. So we start with the max_bpp and calculate 3268 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3269 * till we get the target_chunk_bytes just less than what the sink's 3270 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3271 * 3272 * The decrement is according to the fractional support from PCON DSC 3273 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3274 * 3275 * bpp_target_x16 = bpp_target * 16 3276 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3277 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3278 */ 3279 3280 bpp_target = max_dsc_bpp; 3281 3282 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3283 if (!src_fractional_bpp) 3284 src_fractional_bpp = 1; 3285 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3286 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3287 3288 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3289 int bpp; 3290 3291 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3292 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3293 if (target_bytes <= hdmi_max_chunk_bytes) { 3294 bpp_found = true; 3295 break; 3296 } 3297 bpp_target_x16 -= bpp_decrement_x16; 3298 } 3299 if (bpp_found) 3300 return bpp_target_x16; 3301 3302 return 0; 3303 } 3304