1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/intel/intel_lpe_audio.h> 42 43 #include "g4x_hdmi.h" 44 #include "i915_drv.h" 45 #include "i915_reg.h" 46 #include "intel_atomic.h" 47 #include "intel_audio.h" 48 #include "intel_connector.h" 49 #include "intel_cx0_phy.h" 50 #include "intel_ddi.h" 51 #include "intel_de.h" 52 #include "intel_display_driver.h" 53 #include "intel_display_types.h" 54 #include "intel_dp.h" 55 #include "intel_gmbus.h" 56 #include "intel_hdcp.h" 57 #include "intel_hdcp_regs.h" 58 #include "intel_hdmi.h" 59 #include "intel_lspcon.h" 60 #include "intel_panel.h" 61 #include "intel_snps_phy.h" 62 63 static void 64 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 65 { 66 struct intel_display *display = to_intel_display(intel_hdmi); 67 u32 enabled_bits; 68 69 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 70 71 drm_WARN(display->drm, 72 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 73 "HDMI port enabled, expecting disabled\n"); 74 } 75 76 static void 77 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 78 enum transcoder cpu_transcoder) 79 { 80 drm_WARN(display->drm, 81 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 82 TRANS_DDI_FUNC_ENABLE, 83 "HDMI transcoder function enabled, expecting disabled\n"); 84 } 85 86 static u32 g4x_infoframe_index(unsigned int type) 87 { 88 switch (type) { 89 case HDMI_PACKET_TYPE_GAMUT_METADATA: 90 return VIDEO_DIP_SELECT_GAMUT; 91 case HDMI_INFOFRAME_TYPE_AVI: 92 return VIDEO_DIP_SELECT_AVI; 93 case HDMI_INFOFRAME_TYPE_SPD: 94 return VIDEO_DIP_SELECT_SPD; 95 case HDMI_INFOFRAME_TYPE_VENDOR: 96 return VIDEO_DIP_SELECT_VENDOR; 97 default: 98 MISSING_CASE(type); 99 return 0; 100 } 101 } 102 103 static u32 g4x_infoframe_enable(unsigned int type) 104 { 105 switch (type) { 106 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 107 return VIDEO_DIP_ENABLE_GCP; 108 case HDMI_PACKET_TYPE_GAMUT_METADATA: 109 return VIDEO_DIP_ENABLE_GAMUT; 110 case DP_SDP_VSC: 111 return 0; 112 case DP_SDP_ADAPTIVE_SYNC: 113 return 0; 114 case HDMI_INFOFRAME_TYPE_AVI: 115 return VIDEO_DIP_ENABLE_AVI; 116 case HDMI_INFOFRAME_TYPE_SPD: 117 return VIDEO_DIP_ENABLE_SPD; 118 case HDMI_INFOFRAME_TYPE_VENDOR: 119 return VIDEO_DIP_ENABLE_VENDOR; 120 case HDMI_INFOFRAME_TYPE_DRM: 121 return 0; 122 default: 123 MISSING_CASE(type); 124 return 0; 125 } 126 } 127 128 static u32 hsw_infoframe_enable(unsigned int type) 129 { 130 switch (type) { 131 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 132 return VIDEO_DIP_ENABLE_GCP_HSW; 133 case HDMI_PACKET_TYPE_GAMUT_METADATA: 134 return VIDEO_DIP_ENABLE_GMP_HSW; 135 case DP_SDP_VSC: 136 return VIDEO_DIP_ENABLE_VSC_HSW; 137 case DP_SDP_ADAPTIVE_SYNC: 138 return VIDEO_DIP_ENABLE_AS_ADL; 139 case DP_SDP_PPS: 140 return VDIP_ENABLE_PPS; 141 case HDMI_INFOFRAME_TYPE_AVI: 142 return VIDEO_DIP_ENABLE_AVI_HSW; 143 case HDMI_INFOFRAME_TYPE_SPD: 144 return VIDEO_DIP_ENABLE_SPD_HSW; 145 case HDMI_INFOFRAME_TYPE_VENDOR: 146 return VIDEO_DIP_ENABLE_VS_HSW; 147 case HDMI_INFOFRAME_TYPE_DRM: 148 return VIDEO_DIP_ENABLE_DRM_GLK; 149 default: 150 MISSING_CASE(type); 151 return 0; 152 } 153 } 154 155 static i915_reg_t 156 hsw_dip_data_reg(struct intel_display *display, 157 enum transcoder cpu_transcoder, 158 unsigned int type, 159 int i) 160 { 161 switch (type) { 162 case HDMI_PACKET_TYPE_GAMUT_METADATA: 163 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 164 case DP_SDP_VSC: 165 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 166 case DP_SDP_ADAPTIVE_SYNC: 167 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 168 case DP_SDP_PPS: 169 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 170 case HDMI_INFOFRAME_TYPE_AVI: 171 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 172 case HDMI_INFOFRAME_TYPE_SPD: 173 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 174 case HDMI_INFOFRAME_TYPE_VENDOR: 175 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 176 case HDMI_INFOFRAME_TYPE_DRM: 177 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 178 default: 179 MISSING_CASE(type); 180 return INVALID_MMIO_REG; 181 } 182 } 183 184 static int hsw_dip_data_size(struct intel_display *display, 185 unsigned int type) 186 { 187 switch (type) { 188 case DP_SDP_VSC: 189 return VIDEO_DIP_VSC_DATA_SIZE; 190 case DP_SDP_ADAPTIVE_SYNC: 191 return VIDEO_DIP_ASYNC_DATA_SIZE; 192 case DP_SDP_PPS: 193 return VIDEO_DIP_PPS_DATA_SIZE; 194 case HDMI_PACKET_TYPE_GAMUT_METADATA: 195 if (DISPLAY_VER(display) >= 11) 196 return VIDEO_DIP_GMP_DATA_SIZE; 197 else 198 return VIDEO_DIP_DATA_SIZE; 199 default: 200 return VIDEO_DIP_DATA_SIZE; 201 } 202 } 203 204 static void g4x_write_infoframe(struct intel_encoder *encoder, 205 const struct intel_crtc_state *crtc_state, 206 unsigned int type, 207 const void *frame, ssize_t len) 208 { 209 struct intel_display *display = to_intel_display(encoder); 210 const u32 *data = frame; 211 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 212 int i; 213 214 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 215 "Writing DIP with CTL reg disabled\n"); 216 217 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 218 val |= g4x_infoframe_index(type); 219 220 val &= ~g4x_infoframe_enable(type); 221 222 intel_de_write(display, VIDEO_DIP_CTL, val); 223 224 for (i = 0; i < len; i += 4) { 225 intel_de_write(display, VIDEO_DIP_DATA, *data); 226 data++; 227 } 228 /* Write every possible data byte to force correct ECC calculation. */ 229 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 230 intel_de_write(display, VIDEO_DIP_DATA, 0); 231 232 val |= g4x_infoframe_enable(type); 233 val &= ~VIDEO_DIP_FREQ_MASK; 234 val |= VIDEO_DIP_FREQ_VSYNC; 235 236 intel_de_write(display, VIDEO_DIP_CTL, val); 237 intel_de_posting_read(display, VIDEO_DIP_CTL); 238 } 239 240 static void g4x_read_infoframe(struct intel_encoder *encoder, 241 const struct intel_crtc_state *crtc_state, 242 unsigned int type, 243 void *frame, ssize_t len) 244 { 245 struct intel_display *display = to_intel_display(encoder); 246 u32 *data = frame; 247 int i; 248 249 intel_de_rmw(display, VIDEO_DIP_CTL, 250 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 251 252 for (i = 0; i < len; i += 4) 253 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 254 } 255 256 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 257 const struct intel_crtc_state *pipe_config) 258 { 259 struct intel_display *display = to_intel_display(encoder); 260 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 261 262 if ((val & VIDEO_DIP_ENABLE) == 0) 263 return 0; 264 265 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 266 return 0; 267 268 return val & (VIDEO_DIP_ENABLE_AVI | 269 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 270 } 271 272 static void ibx_write_infoframe(struct intel_encoder *encoder, 273 const struct intel_crtc_state *crtc_state, 274 unsigned int type, 275 const void *frame, ssize_t len) 276 { 277 struct intel_display *display = to_intel_display(encoder); 278 const u32 *data = frame; 279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 280 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 281 u32 val = intel_de_read(display, reg); 282 int i; 283 284 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 285 "Writing DIP with CTL reg disabled\n"); 286 287 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 288 val |= g4x_infoframe_index(type); 289 290 val &= ~g4x_infoframe_enable(type); 291 292 intel_de_write(display, reg, val); 293 294 for (i = 0; i < len; i += 4) { 295 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 296 *data); 297 data++; 298 } 299 /* Write every possible data byte to force correct ECC calculation. */ 300 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 302 303 val |= g4x_infoframe_enable(type); 304 val &= ~VIDEO_DIP_FREQ_MASK; 305 val |= VIDEO_DIP_FREQ_VSYNC; 306 307 intel_de_write(display, reg, val); 308 intel_de_posting_read(display, reg); 309 } 310 311 static void ibx_read_infoframe(struct intel_encoder *encoder, 312 const struct intel_crtc_state *crtc_state, 313 unsigned int type, 314 void *frame, ssize_t len) 315 { 316 struct intel_display *display = to_intel_display(encoder); 317 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 318 u32 *data = frame; 319 int i; 320 321 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 322 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 323 324 for (i = 0; i < len; i += 4) 325 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 326 } 327 328 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 329 const struct intel_crtc_state *pipe_config) 330 { 331 struct intel_display *display = to_intel_display(encoder); 332 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 333 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 334 u32 val = intel_de_read(display, reg); 335 336 if ((val & VIDEO_DIP_ENABLE) == 0) 337 return 0; 338 339 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 340 return 0; 341 342 return val & (VIDEO_DIP_ENABLE_AVI | 343 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 344 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 345 } 346 347 static void cpt_write_infoframe(struct intel_encoder *encoder, 348 const struct intel_crtc_state *crtc_state, 349 unsigned int type, 350 const void *frame, ssize_t len) 351 { 352 struct intel_display *display = to_intel_display(encoder); 353 const u32 *data = frame; 354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 355 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 356 u32 val = intel_de_read(display, reg); 357 int i; 358 359 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 360 "Writing DIP with CTL reg disabled\n"); 361 362 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 363 val |= g4x_infoframe_index(type); 364 365 /* The DIP control register spec says that we need to update the AVI 366 * infoframe without clearing its enable bit */ 367 if (type != HDMI_INFOFRAME_TYPE_AVI) 368 val &= ~g4x_infoframe_enable(type); 369 370 intel_de_write(display, reg, val); 371 372 for (i = 0; i < len; i += 4) { 373 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 374 *data); 375 data++; 376 } 377 /* Write every possible data byte to force correct ECC calculation. */ 378 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 380 381 val |= g4x_infoframe_enable(type); 382 val &= ~VIDEO_DIP_FREQ_MASK; 383 val |= VIDEO_DIP_FREQ_VSYNC; 384 385 intel_de_write(display, reg, val); 386 intel_de_posting_read(display, reg); 387 } 388 389 static void cpt_read_infoframe(struct intel_encoder *encoder, 390 const struct intel_crtc_state *crtc_state, 391 unsigned int type, 392 void *frame, ssize_t len) 393 { 394 struct intel_display *display = to_intel_display(encoder); 395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 396 u32 *data = frame; 397 int i; 398 399 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 400 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 401 402 for (i = 0; i < len; i += 4) 403 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 404 } 405 406 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 407 const struct intel_crtc_state *pipe_config) 408 { 409 struct intel_display *display = to_intel_display(encoder); 410 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 411 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 412 413 if ((val & VIDEO_DIP_ENABLE) == 0) 414 return 0; 415 416 return val & (VIDEO_DIP_ENABLE_AVI | 417 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 418 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 419 } 420 421 static void vlv_write_infoframe(struct intel_encoder *encoder, 422 const struct intel_crtc_state *crtc_state, 423 unsigned int type, 424 const void *frame, ssize_t len) 425 { 426 struct intel_display *display = to_intel_display(encoder); 427 const u32 *data = frame; 428 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 429 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 430 u32 val = intel_de_read(display, reg); 431 int i; 432 433 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 434 "Writing DIP with CTL reg disabled\n"); 435 436 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 437 val |= g4x_infoframe_index(type); 438 439 val &= ~g4x_infoframe_enable(type); 440 441 intel_de_write(display, reg, val); 442 443 for (i = 0; i < len; i += 4) { 444 intel_de_write(display, 445 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 446 data++; 447 } 448 /* Write every possible data byte to force correct ECC calculation. */ 449 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 450 intel_de_write(display, 451 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 452 453 val |= g4x_infoframe_enable(type); 454 val &= ~VIDEO_DIP_FREQ_MASK; 455 val |= VIDEO_DIP_FREQ_VSYNC; 456 457 intel_de_write(display, reg, val); 458 intel_de_posting_read(display, reg); 459 } 460 461 static void vlv_read_infoframe(struct intel_encoder *encoder, 462 const struct intel_crtc_state *crtc_state, 463 unsigned int type, 464 void *frame, ssize_t len) 465 { 466 struct intel_display *display = to_intel_display(encoder); 467 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 468 u32 *data = frame; 469 int i; 470 471 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 472 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 473 474 for (i = 0; i < len; i += 4) 475 *data++ = intel_de_read(display, 476 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 477 } 478 479 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 480 const struct intel_crtc_state *pipe_config) 481 { 482 struct intel_display *display = to_intel_display(encoder); 483 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 484 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 485 486 if ((val & VIDEO_DIP_ENABLE) == 0) 487 return 0; 488 489 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 490 return 0; 491 492 return val & (VIDEO_DIP_ENABLE_AVI | 493 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 494 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 495 } 496 497 void hsw_write_infoframe(struct intel_encoder *encoder, 498 const struct intel_crtc_state *crtc_state, 499 unsigned int type, 500 const void *frame, ssize_t len) 501 { 502 struct intel_display *display = to_intel_display(encoder); 503 const u32 *data = frame; 504 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 505 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 506 int data_size; 507 int i; 508 u32 val = intel_de_read(display, ctl_reg); 509 510 data_size = hsw_dip_data_size(display, type); 511 512 drm_WARN_ON(display->drm, len > data_size); 513 514 val &= ~hsw_infoframe_enable(type); 515 intel_de_write(display, ctl_reg, val); 516 517 for (i = 0; i < len; i += 4) { 518 intel_de_write(display, 519 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 520 *data); 521 data++; 522 } 523 /* Write every possible data byte to force correct ECC calculation. */ 524 for (; i < data_size; i += 4) 525 intel_de_write(display, 526 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 527 0); 528 529 /* Wa_14013475917 */ 530 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 531 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 532 val |= hsw_infoframe_enable(type); 533 534 if (type == DP_SDP_VSC) 535 val |= VSC_DIP_HW_DATA_SW_HEA; 536 537 intel_de_write(display, ctl_reg, val); 538 intel_de_posting_read(display, ctl_reg); 539 } 540 541 void hsw_read_infoframe(struct intel_encoder *encoder, 542 const struct intel_crtc_state *crtc_state, 543 unsigned int type, void *frame, ssize_t len) 544 { 545 struct intel_display *display = to_intel_display(encoder); 546 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 547 u32 *data = frame; 548 int i; 549 550 for (i = 0; i < len; i += 4) 551 *data++ = intel_de_read(display, 552 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 553 } 554 555 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 556 const struct intel_crtc_state *pipe_config) 557 { 558 struct intel_display *display = to_intel_display(encoder); 559 u32 val = intel_de_read(display, 560 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 561 u32 mask; 562 563 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 564 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 565 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 566 567 if (DISPLAY_VER(display) >= 10) 568 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 569 570 if (HAS_AS_SDP(display)) 571 mask |= VIDEO_DIP_ENABLE_AS_ADL; 572 573 return val & mask; 574 } 575 576 static const u8 infoframe_type_to_idx[] = { 577 HDMI_PACKET_TYPE_GENERAL_CONTROL, 578 HDMI_PACKET_TYPE_GAMUT_METADATA, 579 DP_SDP_VSC, 580 DP_SDP_ADAPTIVE_SYNC, 581 HDMI_INFOFRAME_TYPE_AVI, 582 HDMI_INFOFRAME_TYPE_SPD, 583 HDMI_INFOFRAME_TYPE_VENDOR, 584 HDMI_INFOFRAME_TYPE_DRM, 585 }; 586 587 u32 intel_hdmi_infoframe_enable(unsigned int type) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 592 if (infoframe_type_to_idx[i] == type) 593 return BIT(i); 594 } 595 596 return 0; 597 } 598 599 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 600 const struct intel_crtc_state *crtc_state) 601 { 602 struct intel_display *display = to_intel_display(encoder); 603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 604 u32 val, ret = 0; 605 int i; 606 607 val = dig_port->infoframes_enabled(encoder, crtc_state); 608 609 /* map from hardware bits to dip idx */ 610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 611 unsigned int type = infoframe_type_to_idx[i]; 612 613 if (HAS_DDI(display)) { 614 if (val & hsw_infoframe_enable(type)) 615 ret |= BIT(i); 616 } else { 617 if (val & g4x_infoframe_enable(type)) 618 ret |= BIT(i); 619 } 620 } 621 622 return ret; 623 } 624 625 /* 626 * The data we write to the DIP data buffer registers is 1 byte bigger than the 627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 629 * used for both technologies. 630 * 631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 632 * DW1: DB3 | DB2 | DB1 | DB0 633 * DW2: DB7 | DB6 | DB5 | DB4 634 * DW3: ... 635 * 636 * (HB is Header Byte, DB is Data Byte) 637 * 638 * The hdmi pack() functions don't know about that hardware specific hole so we 639 * trick them by giving an offset into the buffer and moving back the header 640 * bytes by one. 641 */ 642 static void intel_write_infoframe(struct intel_encoder *encoder, 643 const struct intel_crtc_state *crtc_state, 644 enum hdmi_infoframe_type type, 645 const union hdmi_infoframe *frame) 646 { 647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 648 u8 buffer[VIDEO_DIP_DATA_SIZE]; 649 ssize_t len; 650 651 if ((crtc_state->infoframes.enable & 652 intel_hdmi_infoframe_enable(type)) == 0) 653 return; 654 655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 656 return; 657 658 /* see comment above for the reason for this offset */ 659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 660 if (drm_WARN_ON(encoder->base.dev, len < 0)) 661 return; 662 663 /* Insert the 'hole' (see big comment above) at position 3 */ 664 memmove(&buffer[0], &buffer[1], 3); 665 buffer[3] = 0; 666 len++; 667 668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 669 } 670 671 void intel_read_infoframe(struct intel_encoder *encoder, 672 const struct intel_crtc_state *crtc_state, 673 enum hdmi_infoframe_type type, 674 union hdmi_infoframe *frame) 675 { 676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 677 u8 buffer[VIDEO_DIP_DATA_SIZE]; 678 int ret; 679 680 if ((crtc_state->infoframes.enable & 681 intel_hdmi_infoframe_enable(type)) == 0) 682 return; 683 684 dig_port->read_infoframe(encoder, crtc_state, 685 type, buffer, sizeof(buffer)); 686 687 /* Fill the 'hole' (see big comment above) at position 3 */ 688 memmove(&buffer[1], &buffer[0], 3); 689 690 /* see comment above for the reason for this offset */ 691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 692 if (ret) { 693 drm_dbg_kms(encoder->base.dev, 694 "Failed to unpack infoframe type 0x%02x\n", type); 695 return; 696 } 697 698 if (frame->any.type != type) 699 drm_dbg_kms(encoder->base.dev, 700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 701 frame->any.type, type); 702 } 703 704 static bool 705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 706 struct intel_crtc_state *crtc_state, 707 struct drm_connector_state *conn_state) 708 { 709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 710 const struct drm_display_mode *adjusted_mode = 711 &crtc_state->hw.adjusted_mode; 712 struct drm_connector *connector = conn_state->connector; 713 int ret; 714 715 if (!crtc_state->has_infoframe) 716 return true; 717 718 crtc_state->infoframes.enable |= 719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 720 721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 722 adjusted_mode); 723 if (ret) 724 return false; 725 726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 727 frame->colorspace = HDMI_COLORSPACE_YUV420; 728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 729 frame->colorspace = HDMI_COLORSPACE_YUV444; 730 else 731 frame->colorspace = HDMI_COLORSPACE_RGB; 732 733 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 734 735 /* nonsense combination */ 736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 738 739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 740 drm_hdmi_avi_infoframe_quant_range(frame, connector, 741 adjusted_mode, 742 crtc_state->limited_color_range ? 743 HDMI_QUANTIZATION_RANGE_LIMITED : 744 HDMI_QUANTIZATION_RANGE_FULL); 745 } else { 746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 748 } 749 750 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 751 752 /* TODO: handle pixel repetition for YCBCR420 outputs */ 753 754 ret = hdmi_avi_infoframe_check(frame); 755 if (drm_WARN_ON(encoder->base.dev, ret)) 756 return false; 757 758 return true; 759 } 760 761 static bool 762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 763 struct intel_crtc_state *crtc_state, 764 struct drm_connector_state *conn_state) 765 { 766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 767 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 768 int ret; 769 770 if (!crtc_state->has_infoframe) 771 return true; 772 773 crtc_state->infoframes.enable |= 774 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 775 776 if (IS_DGFX(i915)) 777 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 778 else 779 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 780 781 if (drm_WARN_ON(encoder->base.dev, ret)) 782 return false; 783 784 frame->sdi = HDMI_SPD_SDI_PC; 785 786 ret = hdmi_spd_infoframe_check(frame); 787 if (drm_WARN_ON(encoder->base.dev, ret)) 788 return false; 789 790 return true; 791 } 792 793 static bool 794 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 795 struct intel_crtc_state *crtc_state, 796 struct drm_connector_state *conn_state) 797 { 798 struct hdmi_vendor_infoframe *frame = 799 &crtc_state->infoframes.hdmi.vendor.hdmi; 800 const struct drm_display_info *info = 801 &conn_state->connector->display_info; 802 int ret; 803 804 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 805 return true; 806 807 crtc_state->infoframes.enable |= 808 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 809 810 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 811 conn_state->connector, 812 &crtc_state->hw.adjusted_mode); 813 if (drm_WARN_ON(encoder->base.dev, ret)) 814 return false; 815 816 ret = hdmi_vendor_infoframe_check(frame); 817 if (drm_WARN_ON(encoder->base.dev, ret)) 818 return false; 819 820 return true; 821 } 822 823 static bool 824 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 825 struct intel_crtc_state *crtc_state, 826 struct drm_connector_state *conn_state) 827 { 828 struct intel_display *display = to_intel_display(encoder); 829 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 830 int ret; 831 832 if (DISPLAY_VER(display) < 10) 833 return true; 834 835 if (!crtc_state->has_infoframe) 836 return true; 837 838 if (!conn_state->hdr_output_metadata) 839 return true; 840 841 crtc_state->infoframes.enable |= 842 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 843 844 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 845 if (ret < 0) { 846 drm_dbg_kms(display->drm, 847 "couldn't set HDR metadata in infoframe\n"); 848 return false; 849 } 850 851 ret = hdmi_drm_infoframe_check(frame); 852 if (drm_WARN_ON(display->drm, ret)) 853 return false; 854 855 return true; 856 } 857 858 static void g4x_set_infoframes(struct intel_encoder *encoder, 859 bool enable, 860 const struct intel_crtc_state *crtc_state, 861 const struct drm_connector_state *conn_state) 862 { 863 struct intel_display *display = to_intel_display(encoder); 864 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 865 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 866 i915_reg_t reg = VIDEO_DIP_CTL; 867 u32 val = intel_de_read(display, reg); 868 u32 port = VIDEO_DIP_PORT(encoder->port); 869 870 assert_hdmi_port_disabled(intel_hdmi); 871 872 /* If the registers were not initialized yet, they might be zeroes, 873 * which means we're selecting the AVI DIP and we're setting its 874 * frequency to once. This seems to really confuse the HW and make 875 * things stop working (the register spec says the AVI always needs to 876 * be sent every VSync). So here we avoid writing to the register more 877 * than we need and also explicitly select the AVI DIP and explicitly 878 * set its frequency to every VSync. Avoiding to write it twice seems to 879 * be enough to solve the problem, but being defensive shouldn't hurt us 880 * either. */ 881 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 882 883 if (!enable) { 884 if (!(val & VIDEO_DIP_ENABLE)) 885 return; 886 if (port != (val & VIDEO_DIP_PORT_MASK)) { 887 drm_dbg_kms(display->drm, 888 "video DIP still enabled on port %c\n", 889 (val & VIDEO_DIP_PORT_MASK) >> 29); 890 return; 891 } 892 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 893 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 894 intel_de_write(display, reg, val); 895 intel_de_posting_read(display, reg); 896 return; 897 } 898 899 if (port != (val & VIDEO_DIP_PORT_MASK)) { 900 if (val & VIDEO_DIP_ENABLE) { 901 drm_dbg_kms(display->drm, 902 "video DIP already enabled on port %c\n", 903 (val & VIDEO_DIP_PORT_MASK) >> 29); 904 return; 905 } 906 val &= ~VIDEO_DIP_PORT_MASK; 907 val |= port; 908 } 909 910 val |= VIDEO_DIP_ENABLE; 911 val &= ~(VIDEO_DIP_ENABLE_AVI | 912 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 913 914 intel_de_write(display, reg, val); 915 intel_de_posting_read(display, reg); 916 917 intel_write_infoframe(encoder, crtc_state, 918 HDMI_INFOFRAME_TYPE_AVI, 919 &crtc_state->infoframes.avi); 920 intel_write_infoframe(encoder, crtc_state, 921 HDMI_INFOFRAME_TYPE_SPD, 922 &crtc_state->infoframes.spd); 923 intel_write_infoframe(encoder, crtc_state, 924 HDMI_INFOFRAME_TYPE_VENDOR, 925 &crtc_state->infoframes.hdmi); 926 } 927 928 /* 929 * Determine if default_phase=1 can be indicated in the GCP infoframe. 930 * 931 * From HDMI specification 1.4a: 932 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 933 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 934 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 935 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 936 * phase of 0 937 */ 938 static bool gcp_default_phase_possible(int pipe_bpp, 939 const struct drm_display_mode *mode) 940 { 941 unsigned int pixels_per_group; 942 943 switch (pipe_bpp) { 944 case 30: 945 /* 4 pixels in 5 clocks */ 946 pixels_per_group = 4; 947 break; 948 case 36: 949 /* 2 pixels in 3 clocks */ 950 pixels_per_group = 2; 951 break; 952 case 48: 953 /* 1 pixel in 2 clocks */ 954 pixels_per_group = 1; 955 break; 956 default: 957 /* phase information not relevant for 8bpc */ 958 return false; 959 } 960 961 return mode->crtc_hdisplay % pixels_per_group == 0 && 962 mode->crtc_htotal % pixels_per_group == 0 && 963 mode->crtc_hblank_start % pixels_per_group == 0 && 964 mode->crtc_hblank_end % pixels_per_group == 0 && 965 mode->crtc_hsync_start % pixels_per_group == 0 && 966 mode->crtc_hsync_end % pixels_per_group == 0 && 967 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 968 mode->crtc_htotal/2 % pixels_per_group == 0); 969 } 970 971 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 972 const struct intel_crtc_state *crtc_state, 973 const struct drm_connector_state *conn_state) 974 { 975 struct intel_display *display = to_intel_display(encoder); 976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 977 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 978 i915_reg_t reg; 979 980 if ((crtc_state->infoframes.enable & 981 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 982 return false; 983 984 if (HAS_DDI(display)) 985 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 986 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 987 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 988 else if (HAS_PCH_SPLIT(dev_priv)) 989 reg = TVIDEO_DIP_GCP(crtc->pipe); 990 else 991 return false; 992 993 intel_de_write(display, reg, crtc_state->infoframes.gcp); 994 995 return true; 996 } 997 998 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 999 struct intel_crtc_state *crtc_state) 1000 { 1001 struct intel_display *display = to_intel_display(encoder); 1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1003 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1004 i915_reg_t reg; 1005 1006 if ((crtc_state->infoframes.enable & 1007 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1008 return; 1009 1010 if (HAS_DDI(display)) 1011 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1012 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1013 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1014 else if (HAS_PCH_SPLIT(dev_priv)) 1015 reg = TVIDEO_DIP_GCP(crtc->pipe); 1016 else 1017 return; 1018 1019 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1020 } 1021 1022 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1023 struct intel_crtc_state *crtc_state, 1024 struct drm_connector_state *conn_state) 1025 { 1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1027 1028 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1029 return; 1030 1031 crtc_state->infoframes.enable |= 1032 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1033 1034 /* Indicate color indication for deep color mode */ 1035 if (crtc_state->pipe_bpp > 24) 1036 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1037 1038 /* Enable default_phase whenever the display mode is suitably aligned */ 1039 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1040 &crtc_state->hw.adjusted_mode)) 1041 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1042 } 1043 1044 static void ibx_set_infoframes(struct intel_encoder *encoder, 1045 bool enable, 1046 const struct intel_crtc_state *crtc_state, 1047 const struct drm_connector_state *conn_state) 1048 { 1049 struct intel_display *display = to_intel_display(encoder); 1050 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1051 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1052 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1053 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1054 u32 val = intel_de_read(display, reg); 1055 u32 port = VIDEO_DIP_PORT(encoder->port); 1056 1057 assert_hdmi_port_disabled(intel_hdmi); 1058 1059 /* See the big comment in g4x_set_infoframes() */ 1060 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1061 1062 if (!enable) { 1063 if (!(val & VIDEO_DIP_ENABLE)) 1064 return; 1065 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1066 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1067 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1068 intel_de_write(display, reg, val); 1069 intel_de_posting_read(display, reg); 1070 return; 1071 } 1072 1073 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1074 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1075 "DIP already enabled on port %c\n", 1076 (val & VIDEO_DIP_PORT_MASK) >> 29); 1077 val &= ~VIDEO_DIP_PORT_MASK; 1078 val |= port; 1079 } 1080 1081 val |= VIDEO_DIP_ENABLE; 1082 val &= ~(VIDEO_DIP_ENABLE_AVI | 1083 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1084 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1085 1086 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1087 val |= VIDEO_DIP_ENABLE_GCP; 1088 1089 intel_de_write(display, reg, val); 1090 intel_de_posting_read(display, reg); 1091 1092 intel_write_infoframe(encoder, crtc_state, 1093 HDMI_INFOFRAME_TYPE_AVI, 1094 &crtc_state->infoframes.avi); 1095 intel_write_infoframe(encoder, crtc_state, 1096 HDMI_INFOFRAME_TYPE_SPD, 1097 &crtc_state->infoframes.spd); 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_VENDOR, 1100 &crtc_state->infoframes.hdmi); 1101 } 1102 1103 static void cpt_set_infoframes(struct intel_encoder *encoder, 1104 bool enable, 1105 const struct intel_crtc_state *crtc_state, 1106 const struct drm_connector_state *conn_state) 1107 { 1108 struct intel_display *display = to_intel_display(encoder); 1109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1110 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1111 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1112 u32 val = intel_de_read(display, reg); 1113 1114 assert_hdmi_port_disabled(intel_hdmi); 1115 1116 /* See the big comment in g4x_set_infoframes() */ 1117 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1118 1119 if (!enable) { 1120 if (!(val & VIDEO_DIP_ENABLE)) 1121 return; 1122 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1123 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1124 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1125 intel_de_write(display, reg, val); 1126 intel_de_posting_read(display, reg); 1127 return; 1128 } 1129 1130 /* Set both together, unset both together: see the spec. */ 1131 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1132 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1133 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1134 1135 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1136 val |= VIDEO_DIP_ENABLE_GCP; 1137 1138 intel_de_write(display, reg, val); 1139 intel_de_posting_read(display, reg); 1140 1141 intel_write_infoframe(encoder, crtc_state, 1142 HDMI_INFOFRAME_TYPE_AVI, 1143 &crtc_state->infoframes.avi); 1144 intel_write_infoframe(encoder, crtc_state, 1145 HDMI_INFOFRAME_TYPE_SPD, 1146 &crtc_state->infoframes.spd); 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_VENDOR, 1149 &crtc_state->infoframes.hdmi); 1150 } 1151 1152 static void vlv_set_infoframes(struct intel_encoder *encoder, 1153 bool enable, 1154 const struct intel_crtc_state *crtc_state, 1155 const struct drm_connector_state *conn_state) 1156 { 1157 struct intel_display *display = to_intel_display(encoder); 1158 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1159 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1160 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1161 u32 val = intel_de_read(display, reg); 1162 u32 port = VIDEO_DIP_PORT(encoder->port); 1163 1164 assert_hdmi_port_disabled(intel_hdmi); 1165 1166 /* See the big comment in g4x_set_infoframes() */ 1167 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1168 1169 if (!enable) { 1170 if (!(val & VIDEO_DIP_ENABLE)) 1171 return; 1172 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1173 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1174 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1175 intel_de_write(display, reg, val); 1176 intel_de_posting_read(display, reg); 1177 return; 1178 } 1179 1180 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1181 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1182 "DIP already enabled on port %c\n", 1183 (val & VIDEO_DIP_PORT_MASK) >> 29); 1184 val &= ~VIDEO_DIP_PORT_MASK; 1185 val |= port; 1186 } 1187 1188 val |= VIDEO_DIP_ENABLE; 1189 val &= ~(VIDEO_DIP_ENABLE_AVI | 1190 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1191 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1192 1193 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1194 val |= VIDEO_DIP_ENABLE_GCP; 1195 1196 intel_de_write(display, reg, val); 1197 intel_de_posting_read(display, reg); 1198 1199 intel_write_infoframe(encoder, crtc_state, 1200 HDMI_INFOFRAME_TYPE_AVI, 1201 &crtc_state->infoframes.avi); 1202 intel_write_infoframe(encoder, crtc_state, 1203 HDMI_INFOFRAME_TYPE_SPD, 1204 &crtc_state->infoframes.spd); 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_VENDOR, 1207 &crtc_state->infoframes.hdmi); 1208 } 1209 1210 static void hsw_set_infoframes(struct intel_encoder *encoder, 1211 bool enable, 1212 const struct intel_crtc_state *crtc_state, 1213 const struct drm_connector_state *conn_state) 1214 { 1215 struct intel_display *display = to_intel_display(encoder); 1216 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1217 crtc_state->cpu_transcoder); 1218 u32 val = intel_de_read(display, reg); 1219 1220 assert_hdmi_transcoder_func_disabled(display, 1221 crtc_state->cpu_transcoder); 1222 1223 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1224 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1225 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1226 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1227 1228 if (!enable) { 1229 intel_de_write(display, reg, val); 1230 intel_de_posting_read(display, reg); 1231 return; 1232 } 1233 1234 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1235 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1236 1237 intel_de_write(display, reg, val); 1238 intel_de_posting_read(display, reg); 1239 1240 intel_write_infoframe(encoder, crtc_state, 1241 HDMI_INFOFRAME_TYPE_AVI, 1242 &crtc_state->infoframes.avi); 1243 intel_write_infoframe(encoder, crtc_state, 1244 HDMI_INFOFRAME_TYPE_SPD, 1245 &crtc_state->infoframes.spd); 1246 intel_write_infoframe(encoder, crtc_state, 1247 HDMI_INFOFRAME_TYPE_VENDOR, 1248 &crtc_state->infoframes.hdmi); 1249 intel_write_infoframe(encoder, crtc_state, 1250 HDMI_INFOFRAME_TYPE_DRM, 1251 &crtc_state->infoframes.drm); 1252 } 1253 1254 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1255 { 1256 struct intel_display *display = to_intel_display(hdmi); 1257 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1258 1259 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1260 return; 1261 1262 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1263 enable ? "Enabling" : "Disabling"); 1264 1265 drm_dp_dual_mode_set_tmds_output(display->drm, 1266 hdmi->dp_dual_mode.type, ddc, enable); 1267 } 1268 1269 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1270 unsigned int offset, void *buffer, size_t size) 1271 { 1272 struct intel_hdmi *hdmi = &dig_port->hdmi; 1273 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1274 int ret; 1275 u8 start = offset & 0xff; 1276 struct i2c_msg msgs[] = { 1277 { 1278 .addr = DRM_HDCP_DDC_ADDR, 1279 .flags = 0, 1280 .len = 1, 1281 .buf = &start, 1282 }, 1283 { 1284 .addr = DRM_HDCP_DDC_ADDR, 1285 .flags = I2C_M_RD, 1286 .len = size, 1287 .buf = buffer 1288 } 1289 }; 1290 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1291 if (ret == ARRAY_SIZE(msgs)) 1292 return 0; 1293 return ret >= 0 ? -EIO : ret; 1294 } 1295 1296 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1297 unsigned int offset, void *buffer, size_t size) 1298 { 1299 struct intel_hdmi *hdmi = &dig_port->hdmi; 1300 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1301 int ret; 1302 u8 *write_buf; 1303 struct i2c_msg msg; 1304 1305 write_buf = kzalloc(size + 1, GFP_KERNEL); 1306 if (!write_buf) 1307 return -ENOMEM; 1308 1309 write_buf[0] = offset & 0xff; 1310 memcpy(&write_buf[1], buffer, size); 1311 1312 msg.addr = DRM_HDCP_DDC_ADDR; 1313 msg.flags = 0, 1314 msg.len = size + 1, 1315 msg.buf = write_buf; 1316 1317 ret = i2c_transfer(ddc, &msg, 1); 1318 if (ret == 1) 1319 ret = 0; 1320 else if (ret >= 0) 1321 ret = -EIO; 1322 1323 kfree(write_buf); 1324 return ret; 1325 } 1326 1327 static 1328 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1329 u8 *an) 1330 { 1331 struct intel_display *display = to_intel_display(dig_port); 1332 struct intel_hdmi *hdmi = &dig_port->hdmi; 1333 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1334 int ret; 1335 1336 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1337 DRM_HDCP_AN_LEN); 1338 if (ret) { 1339 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1340 ret); 1341 return ret; 1342 } 1343 1344 ret = intel_gmbus_output_aksv(ddc); 1345 if (ret < 0) { 1346 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1347 return ret; 1348 } 1349 return 0; 1350 } 1351 1352 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1353 u8 *bksv) 1354 { 1355 struct intel_display *display = to_intel_display(dig_port); 1356 1357 int ret; 1358 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1359 DRM_HDCP_KSV_LEN); 1360 if (ret) 1361 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1362 ret); 1363 return ret; 1364 } 1365 1366 static 1367 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1368 u8 *bstatus) 1369 { 1370 struct intel_display *display = to_intel_display(dig_port); 1371 1372 int ret; 1373 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1374 bstatus, DRM_HDCP_BSTATUS_LEN); 1375 if (ret) 1376 drm_dbg_kms(display->drm, 1377 "Read bstatus over DDC failed (%d)\n", 1378 ret); 1379 return ret; 1380 } 1381 1382 static 1383 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1384 bool *repeater_present) 1385 { 1386 struct intel_display *display = to_intel_display(dig_port); 1387 int ret; 1388 u8 val; 1389 1390 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1391 if (ret) { 1392 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1393 ret); 1394 return ret; 1395 } 1396 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1397 return 0; 1398 } 1399 1400 static 1401 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1402 u8 *ri_prime) 1403 { 1404 struct intel_display *display = to_intel_display(dig_port); 1405 1406 int ret; 1407 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1408 ri_prime, DRM_HDCP_RI_LEN); 1409 if (ret) 1410 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1411 ret); 1412 return ret; 1413 } 1414 1415 static 1416 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1417 bool *ksv_ready) 1418 { 1419 struct intel_display *display = to_intel_display(dig_port); 1420 int ret; 1421 u8 val; 1422 1423 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1424 if (ret) { 1425 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1426 ret); 1427 return ret; 1428 } 1429 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1430 return 0; 1431 } 1432 1433 static 1434 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1435 int num_downstream, u8 *ksv_fifo) 1436 { 1437 struct intel_display *display = to_intel_display(dig_port); 1438 int ret; 1439 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1440 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1441 if (ret) { 1442 drm_dbg_kms(display->drm, 1443 "Read ksv fifo over DDC failed (%d)\n", ret); 1444 return ret; 1445 } 1446 return 0; 1447 } 1448 1449 static 1450 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1451 int i, u32 *part) 1452 { 1453 struct intel_display *display = to_intel_display(dig_port); 1454 int ret; 1455 1456 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1457 return -EINVAL; 1458 1459 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1460 part, DRM_HDCP_V_PRIME_PART_LEN); 1461 if (ret) 1462 drm_dbg_kms(display->drm, 1463 "Read V'[%d] over DDC failed (%d)\n", 1464 i, ret); 1465 return ret; 1466 } 1467 1468 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1469 enum transcoder cpu_transcoder) 1470 { 1471 struct intel_display *display = to_intel_display(connector); 1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1473 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1474 u32 scanline; 1475 int ret; 1476 1477 for (;;) { 1478 scanline = intel_de_read(display, 1479 PIPEDSL(display, crtc->pipe)); 1480 if (scanline > 100 && scanline < 200) 1481 break; 1482 usleep_range(25, 50); 1483 } 1484 1485 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1486 false, TRANS_DDI_HDCP_SIGNALLING); 1487 if (ret) { 1488 drm_err(display->drm, 1489 "Disable HDCP signalling failed (%d)\n", ret); 1490 return ret; 1491 } 1492 1493 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1494 true, TRANS_DDI_HDCP_SIGNALLING); 1495 if (ret) { 1496 drm_err(display->drm, 1497 "Enable HDCP signalling failed (%d)\n", ret); 1498 return ret; 1499 } 1500 1501 return 0; 1502 } 1503 1504 static 1505 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1506 enum transcoder cpu_transcoder, 1507 bool enable) 1508 { 1509 struct intel_display *display = to_intel_display(dig_port); 1510 struct intel_hdmi *hdmi = &dig_port->hdmi; 1511 struct intel_connector *connector = hdmi->attached_connector; 1512 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1513 int ret; 1514 1515 if (!enable) 1516 usleep_range(6, 60); /* Bspec says >= 6us */ 1517 1518 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1519 cpu_transcoder, enable, 1520 TRANS_DDI_HDCP_SIGNALLING); 1521 if (ret) { 1522 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1523 enable ? "Enable" : "Disable", ret); 1524 return ret; 1525 } 1526 1527 /* 1528 * WA: To fix incorrect positioning of the window of 1529 * opportunity and enc_en signalling in KABYLAKE. 1530 */ 1531 if (IS_KABYLAKE(dev_priv) && enable) 1532 return kbl_repositioning_enc_en_signal(connector, 1533 cpu_transcoder); 1534 1535 return 0; 1536 } 1537 1538 static 1539 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1540 struct intel_connector *connector) 1541 { 1542 struct intel_display *display = to_intel_display(dig_port); 1543 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1544 enum port port = dig_port->base.port; 1545 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1546 int ret; 1547 union { 1548 u32 reg; 1549 u8 shim[DRM_HDCP_RI_LEN]; 1550 } ri; 1551 1552 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1553 if (ret) 1554 return false; 1555 1556 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1557 1558 /* Wait for Ri prime match */ 1559 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1560 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1561 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1562 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1563 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1564 port))); 1565 return false; 1566 } 1567 return true; 1568 } 1569 1570 static 1571 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1572 struct intel_connector *connector) 1573 { 1574 struct intel_display *display = to_intel_display(dig_port); 1575 int retry; 1576 1577 for (retry = 0; retry < 3; retry++) 1578 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1579 return true; 1580 1581 drm_err(display->drm, "Link check failed\n"); 1582 return false; 1583 } 1584 1585 struct hdcp2_hdmi_msg_timeout { 1586 u8 msg_id; 1587 u16 timeout; 1588 }; 1589 1590 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1591 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1592 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1593 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1594 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1595 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1596 }; 1597 1598 static 1599 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1600 u8 *rx_status) 1601 { 1602 return intel_hdmi_hdcp_read(dig_port, 1603 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1604 rx_status, 1605 HDCP_2_2_HDMI_RXSTATUS_LEN); 1606 } 1607 1608 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1609 { 1610 int i; 1611 1612 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1613 if (is_paired) 1614 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1615 else 1616 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1617 } 1618 1619 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1620 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1621 return hdcp2_msg_timeout[i].timeout; 1622 } 1623 1624 return -EINVAL; 1625 } 1626 1627 static int 1628 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1629 u8 msg_id, bool *msg_ready, 1630 ssize_t *msg_sz) 1631 { 1632 struct intel_display *display = to_intel_display(dig_port); 1633 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1634 int ret; 1635 1636 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1637 if (ret < 0) { 1638 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1639 ret); 1640 return ret; 1641 } 1642 1643 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1644 rx_status[0]); 1645 1646 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1647 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1648 *msg_sz); 1649 else 1650 *msg_ready = *msg_sz; 1651 1652 return 0; 1653 } 1654 1655 static ssize_t 1656 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1657 u8 msg_id, bool paired) 1658 { 1659 struct intel_display *display = to_intel_display(dig_port); 1660 bool msg_ready = false; 1661 int timeout, ret; 1662 ssize_t msg_sz = 0; 1663 1664 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1665 if (timeout < 0) 1666 return timeout; 1667 1668 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1669 msg_id, &msg_ready, 1670 &msg_sz), 1671 !ret && msg_ready && msg_sz, timeout * 1000, 1672 1000, 5 * 1000); 1673 if (ret) 1674 drm_dbg_kms(display->drm, 1675 "msg_id: %d, ret: %d, timeout: %d\n", 1676 msg_id, ret, timeout); 1677 1678 return ret ? ret : msg_sz; 1679 } 1680 1681 static 1682 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1683 void *buf, size_t size) 1684 { 1685 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1686 unsigned int offset; 1687 1688 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1689 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1690 } 1691 1692 static 1693 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1694 u8 msg_id, void *buf, size_t size) 1695 { 1696 struct intel_display *display = to_intel_display(connector); 1697 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1698 struct intel_hdmi *hdmi = &dig_port->hdmi; 1699 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1700 unsigned int offset; 1701 ssize_t ret; 1702 1703 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1704 hdcp->is_paired); 1705 if (ret < 0) 1706 return ret; 1707 1708 /* 1709 * Available msg size should be equal to or lesser than the 1710 * available buffer. 1711 */ 1712 if (ret > size) { 1713 drm_dbg_kms(display->drm, 1714 "msg_sz(%zd) is more than exp size(%zu)\n", 1715 ret, size); 1716 return -EINVAL; 1717 } 1718 1719 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1720 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1721 if (ret) 1722 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1723 msg_id, ret); 1724 1725 return ret; 1726 } 1727 1728 static 1729 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1730 struct intel_connector *connector) 1731 { 1732 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1733 int ret; 1734 1735 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1736 if (ret) 1737 return ret; 1738 1739 /* 1740 * Re-auth request and Link Integrity Failures are represented by 1741 * same bit. i.e reauth_req. 1742 */ 1743 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1744 ret = HDCP_REAUTH_REQUEST; 1745 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1746 ret = HDCP_TOPOLOGY_CHANGE; 1747 1748 return ret; 1749 } 1750 1751 static 1752 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1753 bool *capable) 1754 { 1755 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1756 u8 hdcp2_version; 1757 int ret; 1758 1759 *capable = false; 1760 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1761 &hdcp2_version, sizeof(hdcp2_version)); 1762 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1763 *capable = true; 1764 1765 return ret; 1766 } 1767 1768 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1769 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1770 .read_bksv = intel_hdmi_hdcp_read_bksv, 1771 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1772 .repeater_present = intel_hdmi_hdcp_repeater_present, 1773 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1774 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1775 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1776 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1777 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1778 .check_link = intel_hdmi_hdcp_check_link, 1779 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1780 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1781 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1782 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1783 .protocol = HDCP_PROTOCOL_HDMI, 1784 }; 1785 1786 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1787 { 1788 struct intel_display *display = to_intel_display(encoder); 1789 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1790 int max_tmds_clock, vbt_max_tmds_clock; 1791 1792 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) 1793 max_tmds_clock = 600000; 1794 else if (DISPLAY_VER(display) >= 10) 1795 max_tmds_clock = 594000; 1796 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) 1797 max_tmds_clock = 300000; 1798 else if (DISPLAY_VER(display) >= 5) 1799 max_tmds_clock = 225000; 1800 else 1801 max_tmds_clock = 165000; 1802 1803 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1804 if (vbt_max_tmds_clock) 1805 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1806 1807 return max_tmds_clock; 1808 } 1809 1810 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1811 const struct drm_connector_state *conn_state) 1812 { 1813 struct intel_connector *connector = hdmi->attached_connector; 1814 1815 return connector->base.display_info.is_hdmi && 1816 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1817 } 1818 1819 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1820 { 1821 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1822 } 1823 1824 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1825 bool respect_downstream_limits, 1826 bool has_hdmi_sink) 1827 { 1828 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1829 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1830 1831 if (respect_downstream_limits) { 1832 struct intel_connector *connector = hdmi->attached_connector; 1833 const struct drm_display_info *info = &connector->base.display_info; 1834 1835 if (hdmi->dp_dual_mode.max_tmds_clock) 1836 max_tmds_clock = min(max_tmds_clock, 1837 hdmi->dp_dual_mode.max_tmds_clock); 1838 1839 if (info->max_tmds_clock) 1840 max_tmds_clock = min(max_tmds_clock, 1841 info->max_tmds_clock); 1842 else if (!has_hdmi_sink) 1843 max_tmds_clock = min(max_tmds_clock, 165000); 1844 } 1845 1846 return max_tmds_clock; 1847 } 1848 1849 static enum drm_mode_status 1850 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1851 int clock, bool respect_downstream_limits, 1852 bool has_hdmi_sink) 1853 { 1854 struct intel_display *display = to_intel_display(hdmi); 1855 struct drm_i915_private *dev_priv = to_i915(display->drm); 1856 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1857 1858 if (clock < 25000) 1859 return MODE_CLOCK_LOW; 1860 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1861 has_hdmi_sink)) 1862 return MODE_CLOCK_HIGH; 1863 1864 /* GLK DPLL can't generate 446-480 MHz */ 1865 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1866 return MODE_CLOCK_RANGE; 1867 1868 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1869 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1870 clock > 223333 && clock < 240000) 1871 return MODE_CLOCK_RANGE; 1872 1873 /* CHV DPLL can't generate 216-240 MHz */ 1874 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1875 return MODE_CLOCK_RANGE; 1876 1877 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1878 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1879 return MODE_CLOCK_RANGE; 1880 1881 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1882 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1883 return MODE_CLOCK_RANGE; 1884 1885 /* 1886 * SNPS PHYs' MPLLB table-based programming can only handle a fixed 1887 * set of link rates. 1888 * 1889 * FIXME: We will hopefully get an algorithmic way of programming 1890 * the MPLLB for HDMI in the future. 1891 */ 1892 if (DISPLAY_VER(display) >= 14) 1893 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); 1894 else if (IS_DG2(dev_priv)) 1895 return intel_snps_phy_check_hdmi_link_rate(clock); 1896 1897 return MODE_OK; 1898 } 1899 1900 int intel_hdmi_tmds_clock(int clock, int bpc, 1901 enum intel_output_format sink_format) 1902 { 1903 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1904 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1905 clock /= 2; 1906 1907 /* 1908 * Need to adjust the port link by: 1909 * 1.5x for 12bpc 1910 * 1.25x for 10bpc 1911 */ 1912 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1913 } 1914 1915 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1916 { 1917 switch (bpc) { 1918 case 12: 1919 return !HAS_GMCH(display); 1920 case 10: 1921 return DISPLAY_VER(display) >= 11; 1922 case 8: 1923 return true; 1924 default: 1925 MISSING_CASE(bpc); 1926 return false; 1927 } 1928 } 1929 1930 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, 1931 int bpc, bool has_hdmi_sink, 1932 enum intel_output_format sink_format) 1933 { 1934 const struct drm_display_info *info = &connector->display_info; 1935 const struct drm_hdmi_info *hdmi = &info->hdmi; 1936 1937 switch (bpc) { 1938 case 12: 1939 if (!has_hdmi_sink) 1940 return false; 1941 1942 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1943 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1944 else 1945 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1946 case 10: 1947 if (!has_hdmi_sink) 1948 return false; 1949 1950 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1951 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1952 else 1953 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1954 case 8: 1955 return true; 1956 default: 1957 MISSING_CASE(bpc); 1958 return false; 1959 } 1960 } 1961 1962 static enum drm_mode_status 1963 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1964 bool has_hdmi_sink, 1965 enum intel_output_format sink_format) 1966 { 1967 struct intel_display *display = to_intel_display(connector->dev); 1968 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1969 enum drm_mode_status status = MODE_OK; 1970 int bpc; 1971 1972 /* 1973 * Try all color depths since valid port clock range 1974 * can have holes. Any mode that can be used with at 1975 * least one color depth is accepted. 1976 */ 1977 for (bpc = 12; bpc >= 8; bpc -= 2) { 1978 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1979 1980 if (!intel_hdmi_source_bpc_possible(display, bpc)) 1981 continue; 1982 1983 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) 1984 continue; 1985 1986 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 1987 if (status == MODE_OK) 1988 return MODE_OK; 1989 } 1990 1991 /* can never happen */ 1992 drm_WARN_ON(display->drm, status == MODE_OK); 1993 1994 return status; 1995 } 1996 1997 static enum drm_mode_status 1998 intel_hdmi_mode_valid(struct drm_connector *connector, 1999 struct drm_display_mode *mode) 2000 { 2001 struct intel_display *display = to_intel_display(connector->dev); 2002 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2003 struct drm_i915_private *dev_priv = to_i915(display->drm); 2004 enum drm_mode_status status; 2005 int clock = mode->clock; 2006 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; 2007 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 2008 bool ycbcr_420_only; 2009 enum intel_output_format sink_format; 2010 2011 status = intel_cpu_transcoder_mode_valid(dev_priv, mode); 2012 if (status != MODE_OK) 2013 return status; 2014 2015 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2016 clock *= 2; 2017 2018 if (clock > max_dotclk) 2019 return MODE_CLOCK_HIGH; 2020 2021 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2022 if (!has_hdmi_sink) 2023 return MODE_CLOCK_LOW; 2024 clock *= 2; 2025 } 2026 2027 /* 2028 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2029 * enumerated only if FRL is supported. Current platforms do not support 2030 * FRL so prune the higher resolution modes that require doctclock more 2031 * than 600MHz. 2032 */ 2033 if (clock > 600000) 2034 return MODE_CLOCK_HIGH; 2035 2036 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 2037 2038 if (ycbcr_420_only) 2039 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2040 else 2041 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2042 2043 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2044 if (status != MODE_OK) { 2045 if (ycbcr_420_only || 2046 !connector->ycbcr_420_allowed || 2047 !drm_mode_is_420_also(&connector->display_info, mode)) 2048 return status; 2049 2050 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2051 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); 2052 if (status != MODE_OK) 2053 return status; 2054 } 2055 2056 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 2057 } 2058 2059 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2060 int bpc, bool has_hdmi_sink) 2061 { 2062 struct drm_atomic_state *state = crtc_state->uapi.state; 2063 struct drm_connector_state *connector_state; 2064 struct drm_connector *connector; 2065 int i; 2066 2067 for_each_new_connector_in_state(state, connector, connector_state, i) { 2068 if (connector_state->crtc != crtc_state->uapi.crtc) 2069 continue; 2070 2071 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, 2072 crtc_state->sink_format)) 2073 return false; 2074 } 2075 2076 return true; 2077 } 2078 2079 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2080 { 2081 struct intel_display *display = to_intel_display(crtc_state); 2082 const struct drm_display_mode *adjusted_mode = 2083 &crtc_state->hw.adjusted_mode; 2084 2085 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2086 return false; 2087 2088 /* Display Wa_1405510057:icl,ehl */ 2089 if (intel_hdmi_is_ycbcr420(crtc_state) && 2090 bpc == 10 && DISPLAY_VER(display) == 11 && 2091 (adjusted_mode->crtc_hblank_end - 2092 adjusted_mode->crtc_hblank_start) % 8 == 2) 2093 return false; 2094 2095 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2096 } 2097 2098 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2099 struct intel_crtc_state *crtc_state, 2100 int clock, bool respect_downstream_limits) 2101 { 2102 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2103 int bpc; 2104 2105 /* 2106 * pipe_bpp could already be below 8bpc due to FDI 2107 * bandwidth constraints. HDMI minimum is 8bpc however. 2108 */ 2109 bpc = max(crtc_state->pipe_bpp / 3, 8); 2110 2111 /* 2112 * We will never exceed downstream TMDS clock limits while 2113 * attempting deep color. If the user insists on forcing an 2114 * out of spec mode they will have to be satisfied with 8bpc. 2115 */ 2116 if (!respect_downstream_limits) 2117 bpc = 8; 2118 2119 for (; bpc >= 8; bpc -= 2) { 2120 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2121 crtc_state->sink_format); 2122 2123 if (hdmi_bpc_possible(crtc_state, bpc) && 2124 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2125 respect_downstream_limits, 2126 crtc_state->has_hdmi_sink) == MODE_OK) 2127 return bpc; 2128 } 2129 2130 return -EINVAL; 2131 } 2132 2133 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2134 struct intel_crtc_state *crtc_state, 2135 bool respect_downstream_limits) 2136 { 2137 struct intel_display *display = to_intel_display(encoder); 2138 const struct drm_display_mode *adjusted_mode = 2139 &crtc_state->hw.adjusted_mode; 2140 int bpc, clock = adjusted_mode->crtc_clock; 2141 2142 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2143 clock *= 2; 2144 2145 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2146 respect_downstream_limits); 2147 if (bpc < 0) 2148 return bpc; 2149 2150 crtc_state->port_clock = 2151 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2152 2153 /* 2154 * pipe_bpp could already be below 8bpc due to 2155 * FDI bandwidth constraints. We shouldn't bump it 2156 * back up to the HDMI minimum 8bpc in that case. 2157 */ 2158 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2159 2160 drm_dbg_kms(display->drm, 2161 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2162 bpc, crtc_state->pipe_bpp); 2163 2164 return 0; 2165 } 2166 2167 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2168 const struct drm_connector_state *conn_state) 2169 { 2170 const struct intel_digital_connector_state *intel_conn_state = 2171 to_intel_digital_connector_state(conn_state); 2172 const struct drm_display_mode *adjusted_mode = 2173 &crtc_state->hw.adjusted_mode; 2174 2175 /* 2176 * Our YCbCr output is always limited range. 2177 * crtc_state->limited_color_range only applies to RGB, 2178 * and it must never be set for YCbCr or we risk setting 2179 * some conflicting bits in TRANSCONF which will mess up 2180 * the colors on the monitor. 2181 */ 2182 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2183 return false; 2184 2185 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2186 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2187 return crtc_state->has_hdmi_sink && 2188 drm_default_rgb_quant_range(adjusted_mode) == 2189 HDMI_QUANTIZATION_RANGE_LIMITED; 2190 } else { 2191 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2192 } 2193 } 2194 2195 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2196 const struct intel_crtc_state *crtc_state, 2197 const struct drm_connector_state *conn_state) 2198 { 2199 struct drm_connector *connector = conn_state->connector; 2200 const struct intel_digital_connector_state *intel_conn_state = 2201 to_intel_digital_connector_state(conn_state); 2202 2203 if (!crtc_state->has_hdmi_sink) 2204 return false; 2205 2206 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2207 return connector->display_info.has_audio; 2208 else 2209 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2210 } 2211 2212 static enum intel_output_format 2213 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2214 struct intel_connector *connector, 2215 bool ycbcr_420_output) 2216 { 2217 if (!crtc_state->has_hdmi_sink) 2218 return INTEL_OUTPUT_FORMAT_RGB; 2219 2220 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2221 return INTEL_OUTPUT_FORMAT_YCBCR420; 2222 else 2223 return INTEL_OUTPUT_FORMAT_RGB; 2224 } 2225 2226 static enum intel_output_format 2227 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2228 { 2229 return crtc_state->sink_format; 2230 } 2231 2232 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2233 struct intel_crtc_state *crtc_state, 2234 const struct drm_connector_state *conn_state, 2235 bool respect_downstream_limits) 2236 { 2237 struct intel_display *display = to_intel_display(encoder); 2238 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2239 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2240 const struct drm_display_info *info = &connector->base.display_info; 2241 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2242 int ret; 2243 2244 crtc_state->sink_format = 2245 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2246 2247 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2248 drm_dbg_kms(display->drm, 2249 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2250 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2251 } 2252 2253 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2254 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2255 if (ret) { 2256 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2257 !crtc_state->has_hdmi_sink || 2258 !connector->base.ycbcr_420_allowed || 2259 !drm_mode_is_420_also(info, adjusted_mode)) 2260 return ret; 2261 2262 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2263 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2264 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2265 } 2266 2267 return ret; 2268 } 2269 2270 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2271 { 2272 return crtc_state->uapi.encoder_mask && 2273 !is_power_of_2(crtc_state->uapi.encoder_mask); 2274 } 2275 2276 static bool source_supports_scrambling(struct intel_encoder *encoder) 2277 { 2278 /* 2279 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2280 * scrambling is supported. 2281 * But there seem to be cases where certain platforms that support 2282 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2283 * capped by VBT to less than 340MHz. 2284 * 2285 * In such cases when an HDMI2.0 sink is connected, it creates a 2286 * problem : the platform and the sink both support scrambling but the 2287 * HDMI 1.4 retimer chip doesn't. 2288 * 2289 * So go for scrambling, based on the max tmds clock taking into account, 2290 * restrictions coming from VBT. 2291 */ 2292 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2293 } 2294 2295 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2296 const struct intel_crtc_state *crtc_state, 2297 const struct drm_connector_state *conn_state) 2298 { 2299 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2300 2301 return intel_has_hdmi_sink(hdmi, conn_state) && 2302 !intel_hdmi_is_cloned(crtc_state); 2303 } 2304 2305 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2306 struct intel_crtc_state *pipe_config, 2307 struct drm_connector_state *conn_state) 2308 { 2309 struct intel_display *display = to_intel_display(encoder); 2310 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2311 struct drm_connector *connector = conn_state->connector; 2312 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2313 int ret; 2314 2315 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2316 return -EINVAL; 2317 2318 if (!connector->interlace_allowed && 2319 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2320 return -EINVAL; 2321 2322 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2323 2324 if (pipe_config->has_hdmi_sink) 2325 pipe_config->has_infoframe = true; 2326 2327 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2328 pipe_config->pixel_multiplier = 2; 2329 2330 pipe_config->has_audio = 2331 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2332 intel_audio_compute_config(encoder, pipe_config, conn_state); 2333 2334 /* 2335 * Try to respect downstream TMDS clock limits first, if 2336 * that fails assume the user might know something we don't. 2337 */ 2338 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2339 if (ret) 2340 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2341 if (ret) { 2342 drm_dbg_kms(display->drm, 2343 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2344 pipe_config->hw.adjusted_mode.crtc_clock); 2345 return ret; 2346 } 2347 2348 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2349 ret = intel_panel_fitting(pipe_config, conn_state); 2350 if (ret) 2351 return ret; 2352 } 2353 2354 pipe_config->limited_color_range = 2355 intel_hdmi_limited_color_range(pipe_config, conn_state); 2356 2357 if (conn_state->picture_aspect_ratio) 2358 adjusted_mode->picture_aspect_ratio = 2359 conn_state->picture_aspect_ratio; 2360 2361 pipe_config->lane_count = 4; 2362 2363 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2364 if (scdc->scrambling.low_rates) 2365 pipe_config->hdmi_scrambling = true; 2366 2367 if (pipe_config->port_clock > 340000) { 2368 pipe_config->hdmi_scrambling = true; 2369 pipe_config->hdmi_high_tmds_clock_ratio = true; 2370 } 2371 } 2372 2373 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2374 conn_state); 2375 2376 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2377 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2378 return -EINVAL; 2379 } 2380 2381 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2382 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2383 return -EINVAL; 2384 } 2385 2386 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2387 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2388 return -EINVAL; 2389 } 2390 2391 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2392 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2393 return -EINVAL; 2394 } 2395 2396 return 0; 2397 } 2398 2399 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2400 { 2401 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2402 2403 /* 2404 * Give a hand to buggy BIOSen which forget to turn 2405 * the TMDS output buffers back on after a reboot. 2406 */ 2407 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2408 } 2409 2410 static void 2411 intel_hdmi_unset_edid(struct drm_connector *connector) 2412 { 2413 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2414 2415 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2416 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2417 2418 drm_edid_free(to_intel_connector(connector)->detect_edid); 2419 to_intel_connector(connector)->detect_edid = NULL; 2420 } 2421 2422 static void 2423 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) 2424 { 2425 struct intel_display *display = to_intel_display(connector->dev); 2426 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2427 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2428 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2429 struct i2c_adapter *ddc = connector->ddc; 2430 enum drm_dp_dual_mode_type type; 2431 2432 type = drm_dp_dual_mode_detect(display->drm, ddc); 2433 2434 /* 2435 * Type 1 DVI adaptors are not required to implement any 2436 * registers, so we can't always detect their presence. 2437 * Ideally we should be able to check the state of the 2438 * CONFIG1 pin, but no such luck on our hardware. 2439 * 2440 * The only method left to us is to check the VBT to see 2441 * if the port is a dual mode capable DP port. 2442 */ 2443 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2444 if (!connector->force && 2445 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2446 drm_dbg_kms(display->drm, 2447 "Assuming DP dual mode adaptor presence based on VBT\n"); 2448 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2449 } else { 2450 type = DRM_DP_DUAL_MODE_NONE; 2451 } 2452 } 2453 2454 if (type == DRM_DP_DUAL_MODE_NONE) 2455 return; 2456 2457 hdmi->dp_dual_mode.type = type; 2458 hdmi->dp_dual_mode.max_tmds_clock = 2459 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2460 2461 drm_dbg_kms(display->drm, 2462 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2463 drm_dp_get_dual_mode_type_name(type), 2464 hdmi->dp_dual_mode.max_tmds_clock); 2465 2466 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2467 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && 2468 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2469 drm_dbg_kms(display->drm, 2470 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2471 hdmi->dp_dual_mode.max_tmds_clock = 0; 2472 } 2473 } 2474 2475 static bool 2476 intel_hdmi_set_edid(struct drm_connector *connector) 2477 { 2478 struct intel_display *display = to_intel_display(connector->dev); 2479 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2480 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2481 struct i2c_adapter *ddc = connector->ddc; 2482 intel_wakeref_t wakeref; 2483 const struct drm_edid *drm_edid; 2484 bool connected = false; 2485 2486 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2487 2488 drm_edid = drm_edid_read_ddc(connector, ddc); 2489 2490 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2491 drm_dbg_kms(display->drm, 2492 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2493 intel_gmbus_force_bit(ddc, true); 2494 drm_edid = drm_edid_read_ddc(connector, ddc); 2495 intel_gmbus_force_bit(ddc, false); 2496 } 2497 2498 /* Below we depend on display info having been updated */ 2499 drm_edid_connector_update(connector, drm_edid); 2500 2501 to_intel_connector(connector)->detect_edid = drm_edid; 2502 2503 if (drm_edid_is_digital(drm_edid)) { 2504 intel_hdmi_dp_dual_mode_detect(connector); 2505 2506 connected = true; 2507 } 2508 2509 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2510 2511 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2512 connector->display_info.source_physical_address); 2513 2514 return connected; 2515 } 2516 2517 static enum drm_connector_status 2518 intel_hdmi_detect(struct drm_connector *connector, bool force) 2519 { 2520 struct intel_display *display = to_intel_display(connector->dev); 2521 enum drm_connector_status status = connector_status_disconnected; 2522 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2523 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2524 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2525 intel_wakeref_t wakeref; 2526 2527 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2528 connector->base.id, connector->name); 2529 2530 if (!intel_display_device_enabled(dev_priv)) 2531 return connector_status_disconnected; 2532 2533 if (!intel_display_driver_check_access(dev_priv)) 2534 return connector->status; 2535 2536 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2537 2538 if (DISPLAY_VER(display) >= 11 && 2539 !intel_digital_port_connected(encoder)) 2540 goto out; 2541 2542 intel_hdmi_unset_edid(connector); 2543 2544 if (intel_hdmi_set_edid(connector)) 2545 status = connector_status_connected; 2546 2547 out: 2548 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2549 2550 if (status != connector_status_connected) 2551 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2552 2553 return status; 2554 } 2555 2556 static void 2557 intel_hdmi_force(struct drm_connector *connector) 2558 { 2559 struct intel_display *display = to_intel_display(connector->dev); 2560 struct drm_i915_private *i915 = to_i915(connector->dev); 2561 2562 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2563 connector->base.id, connector->name); 2564 2565 if (!intel_display_driver_check_access(i915)) 2566 return; 2567 2568 intel_hdmi_unset_edid(connector); 2569 2570 if (connector->status != connector_status_connected) 2571 return; 2572 2573 intel_hdmi_set_edid(connector); 2574 } 2575 2576 static int intel_hdmi_get_modes(struct drm_connector *connector) 2577 { 2578 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2579 return drm_edid_connector_add_modes(connector); 2580 } 2581 2582 static int 2583 intel_hdmi_connector_register(struct drm_connector *connector) 2584 { 2585 int ret; 2586 2587 ret = intel_connector_register(connector); 2588 if (ret) 2589 return ret; 2590 2591 return ret; 2592 } 2593 2594 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2595 { 2596 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2597 2598 cec_notifier_conn_unregister(n); 2599 2600 intel_connector_unregister(connector); 2601 } 2602 2603 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2604 .detect = intel_hdmi_detect, 2605 .force = intel_hdmi_force, 2606 .fill_modes = drm_helper_probe_single_connector_modes, 2607 .atomic_get_property = intel_digital_connector_atomic_get_property, 2608 .atomic_set_property = intel_digital_connector_atomic_set_property, 2609 .late_register = intel_hdmi_connector_register, 2610 .early_unregister = intel_hdmi_connector_unregister, 2611 .destroy = intel_connector_destroy, 2612 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2613 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2614 }; 2615 2616 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, 2617 struct drm_atomic_state *state) 2618 { 2619 struct intel_display *display = to_intel_display(connector->dev); 2620 2621 if (HAS_DDI(display)) 2622 return intel_digital_connector_atomic_check(connector, state); 2623 else 2624 return g4x_hdmi_connector_atomic_check(connector, state); 2625 } 2626 2627 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2628 .get_modes = intel_hdmi_get_modes, 2629 .mode_valid = intel_hdmi_mode_valid, 2630 .atomic_check = intel_hdmi_connector_atomic_check, 2631 }; 2632 2633 static void 2634 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2635 { 2636 struct intel_display *display = to_intel_display(intel_hdmi); 2637 2638 intel_attach_force_audio_property(connector); 2639 intel_attach_broadcast_rgb_property(connector); 2640 intel_attach_aspect_ratio_property(connector); 2641 2642 intel_attach_hdmi_colorspace_property(connector); 2643 drm_connector_attach_content_type_property(connector); 2644 2645 if (DISPLAY_VER(display) >= 10) 2646 drm_connector_attach_hdr_output_metadata_property(connector); 2647 2648 if (!HAS_GMCH(display)) 2649 drm_connector_attach_max_bpc_property(connector, 8, 12); 2650 } 2651 2652 /* 2653 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2654 * @encoder: intel_encoder 2655 * @connector: drm_connector 2656 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2657 * or reset the high tmds clock ratio for scrambling 2658 * @scrambling: bool to Indicate if the function needs to set or reset 2659 * sink scrambling 2660 * 2661 * This function handles scrambling on HDMI 2.0 capable sinks. 2662 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2663 * it enables scrambling. This should be called before enabling the HDMI 2664 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2665 * detect a scrambled clock within 100 ms. 2666 * 2667 * Returns: 2668 * True on success, false on failure. 2669 */ 2670 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2671 struct drm_connector *connector, 2672 bool high_tmds_clock_ratio, 2673 bool scrambling) 2674 { 2675 struct intel_display *display = to_intel_display(encoder); 2676 struct drm_scrambling *sink_scrambling = 2677 &connector->display_info.hdmi.scdc.scrambling; 2678 2679 if (!sink_scrambling->supported) 2680 return true; 2681 2682 drm_dbg_kms(display->drm, 2683 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2684 connector->base.id, connector->name, 2685 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2686 2687 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2688 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && 2689 drm_scdc_set_scrambling(connector, scrambling); 2690 } 2691 2692 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2693 { 2694 enum port port = encoder->port; 2695 u8 ddc_pin; 2696 2697 switch (port) { 2698 case PORT_B: 2699 ddc_pin = GMBUS_PIN_DPB; 2700 break; 2701 case PORT_C: 2702 ddc_pin = GMBUS_PIN_DPC; 2703 break; 2704 case PORT_D: 2705 ddc_pin = GMBUS_PIN_DPD_CHV; 2706 break; 2707 default: 2708 MISSING_CASE(port); 2709 ddc_pin = GMBUS_PIN_DPB; 2710 break; 2711 } 2712 return ddc_pin; 2713 } 2714 2715 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2716 { 2717 enum port port = encoder->port; 2718 u8 ddc_pin; 2719 2720 switch (port) { 2721 case PORT_B: 2722 ddc_pin = GMBUS_PIN_1_BXT; 2723 break; 2724 case PORT_C: 2725 ddc_pin = GMBUS_PIN_2_BXT; 2726 break; 2727 default: 2728 MISSING_CASE(port); 2729 ddc_pin = GMBUS_PIN_1_BXT; 2730 break; 2731 } 2732 return ddc_pin; 2733 } 2734 2735 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2736 { 2737 enum port port = encoder->port; 2738 u8 ddc_pin; 2739 2740 switch (port) { 2741 case PORT_B: 2742 ddc_pin = GMBUS_PIN_1_BXT; 2743 break; 2744 case PORT_C: 2745 ddc_pin = GMBUS_PIN_2_BXT; 2746 break; 2747 case PORT_D: 2748 ddc_pin = GMBUS_PIN_4_CNP; 2749 break; 2750 case PORT_F: 2751 ddc_pin = GMBUS_PIN_3_BXT; 2752 break; 2753 default: 2754 MISSING_CASE(port); 2755 ddc_pin = GMBUS_PIN_1_BXT; 2756 break; 2757 } 2758 return ddc_pin; 2759 } 2760 2761 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2762 { 2763 struct intel_display *display = to_intel_display(encoder); 2764 enum port port = encoder->port; 2765 2766 if (intel_encoder_is_combo(encoder)) 2767 return GMBUS_PIN_1_BXT + port; 2768 else if (intel_encoder_is_tc(encoder)) 2769 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2770 2771 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2772 return GMBUS_PIN_2_BXT; 2773 } 2774 2775 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2776 { 2777 enum phy phy = intel_encoder_to_phy(encoder); 2778 u8 ddc_pin; 2779 2780 switch (phy) { 2781 case PHY_A: 2782 ddc_pin = GMBUS_PIN_1_BXT; 2783 break; 2784 case PHY_B: 2785 ddc_pin = GMBUS_PIN_2_BXT; 2786 break; 2787 case PHY_C: 2788 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2789 break; 2790 default: 2791 MISSING_CASE(phy); 2792 ddc_pin = GMBUS_PIN_1_BXT; 2793 break; 2794 } 2795 return ddc_pin; 2796 } 2797 2798 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2799 { 2800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2801 enum phy phy = intel_encoder_to_phy(encoder); 2802 2803 WARN_ON(encoder->port == PORT_C); 2804 2805 /* 2806 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2807 * final two outputs use type-c pins, even though they're actually 2808 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2809 * all outputs. 2810 */ 2811 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2812 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2813 2814 return GMBUS_PIN_1_BXT + phy; 2815 } 2816 2817 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2818 { 2819 struct intel_display *display = to_intel_display(encoder); 2820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2821 enum phy phy = intel_encoder_to_phy(encoder); 2822 2823 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2824 2825 /* 2826 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2827 * final two outputs use type-c pins, even though they're actually 2828 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2829 * all outputs. 2830 */ 2831 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2832 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2833 2834 return GMBUS_PIN_1_BXT + phy; 2835 } 2836 2837 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2838 { 2839 return intel_encoder_to_phy(encoder) + 1; 2840 } 2841 2842 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2843 { 2844 enum phy phy = intel_encoder_to_phy(encoder); 2845 2846 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2847 2848 /* 2849 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2850 * except first combo output. 2851 */ 2852 if (phy == PHY_A) 2853 return GMBUS_PIN_1_BXT; 2854 2855 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2856 } 2857 2858 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2859 { 2860 enum port port = encoder->port; 2861 u8 ddc_pin; 2862 2863 switch (port) { 2864 case PORT_B: 2865 ddc_pin = GMBUS_PIN_DPB; 2866 break; 2867 case PORT_C: 2868 ddc_pin = GMBUS_PIN_DPC; 2869 break; 2870 case PORT_D: 2871 ddc_pin = GMBUS_PIN_DPD; 2872 break; 2873 default: 2874 MISSING_CASE(port); 2875 ddc_pin = GMBUS_PIN_DPB; 2876 break; 2877 } 2878 return ddc_pin; 2879 } 2880 2881 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2882 { 2883 struct intel_display *display = to_intel_display(encoder); 2884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2885 u8 ddc_pin; 2886 2887 if (IS_ALDERLAKE_S(dev_priv)) 2888 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2889 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2890 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2891 else if (IS_ROCKETLAKE(dev_priv)) 2892 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2893 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) 2894 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2895 else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) && 2896 HAS_PCH_TGP(dev_priv)) 2897 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2898 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2899 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2900 else if (HAS_PCH_CNP(dev_priv)) 2901 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2902 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2903 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2904 else if (IS_CHERRYVIEW(dev_priv)) 2905 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2906 else 2907 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2908 2909 return ddc_pin; 2910 } 2911 2912 static struct intel_encoder * 2913 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2914 { 2915 struct intel_display *display = to_intel_display(encoder); 2916 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2917 struct intel_encoder *other; 2918 2919 for_each_intel_encoder(display->drm, other) { 2920 struct intel_connector *connector; 2921 2922 if (other == encoder) 2923 continue; 2924 2925 if (!intel_encoder_is_dig_port(other)) 2926 continue; 2927 2928 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2929 2930 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) 2931 return other; 2932 } 2933 2934 return NULL; 2935 } 2936 2937 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2938 { 2939 struct intel_display *display = to_intel_display(encoder); 2940 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2941 struct intel_encoder *other; 2942 const char *source; 2943 u8 ddc_pin; 2944 2945 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2946 source = "VBT"; 2947 2948 if (!ddc_pin) { 2949 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2950 source = "platform default"; 2951 } 2952 2953 if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) { 2954 drm_dbg_kms(display->drm, 2955 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2956 encoder->base.base.id, encoder->base.name, ddc_pin); 2957 return 0; 2958 } 2959 2960 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2961 if (other) { 2962 drm_dbg_kms(display->drm, 2963 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2964 encoder->base.base.id, encoder->base.name, ddc_pin, 2965 other->base.base.id, other->base.name); 2966 return 0; 2967 } 2968 2969 drm_dbg_kms(display->drm, 2970 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2971 encoder->base.base.id, encoder->base.name, 2972 ddc_pin, source); 2973 2974 return ddc_pin; 2975 } 2976 2977 void intel_infoframe_init(struct intel_digital_port *dig_port) 2978 { 2979 struct intel_display *display = to_intel_display(dig_port); 2980 struct drm_i915_private *dev_priv = 2981 to_i915(dig_port->base.base.dev); 2982 2983 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2984 dig_port->write_infoframe = vlv_write_infoframe; 2985 dig_port->read_infoframe = vlv_read_infoframe; 2986 dig_port->set_infoframes = vlv_set_infoframes; 2987 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2988 } else if (IS_G4X(dev_priv)) { 2989 dig_port->write_infoframe = g4x_write_infoframe; 2990 dig_port->read_infoframe = g4x_read_infoframe; 2991 dig_port->set_infoframes = g4x_set_infoframes; 2992 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2993 } else if (HAS_DDI(display)) { 2994 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 2995 dig_port->write_infoframe = lspcon_write_infoframe; 2996 dig_port->read_infoframe = lspcon_read_infoframe; 2997 dig_port->set_infoframes = lspcon_set_infoframes; 2998 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2999 } else { 3000 dig_port->write_infoframe = hsw_write_infoframe; 3001 dig_port->read_infoframe = hsw_read_infoframe; 3002 dig_port->set_infoframes = hsw_set_infoframes; 3003 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3004 } 3005 } else if (HAS_PCH_IBX(dev_priv)) { 3006 dig_port->write_infoframe = ibx_write_infoframe; 3007 dig_port->read_infoframe = ibx_read_infoframe; 3008 dig_port->set_infoframes = ibx_set_infoframes; 3009 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3010 } else { 3011 dig_port->write_infoframe = cpt_write_infoframe; 3012 dig_port->read_infoframe = cpt_read_infoframe; 3013 dig_port->set_infoframes = cpt_set_infoframes; 3014 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3015 } 3016 } 3017 3018 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3019 struct intel_connector *intel_connector) 3020 { 3021 struct intel_display *display = to_intel_display(dig_port); 3022 struct drm_connector *connector = &intel_connector->base; 3023 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3024 struct intel_encoder *intel_encoder = &dig_port->base; 3025 struct drm_device *dev = intel_encoder->base.dev; 3026 struct drm_i915_private *dev_priv = to_i915(dev); 3027 enum port port = intel_encoder->port; 3028 struct cec_connector_info conn_info; 3029 u8 ddc_pin; 3030 3031 drm_dbg_kms(display->drm, 3032 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3033 intel_encoder->base.base.id, intel_encoder->base.name); 3034 3035 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3036 return; 3037 3038 if (drm_WARN(dev, dig_port->max_lanes < 4, 3039 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3040 dig_port->max_lanes, intel_encoder->base.base.id, 3041 intel_encoder->base.name)) 3042 return; 3043 3044 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3045 if (!ddc_pin) 3046 return; 3047 3048 drm_connector_init_with_ddc(dev, connector, 3049 &intel_hdmi_connector_funcs, 3050 DRM_MODE_CONNECTOR_HDMIA, 3051 intel_gmbus_get_adapter(dev_priv, ddc_pin)); 3052 3053 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3054 3055 if (DISPLAY_VER(display) < 12) 3056 connector->interlace_allowed = true; 3057 3058 connector->stereo_allowed = true; 3059 3060 if (DISPLAY_VER(display) >= 10) 3061 connector->ycbcr_420_allowed = true; 3062 3063 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3064 intel_connector->base.polled = intel_connector->polled; 3065 3066 if (HAS_DDI(display)) 3067 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3068 else 3069 intel_connector->get_hw_state = intel_connector_get_hw_state; 3070 3071 intel_hdmi_add_properties(intel_hdmi, connector); 3072 3073 intel_connector_attach_encoder(intel_connector, intel_encoder); 3074 intel_hdmi->attached_connector = intel_connector; 3075 3076 if (is_hdcp_supported(dev_priv, port)) { 3077 int ret = intel_hdcp_init(intel_connector, dig_port, 3078 &intel_hdmi_hdcp_shim); 3079 if (ret) 3080 drm_dbg_kms(display->drm, 3081 "HDCP init failed, skipping.\n"); 3082 } 3083 3084 cec_fill_conn_info_from_drm(&conn_info, connector); 3085 3086 intel_hdmi->cec_notifier = 3087 cec_notifier_conn_register(dev->dev, port_identifier(port), 3088 &conn_info); 3089 if (!intel_hdmi->cec_notifier) 3090 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3091 } 3092 3093 /* 3094 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3095 * @vactive: Vactive of a display mode 3096 * 3097 * @return: appropriate dsc slice height for a given mode. 3098 */ 3099 int intel_hdmi_dsc_get_slice_height(int vactive) 3100 { 3101 int slice_height; 3102 3103 /* 3104 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3105 * Select smallest slice height >=96, that results in a valid PPS and 3106 * requires minimum padding lines required for final slice. 3107 * 3108 * Assumption : Vactive is even. 3109 */ 3110 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3111 if (vactive % slice_height == 0) 3112 return slice_height; 3113 3114 return 0; 3115 } 3116 3117 /* 3118 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3119 * and dsc decoder capabilities 3120 * 3121 * @crtc_state: intel crtc_state 3122 * @src_max_slices: maximum slices supported by the DSC encoder 3123 * @src_max_slice_width: maximum slice width supported by DSC encoder 3124 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3125 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3126 * 3127 * @return: num of dsc slices that can be supported by the dsc encoder 3128 * and decoder. 3129 */ 3130 int 3131 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3132 int src_max_slices, int src_max_slice_width, 3133 int hdmi_max_slices, int hdmi_throughput) 3134 { 3135 /* Pixel rates in KPixels/sec */ 3136 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3137 /* 3138 * Rates at which the source and sink are required to process pixels in each 3139 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3140 */ 3141 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3142 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3143 3144 /* Spec limits the slice width to 2720 pixels */ 3145 #define MAX_HDMI_SLICE_WIDTH 2720 3146 int kslice_adjust; 3147 int adjusted_clk_khz; 3148 int min_slices; 3149 int target_slices; 3150 int max_throughput; /* max clock freq. in khz per slice */ 3151 int max_slice_width; 3152 int slice_width; 3153 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3154 3155 if (!hdmi_throughput) 3156 return 0; 3157 3158 /* 3159 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3160 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3161 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3162 * dividing adjusted clock value by 10. 3163 */ 3164 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3165 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3166 kslice_adjust = 10; 3167 else 3168 kslice_adjust = 5; 3169 3170 /* 3171 * As per spec, the rate at which the source and the sink process 3172 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3173 * This depends upon the pixel clock rate and output formats 3174 * (kslice adjust). 3175 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3176 * at max 340MHz, otherwise they can be processed at max 400MHz. 3177 */ 3178 3179 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3180 3181 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3182 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3183 else 3184 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3185 3186 /* 3187 * Taking into account the sink's capability for maximum 3188 * clock per slice (in MHz) as read from HF-VSDB. 3189 */ 3190 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3191 3192 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3193 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3194 3195 /* 3196 * Keep on increasing the num of slices/line, starting from min_slices 3197 * per line till we get such a number, for which the slice_width is 3198 * just less than max_slice_width. The slices/line selected should be 3199 * less than or equal to the max horizontal slices that the combination 3200 * of PCON encoder and HDMI decoder can support. 3201 */ 3202 slice_width = max_slice_width; 3203 3204 do { 3205 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3206 target_slices = 1; 3207 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3208 target_slices = 2; 3209 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3210 target_slices = 4; 3211 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3212 target_slices = 8; 3213 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3214 target_slices = 12; 3215 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3216 target_slices = 16; 3217 else 3218 return 0; 3219 3220 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3221 if (slice_width >= max_slice_width) 3222 min_slices = target_slices + 1; 3223 } while (slice_width >= max_slice_width); 3224 3225 return target_slices; 3226 } 3227 3228 /* 3229 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3230 * source and sink capabilities. 3231 * 3232 * @src_fraction_bpp: fractional bpp supported by the source 3233 * @slice_width: dsc slice width supported by the source and sink 3234 * @num_slices: num of slices supported by the source and sink 3235 * @output_format: video output format 3236 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3237 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3238 * 3239 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3240 */ 3241 int 3242 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3243 int output_format, bool hdmi_all_bpp, 3244 int hdmi_max_chunk_bytes) 3245 { 3246 int max_dsc_bpp, min_dsc_bpp; 3247 int target_bytes; 3248 bool bpp_found = false; 3249 int bpp_decrement_x16; 3250 int bpp_target; 3251 int bpp_target_x16; 3252 3253 /* 3254 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3255 * Start with the max bpp and keep on decrementing with 3256 * fractional bpp, if supported by PCON DSC encoder 3257 * 3258 * for each bpp we check if no of bytes can be supported by HDMI sink 3259 */ 3260 3261 /* Assuming: bpc as 8*/ 3262 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3263 min_dsc_bpp = 6; 3264 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3265 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3266 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3267 min_dsc_bpp = 8; 3268 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3269 } else { 3270 /* Assuming 4:2:2 encoding */ 3271 min_dsc_bpp = 7; 3272 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3273 } 3274 3275 /* 3276 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3277 * Section 7.7.34 : Source shall not enable compressed Video 3278 * Transport with bpp_target settings above 12 bpp unless 3279 * DSC_all_bpp is set to 1. 3280 */ 3281 if (!hdmi_all_bpp) 3282 max_dsc_bpp = min(max_dsc_bpp, 12); 3283 3284 /* 3285 * The Sink has a limit of compressed data in bytes for a scanline, 3286 * as described in max_chunk_bytes field in HFVSDB block of edid. 3287 * The no. of bytes depend on the target bits per pixel that the 3288 * source configures. So we start with the max_bpp and calculate 3289 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3290 * till we get the target_chunk_bytes just less than what the sink's 3291 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3292 * 3293 * The decrement is according to the fractional support from PCON DSC 3294 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3295 * 3296 * bpp_target_x16 = bpp_target * 16 3297 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3298 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3299 */ 3300 3301 bpp_target = max_dsc_bpp; 3302 3303 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3304 if (!src_fractional_bpp) 3305 src_fractional_bpp = 1; 3306 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3307 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3308 3309 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3310 int bpp; 3311 3312 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3313 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3314 if (target_bytes <= hdmi_max_chunk_bytes) { 3315 bpp_found = true; 3316 break; 3317 } 3318 bpp_target_x16 -= bpp_decrement_x16; 3319 } 3320 if (bpp_found) 3321 return bpp_target_x16; 3322 3323 return 0; 3324 } 3325