1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/iopoll.h> 33 #include <linux/slab.h> 34 #include <linux/string_helpers.h> 35 36 #include <drm/display/drm_hdcp_helper.h> 37 #include <drm/display/drm_hdmi_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_crtc.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/intel/intel_lpe_audio.h> 45 #include <media/cec-notifier.h> 46 47 #include "g4x_hdmi.h" 48 #include "intel_atomic.h" 49 #include "intel_audio.h" 50 #include "intel_connector.h" 51 #include "intel_cx0_phy.h" 52 #include "intel_ddi.h" 53 #include "intel_de.h" 54 #include "intel_display_driver.h" 55 #include "intel_display_regs.h" 56 #include "intel_display_types.h" 57 #include "intel_display_utils.h" 58 #include "intel_dp.h" 59 #include "intel_dpll.h" 60 #include "intel_gmbus.h" 61 #include "intel_hdcp.h" 62 #include "intel_hdcp_regs.h" 63 #include "intel_hdcp_shim.h" 64 #include "intel_hdmi.h" 65 #include "intel_link_bw.h" 66 #include "intel_lspcon.h" 67 #include "intel_panel.h" 68 #include "intel_pfit.h" 69 #include "intel_snps_phy.h" 70 #include "intel_vrr.h" 71 72 bool intel_hdmi_is_frl(u32 clock) 73 { 74 u32 rates[] = { 300000, 600000, 800000, 1000000, 1200000 }; 75 int i; 76 77 for (i = 0; i < ARRAY_SIZE(rates); i++) 78 if (intel_dpll_clock_matches(clock, rates[i])) 79 return true; 80 81 return false; 82 } 83 84 static void 85 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 86 { 87 struct intel_display *display = to_intel_display(intel_hdmi); 88 u32 enabled_bits; 89 90 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 91 92 drm_WARN(display->drm, 93 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 94 "HDMI port enabled, expecting disabled\n"); 95 } 96 97 static void 98 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 99 enum transcoder cpu_transcoder) 100 { 101 drm_WARN(display->drm, 102 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 103 TRANS_DDI_FUNC_ENABLE, 104 "HDMI transcoder function enabled, expecting disabled\n"); 105 } 106 107 static u32 g4x_infoframe_index(unsigned int type) 108 { 109 switch (type) { 110 case HDMI_PACKET_TYPE_GAMUT_METADATA: 111 return VIDEO_DIP_SELECT_GAMUT; 112 case HDMI_INFOFRAME_TYPE_AVI: 113 return VIDEO_DIP_SELECT_AVI; 114 case HDMI_INFOFRAME_TYPE_SPD: 115 return VIDEO_DIP_SELECT_SPD; 116 case HDMI_INFOFRAME_TYPE_VENDOR: 117 return VIDEO_DIP_SELECT_VENDOR; 118 default: 119 MISSING_CASE(type); 120 return 0; 121 } 122 } 123 124 static u32 g4x_infoframe_enable(unsigned int type) 125 { 126 switch (type) { 127 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 128 return VIDEO_DIP_ENABLE_GCP; 129 case HDMI_PACKET_TYPE_GAMUT_METADATA: 130 return VIDEO_DIP_ENABLE_GAMUT; 131 case DP_SDP_VSC: 132 return 0; 133 case DP_SDP_ADAPTIVE_SYNC: 134 return 0; 135 case HDMI_INFOFRAME_TYPE_AVI: 136 return VIDEO_DIP_ENABLE_AVI; 137 case HDMI_INFOFRAME_TYPE_SPD: 138 return VIDEO_DIP_ENABLE_SPD; 139 case HDMI_INFOFRAME_TYPE_VENDOR: 140 return VIDEO_DIP_ENABLE_VENDOR; 141 case HDMI_INFOFRAME_TYPE_DRM: 142 return 0; 143 default: 144 MISSING_CASE(type); 145 return 0; 146 } 147 } 148 149 static u32 hsw_infoframe_enable(unsigned int type) 150 { 151 switch (type) { 152 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 153 return VIDEO_DIP_ENABLE_GCP_HSW; 154 case HDMI_PACKET_TYPE_GAMUT_METADATA: 155 return VIDEO_DIP_ENABLE_GMP_HSW; 156 case DP_SDP_VSC: 157 return VIDEO_DIP_ENABLE_VSC_HSW; 158 case DP_SDP_ADAPTIVE_SYNC: 159 return VIDEO_DIP_ENABLE_AS_ADL; 160 case DP_SDP_PPS: 161 return VDIP_ENABLE_PPS; 162 case HDMI_INFOFRAME_TYPE_AVI: 163 return VIDEO_DIP_ENABLE_AVI_HSW; 164 case HDMI_INFOFRAME_TYPE_SPD: 165 return VIDEO_DIP_ENABLE_SPD_HSW; 166 case HDMI_INFOFRAME_TYPE_VENDOR: 167 return VIDEO_DIP_ENABLE_VS_HSW; 168 case HDMI_INFOFRAME_TYPE_DRM: 169 return VIDEO_DIP_ENABLE_DRM_GLK; 170 default: 171 MISSING_CASE(type); 172 return 0; 173 } 174 } 175 176 static i915_reg_t 177 hsw_dip_data_reg(struct intel_display *display, 178 enum transcoder cpu_transcoder, 179 unsigned int type, 180 int i) 181 { 182 switch (type) { 183 case HDMI_PACKET_TYPE_GAMUT_METADATA: 184 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 185 case DP_SDP_VSC: 186 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 187 case DP_SDP_ADAPTIVE_SYNC: 188 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 189 case DP_SDP_PPS: 190 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 191 case HDMI_INFOFRAME_TYPE_AVI: 192 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 193 case HDMI_INFOFRAME_TYPE_SPD: 194 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 195 case HDMI_INFOFRAME_TYPE_VENDOR: 196 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 197 case HDMI_INFOFRAME_TYPE_DRM: 198 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 199 default: 200 MISSING_CASE(type); 201 return INVALID_MMIO_REG; 202 } 203 } 204 205 static int hsw_dip_data_size(struct intel_display *display, 206 unsigned int type) 207 { 208 switch (type) { 209 case DP_SDP_VSC: 210 return VIDEO_DIP_VSC_DATA_SIZE; 211 case DP_SDP_ADAPTIVE_SYNC: 212 return VIDEO_DIP_ASYNC_DATA_SIZE; 213 case DP_SDP_PPS: 214 return VIDEO_DIP_PPS_DATA_SIZE; 215 case HDMI_PACKET_TYPE_GAMUT_METADATA: 216 if (DISPLAY_VER(display) >= 11) 217 return VIDEO_DIP_GMP_DATA_SIZE; 218 else 219 return VIDEO_DIP_DATA_SIZE; 220 default: 221 return VIDEO_DIP_DATA_SIZE; 222 } 223 } 224 225 static void g4x_write_infoframe(struct intel_encoder *encoder, 226 const struct intel_crtc_state *crtc_state, 227 unsigned int type, 228 const void *frame, ssize_t len) 229 { 230 struct intel_display *display = to_intel_display(encoder); 231 const u32 *data = frame; 232 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 233 int i; 234 235 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 236 "Writing DIP with CTL reg disabled\n"); 237 238 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 239 val |= g4x_infoframe_index(type); 240 241 val &= ~g4x_infoframe_enable(type); 242 243 intel_de_write(display, VIDEO_DIP_CTL, val); 244 245 for (i = 0; i < len; i += 4) { 246 intel_de_write(display, VIDEO_DIP_DATA, *data); 247 data++; 248 } 249 /* Write every possible data byte to force correct ECC calculation. */ 250 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 251 intel_de_write(display, VIDEO_DIP_DATA, 0); 252 253 val |= g4x_infoframe_enable(type); 254 val &= ~VIDEO_DIP_FREQ_MASK; 255 val |= VIDEO_DIP_FREQ_VSYNC; 256 257 intel_de_write(display, VIDEO_DIP_CTL, val); 258 intel_de_posting_read(display, VIDEO_DIP_CTL); 259 } 260 261 static void g4x_read_infoframe(struct intel_encoder *encoder, 262 const struct intel_crtc_state *crtc_state, 263 unsigned int type, 264 void *frame, ssize_t len) 265 { 266 struct intel_display *display = to_intel_display(encoder); 267 u32 *data = frame; 268 int i; 269 270 intel_de_rmw(display, VIDEO_DIP_CTL, 271 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 272 273 for (i = 0; i < len; i += 4) 274 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 275 } 276 277 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 278 const struct intel_crtc_state *pipe_config) 279 { 280 struct intel_display *display = to_intel_display(encoder); 281 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 282 283 if ((val & VIDEO_DIP_ENABLE) == 0) 284 return 0; 285 286 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 287 return 0; 288 289 return val & (VIDEO_DIP_ENABLE_AVI | 290 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 291 } 292 293 static void ibx_write_infoframe(struct intel_encoder *encoder, 294 const struct intel_crtc_state *crtc_state, 295 unsigned int type, 296 const void *frame, ssize_t len) 297 { 298 struct intel_display *display = to_intel_display(encoder); 299 const u32 *data = frame; 300 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 301 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 302 u32 val = intel_de_read(display, reg); 303 int i; 304 305 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 306 "Writing DIP with CTL reg disabled\n"); 307 308 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 309 val |= g4x_infoframe_index(type); 310 311 val &= ~g4x_infoframe_enable(type); 312 313 intel_de_write(display, reg, val); 314 315 for (i = 0; i < len; i += 4) { 316 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 317 *data); 318 data++; 319 } 320 /* Write every possible data byte to force correct ECC calculation. */ 321 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 322 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 323 324 val |= g4x_infoframe_enable(type); 325 val &= ~VIDEO_DIP_FREQ_MASK; 326 val |= VIDEO_DIP_FREQ_VSYNC; 327 328 intel_de_write(display, reg, val); 329 intel_de_posting_read(display, reg); 330 } 331 332 static void ibx_read_infoframe(struct intel_encoder *encoder, 333 const struct intel_crtc_state *crtc_state, 334 unsigned int type, 335 void *frame, ssize_t len) 336 { 337 struct intel_display *display = to_intel_display(encoder); 338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 339 u32 *data = frame; 340 int i; 341 342 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 343 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 344 345 for (i = 0; i < len; i += 4) 346 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 347 } 348 349 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 350 const struct intel_crtc_state *pipe_config) 351 { 352 struct intel_display *display = to_intel_display(encoder); 353 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 354 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 355 u32 val = intel_de_read(display, reg); 356 357 if ((val & VIDEO_DIP_ENABLE) == 0) 358 return 0; 359 360 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 361 return 0; 362 363 return val & (VIDEO_DIP_ENABLE_AVI | 364 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 365 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 366 } 367 368 static void cpt_write_infoframe(struct intel_encoder *encoder, 369 const struct intel_crtc_state *crtc_state, 370 unsigned int type, 371 const void *frame, ssize_t len) 372 { 373 struct intel_display *display = to_intel_display(encoder); 374 const u32 *data = frame; 375 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 376 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 377 u32 val = intel_de_read(display, reg); 378 int i; 379 380 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 381 "Writing DIP with CTL reg disabled\n"); 382 383 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 384 val |= g4x_infoframe_index(type); 385 386 /* The DIP control register spec says that we need to update the AVI 387 * infoframe without clearing its enable bit */ 388 if (type != HDMI_INFOFRAME_TYPE_AVI) 389 val &= ~g4x_infoframe_enable(type); 390 391 intel_de_write(display, reg, val); 392 393 for (i = 0; i < len; i += 4) { 394 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 395 *data); 396 data++; 397 } 398 /* Write every possible data byte to force correct ECC calculation. */ 399 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 400 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 401 402 val |= g4x_infoframe_enable(type); 403 val &= ~VIDEO_DIP_FREQ_MASK; 404 val |= VIDEO_DIP_FREQ_VSYNC; 405 406 intel_de_write(display, reg, val); 407 intel_de_posting_read(display, reg); 408 } 409 410 static void cpt_read_infoframe(struct intel_encoder *encoder, 411 const struct intel_crtc_state *crtc_state, 412 unsigned int type, 413 void *frame, ssize_t len) 414 { 415 struct intel_display *display = to_intel_display(encoder); 416 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 417 u32 *data = frame; 418 int i; 419 420 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 421 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 422 423 for (i = 0; i < len; i += 4) 424 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 425 } 426 427 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 428 const struct intel_crtc_state *pipe_config) 429 { 430 struct intel_display *display = to_intel_display(encoder); 431 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 432 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 433 434 if ((val & VIDEO_DIP_ENABLE) == 0) 435 return 0; 436 437 return val & (VIDEO_DIP_ENABLE_AVI | 438 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 439 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 440 } 441 442 static void vlv_write_infoframe(struct intel_encoder *encoder, 443 const struct intel_crtc_state *crtc_state, 444 unsigned int type, 445 const void *frame, ssize_t len) 446 { 447 struct intel_display *display = to_intel_display(encoder); 448 const u32 *data = frame; 449 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 450 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 451 u32 val = intel_de_read(display, reg); 452 int i; 453 454 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 455 "Writing DIP with CTL reg disabled\n"); 456 457 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 458 val |= g4x_infoframe_index(type); 459 460 val &= ~g4x_infoframe_enable(type); 461 462 intel_de_write(display, reg, val); 463 464 for (i = 0; i < len; i += 4) { 465 intel_de_write(display, 466 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 467 data++; 468 } 469 /* Write every possible data byte to force correct ECC calculation. */ 470 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 471 intel_de_write(display, 472 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 473 474 val |= g4x_infoframe_enable(type); 475 val &= ~VIDEO_DIP_FREQ_MASK; 476 val |= VIDEO_DIP_FREQ_VSYNC; 477 478 intel_de_write(display, reg, val); 479 intel_de_posting_read(display, reg); 480 } 481 482 static void vlv_read_infoframe(struct intel_encoder *encoder, 483 const struct intel_crtc_state *crtc_state, 484 unsigned int type, 485 void *frame, ssize_t len) 486 { 487 struct intel_display *display = to_intel_display(encoder); 488 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 489 u32 *data = frame; 490 int i; 491 492 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 493 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 494 495 for (i = 0; i < len; i += 4) 496 *data++ = intel_de_read(display, 497 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 498 } 499 500 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 501 const struct intel_crtc_state *pipe_config) 502 { 503 struct intel_display *display = to_intel_display(encoder); 504 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 505 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 506 507 if ((val & VIDEO_DIP_ENABLE) == 0) 508 return 0; 509 510 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 511 return 0; 512 513 return val & (VIDEO_DIP_ENABLE_AVI | 514 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 515 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 516 } 517 518 void hsw_write_infoframe(struct intel_encoder *encoder, 519 const struct intel_crtc_state *crtc_state, 520 unsigned int type, 521 const void *frame, ssize_t len) 522 { 523 struct intel_display *display = to_intel_display(encoder); 524 const u32 *data = frame; 525 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 526 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 527 int data_size; 528 int i; 529 u32 val = intel_de_read(display, ctl_reg); 530 531 data_size = hsw_dip_data_size(display, type); 532 533 drm_WARN_ON(display->drm, len > data_size); 534 535 val &= ~hsw_infoframe_enable(type); 536 intel_de_write(display, ctl_reg, val); 537 538 for (i = 0; i < len; i += 4) { 539 intel_de_write(display, 540 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 541 *data); 542 data++; 543 } 544 /* Write every possible data byte to force correct ECC calculation. */ 545 for (; i < data_size; i += 4) 546 intel_de_write(display, 547 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 548 0); 549 550 /* Wa_14013475917 */ 551 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 552 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 553 val |= hsw_infoframe_enable(type); 554 555 if (type == DP_SDP_VSC) 556 val |= VSC_DIP_HW_DATA_SW_HEA; 557 558 intel_de_write(display, ctl_reg, val); 559 intel_de_posting_read(display, ctl_reg); 560 } 561 562 void hsw_read_infoframe(struct intel_encoder *encoder, 563 const struct intel_crtc_state *crtc_state, 564 unsigned int type, void *frame, ssize_t len) 565 { 566 struct intel_display *display = to_intel_display(encoder); 567 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 568 u32 *data = frame; 569 int i; 570 571 for (i = 0; i < len; i += 4) 572 *data++ = intel_de_read(display, 573 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 574 } 575 576 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 577 const struct intel_crtc_state *pipe_config) 578 { 579 struct intel_display *display = to_intel_display(encoder); 580 u32 val = intel_de_read(display, 581 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 582 u32 mask; 583 584 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 585 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 586 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 587 588 if (DISPLAY_VER(display) >= 10) 589 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 590 591 if (HAS_AS_SDP(display)) 592 mask |= VIDEO_DIP_ENABLE_AS_ADL; 593 594 return val & mask; 595 } 596 597 static const u8 infoframe_type_to_idx[] = { 598 HDMI_PACKET_TYPE_GENERAL_CONTROL, 599 HDMI_PACKET_TYPE_GAMUT_METADATA, 600 DP_SDP_VSC, 601 DP_SDP_ADAPTIVE_SYNC, 602 HDMI_INFOFRAME_TYPE_AVI, 603 HDMI_INFOFRAME_TYPE_SPD, 604 HDMI_INFOFRAME_TYPE_VENDOR, 605 HDMI_INFOFRAME_TYPE_DRM, 606 }; 607 608 u32 intel_hdmi_infoframe_enable(unsigned int type) 609 { 610 int i; 611 612 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 613 if (infoframe_type_to_idx[i] == type) 614 return BIT(i); 615 } 616 617 return 0; 618 } 619 620 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 621 const struct intel_crtc_state *crtc_state) 622 { 623 struct intel_display *display = to_intel_display(encoder); 624 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 625 u32 val, ret = 0; 626 int i; 627 628 val = dig_port->infoframes_enabled(encoder, crtc_state); 629 630 /* map from hardware bits to dip idx */ 631 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 632 unsigned int type = infoframe_type_to_idx[i]; 633 634 if (HAS_DDI(display)) { 635 if (val & hsw_infoframe_enable(type)) 636 ret |= BIT(i); 637 } else { 638 if (val & g4x_infoframe_enable(type)) 639 ret |= BIT(i); 640 } 641 } 642 643 return ret; 644 } 645 646 /* 647 * The data we write to the DIP data buffer registers is 1 byte bigger than the 648 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 649 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 650 * used for both technologies. 651 * 652 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 653 * DW1: DB3 | DB2 | DB1 | DB0 654 * DW2: DB7 | DB6 | DB5 | DB4 655 * DW3: ... 656 * 657 * (HB is Header Byte, DB is Data Byte) 658 * 659 * The hdmi pack() functions don't know about that hardware specific hole so we 660 * trick them by giving an offset into the buffer and moving back the header 661 * bytes by one. 662 */ 663 static void intel_write_infoframe(struct intel_encoder *encoder, 664 const struct intel_crtc_state *crtc_state, 665 enum hdmi_infoframe_type type, 666 const union hdmi_infoframe *frame) 667 { 668 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 669 u8 buffer[VIDEO_DIP_DATA_SIZE]; 670 ssize_t len; 671 672 if ((crtc_state->infoframes.enable & 673 intel_hdmi_infoframe_enable(type)) == 0) 674 return; 675 676 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 677 return; 678 679 /* see comment above for the reason for this offset */ 680 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 681 if (drm_WARN_ON(encoder->base.dev, len < 0)) 682 return; 683 684 /* Insert the 'hole' (see big comment above) at position 3 */ 685 memmove(&buffer[0], &buffer[1], 3); 686 buffer[3] = 0; 687 len++; 688 689 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 690 } 691 692 void intel_read_infoframe(struct intel_encoder *encoder, 693 const struct intel_crtc_state *crtc_state, 694 enum hdmi_infoframe_type type, 695 union hdmi_infoframe *frame) 696 { 697 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 698 u8 buffer[VIDEO_DIP_DATA_SIZE]; 699 int ret; 700 701 if ((crtc_state->infoframes.enable & 702 intel_hdmi_infoframe_enable(type)) == 0) 703 return; 704 705 dig_port->read_infoframe(encoder, crtc_state, 706 type, buffer, sizeof(buffer)); 707 708 /* Fill the 'hole' (see big comment above) at position 3 */ 709 memmove(&buffer[1], &buffer[0], 3); 710 711 /* see comment above for the reason for this offset */ 712 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 713 if (ret) { 714 drm_dbg_kms(encoder->base.dev, 715 "Failed to unpack infoframe type 0x%02x\n", type); 716 return; 717 } 718 719 if (frame->any.type != type) 720 drm_dbg_kms(encoder->base.dev, 721 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 722 frame->any.type, type); 723 } 724 725 static bool 726 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 727 struct intel_crtc_state *crtc_state, 728 struct drm_connector_state *conn_state) 729 { 730 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 731 const struct drm_display_mode *adjusted_mode = 732 &crtc_state->hw.adjusted_mode; 733 struct intel_connector *connector = to_intel_connector(conn_state->connector); 734 int ret; 735 736 if (!crtc_state->has_infoframe) 737 return true; 738 739 crtc_state->infoframes.enable |= 740 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 741 742 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base, 743 adjusted_mode); 744 if (ret) 745 return false; 746 747 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 748 frame->colorspace = HDMI_COLORSPACE_YUV420; 749 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 750 frame->colorspace = HDMI_COLORSPACE_YUV444; 751 else 752 frame->colorspace = HDMI_COLORSPACE_RGB; 753 754 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 755 756 /* nonsense combination */ 757 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 758 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 759 760 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 761 drm_hdmi_avi_infoframe_quant_range(frame, &connector->base, 762 adjusted_mode, 763 crtc_state->limited_color_range ? 764 HDMI_QUANTIZATION_RANGE_LIMITED : 765 HDMI_QUANTIZATION_RANGE_FULL); 766 } else { 767 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 768 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 769 } 770 771 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 772 773 /* TODO: handle pixel repetition for YCBCR420 outputs */ 774 775 ret = hdmi_avi_infoframe_check(frame); 776 if (drm_WARN_ON(encoder->base.dev, ret)) 777 return false; 778 779 return true; 780 } 781 782 static bool 783 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 784 struct intel_crtc_state *crtc_state, 785 struct drm_connector_state *conn_state) 786 { 787 struct intel_display *display = to_intel_display(crtc_state); 788 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 789 int ret; 790 791 if (!crtc_state->has_infoframe) 792 return true; 793 794 crtc_state->infoframes.enable |= 795 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 796 797 if (display->platform.dgfx) 798 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 799 else 800 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 801 802 if (drm_WARN_ON(encoder->base.dev, ret)) 803 return false; 804 805 frame->sdi = HDMI_SPD_SDI_PC; 806 807 ret = hdmi_spd_infoframe_check(frame); 808 if (drm_WARN_ON(encoder->base.dev, ret)) 809 return false; 810 811 return true; 812 } 813 814 static bool 815 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 816 struct intel_crtc_state *crtc_state, 817 struct drm_connector_state *conn_state) 818 { 819 struct hdmi_vendor_infoframe *frame = 820 &crtc_state->infoframes.hdmi.vendor.hdmi; 821 const struct drm_display_info *info = 822 &conn_state->connector->display_info; 823 int ret; 824 825 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 826 return true; 827 828 crtc_state->infoframes.enable |= 829 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 830 831 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 832 conn_state->connector, 833 &crtc_state->hw.adjusted_mode); 834 if (drm_WARN_ON(encoder->base.dev, ret)) 835 return false; 836 837 ret = hdmi_vendor_infoframe_check(frame); 838 if (drm_WARN_ON(encoder->base.dev, ret)) 839 return false; 840 841 return true; 842 } 843 844 static bool 845 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 846 struct intel_crtc_state *crtc_state, 847 struct drm_connector_state *conn_state) 848 { 849 struct intel_display *display = to_intel_display(encoder); 850 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 851 int ret; 852 853 if (DISPLAY_VER(display) < 10) 854 return true; 855 856 if (!crtc_state->has_infoframe) 857 return true; 858 859 if (!conn_state->hdr_output_metadata) 860 return true; 861 862 crtc_state->infoframes.enable |= 863 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 864 865 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 866 if (ret < 0) { 867 drm_dbg_kms(display->drm, 868 "couldn't set HDR metadata in infoframe\n"); 869 return false; 870 } 871 872 ret = hdmi_drm_infoframe_check(frame); 873 if (drm_WARN_ON(display->drm, ret)) 874 return false; 875 876 return true; 877 } 878 879 static void g4x_set_infoframes(struct intel_encoder *encoder, 880 bool enable, 881 const struct intel_crtc_state *crtc_state, 882 const struct drm_connector_state *conn_state) 883 { 884 struct intel_display *display = to_intel_display(encoder); 885 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 886 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 887 i915_reg_t reg = VIDEO_DIP_CTL; 888 u32 val = intel_de_read(display, reg); 889 u32 port = VIDEO_DIP_PORT(encoder->port); 890 891 assert_hdmi_port_disabled(intel_hdmi); 892 893 /* If the registers were not initialized yet, they might be zeroes, 894 * which means we're selecting the AVI DIP and we're setting its 895 * frequency to once. This seems to really confuse the HW and make 896 * things stop working (the register spec says the AVI always needs to 897 * be sent every VSync). So here we avoid writing to the register more 898 * than we need and also explicitly select the AVI DIP and explicitly 899 * set its frequency to every VSync. Avoiding to write it twice seems to 900 * be enough to solve the problem, but being defensive shouldn't hurt us 901 * either. */ 902 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 903 904 if (!enable) { 905 if (!(val & VIDEO_DIP_ENABLE)) 906 return; 907 if (port != (val & VIDEO_DIP_PORT_MASK)) { 908 drm_dbg_kms(display->drm, 909 "video DIP still enabled on port %c\n", 910 (val & VIDEO_DIP_PORT_MASK) >> 29); 911 return; 912 } 913 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 914 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 915 intel_de_write(display, reg, val); 916 intel_de_posting_read(display, reg); 917 return; 918 } 919 920 if (port != (val & VIDEO_DIP_PORT_MASK)) { 921 if (val & VIDEO_DIP_ENABLE) { 922 drm_dbg_kms(display->drm, 923 "video DIP already enabled on port %c\n", 924 (val & VIDEO_DIP_PORT_MASK) >> 29); 925 return; 926 } 927 val &= ~VIDEO_DIP_PORT_MASK; 928 val |= port; 929 } 930 931 val |= VIDEO_DIP_ENABLE; 932 val &= ~(VIDEO_DIP_ENABLE_AVI | 933 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 934 935 intel_de_write(display, reg, val); 936 intel_de_posting_read(display, reg); 937 938 intel_write_infoframe(encoder, crtc_state, 939 HDMI_INFOFRAME_TYPE_AVI, 940 &crtc_state->infoframes.avi); 941 intel_write_infoframe(encoder, crtc_state, 942 HDMI_INFOFRAME_TYPE_SPD, 943 &crtc_state->infoframes.spd); 944 intel_write_infoframe(encoder, crtc_state, 945 HDMI_INFOFRAME_TYPE_VENDOR, 946 &crtc_state->infoframes.hdmi); 947 } 948 949 /* 950 * Determine if default_phase=1 can be indicated in the GCP infoframe. 951 * 952 * From HDMI specification 1.4a: 953 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 954 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 955 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 956 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 957 * phase of 0 958 */ 959 static bool gcp_default_phase_possible(int pipe_bpp, 960 const struct drm_display_mode *mode) 961 { 962 unsigned int pixels_per_group; 963 964 switch (pipe_bpp) { 965 case 30: 966 /* 4 pixels in 5 clocks */ 967 pixels_per_group = 4; 968 break; 969 case 36: 970 /* 2 pixels in 3 clocks */ 971 pixels_per_group = 2; 972 break; 973 case 48: 974 /* 1 pixel in 2 clocks */ 975 pixels_per_group = 1; 976 break; 977 default: 978 /* phase information not relevant for 8bpc */ 979 return false; 980 } 981 982 return mode->crtc_hdisplay % pixels_per_group == 0 && 983 mode->crtc_htotal % pixels_per_group == 0 && 984 mode->crtc_hblank_start % pixels_per_group == 0 && 985 mode->crtc_hblank_end % pixels_per_group == 0 && 986 mode->crtc_hsync_start % pixels_per_group == 0 && 987 mode->crtc_hsync_end % pixels_per_group == 0 && 988 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 989 mode->crtc_htotal/2 % pixels_per_group == 0); 990 } 991 992 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 993 const struct intel_crtc_state *crtc_state, 994 const struct drm_connector_state *conn_state) 995 { 996 struct intel_display *display = to_intel_display(encoder); 997 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 998 i915_reg_t reg; 999 1000 if ((crtc_state->infoframes.enable & 1001 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1002 return false; 1003 1004 if (HAS_DDI(display)) 1005 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1006 else if (display->platform.valleyview || display->platform.cherryview) 1007 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1008 else if (HAS_PCH_SPLIT(display)) 1009 reg = TVIDEO_DIP_GCP(crtc->pipe); 1010 else 1011 return false; 1012 1013 intel_de_write(display, reg, crtc_state->infoframes.gcp); 1014 1015 return true; 1016 } 1017 1018 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1019 struct intel_crtc_state *crtc_state) 1020 { 1021 struct intel_display *display = to_intel_display(encoder); 1022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1023 i915_reg_t reg; 1024 1025 if ((crtc_state->infoframes.enable & 1026 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1027 return; 1028 1029 if (HAS_DDI(display)) 1030 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1031 else if (display->platform.valleyview || display->platform.cherryview) 1032 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1033 else if (HAS_PCH_SPLIT(display)) 1034 reg = TVIDEO_DIP_GCP(crtc->pipe); 1035 else 1036 return; 1037 1038 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1039 } 1040 1041 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1042 struct intel_crtc_state *crtc_state, 1043 struct drm_connector_state *conn_state) 1044 { 1045 struct intel_display *display = to_intel_display(encoder); 1046 1047 if (display->platform.g4x || !crtc_state->has_infoframe) 1048 return; 1049 1050 crtc_state->infoframes.enable |= 1051 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1052 1053 /* Indicate color indication for deep color mode */ 1054 if (crtc_state->pipe_bpp > 24) 1055 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1056 1057 /* Enable default_phase whenever the display mode is suitably aligned */ 1058 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1059 &crtc_state->hw.adjusted_mode)) 1060 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1061 } 1062 1063 static void ibx_set_infoframes(struct intel_encoder *encoder, 1064 bool enable, 1065 const struct intel_crtc_state *crtc_state, 1066 const struct drm_connector_state *conn_state) 1067 { 1068 struct intel_display *display = to_intel_display(encoder); 1069 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1070 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1071 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1072 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1073 u32 val = intel_de_read(display, reg); 1074 u32 port = VIDEO_DIP_PORT(encoder->port); 1075 1076 assert_hdmi_port_disabled(intel_hdmi); 1077 1078 /* See the big comment in g4x_set_infoframes() */ 1079 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1080 1081 if (!enable) { 1082 if (!(val & VIDEO_DIP_ENABLE)) 1083 return; 1084 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1085 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1086 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1087 intel_de_write(display, reg, val); 1088 intel_de_posting_read(display, reg); 1089 return; 1090 } 1091 1092 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1093 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1094 "DIP already enabled on port %c\n", 1095 (val & VIDEO_DIP_PORT_MASK) >> 29); 1096 val &= ~VIDEO_DIP_PORT_MASK; 1097 val |= port; 1098 } 1099 1100 val |= VIDEO_DIP_ENABLE; 1101 val &= ~(VIDEO_DIP_ENABLE_AVI | 1102 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1103 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1104 1105 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1106 val |= VIDEO_DIP_ENABLE_GCP; 1107 1108 intel_de_write(display, reg, val); 1109 intel_de_posting_read(display, reg); 1110 1111 intel_write_infoframe(encoder, crtc_state, 1112 HDMI_INFOFRAME_TYPE_AVI, 1113 &crtc_state->infoframes.avi); 1114 intel_write_infoframe(encoder, crtc_state, 1115 HDMI_INFOFRAME_TYPE_SPD, 1116 &crtc_state->infoframes.spd); 1117 intel_write_infoframe(encoder, crtc_state, 1118 HDMI_INFOFRAME_TYPE_VENDOR, 1119 &crtc_state->infoframes.hdmi); 1120 } 1121 1122 static void cpt_set_infoframes(struct intel_encoder *encoder, 1123 bool enable, 1124 const struct intel_crtc_state *crtc_state, 1125 const struct drm_connector_state *conn_state) 1126 { 1127 struct intel_display *display = to_intel_display(encoder); 1128 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1129 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1130 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1131 u32 val = intel_de_read(display, reg); 1132 1133 assert_hdmi_port_disabled(intel_hdmi); 1134 1135 /* See the big comment in g4x_set_infoframes() */ 1136 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1137 1138 if (!enable) { 1139 if (!(val & VIDEO_DIP_ENABLE)) 1140 return; 1141 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1142 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1143 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1144 intel_de_write(display, reg, val); 1145 intel_de_posting_read(display, reg); 1146 return; 1147 } 1148 1149 /* Set both together, unset both together: see the spec. */ 1150 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1151 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1152 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1153 1154 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1155 val |= VIDEO_DIP_ENABLE_GCP; 1156 1157 intel_de_write(display, reg, val); 1158 intel_de_posting_read(display, reg); 1159 1160 intel_write_infoframe(encoder, crtc_state, 1161 HDMI_INFOFRAME_TYPE_AVI, 1162 &crtc_state->infoframes.avi); 1163 intel_write_infoframe(encoder, crtc_state, 1164 HDMI_INFOFRAME_TYPE_SPD, 1165 &crtc_state->infoframes.spd); 1166 intel_write_infoframe(encoder, crtc_state, 1167 HDMI_INFOFRAME_TYPE_VENDOR, 1168 &crtc_state->infoframes.hdmi); 1169 } 1170 1171 static void vlv_set_infoframes(struct intel_encoder *encoder, 1172 bool enable, 1173 const struct intel_crtc_state *crtc_state, 1174 const struct drm_connector_state *conn_state) 1175 { 1176 struct intel_display *display = to_intel_display(encoder); 1177 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1178 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1179 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1180 u32 val = intel_de_read(display, reg); 1181 u32 port = VIDEO_DIP_PORT(encoder->port); 1182 1183 assert_hdmi_port_disabled(intel_hdmi); 1184 1185 /* See the big comment in g4x_set_infoframes() */ 1186 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1187 1188 if (!enable) { 1189 if (!(val & VIDEO_DIP_ENABLE)) 1190 return; 1191 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1192 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1193 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1194 intel_de_write(display, reg, val); 1195 intel_de_posting_read(display, reg); 1196 return; 1197 } 1198 1199 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1200 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1201 "DIP already enabled on port %c\n", 1202 (val & VIDEO_DIP_PORT_MASK) >> 29); 1203 val &= ~VIDEO_DIP_PORT_MASK; 1204 val |= port; 1205 } 1206 1207 val |= VIDEO_DIP_ENABLE; 1208 val &= ~(VIDEO_DIP_ENABLE_AVI | 1209 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1210 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1211 1212 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1213 val |= VIDEO_DIP_ENABLE_GCP; 1214 1215 intel_de_write(display, reg, val); 1216 intel_de_posting_read(display, reg); 1217 1218 intel_write_infoframe(encoder, crtc_state, 1219 HDMI_INFOFRAME_TYPE_AVI, 1220 &crtc_state->infoframes.avi); 1221 intel_write_infoframe(encoder, crtc_state, 1222 HDMI_INFOFRAME_TYPE_SPD, 1223 &crtc_state->infoframes.spd); 1224 intel_write_infoframe(encoder, crtc_state, 1225 HDMI_INFOFRAME_TYPE_VENDOR, 1226 &crtc_state->infoframes.hdmi); 1227 } 1228 1229 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, 1230 const struct intel_crtc_state *crtc_state, 1231 const struct drm_connector_state *conn_state) 1232 { 1233 struct intel_display *display = to_intel_display(encoder); 1234 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1235 crtc_state->cpu_transcoder); 1236 u32 val = intel_de_read(display, reg); 1237 1238 if ((crtc_state->infoframes.enable & 1239 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 && 1240 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0) 1241 return; 1242 1243 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK); 1244 1245 intel_de_write(display, reg, val); 1246 intel_de_posting_read(display, reg); 1247 1248 intel_write_infoframe(encoder, crtc_state, 1249 HDMI_INFOFRAME_TYPE_DRM, 1250 &crtc_state->infoframes.drm); 1251 } 1252 1253 static void hsw_set_infoframes(struct intel_encoder *encoder, 1254 bool enable, 1255 const struct intel_crtc_state *crtc_state, 1256 const struct drm_connector_state *conn_state) 1257 { 1258 struct intel_display *display = to_intel_display(encoder); 1259 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1260 crtc_state->cpu_transcoder); 1261 u32 val = intel_de_read(display, reg); 1262 1263 assert_hdmi_transcoder_func_disabled(display, 1264 crtc_state->cpu_transcoder); 1265 1266 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1267 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1268 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1269 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1270 1271 if (!enable) { 1272 intel_de_write(display, reg, val); 1273 intel_de_posting_read(display, reg); 1274 return; 1275 } 1276 1277 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1278 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1279 1280 intel_de_write(display, reg, val); 1281 intel_de_posting_read(display, reg); 1282 1283 intel_write_infoframe(encoder, crtc_state, 1284 HDMI_INFOFRAME_TYPE_AVI, 1285 &crtc_state->infoframes.avi); 1286 intel_write_infoframe(encoder, crtc_state, 1287 HDMI_INFOFRAME_TYPE_SPD, 1288 &crtc_state->infoframes.spd); 1289 intel_write_infoframe(encoder, crtc_state, 1290 HDMI_INFOFRAME_TYPE_VENDOR, 1291 &crtc_state->infoframes.hdmi); 1292 intel_write_infoframe(encoder, crtc_state, 1293 HDMI_INFOFRAME_TYPE_DRM, 1294 &crtc_state->infoframes.drm); 1295 } 1296 1297 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1298 { 1299 struct intel_display *display = to_intel_display(hdmi); 1300 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1301 1302 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1303 return; 1304 1305 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1306 enable ? "Enabling" : "Disabling"); 1307 1308 drm_dp_dual_mode_set_tmds_output(display->drm, 1309 hdmi->dp_dual_mode.type, ddc, enable); 1310 } 1311 1312 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1313 unsigned int offset, void *buffer, size_t size) 1314 { 1315 struct intel_hdmi *hdmi = &dig_port->hdmi; 1316 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1317 int ret; 1318 u8 start = offset & 0xff; 1319 struct i2c_msg msgs[] = { 1320 { 1321 .addr = DRM_HDCP_DDC_ADDR, 1322 .flags = 0, 1323 .len = 1, 1324 .buf = &start, 1325 }, 1326 { 1327 .addr = DRM_HDCP_DDC_ADDR, 1328 .flags = I2C_M_RD, 1329 .len = size, 1330 .buf = buffer 1331 } 1332 }; 1333 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1334 if (ret == ARRAY_SIZE(msgs)) 1335 return 0; 1336 return ret >= 0 ? -EIO : ret; 1337 } 1338 1339 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1340 unsigned int offset, void *buffer, size_t size) 1341 { 1342 struct intel_hdmi *hdmi = &dig_port->hdmi; 1343 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1344 int ret; 1345 u8 *write_buf; 1346 struct i2c_msg msg; 1347 1348 write_buf = kzalloc(size + 1, GFP_KERNEL); 1349 if (!write_buf) 1350 return -ENOMEM; 1351 1352 write_buf[0] = offset & 0xff; 1353 memcpy(&write_buf[1], buffer, size); 1354 1355 msg.addr = DRM_HDCP_DDC_ADDR; 1356 msg.flags = 0; 1357 msg.len = size + 1; 1358 msg.buf = write_buf; 1359 1360 ret = i2c_transfer(ddc, &msg, 1); 1361 if (ret == 1) 1362 ret = 0; 1363 else if (ret >= 0) 1364 ret = -EIO; 1365 1366 kfree(write_buf); 1367 return ret; 1368 } 1369 1370 static 1371 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1372 u8 *an) 1373 { 1374 struct intel_display *display = to_intel_display(dig_port); 1375 struct intel_hdmi *hdmi = &dig_port->hdmi; 1376 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1377 int ret; 1378 1379 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1380 DRM_HDCP_AN_LEN); 1381 if (ret) { 1382 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1383 ret); 1384 return ret; 1385 } 1386 1387 ret = intel_gmbus_output_aksv(ddc); 1388 if (ret < 0) { 1389 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1390 return ret; 1391 } 1392 return 0; 1393 } 1394 1395 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1396 u8 *bksv) 1397 { 1398 struct intel_display *display = to_intel_display(dig_port); 1399 1400 int ret; 1401 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1402 DRM_HDCP_KSV_LEN); 1403 if (ret) 1404 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1405 ret); 1406 return ret; 1407 } 1408 1409 static 1410 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1411 u8 *bstatus) 1412 { 1413 struct intel_display *display = to_intel_display(dig_port); 1414 1415 int ret; 1416 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1417 bstatus, DRM_HDCP_BSTATUS_LEN); 1418 if (ret) 1419 drm_dbg_kms(display->drm, 1420 "Read bstatus over DDC failed (%d)\n", 1421 ret); 1422 return ret; 1423 } 1424 1425 static 1426 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1427 bool *repeater_present) 1428 { 1429 struct intel_display *display = to_intel_display(dig_port); 1430 int ret; 1431 u8 val; 1432 1433 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1434 if (ret) { 1435 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1436 ret); 1437 return ret; 1438 } 1439 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1440 return 0; 1441 } 1442 1443 static 1444 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1445 u8 *ri_prime) 1446 { 1447 struct intel_display *display = to_intel_display(dig_port); 1448 1449 int ret; 1450 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1451 ri_prime, DRM_HDCP_RI_LEN); 1452 if (ret) 1453 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1454 ret); 1455 return ret; 1456 } 1457 1458 static 1459 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1460 bool *ksv_ready) 1461 { 1462 struct intel_display *display = to_intel_display(dig_port); 1463 int ret; 1464 u8 val; 1465 1466 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1467 if (ret) { 1468 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1469 ret); 1470 return ret; 1471 } 1472 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1473 return 0; 1474 } 1475 1476 static 1477 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1478 int num_downstream, u8 *ksv_fifo) 1479 { 1480 struct intel_display *display = to_intel_display(dig_port); 1481 int ret; 1482 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1483 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1484 if (ret) { 1485 drm_dbg_kms(display->drm, 1486 "Read ksv fifo over DDC failed (%d)\n", ret); 1487 return ret; 1488 } 1489 return 0; 1490 } 1491 1492 static 1493 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1494 int i, u32 *part) 1495 { 1496 struct intel_display *display = to_intel_display(dig_port); 1497 int ret; 1498 1499 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1500 return -EINVAL; 1501 1502 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1503 part, DRM_HDCP_V_PRIME_PART_LEN); 1504 if (ret) 1505 drm_dbg_kms(display->drm, 1506 "Read V'[%d] over DDC failed (%d)\n", 1507 i, ret); 1508 return ret; 1509 } 1510 1511 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1512 enum transcoder cpu_transcoder) 1513 { 1514 struct intel_display *display = to_intel_display(connector); 1515 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1516 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1517 u32 scanline; 1518 int ret; 1519 1520 for (;;) { 1521 scanline = intel_de_read(display, 1522 PIPEDSL(display, crtc->pipe)); 1523 if (scanline > 100 && scanline < 200) 1524 break; 1525 usleep_range(25, 50); 1526 } 1527 1528 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1529 false, TRANS_DDI_HDCP_SIGNALLING); 1530 if (ret) { 1531 drm_err(display->drm, 1532 "Disable HDCP signalling failed (%d)\n", ret); 1533 return ret; 1534 } 1535 1536 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1537 true, TRANS_DDI_HDCP_SIGNALLING); 1538 if (ret) { 1539 drm_err(display->drm, 1540 "Enable HDCP signalling failed (%d)\n", ret); 1541 return ret; 1542 } 1543 1544 return 0; 1545 } 1546 1547 static 1548 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1549 enum transcoder cpu_transcoder, 1550 bool enable) 1551 { 1552 struct intel_display *display = to_intel_display(dig_port); 1553 struct intel_hdmi *hdmi = &dig_port->hdmi; 1554 struct intel_connector *connector = hdmi->attached_connector; 1555 int ret; 1556 1557 if (!enable) 1558 usleep_range(6, 60); /* Bspec says >= 6us */ 1559 1560 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1561 cpu_transcoder, enable, 1562 TRANS_DDI_HDCP_SIGNALLING); 1563 if (ret) { 1564 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1565 enable ? "Enable" : "Disable", ret); 1566 return ret; 1567 } 1568 1569 /* 1570 * WA: To fix incorrect positioning of the window of 1571 * opportunity and enc_en signalling in KABYLAKE. 1572 */ 1573 if (display->platform.kabylake && enable) 1574 return kbl_repositioning_enc_en_signal(connector, 1575 cpu_transcoder); 1576 1577 return 0; 1578 } 1579 1580 static 1581 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1582 struct intel_connector *connector) 1583 { 1584 struct intel_display *display = to_intel_display(dig_port); 1585 enum port port = dig_port->base.port; 1586 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1587 int ret; 1588 union { 1589 u32 reg; 1590 u8 shim[DRM_HDCP_RI_LEN]; 1591 } ri; 1592 1593 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1594 if (ret) 1595 return false; 1596 1597 intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg); 1598 1599 /* Wait for Ri prime match */ 1600 ret = intel_de_wait_for_set_ms(display, HDCP_STATUS(display, cpu_transcoder, port), 1601 HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1); 1602 if (ret) { 1603 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1604 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, 1605 port))); 1606 return false; 1607 } 1608 return true; 1609 } 1610 1611 static 1612 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1613 struct intel_connector *connector) 1614 { 1615 int retry; 1616 1617 for (retry = 0; retry < 3; retry++) 1618 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1619 return true; 1620 1621 return false; 1622 } 1623 1624 struct hdcp2_hdmi_msg_timeout { 1625 u8 msg_id; 1626 u16 timeout; 1627 }; 1628 1629 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1630 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1631 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1632 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1633 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1634 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1635 }; 1636 1637 static 1638 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1639 u8 *rx_status) 1640 { 1641 return intel_hdmi_hdcp_read(dig_port, 1642 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1643 rx_status, 1644 HDCP_2_2_HDMI_RXSTATUS_LEN); 1645 } 1646 1647 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1648 { 1649 int i; 1650 1651 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1652 if (is_paired) 1653 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1654 else 1655 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1656 } 1657 1658 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1659 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1660 return hdcp2_msg_timeout[i].timeout; 1661 } 1662 1663 return -EINVAL; 1664 } 1665 1666 static int 1667 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1668 u8 msg_id, bool *msg_ready, 1669 ssize_t *msg_sz) 1670 { 1671 struct intel_display *display = to_intel_display(dig_port); 1672 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1673 int ret; 1674 1675 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1676 if (ret < 0) { 1677 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1678 ret); 1679 return ret; 1680 } 1681 1682 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1683 rx_status[0]); 1684 1685 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1686 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1687 *msg_sz); 1688 else 1689 *msg_ready = *msg_sz; 1690 1691 return 0; 1692 } 1693 1694 static ssize_t 1695 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1696 u8 msg_id, bool paired) 1697 { 1698 struct intel_display *display = to_intel_display(dig_port); 1699 bool msg_ready = false; 1700 int timeout, ret; 1701 ssize_t msg_sz = 0; 1702 1703 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1704 if (timeout < 0) 1705 return timeout; 1706 1707 ret = poll_timeout_us(ret = hdcp2_detect_msg_availability(dig_port, msg_id, 1708 &msg_ready, &msg_sz), 1709 !ret && msg_ready && msg_sz, 1710 4000, timeout * 1000, false); 1711 if (ret) 1712 drm_dbg_kms(display->drm, 1713 "msg_id: %d, ret: %d, timeout: %d\n", 1714 msg_id, ret, timeout); 1715 1716 return ret ? ret : msg_sz; 1717 } 1718 1719 static 1720 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1721 void *buf, size_t size) 1722 { 1723 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1724 unsigned int offset; 1725 1726 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1727 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1728 } 1729 1730 static 1731 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1732 u8 msg_id, void *buf, size_t size) 1733 { 1734 struct intel_display *display = to_intel_display(connector); 1735 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1736 struct intel_hdmi *hdmi = &dig_port->hdmi; 1737 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1738 unsigned int offset; 1739 ssize_t ret; 1740 1741 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1742 hdcp->is_paired); 1743 if (ret < 0) 1744 return ret; 1745 1746 /* 1747 * Available msg size should be equal to or lesser than the 1748 * available buffer. 1749 */ 1750 if (ret > size) { 1751 drm_dbg_kms(display->drm, 1752 "msg_sz(%zd) is more than exp size(%zu)\n", 1753 ret, size); 1754 return -EINVAL; 1755 } 1756 1757 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1758 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1759 if (ret) 1760 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1761 msg_id, ret); 1762 1763 return ret; 1764 } 1765 1766 static 1767 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1768 struct intel_connector *connector) 1769 { 1770 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1771 int ret; 1772 1773 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1774 if (ret) 1775 return ret; 1776 1777 /* 1778 * Re-auth request and Link Integrity Failures are represented by 1779 * same bit. i.e reauth_req. 1780 */ 1781 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1782 ret = HDCP_REAUTH_REQUEST; 1783 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1784 ret = HDCP_TOPOLOGY_CHANGE; 1785 1786 return ret; 1787 } 1788 1789 static 1790 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1791 bool *capable) 1792 { 1793 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1794 u8 hdcp2_version; 1795 int ret; 1796 1797 *capable = false; 1798 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1799 &hdcp2_version, sizeof(hdcp2_version)); 1800 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1801 *capable = true; 1802 1803 return ret; 1804 } 1805 1806 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1807 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1808 .read_bksv = intel_hdmi_hdcp_read_bksv, 1809 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1810 .repeater_present = intel_hdmi_hdcp_repeater_present, 1811 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1812 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1813 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1814 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1815 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1816 .check_link = intel_hdmi_hdcp_check_link, 1817 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1818 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1819 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1820 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1821 .protocol = HDCP_PROTOCOL_HDMI, 1822 }; 1823 1824 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1825 { 1826 struct intel_display *display = to_intel_display(encoder); 1827 int max_tmds_clock, vbt_max_tmds_clock; 1828 1829 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s) 1830 max_tmds_clock = 600000; 1831 else if (DISPLAY_VER(display) >= 10) 1832 max_tmds_clock = 594000; 1833 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) 1834 max_tmds_clock = 300000; 1835 else if (DISPLAY_VER(display) >= 5) 1836 max_tmds_clock = 225000; 1837 else 1838 max_tmds_clock = 165000; 1839 1840 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1841 if (vbt_max_tmds_clock) 1842 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1843 1844 return max_tmds_clock; 1845 } 1846 1847 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1848 const struct drm_connector_state *conn_state) 1849 { 1850 struct intel_connector *connector = hdmi->attached_connector; 1851 1852 return connector->base.display_info.is_hdmi && 1853 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1854 } 1855 1856 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1857 { 1858 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1859 } 1860 1861 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1862 bool respect_downstream_limits, 1863 bool has_hdmi_sink) 1864 { 1865 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1866 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1867 1868 if (respect_downstream_limits) { 1869 struct intel_connector *connector = hdmi->attached_connector; 1870 const struct drm_display_info *info = &connector->base.display_info; 1871 1872 if (hdmi->dp_dual_mode.max_tmds_clock) 1873 max_tmds_clock = min(max_tmds_clock, 1874 hdmi->dp_dual_mode.max_tmds_clock); 1875 1876 if (info->max_tmds_clock) 1877 max_tmds_clock = min(max_tmds_clock, 1878 info->max_tmds_clock); 1879 else if (!has_hdmi_sink) 1880 max_tmds_clock = min(max_tmds_clock, 165000); 1881 } 1882 1883 return max_tmds_clock; 1884 } 1885 1886 static enum drm_mode_status 1887 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1888 int clock, bool respect_downstream_limits, 1889 bool has_hdmi_sink) 1890 { 1891 struct intel_display *display = to_intel_display(hdmi); 1892 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1893 1894 if (clock < 25000) 1895 return MODE_CLOCK_LOW; 1896 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1897 has_hdmi_sink)) 1898 return MODE_CLOCK_HIGH; 1899 1900 /* GLK DPLL can't generate 446-480 MHz */ 1901 if (display->platform.geminilake && clock > 446666 && clock < 480000) 1902 return MODE_CLOCK_RANGE; 1903 1904 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1905 if ((display->platform.geminilake || display->platform.broxton) && 1906 clock > 223333 && clock < 240000) 1907 return MODE_CLOCK_RANGE; 1908 1909 /* CHV DPLL can't generate 216-240 MHz */ 1910 if (display->platform.cherryview && clock > 216000 && clock < 240000) 1911 return MODE_CLOCK_RANGE; 1912 1913 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1914 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1915 return MODE_CLOCK_RANGE; 1916 1917 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1918 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1919 return MODE_CLOCK_RANGE; 1920 1921 return MODE_OK; 1922 } 1923 1924 int intel_hdmi_tmds_clock(int clock, int bpc, 1925 enum intel_output_format sink_format) 1926 { 1927 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1928 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1929 clock /= 2; 1930 1931 /* 1932 * Need to adjust the port link by: 1933 * 1.5x for 12bpc 1934 * 1.25x for 10bpc 1935 */ 1936 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1937 } 1938 1939 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1940 { 1941 switch (bpc) { 1942 case 12: 1943 return !HAS_GMCH(display); 1944 case 10: 1945 return DISPLAY_VER(display) >= 11; 1946 case 8: 1947 return true; 1948 default: 1949 MISSING_CASE(bpc); 1950 return false; 1951 } 1952 } 1953 1954 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector, 1955 int bpc, bool has_hdmi_sink, 1956 enum intel_output_format sink_format) 1957 { 1958 struct intel_connector *connector = to_intel_connector(_connector); 1959 const struct drm_display_info *info = &connector->base.display_info; 1960 const struct drm_hdmi_info *hdmi = &info->hdmi; 1961 1962 switch (bpc) { 1963 case 12: 1964 if (!has_hdmi_sink) 1965 return false; 1966 1967 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1968 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1969 else 1970 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1971 case 10: 1972 if (!has_hdmi_sink) 1973 return false; 1974 1975 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1976 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1977 else 1978 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1979 case 8: 1980 return true; 1981 default: 1982 MISSING_CASE(bpc); 1983 return false; 1984 } 1985 } 1986 1987 static enum drm_mode_status 1988 intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, 1989 bool has_hdmi_sink, 1990 enum intel_output_format sink_format) 1991 { 1992 struct intel_connector *connector = to_intel_connector(_connector); 1993 struct intel_display *display = to_intel_display(connector); 1994 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1995 enum drm_mode_status status = MODE_OK; 1996 int bpc; 1997 1998 /* 1999 * Try all color depths since valid port clock range 2000 * can have holes. Any mode that can be used with at 2001 * least one color depth is accepted. 2002 */ 2003 for (bpc = 12; bpc >= 8; bpc -= 2) { 2004 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 2005 2006 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2007 continue; 2008 2009 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2010 sink_format)) 2011 continue; 2012 2013 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 2014 if (status == MODE_OK) 2015 return MODE_OK; 2016 } 2017 2018 /* can never happen */ 2019 drm_WARN_ON(display->drm, status == MODE_OK); 2020 2021 return status; 2022 } 2023 2024 static enum drm_mode_status 2025 intel_hdmi_mode_valid(struct drm_connector *_connector, 2026 const struct drm_display_mode *mode) 2027 { 2028 struct intel_connector *connector = to_intel_connector(_connector); 2029 struct intel_display *display = to_intel_display(connector); 2030 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2031 enum drm_mode_status status; 2032 int clock = mode->clock; 2033 int max_dotclk = display->cdclk.max_dotclk_freq; 2034 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); 2035 bool ycbcr_420_only; 2036 enum intel_output_format sink_format; 2037 2038 status = intel_cpu_transcoder_mode_valid(display, mode); 2039 if (status != MODE_OK) 2040 return status; 2041 2042 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2043 clock *= 2; 2044 2045 if (clock > max_dotclk) 2046 return MODE_CLOCK_HIGH; 2047 2048 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2049 if (!has_hdmi_sink) 2050 return MODE_CLOCK_LOW; 2051 clock *= 2; 2052 } 2053 2054 /* 2055 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2056 * enumerated only if FRL is supported. Current platforms do not support 2057 * FRL so prune the higher resolution modes that require doctclock more 2058 * than 600MHz. 2059 */ 2060 if (clock > 600000) 2061 return MODE_CLOCK_HIGH; 2062 2063 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); 2064 2065 if (ycbcr_420_only) 2066 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2067 else 2068 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2069 2070 status = intel_pfit_mode_valid(display, mode, sink_format, 0); 2071 if (status != MODE_OK) 2072 return status; 2073 2074 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); 2075 if (status != MODE_OK) { 2076 if (ycbcr_420_only || 2077 !connector->base.ycbcr_420_allowed || 2078 !drm_mode_is_420_also(&connector->base.display_info, mode)) 2079 return status; 2080 2081 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2082 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, 2083 sink_format); 2084 if (status != MODE_OK) 2085 return status; 2086 } 2087 2088 return intel_mode_valid_max_plane_size(display, mode, 1); 2089 } 2090 2091 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2092 int bpc, bool has_hdmi_sink) 2093 { 2094 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 2095 struct intel_digital_connector_state *connector_state; 2096 struct intel_connector *connector; 2097 int i; 2098 2099 for_each_new_intel_connector_in_state(state, connector, connector_state, i) { 2100 if (connector_state->base.crtc != crtc_state->uapi.crtc) 2101 continue; 2102 2103 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2104 crtc_state->sink_format)) 2105 return false; 2106 } 2107 2108 return true; 2109 } 2110 2111 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2112 { 2113 struct intel_display *display = to_intel_display(crtc_state); 2114 const struct drm_display_mode *adjusted_mode = 2115 &crtc_state->hw.adjusted_mode; 2116 2117 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2118 return false; 2119 2120 /* Display Wa_1405510057:icl,ehl */ 2121 if (intel_hdmi_is_ycbcr420(crtc_state) && 2122 bpc == 10 && DISPLAY_VER(display) == 11 && 2123 (adjusted_mode->crtc_hblank_end - 2124 adjusted_mode->crtc_hblank_start) % 8 == 2) 2125 return false; 2126 2127 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2128 } 2129 2130 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2131 struct intel_crtc_state *crtc_state, 2132 int clock, bool respect_downstream_limits) 2133 { 2134 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2135 int bpc; 2136 2137 /* 2138 * pipe_bpp could already be below 8bpc due to FDI 2139 * bandwidth constraints. HDMI minimum is 8bpc however. 2140 */ 2141 bpc = max(crtc_state->pipe_bpp / 3, 8); 2142 2143 /* 2144 * We will never exceed downstream TMDS clock limits while 2145 * attempting deep color. If the user insists on forcing an 2146 * out of spec mode they will have to be satisfied with 8bpc. 2147 */ 2148 if (!respect_downstream_limits) 2149 bpc = 8; 2150 2151 for (; bpc >= 8; bpc -= 2) { 2152 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2153 crtc_state->sink_format); 2154 2155 if (hdmi_bpc_possible(crtc_state, bpc) && 2156 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2157 respect_downstream_limits, 2158 crtc_state->has_hdmi_sink) == MODE_OK) 2159 return bpc; 2160 } 2161 2162 return -EINVAL; 2163 } 2164 2165 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2166 struct intel_crtc_state *crtc_state, 2167 bool respect_downstream_limits) 2168 { 2169 struct intel_display *display = to_intel_display(encoder); 2170 const struct drm_display_mode *adjusted_mode = 2171 &crtc_state->hw.adjusted_mode; 2172 int bpc, clock = adjusted_mode->crtc_clock; 2173 2174 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2175 clock *= 2; 2176 2177 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2178 respect_downstream_limits); 2179 if (bpc < 0) 2180 return bpc; 2181 2182 crtc_state->port_clock = 2183 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2184 2185 /* 2186 * pipe_bpp could already be below 8bpc due to 2187 * FDI bandwidth constraints. We shouldn't bump it 2188 * back up to the HDMI minimum 8bpc in that case. 2189 */ 2190 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2191 2192 drm_dbg_kms(display->drm, 2193 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2194 bpc, crtc_state->pipe_bpp); 2195 2196 return 0; 2197 } 2198 2199 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2200 const struct drm_connector_state *conn_state) 2201 { 2202 const struct intel_digital_connector_state *intel_conn_state = 2203 to_intel_digital_connector_state(conn_state); 2204 const struct drm_display_mode *adjusted_mode = 2205 &crtc_state->hw.adjusted_mode; 2206 2207 /* 2208 * Our YCbCr output is always limited range. 2209 * crtc_state->limited_color_range only applies to RGB, 2210 * and it must never be set for YCbCr or we risk setting 2211 * some conflicting bits in TRANSCONF which will mess up 2212 * the colors on the monitor. 2213 */ 2214 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2215 return false; 2216 2217 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2218 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2219 return crtc_state->has_hdmi_sink && 2220 drm_default_rgb_quant_range(adjusted_mode) == 2221 HDMI_QUANTIZATION_RANGE_LIMITED; 2222 } else { 2223 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2224 } 2225 } 2226 2227 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2228 const struct intel_crtc_state *crtc_state, 2229 const struct drm_connector_state *conn_state) 2230 { 2231 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2232 const struct intel_digital_connector_state *intel_conn_state = 2233 to_intel_digital_connector_state(conn_state); 2234 2235 if (!crtc_state->has_hdmi_sink) 2236 return false; 2237 2238 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2239 return connector->base.display_info.has_audio; 2240 else 2241 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2242 } 2243 2244 static enum intel_output_format 2245 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2246 struct intel_connector *connector, 2247 bool ycbcr_420_output) 2248 { 2249 if (!crtc_state->has_hdmi_sink) 2250 return INTEL_OUTPUT_FORMAT_RGB; 2251 2252 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2253 return INTEL_OUTPUT_FORMAT_YCBCR420; 2254 else 2255 return INTEL_OUTPUT_FORMAT_RGB; 2256 } 2257 2258 static enum intel_output_format 2259 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2260 { 2261 return crtc_state->sink_format; 2262 } 2263 2264 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2265 struct intel_crtc_state *crtc_state, 2266 const struct drm_connector_state *conn_state, 2267 bool respect_downstream_limits) 2268 { 2269 struct intel_display *display = to_intel_display(encoder); 2270 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2271 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2272 const struct drm_display_info *info = &connector->base.display_info; 2273 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2274 int ret; 2275 2276 crtc_state->sink_format = 2277 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2278 2279 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2280 drm_dbg_kms(display->drm, 2281 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2282 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2283 } 2284 2285 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2286 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2287 if (ret) { 2288 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2289 !crtc_state->has_hdmi_sink || 2290 !connector->base.ycbcr_420_allowed || 2291 !drm_mode_is_420_also(info, adjusted_mode)) 2292 return ret; 2293 2294 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2295 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2296 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2297 } 2298 2299 return ret; 2300 } 2301 2302 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2303 { 2304 return crtc_state->uapi.encoder_mask && 2305 !is_power_of_2(crtc_state->uapi.encoder_mask); 2306 } 2307 2308 static bool source_supports_scrambling(struct intel_encoder *encoder) 2309 { 2310 /* 2311 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2312 * scrambling is supported. 2313 * But there seem to be cases where certain platforms that support 2314 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2315 * capped by VBT to less than 340MHz. 2316 * 2317 * In such cases when an HDMI2.0 sink is connected, it creates a 2318 * problem : the platform and the sink both support scrambling but the 2319 * HDMI 1.4 retimer chip doesn't. 2320 * 2321 * So go for scrambling, based on the max tmds clock taking into account, 2322 * restrictions coming from VBT. 2323 */ 2324 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2325 } 2326 2327 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2328 const struct intel_crtc_state *crtc_state, 2329 const struct drm_connector_state *conn_state) 2330 { 2331 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2332 2333 return intel_has_hdmi_sink(hdmi, conn_state) && 2334 !intel_hdmi_is_cloned(crtc_state); 2335 } 2336 2337 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2338 struct intel_crtc_state *pipe_config, 2339 struct drm_connector_state *conn_state) 2340 { 2341 struct intel_display *display = to_intel_display(encoder); 2342 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2343 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2344 struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc; 2345 int ret; 2346 2347 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2348 return -EINVAL; 2349 2350 if (!connector->base.interlace_allowed && 2351 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2352 return -EINVAL; 2353 2354 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2355 2356 if (pipe_config->has_hdmi_sink) 2357 pipe_config->has_infoframe = true; 2358 2359 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2360 pipe_config->pixel_multiplier = 2; 2361 2362 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) 2363 return -EINVAL; 2364 2365 pipe_config->has_audio = 2366 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2367 intel_audio_compute_config(encoder, pipe_config, conn_state); 2368 2369 /* 2370 * Try to respect downstream TMDS clock limits first, if 2371 * that fails assume the user might know something we don't. 2372 */ 2373 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2374 if (ret) 2375 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2376 if (ret) { 2377 drm_dbg_kms(display->drm, 2378 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2379 pipe_config->hw.adjusted_mode.crtc_clock); 2380 return ret; 2381 } 2382 2383 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2384 ret = intel_pfit_compute_config(pipe_config, conn_state); 2385 if (ret) 2386 return ret; 2387 } 2388 2389 pipe_config->limited_color_range = 2390 intel_hdmi_limited_color_range(pipe_config, conn_state); 2391 2392 if (conn_state->picture_aspect_ratio) 2393 adjusted_mode->picture_aspect_ratio = 2394 conn_state->picture_aspect_ratio; 2395 2396 pipe_config->lane_count = 4; 2397 2398 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2399 if (scdc->scrambling.low_rates) 2400 pipe_config->hdmi_scrambling = true; 2401 2402 if (pipe_config->port_clock > 340000) { 2403 pipe_config->hdmi_scrambling = true; 2404 pipe_config->hdmi_high_tmds_clock_ratio = true; 2405 } 2406 } 2407 2408 intel_vrr_compute_config(pipe_config, conn_state); 2409 2410 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2411 conn_state); 2412 2413 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2414 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2415 return -EINVAL; 2416 } 2417 2418 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2419 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2420 return -EINVAL; 2421 } 2422 2423 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2424 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2425 return -EINVAL; 2426 } 2427 2428 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2429 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2430 return -EINVAL; 2431 } 2432 2433 return 0; 2434 } 2435 2436 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2437 { 2438 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2439 2440 /* 2441 * Give a hand to buggy BIOSen which forget to turn 2442 * the TMDS output buffers back on after a reboot. 2443 */ 2444 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2445 } 2446 2447 static void 2448 intel_hdmi_unset_edid(struct drm_connector *_connector) 2449 { 2450 struct intel_connector *connector = to_intel_connector(_connector); 2451 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2452 2453 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2454 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2455 2456 drm_edid_free(connector->detect_edid); 2457 connector->detect_edid = NULL; 2458 } 2459 2460 static void 2461 intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector) 2462 { 2463 struct intel_connector *connector = to_intel_connector(_connector); 2464 struct intel_display *display = to_intel_display(connector); 2465 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2466 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2467 struct i2c_adapter *ddc = connector->base.ddc; 2468 enum drm_dp_dual_mode_type type; 2469 2470 type = drm_dp_dual_mode_detect(display->drm, ddc); 2471 2472 /* 2473 * Type 1 DVI adaptors are not required to implement any 2474 * registers, so we can't always detect their presence. 2475 * Ideally we should be able to check the state of the 2476 * CONFIG1 pin, but no such luck on our hardware. 2477 * 2478 * The only method left to us is to check the VBT to see 2479 * if the port is a dual mode capable DP port. 2480 */ 2481 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2482 if (!connector->base.force && 2483 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2484 drm_dbg_kms(display->drm, 2485 "Assuming DP dual mode adaptor presence based on VBT\n"); 2486 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2487 } else { 2488 type = DRM_DP_DUAL_MODE_NONE; 2489 } 2490 } 2491 2492 if (type == DRM_DP_DUAL_MODE_NONE) 2493 return; 2494 2495 hdmi->dp_dual_mode.type = type; 2496 hdmi->dp_dual_mode.max_tmds_clock = 2497 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2498 2499 drm_dbg_kms(display->drm, 2500 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2501 drm_dp_get_dual_mode_type_name(type), 2502 hdmi->dp_dual_mode.max_tmds_clock); 2503 2504 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2505 if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) && 2506 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2507 drm_dbg_kms(display->drm, 2508 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2509 hdmi->dp_dual_mode.max_tmds_clock = 0; 2510 } 2511 } 2512 2513 static bool 2514 intel_hdmi_set_edid(struct drm_connector *_connector) 2515 { 2516 struct intel_connector *connector = to_intel_connector(_connector); 2517 struct intel_display *display = to_intel_display(connector); 2518 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2519 struct i2c_adapter *ddc = connector->base.ddc; 2520 struct ref_tracker *wakeref; 2521 const struct drm_edid *drm_edid; 2522 bool connected = false; 2523 2524 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2525 2526 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2527 2528 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2529 drm_dbg_kms(display->drm, 2530 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2531 intel_gmbus_force_bit(ddc, true); 2532 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2533 intel_gmbus_force_bit(ddc, false); 2534 } 2535 2536 /* Below we depend on display info having been updated */ 2537 drm_edid_connector_update(&connector->base, drm_edid); 2538 2539 connector->detect_edid = drm_edid; 2540 2541 if (drm_edid_is_digital(drm_edid)) { 2542 intel_hdmi_dp_dual_mode_detect(&connector->base); 2543 2544 connected = true; 2545 } 2546 2547 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2548 2549 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2550 connector->base.display_info.source_physical_address); 2551 2552 return connected; 2553 } 2554 2555 static enum drm_connector_status 2556 intel_hdmi_detect(struct drm_connector *_connector, bool force) 2557 { 2558 struct intel_connector *connector = to_intel_connector(_connector); 2559 struct intel_display *display = to_intel_display(connector); 2560 enum drm_connector_status status = connector_status_disconnected; 2561 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2562 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2563 struct ref_tracker *wakeref; 2564 2565 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2566 connector->base.base.id, connector->base.name); 2567 2568 if (!intel_display_device_enabled(display)) 2569 return connector_status_disconnected; 2570 2571 if (!intel_display_driver_check_access(display)) 2572 return connector->base.status; 2573 2574 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2575 2576 if (DISPLAY_VER(display) >= 11 && 2577 !intel_digital_port_connected(encoder)) 2578 goto out; 2579 2580 intel_hdmi_unset_edid(&connector->base); 2581 2582 if (intel_hdmi_set_edid(&connector->base)) 2583 status = connector_status_connected; 2584 2585 out: 2586 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2587 2588 if (status != connector_status_connected) 2589 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2590 2591 return status; 2592 } 2593 2594 static void 2595 intel_hdmi_force(struct drm_connector *_connector) 2596 { 2597 struct intel_connector *connector = to_intel_connector(_connector); 2598 struct intel_display *display = to_intel_display(connector); 2599 2600 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2601 connector->base.base.id, connector->base.name); 2602 2603 if (!intel_display_driver_check_access(display)) 2604 return; 2605 2606 intel_hdmi_unset_edid(&connector->base); 2607 2608 if (connector->base.status != connector_status_connected) 2609 return; 2610 2611 intel_hdmi_set_edid(&connector->base); 2612 } 2613 2614 static int intel_hdmi_get_modes(struct drm_connector *_connector) 2615 { 2616 struct intel_connector *connector = to_intel_connector(_connector); 2617 2618 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2619 return drm_edid_connector_add_modes(&connector->base); 2620 } 2621 2622 static int 2623 intel_hdmi_connector_register(struct drm_connector *_connector) 2624 { 2625 struct intel_connector *connector = to_intel_connector(_connector); 2626 int ret; 2627 2628 ret = intel_connector_register(&connector->base); 2629 if (ret) 2630 return ret; 2631 2632 return ret; 2633 } 2634 2635 static void intel_hdmi_connector_unregister(struct drm_connector *_connector) 2636 { 2637 struct intel_connector *connector = to_intel_connector(_connector); 2638 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; 2639 2640 cec_notifier_conn_unregister(n); 2641 2642 intel_connector_unregister(&connector->base); 2643 } 2644 2645 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2646 .detect = intel_hdmi_detect, 2647 .force = intel_hdmi_force, 2648 .fill_modes = drm_helper_probe_single_connector_modes, 2649 .atomic_get_property = intel_digital_connector_atomic_get_property, 2650 .atomic_set_property = intel_digital_connector_atomic_set_property, 2651 .late_register = intel_hdmi_connector_register, 2652 .early_unregister = intel_hdmi_connector_unregister, 2653 .destroy = intel_connector_destroy, 2654 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2655 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2656 }; 2657 2658 static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, 2659 struct drm_atomic_state *state) 2660 { 2661 struct intel_connector *connector = to_intel_connector(_connector); 2662 struct intel_display *display = to_intel_display(connector); 2663 2664 if (HAS_DDI(display)) 2665 return intel_digital_connector_atomic_check(&connector->base, state); 2666 else 2667 return g4x_hdmi_connector_atomic_check(&connector->base, state); 2668 } 2669 2670 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2671 .get_modes = intel_hdmi_get_modes, 2672 .mode_valid = intel_hdmi_mode_valid, 2673 .atomic_check = intel_hdmi_connector_atomic_check, 2674 }; 2675 2676 static void 2677 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_connector) 2678 { 2679 struct intel_connector *connector = to_intel_connector(_connector); 2680 struct intel_display *display = to_intel_display(intel_hdmi); 2681 2682 intel_attach_force_audio_property(&connector->base); 2683 intel_attach_broadcast_rgb_property(&connector->base); 2684 intel_attach_aspect_ratio_property(&connector->base); 2685 2686 intel_attach_hdmi_colorspace_property(&connector->base); 2687 drm_connector_attach_content_type_property(&connector->base); 2688 2689 if (DISPLAY_VER(display) >= 10) 2690 drm_connector_attach_hdr_output_metadata_property(&connector->base); 2691 2692 if (!HAS_GMCH(display)) 2693 drm_connector_attach_max_bpc_property(&connector->base, 8, 12); 2694 } 2695 2696 /* 2697 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2698 * @encoder: intel_encoder 2699 * @connector: drm_connector 2700 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2701 * or reset the high tmds clock ratio for scrambling 2702 * @scrambling: bool to Indicate if the function needs to set or reset 2703 * sink scrambling 2704 * 2705 * This function handles scrambling on HDMI 2.0 capable sinks. 2706 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2707 * it enables scrambling. This should be called before enabling the HDMI 2708 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2709 * detect a scrambled clock within 100 ms. 2710 * 2711 * Returns: 2712 * True on success, false on failure. 2713 */ 2714 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2715 struct drm_connector *_connector, 2716 bool high_tmds_clock_ratio, 2717 bool scrambling) 2718 { 2719 struct intel_connector *connector = to_intel_connector(_connector); 2720 struct intel_display *display = to_intel_display(encoder); 2721 struct drm_scrambling *sink_scrambling = 2722 &connector->base.display_info.hdmi.scdc.scrambling; 2723 2724 if (!sink_scrambling->supported) 2725 return true; 2726 2727 drm_dbg_kms(display->drm, 2728 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2729 connector->base.base.id, connector->base.name, 2730 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2731 2732 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2733 return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) && 2734 drm_scdc_set_scrambling(&connector->base, scrambling); 2735 } 2736 2737 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2738 { 2739 enum port port = encoder->port; 2740 u8 ddc_pin; 2741 2742 switch (port) { 2743 case PORT_B: 2744 ddc_pin = GMBUS_PIN_DPB; 2745 break; 2746 case PORT_C: 2747 ddc_pin = GMBUS_PIN_DPC; 2748 break; 2749 case PORT_D: 2750 ddc_pin = GMBUS_PIN_DPD_CHV; 2751 break; 2752 default: 2753 MISSING_CASE(port); 2754 ddc_pin = GMBUS_PIN_DPB; 2755 break; 2756 } 2757 return ddc_pin; 2758 } 2759 2760 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2761 { 2762 enum port port = encoder->port; 2763 u8 ddc_pin; 2764 2765 switch (port) { 2766 case PORT_B: 2767 ddc_pin = GMBUS_PIN_1_BXT; 2768 break; 2769 case PORT_C: 2770 ddc_pin = GMBUS_PIN_2_BXT; 2771 break; 2772 default: 2773 MISSING_CASE(port); 2774 ddc_pin = GMBUS_PIN_1_BXT; 2775 break; 2776 } 2777 return ddc_pin; 2778 } 2779 2780 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2781 { 2782 enum port port = encoder->port; 2783 u8 ddc_pin; 2784 2785 switch (port) { 2786 case PORT_B: 2787 ddc_pin = GMBUS_PIN_1_BXT; 2788 break; 2789 case PORT_C: 2790 ddc_pin = GMBUS_PIN_2_BXT; 2791 break; 2792 case PORT_D: 2793 ddc_pin = GMBUS_PIN_4_CNP; 2794 break; 2795 case PORT_F: 2796 ddc_pin = GMBUS_PIN_3_BXT; 2797 break; 2798 default: 2799 MISSING_CASE(port); 2800 ddc_pin = GMBUS_PIN_1_BXT; 2801 break; 2802 } 2803 return ddc_pin; 2804 } 2805 2806 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2807 { 2808 struct intel_display *display = to_intel_display(encoder); 2809 enum port port = encoder->port; 2810 2811 if (intel_encoder_is_combo(encoder)) 2812 return GMBUS_PIN_1_BXT + port; 2813 else if (intel_encoder_is_tc(encoder)) 2814 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2815 2816 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2817 return GMBUS_PIN_2_BXT; 2818 } 2819 2820 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2821 { 2822 enum phy phy = intel_encoder_to_phy(encoder); 2823 u8 ddc_pin; 2824 2825 switch (phy) { 2826 case PHY_A: 2827 ddc_pin = GMBUS_PIN_1_BXT; 2828 break; 2829 case PHY_B: 2830 ddc_pin = GMBUS_PIN_2_BXT; 2831 break; 2832 case PHY_C: 2833 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2834 break; 2835 default: 2836 MISSING_CASE(phy); 2837 ddc_pin = GMBUS_PIN_1_BXT; 2838 break; 2839 } 2840 return ddc_pin; 2841 } 2842 2843 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2844 { 2845 struct intel_display *display = to_intel_display(encoder); 2846 enum phy phy = intel_encoder_to_phy(encoder); 2847 2848 WARN_ON(encoder->port == PORT_C); 2849 2850 /* 2851 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2852 * final two outputs use type-c pins, even though they're actually 2853 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2854 * all outputs. 2855 */ 2856 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2857 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2858 2859 return GMBUS_PIN_1_BXT + phy; 2860 } 2861 2862 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2863 { 2864 struct intel_display *display = to_intel_display(encoder); 2865 enum phy phy = intel_encoder_to_phy(encoder); 2866 2867 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2868 2869 /* 2870 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2871 * final two outputs use type-c pins, even though they're actually 2872 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2873 * all outputs. 2874 */ 2875 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2876 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2877 2878 return GMBUS_PIN_1_BXT + phy; 2879 } 2880 2881 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2882 { 2883 return intel_encoder_to_phy(encoder) + 1; 2884 } 2885 2886 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2887 { 2888 enum phy phy = intel_encoder_to_phy(encoder); 2889 2890 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2891 2892 /* 2893 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2894 * except first combo output. 2895 */ 2896 if (phy == PHY_A) 2897 return GMBUS_PIN_1_BXT; 2898 2899 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2900 } 2901 2902 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2903 { 2904 enum port port = encoder->port; 2905 u8 ddc_pin; 2906 2907 switch (port) { 2908 case PORT_B: 2909 ddc_pin = GMBUS_PIN_DPB; 2910 break; 2911 case PORT_C: 2912 ddc_pin = GMBUS_PIN_DPC; 2913 break; 2914 case PORT_D: 2915 ddc_pin = GMBUS_PIN_DPD; 2916 break; 2917 default: 2918 MISSING_CASE(port); 2919 ddc_pin = GMBUS_PIN_DPB; 2920 break; 2921 } 2922 return ddc_pin; 2923 } 2924 2925 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2926 { 2927 struct intel_display *display = to_intel_display(encoder); 2928 u8 ddc_pin; 2929 2930 if (display->platform.alderlake_s) 2931 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2932 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 2933 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2934 else if (display->platform.rocketlake) 2935 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2936 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display)) 2937 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2938 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 2939 HAS_PCH_TGP(display)) 2940 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2941 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2942 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2943 else if (HAS_PCH_CNP(display)) 2944 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2945 else if (display->platform.geminilake || display->platform.broxton) 2946 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2947 else if (display->platform.cherryview) 2948 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2949 else 2950 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2951 2952 return ddc_pin; 2953 } 2954 2955 static struct intel_encoder * 2956 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2957 { 2958 struct intel_display *display = to_intel_display(encoder); 2959 struct intel_encoder *other; 2960 2961 for_each_intel_encoder(display->drm, other) { 2962 struct intel_connector *connector; 2963 2964 if (other == encoder) 2965 continue; 2966 2967 if (!intel_encoder_is_dig_port(other)) 2968 continue; 2969 2970 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2971 2972 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) 2973 return other; 2974 } 2975 2976 return NULL; 2977 } 2978 2979 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2980 { 2981 struct intel_display *display = to_intel_display(encoder); 2982 struct intel_encoder *other; 2983 const char *source; 2984 u8 ddc_pin; 2985 2986 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2987 source = "VBT"; 2988 2989 if (!ddc_pin) { 2990 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2991 source = "platform default"; 2992 } 2993 2994 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { 2995 drm_dbg_kms(display->drm, 2996 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2997 encoder->base.base.id, encoder->base.name, ddc_pin); 2998 return 0; 2999 } 3000 3001 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 3002 if (other) { 3003 drm_dbg_kms(display->drm, 3004 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 3005 encoder->base.base.id, encoder->base.name, ddc_pin, 3006 other->base.base.id, other->base.name); 3007 return 0; 3008 } 3009 3010 drm_dbg_kms(display->drm, 3011 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 3012 encoder->base.base.id, encoder->base.name, 3013 ddc_pin, source); 3014 3015 return ddc_pin; 3016 } 3017 3018 void intel_infoframe_init(struct intel_digital_port *dig_port) 3019 { 3020 struct intel_display *display = to_intel_display(dig_port); 3021 3022 if (display->platform.valleyview || display->platform.cherryview) { 3023 dig_port->write_infoframe = vlv_write_infoframe; 3024 dig_port->read_infoframe = vlv_read_infoframe; 3025 dig_port->set_infoframes = vlv_set_infoframes; 3026 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3027 } else if (display->platform.g4x) { 3028 dig_port->write_infoframe = g4x_write_infoframe; 3029 dig_port->read_infoframe = g4x_read_infoframe; 3030 dig_port->set_infoframes = g4x_set_infoframes; 3031 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3032 } else if (HAS_DDI(display)) { 3033 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 3034 dig_port->write_infoframe = lspcon_write_infoframe; 3035 dig_port->read_infoframe = lspcon_read_infoframe; 3036 dig_port->set_infoframes = lspcon_set_infoframes; 3037 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3038 } else { 3039 dig_port->write_infoframe = hsw_write_infoframe; 3040 dig_port->read_infoframe = hsw_read_infoframe; 3041 dig_port->set_infoframes = hsw_set_infoframes; 3042 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3043 } 3044 } else if (HAS_PCH_IBX(display)) { 3045 dig_port->write_infoframe = ibx_write_infoframe; 3046 dig_port->read_infoframe = ibx_read_infoframe; 3047 dig_port->set_infoframes = ibx_set_infoframes; 3048 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3049 } else { 3050 dig_port->write_infoframe = cpt_write_infoframe; 3051 dig_port->read_infoframe = cpt_read_infoframe; 3052 dig_port->set_infoframes = cpt_set_infoframes; 3053 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3054 } 3055 } 3056 3057 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3058 struct intel_connector *intel_connector) 3059 { 3060 struct intel_display *display = to_intel_display(dig_port); 3061 struct drm_connector *connector = &intel_connector->base; 3062 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3063 struct intel_encoder *intel_encoder = &dig_port->base; 3064 struct drm_device *dev = intel_encoder->base.dev; 3065 enum port port = intel_encoder->port; 3066 struct cec_connector_info conn_info; 3067 u8 ddc_pin; 3068 3069 drm_dbg_kms(display->drm, 3070 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3071 intel_encoder->base.base.id, intel_encoder->base.name); 3072 3073 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3074 return false; 3075 3076 if (drm_WARN(dev, dig_port->max_lanes < 4, 3077 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3078 dig_port->max_lanes, intel_encoder->base.base.id, 3079 intel_encoder->base.name)) 3080 return false; 3081 3082 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3083 if (!ddc_pin) 3084 return false; 3085 3086 drm_connector_init_with_ddc(dev, connector, 3087 &intel_hdmi_connector_funcs, 3088 DRM_MODE_CONNECTOR_HDMIA, 3089 intel_gmbus_get_adapter(display, ddc_pin)); 3090 3091 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3092 3093 if (DISPLAY_VER(display) < 12) 3094 connector->interlace_allowed = true; 3095 3096 connector->stereo_allowed = true; 3097 3098 if (DISPLAY_VER(display) >= 10) 3099 connector->ycbcr_420_allowed = true; 3100 3101 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3102 intel_connector->base.polled = intel_connector->polled; 3103 3104 if (HAS_DDI(display)) 3105 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3106 else 3107 intel_connector->get_hw_state = intel_connector_get_hw_state; 3108 3109 intel_hdmi_add_properties(intel_hdmi, connector); 3110 3111 intel_connector_attach_encoder(intel_connector, intel_encoder); 3112 intel_hdmi->attached_connector = intel_connector; 3113 3114 if (is_hdcp_supported(display, port)) { 3115 int ret = intel_hdcp_init(intel_connector, dig_port, 3116 &intel_hdmi_hdcp_shim); 3117 if (ret) 3118 drm_dbg_kms(display->drm, 3119 "HDCP init failed, skipping.\n"); 3120 } 3121 3122 cec_fill_conn_info_from_drm(&conn_info, connector); 3123 3124 intel_hdmi->cec_notifier = 3125 cec_notifier_conn_register(dev->dev, port_identifier(port), 3126 &conn_info); 3127 if (!intel_hdmi->cec_notifier) 3128 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3129 3130 return true; 3131 } 3132 3133 /* 3134 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3135 * @vactive: Vactive of a display mode 3136 * 3137 * @return: appropriate dsc slice height for a given mode. 3138 */ 3139 int intel_hdmi_dsc_get_slice_height(int vactive) 3140 { 3141 int slice_height; 3142 3143 /* 3144 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3145 * Select smallest slice height >=96, that results in a valid PPS and 3146 * requires minimum padding lines required for final slice. 3147 * 3148 * Assumption : Vactive is even. 3149 */ 3150 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3151 if (vactive % slice_height == 0) 3152 return slice_height; 3153 3154 return 0; 3155 } 3156 3157 /* 3158 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3159 * and dsc decoder capabilities 3160 * 3161 * @crtc_state: intel crtc_state 3162 * @src_max_slices: maximum slices supported by the DSC encoder 3163 * @src_max_slice_width: maximum slice width supported by DSC encoder 3164 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3165 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3166 * 3167 * @return: num of dsc slices that can be supported by the dsc encoder 3168 * and decoder. 3169 */ 3170 int 3171 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3172 int src_max_slices, int src_max_slice_width, 3173 int hdmi_max_slices, int hdmi_throughput) 3174 { 3175 /* Pixel rates in KPixels/sec */ 3176 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3177 /* 3178 * Rates at which the source and sink are required to process pixels in each 3179 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3180 */ 3181 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3182 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3183 3184 /* Spec limits the slice width to 2720 pixels */ 3185 #define MAX_HDMI_SLICE_WIDTH 2720 3186 int kslice_adjust; 3187 int adjusted_clk_khz; 3188 int min_slices; 3189 int target_slices; 3190 int max_throughput; /* max clock freq. in khz per slice */ 3191 int max_slice_width; 3192 int slice_width; 3193 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3194 3195 if (!hdmi_throughput) 3196 return 0; 3197 3198 /* 3199 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3200 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3201 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3202 * dividing adjusted clock value by 10. 3203 */ 3204 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3205 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3206 kslice_adjust = 10; 3207 else 3208 kslice_adjust = 5; 3209 3210 /* 3211 * As per spec, the rate at which the source and the sink process 3212 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3213 * This depends upon the pixel clock rate and output formats 3214 * (kslice adjust). 3215 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3216 * at max 340MHz, otherwise they can be processed at max 400MHz. 3217 */ 3218 3219 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3220 3221 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3222 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3223 else 3224 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3225 3226 /* 3227 * Taking into account the sink's capability for maximum 3228 * clock per slice (in MHz) as read from HF-VSDB. 3229 */ 3230 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3231 3232 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3233 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3234 3235 /* 3236 * Keep on increasing the num of slices/line, starting from min_slices 3237 * per line till we get such a number, for which the slice_width is 3238 * just less than max_slice_width. The slices/line selected should be 3239 * less than or equal to the max horizontal slices that the combination 3240 * of PCON encoder and HDMI decoder can support. 3241 */ 3242 slice_width = max_slice_width; 3243 3244 do { 3245 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3246 target_slices = 1; 3247 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3248 target_slices = 2; 3249 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3250 target_slices = 4; 3251 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3252 target_slices = 8; 3253 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3254 target_slices = 12; 3255 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3256 target_slices = 16; 3257 else 3258 return 0; 3259 3260 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3261 if (slice_width >= max_slice_width) 3262 min_slices = target_slices + 1; 3263 } while (slice_width >= max_slice_width); 3264 3265 return target_slices; 3266 } 3267 3268 /* 3269 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3270 * source and sink capabilities. 3271 * 3272 * @src_fraction_bpp: fractional bpp supported by the source 3273 * @slice_width: dsc slice width supported by the source and sink 3274 * @num_slices: num of slices supported by the source and sink 3275 * @output_format: video output format 3276 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3277 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3278 * 3279 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3280 */ 3281 int 3282 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3283 int output_format, bool hdmi_all_bpp, 3284 int hdmi_max_chunk_bytes) 3285 { 3286 int max_dsc_bpp, min_dsc_bpp; 3287 int target_bytes; 3288 bool bpp_found = false; 3289 int bpp_decrement_x16; 3290 int bpp_target; 3291 int bpp_target_x16; 3292 3293 /* 3294 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3295 * Start with the max bpp and keep on decrementing with 3296 * fractional bpp, if supported by PCON DSC encoder 3297 * 3298 * for each bpp we check if no of bytes can be supported by HDMI sink 3299 */ 3300 3301 /* Assuming: bpc as 8*/ 3302 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3303 min_dsc_bpp = 6; 3304 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3305 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3306 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3307 min_dsc_bpp = 8; 3308 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3309 } else { 3310 /* Assuming 4:2:2 encoding */ 3311 min_dsc_bpp = 7; 3312 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3313 } 3314 3315 /* 3316 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3317 * Section 7.7.34 : Source shall not enable compressed Video 3318 * Transport with bpp_target settings above 12 bpp unless 3319 * DSC_all_bpp is set to 1. 3320 */ 3321 if (!hdmi_all_bpp) 3322 max_dsc_bpp = min(max_dsc_bpp, 12); 3323 3324 /* 3325 * The Sink has a limit of compressed data in bytes for a scanline, 3326 * as described in max_chunk_bytes field in HFVSDB block of edid. 3327 * The no. of bytes depend on the target bits per pixel that the 3328 * source configures. So we start with the max_bpp and calculate 3329 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3330 * till we get the target_chunk_bytes just less than what the sink's 3331 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3332 * 3333 * The decrement is according to the fractional support from PCON DSC 3334 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3335 * 3336 * bpp_target_x16 = bpp_target * 16 3337 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3338 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3339 */ 3340 3341 bpp_target = max_dsc_bpp; 3342 3343 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3344 if (!src_fractional_bpp) 3345 src_fractional_bpp = 1; 3346 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3347 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3348 3349 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3350 int bpp; 3351 3352 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3353 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3354 if (target_bytes <= hdmi_max_chunk_bytes) { 3355 bpp_found = true; 3356 break; 3357 } 3358 bpp_target_x16 -= bpp_decrement_x16; 3359 } 3360 if (bpp_found) 3361 return bpp_target_x16; 3362 3363 return 0; 3364 } 3365