1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <drm/display/drm_hdcp_helper.h> 36 #include <drm/display/drm_hdmi_helper.h> 37 #include <drm/display/drm_scdc_helper.h> 38 #include <drm/drm_atomic_helper.h> 39 #include <drm/drm_crtc.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_print.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/intel/intel_lpe_audio.h> 44 #include <media/cec-notifier.h> 45 46 #include "g4x_hdmi.h" 47 #include "i915_utils.h" 48 #include "intel_atomic.h" 49 #include "intel_audio.h" 50 #include "intel_connector.h" 51 #include "intel_cx0_phy.h" 52 #include "intel_ddi.h" 53 #include "intel_de.h" 54 #include "intel_display_driver.h" 55 #include "intel_display_regs.h" 56 #include "intel_display_types.h" 57 #include "intel_dp.h" 58 #include "intel_gmbus.h" 59 #include "intel_hdcp.h" 60 #include "intel_hdcp_regs.h" 61 #include "intel_hdcp_shim.h" 62 #include "intel_hdmi.h" 63 #include "intel_lspcon.h" 64 #include "intel_panel.h" 65 #include "intel_pfit.h" 66 #include "intel_snps_phy.h" 67 #include "intel_vrr.h" 68 69 static void 70 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 71 { 72 struct intel_display *display = to_intel_display(intel_hdmi); 73 u32 enabled_bits; 74 75 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 76 77 drm_WARN(display->drm, 78 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 79 "HDMI port enabled, expecting disabled\n"); 80 } 81 82 static void 83 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 84 enum transcoder cpu_transcoder) 85 { 86 drm_WARN(display->drm, 87 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 88 TRANS_DDI_FUNC_ENABLE, 89 "HDMI transcoder function enabled, expecting disabled\n"); 90 } 91 92 static u32 g4x_infoframe_index(unsigned int type) 93 { 94 switch (type) { 95 case HDMI_PACKET_TYPE_GAMUT_METADATA: 96 return VIDEO_DIP_SELECT_GAMUT; 97 case HDMI_INFOFRAME_TYPE_AVI: 98 return VIDEO_DIP_SELECT_AVI; 99 case HDMI_INFOFRAME_TYPE_SPD: 100 return VIDEO_DIP_SELECT_SPD; 101 case HDMI_INFOFRAME_TYPE_VENDOR: 102 return VIDEO_DIP_SELECT_VENDOR; 103 default: 104 MISSING_CASE(type); 105 return 0; 106 } 107 } 108 109 static u32 g4x_infoframe_enable(unsigned int type) 110 { 111 switch (type) { 112 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 113 return VIDEO_DIP_ENABLE_GCP; 114 case HDMI_PACKET_TYPE_GAMUT_METADATA: 115 return VIDEO_DIP_ENABLE_GAMUT; 116 case DP_SDP_VSC: 117 return 0; 118 case DP_SDP_ADAPTIVE_SYNC: 119 return 0; 120 case HDMI_INFOFRAME_TYPE_AVI: 121 return VIDEO_DIP_ENABLE_AVI; 122 case HDMI_INFOFRAME_TYPE_SPD: 123 return VIDEO_DIP_ENABLE_SPD; 124 case HDMI_INFOFRAME_TYPE_VENDOR: 125 return VIDEO_DIP_ENABLE_VENDOR; 126 case HDMI_INFOFRAME_TYPE_DRM: 127 return 0; 128 default: 129 MISSING_CASE(type); 130 return 0; 131 } 132 } 133 134 static u32 hsw_infoframe_enable(unsigned int type) 135 { 136 switch (type) { 137 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 138 return VIDEO_DIP_ENABLE_GCP_HSW; 139 case HDMI_PACKET_TYPE_GAMUT_METADATA: 140 return VIDEO_DIP_ENABLE_GMP_HSW; 141 case DP_SDP_VSC: 142 return VIDEO_DIP_ENABLE_VSC_HSW; 143 case DP_SDP_ADAPTIVE_SYNC: 144 return VIDEO_DIP_ENABLE_AS_ADL; 145 case DP_SDP_PPS: 146 return VDIP_ENABLE_PPS; 147 case HDMI_INFOFRAME_TYPE_AVI: 148 return VIDEO_DIP_ENABLE_AVI_HSW; 149 case HDMI_INFOFRAME_TYPE_SPD: 150 return VIDEO_DIP_ENABLE_SPD_HSW; 151 case HDMI_INFOFRAME_TYPE_VENDOR: 152 return VIDEO_DIP_ENABLE_VS_HSW; 153 case HDMI_INFOFRAME_TYPE_DRM: 154 return VIDEO_DIP_ENABLE_DRM_GLK; 155 default: 156 MISSING_CASE(type); 157 return 0; 158 } 159 } 160 161 static i915_reg_t 162 hsw_dip_data_reg(struct intel_display *display, 163 enum transcoder cpu_transcoder, 164 unsigned int type, 165 int i) 166 { 167 switch (type) { 168 case HDMI_PACKET_TYPE_GAMUT_METADATA: 169 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 170 case DP_SDP_VSC: 171 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 172 case DP_SDP_ADAPTIVE_SYNC: 173 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 174 case DP_SDP_PPS: 175 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 176 case HDMI_INFOFRAME_TYPE_AVI: 177 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 178 case HDMI_INFOFRAME_TYPE_SPD: 179 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_VENDOR: 181 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_DRM: 183 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 184 default: 185 MISSING_CASE(type); 186 return INVALID_MMIO_REG; 187 } 188 } 189 190 static int hsw_dip_data_size(struct intel_display *display, 191 unsigned int type) 192 { 193 switch (type) { 194 case DP_SDP_VSC: 195 return VIDEO_DIP_VSC_DATA_SIZE; 196 case DP_SDP_ADAPTIVE_SYNC: 197 return VIDEO_DIP_ASYNC_DATA_SIZE; 198 case DP_SDP_PPS: 199 return VIDEO_DIP_PPS_DATA_SIZE; 200 case HDMI_PACKET_TYPE_GAMUT_METADATA: 201 if (DISPLAY_VER(display) >= 11) 202 return VIDEO_DIP_GMP_DATA_SIZE; 203 else 204 return VIDEO_DIP_DATA_SIZE; 205 default: 206 return VIDEO_DIP_DATA_SIZE; 207 } 208 } 209 210 static void g4x_write_infoframe(struct intel_encoder *encoder, 211 const struct intel_crtc_state *crtc_state, 212 unsigned int type, 213 const void *frame, ssize_t len) 214 { 215 struct intel_display *display = to_intel_display(encoder); 216 const u32 *data = frame; 217 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 218 int i; 219 220 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 221 "Writing DIP with CTL reg disabled\n"); 222 223 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 224 val |= g4x_infoframe_index(type); 225 226 val &= ~g4x_infoframe_enable(type); 227 228 intel_de_write(display, VIDEO_DIP_CTL, val); 229 230 for (i = 0; i < len; i += 4) { 231 intel_de_write(display, VIDEO_DIP_DATA, *data); 232 data++; 233 } 234 /* Write every possible data byte to force correct ECC calculation. */ 235 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 236 intel_de_write(display, VIDEO_DIP_DATA, 0); 237 238 val |= g4x_infoframe_enable(type); 239 val &= ~VIDEO_DIP_FREQ_MASK; 240 val |= VIDEO_DIP_FREQ_VSYNC; 241 242 intel_de_write(display, VIDEO_DIP_CTL, val); 243 intel_de_posting_read(display, VIDEO_DIP_CTL); 244 } 245 246 static void g4x_read_infoframe(struct intel_encoder *encoder, 247 const struct intel_crtc_state *crtc_state, 248 unsigned int type, 249 void *frame, ssize_t len) 250 { 251 struct intel_display *display = to_intel_display(encoder); 252 u32 *data = frame; 253 int i; 254 255 intel_de_rmw(display, VIDEO_DIP_CTL, 256 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 257 258 for (i = 0; i < len; i += 4) 259 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 260 } 261 262 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 263 const struct intel_crtc_state *pipe_config) 264 { 265 struct intel_display *display = to_intel_display(encoder); 266 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 267 268 if ((val & VIDEO_DIP_ENABLE) == 0) 269 return 0; 270 271 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 272 return 0; 273 274 return val & (VIDEO_DIP_ENABLE_AVI | 275 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 276 } 277 278 static void ibx_write_infoframe(struct intel_encoder *encoder, 279 const struct intel_crtc_state *crtc_state, 280 unsigned int type, 281 const void *frame, ssize_t len) 282 { 283 struct intel_display *display = to_intel_display(encoder); 284 const u32 *data = frame; 285 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 286 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 287 u32 val = intel_de_read(display, reg); 288 int i; 289 290 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 291 "Writing DIP with CTL reg disabled\n"); 292 293 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 294 val |= g4x_infoframe_index(type); 295 296 val &= ~g4x_infoframe_enable(type); 297 298 intel_de_write(display, reg, val); 299 300 for (i = 0; i < len; i += 4) { 301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 302 *data); 303 data++; 304 } 305 /* Write every possible data byte to force correct ECC calculation. */ 306 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 307 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 308 309 val |= g4x_infoframe_enable(type); 310 val &= ~VIDEO_DIP_FREQ_MASK; 311 val |= VIDEO_DIP_FREQ_VSYNC; 312 313 intel_de_write(display, reg, val); 314 intel_de_posting_read(display, reg); 315 } 316 317 static void ibx_read_infoframe(struct intel_encoder *encoder, 318 const struct intel_crtc_state *crtc_state, 319 unsigned int type, 320 void *frame, ssize_t len) 321 { 322 struct intel_display *display = to_intel_display(encoder); 323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 324 u32 *data = frame; 325 int i; 326 327 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 328 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 329 330 for (i = 0; i < len; i += 4) 331 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 332 } 333 334 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 335 const struct intel_crtc_state *pipe_config) 336 { 337 struct intel_display *display = to_intel_display(encoder); 338 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 339 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 340 u32 val = intel_de_read(display, reg); 341 342 if ((val & VIDEO_DIP_ENABLE) == 0) 343 return 0; 344 345 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 346 return 0; 347 348 return val & (VIDEO_DIP_ENABLE_AVI | 349 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 350 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 351 } 352 353 static void cpt_write_infoframe(struct intel_encoder *encoder, 354 const struct intel_crtc_state *crtc_state, 355 unsigned int type, 356 const void *frame, ssize_t len) 357 { 358 struct intel_display *display = to_intel_display(encoder); 359 const u32 *data = frame; 360 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 361 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 362 u32 val = intel_de_read(display, reg); 363 int i; 364 365 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 366 "Writing DIP with CTL reg disabled\n"); 367 368 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 369 val |= g4x_infoframe_index(type); 370 371 /* The DIP control register spec says that we need to update the AVI 372 * infoframe without clearing its enable bit */ 373 if (type != HDMI_INFOFRAME_TYPE_AVI) 374 val &= ~g4x_infoframe_enable(type); 375 376 intel_de_write(display, reg, val); 377 378 for (i = 0; i < len; i += 4) { 379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 380 *data); 381 data++; 382 } 383 /* Write every possible data byte to force correct ECC calculation. */ 384 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 385 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 386 387 val |= g4x_infoframe_enable(type); 388 val &= ~VIDEO_DIP_FREQ_MASK; 389 val |= VIDEO_DIP_FREQ_VSYNC; 390 391 intel_de_write(display, reg, val); 392 intel_de_posting_read(display, reg); 393 } 394 395 static void cpt_read_infoframe(struct intel_encoder *encoder, 396 const struct intel_crtc_state *crtc_state, 397 unsigned int type, 398 void *frame, ssize_t len) 399 { 400 struct intel_display *display = to_intel_display(encoder); 401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 402 u32 *data = frame; 403 int i; 404 405 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 406 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 407 408 for (i = 0; i < len; i += 4) 409 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 410 } 411 412 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 413 const struct intel_crtc_state *pipe_config) 414 { 415 struct intel_display *display = to_intel_display(encoder); 416 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 417 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 418 419 if ((val & VIDEO_DIP_ENABLE) == 0) 420 return 0; 421 422 return val & (VIDEO_DIP_ENABLE_AVI | 423 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 424 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 425 } 426 427 static void vlv_write_infoframe(struct intel_encoder *encoder, 428 const struct intel_crtc_state *crtc_state, 429 unsigned int type, 430 const void *frame, ssize_t len) 431 { 432 struct intel_display *display = to_intel_display(encoder); 433 const u32 *data = frame; 434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 435 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 436 u32 val = intel_de_read(display, reg); 437 int i; 438 439 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 440 "Writing DIP with CTL reg disabled\n"); 441 442 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 443 val |= g4x_infoframe_index(type); 444 445 val &= ~g4x_infoframe_enable(type); 446 447 intel_de_write(display, reg, val); 448 449 for (i = 0; i < len; i += 4) { 450 intel_de_write(display, 451 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 452 data++; 453 } 454 /* Write every possible data byte to force correct ECC calculation. */ 455 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 456 intel_de_write(display, 457 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 458 459 val |= g4x_infoframe_enable(type); 460 val &= ~VIDEO_DIP_FREQ_MASK; 461 val |= VIDEO_DIP_FREQ_VSYNC; 462 463 intel_de_write(display, reg, val); 464 intel_de_posting_read(display, reg); 465 } 466 467 static void vlv_read_infoframe(struct intel_encoder *encoder, 468 const struct intel_crtc_state *crtc_state, 469 unsigned int type, 470 void *frame, ssize_t len) 471 { 472 struct intel_display *display = to_intel_display(encoder); 473 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 474 u32 *data = frame; 475 int i; 476 477 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 478 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 479 480 for (i = 0; i < len; i += 4) 481 *data++ = intel_de_read(display, 482 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 483 } 484 485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 486 const struct intel_crtc_state *pipe_config) 487 { 488 struct intel_display *display = to_intel_display(encoder); 489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 490 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 491 492 if ((val & VIDEO_DIP_ENABLE) == 0) 493 return 0; 494 495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 496 return 0; 497 498 return val & (VIDEO_DIP_ENABLE_AVI | 499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 501 } 502 503 void hsw_write_infoframe(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 unsigned int type, 506 const void *frame, ssize_t len) 507 { 508 struct intel_display *display = to_intel_display(encoder); 509 const u32 *data = frame; 510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 512 int data_size; 513 int i; 514 u32 val = intel_de_read(display, ctl_reg); 515 516 data_size = hsw_dip_data_size(display, type); 517 518 drm_WARN_ON(display->drm, len > data_size); 519 520 val &= ~hsw_infoframe_enable(type); 521 intel_de_write(display, ctl_reg, val); 522 523 for (i = 0; i < len; i += 4) { 524 intel_de_write(display, 525 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 526 *data); 527 data++; 528 } 529 /* Write every possible data byte to force correct ECC calculation. */ 530 for (; i < data_size; i += 4) 531 intel_de_write(display, 532 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 533 0); 534 535 /* Wa_14013475917 */ 536 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 537 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 538 val |= hsw_infoframe_enable(type); 539 540 if (type == DP_SDP_VSC) 541 val |= VSC_DIP_HW_DATA_SW_HEA; 542 543 intel_de_write(display, ctl_reg, val); 544 intel_de_posting_read(display, ctl_reg); 545 } 546 547 void hsw_read_infoframe(struct intel_encoder *encoder, 548 const struct intel_crtc_state *crtc_state, 549 unsigned int type, void *frame, ssize_t len) 550 { 551 struct intel_display *display = to_intel_display(encoder); 552 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 553 u32 *data = frame; 554 int i; 555 556 for (i = 0; i < len; i += 4) 557 *data++ = intel_de_read(display, 558 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 559 } 560 561 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 562 const struct intel_crtc_state *pipe_config) 563 { 564 struct intel_display *display = to_intel_display(encoder); 565 u32 val = intel_de_read(display, 566 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 567 u32 mask; 568 569 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 570 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 571 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 572 573 if (DISPLAY_VER(display) >= 10) 574 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 575 576 if (HAS_AS_SDP(display)) 577 mask |= VIDEO_DIP_ENABLE_AS_ADL; 578 579 return val & mask; 580 } 581 582 static const u8 infoframe_type_to_idx[] = { 583 HDMI_PACKET_TYPE_GENERAL_CONTROL, 584 HDMI_PACKET_TYPE_GAMUT_METADATA, 585 DP_SDP_VSC, 586 DP_SDP_ADAPTIVE_SYNC, 587 HDMI_INFOFRAME_TYPE_AVI, 588 HDMI_INFOFRAME_TYPE_SPD, 589 HDMI_INFOFRAME_TYPE_VENDOR, 590 HDMI_INFOFRAME_TYPE_DRM, 591 }; 592 593 u32 intel_hdmi_infoframe_enable(unsigned int type) 594 { 595 int i; 596 597 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 598 if (infoframe_type_to_idx[i] == type) 599 return BIT(i); 600 } 601 602 return 0; 603 } 604 605 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 606 const struct intel_crtc_state *crtc_state) 607 { 608 struct intel_display *display = to_intel_display(encoder); 609 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 610 u32 val, ret = 0; 611 int i; 612 613 val = dig_port->infoframes_enabled(encoder, crtc_state); 614 615 /* map from hardware bits to dip idx */ 616 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 617 unsigned int type = infoframe_type_to_idx[i]; 618 619 if (HAS_DDI(display)) { 620 if (val & hsw_infoframe_enable(type)) 621 ret |= BIT(i); 622 } else { 623 if (val & g4x_infoframe_enable(type)) 624 ret |= BIT(i); 625 } 626 } 627 628 return ret; 629 } 630 631 /* 632 * The data we write to the DIP data buffer registers is 1 byte bigger than the 633 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 634 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 635 * used for both technologies. 636 * 637 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 638 * DW1: DB3 | DB2 | DB1 | DB0 639 * DW2: DB7 | DB6 | DB5 | DB4 640 * DW3: ... 641 * 642 * (HB is Header Byte, DB is Data Byte) 643 * 644 * The hdmi pack() functions don't know about that hardware specific hole so we 645 * trick them by giving an offset into the buffer and moving back the header 646 * bytes by one. 647 */ 648 static void intel_write_infoframe(struct intel_encoder *encoder, 649 const struct intel_crtc_state *crtc_state, 650 enum hdmi_infoframe_type type, 651 const union hdmi_infoframe *frame) 652 { 653 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 654 u8 buffer[VIDEO_DIP_DATA_SIZE]; 655 ssize_t len; 656 657 if ((crtc_state->infoframes.enable & 658 intel_hdmi_infoframe_enable(type)) == 0) 659 return; 660 661 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 662 return; 663 664 /* see comment above for the reason for this offset */ 665 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 666 if (drm_WARN_ON(encoder->base.dev, len < 0)) 667 return; 668 669 /* Insert the 'hole' (see big comment above) at position 3 */ 670 memmove(&buffer[0], &buffer[1], 3); 671 buffer[3] = 0; 672 len++; 673 674 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 675 } 676 677 void intel_read_infoframe(struct intel_encoder *encoder, 678 const struct intel_crtc_state *crtc_state, 679 enum hdmi_infoframe_type type, 680 union hdmi_infoframe *frame) 681 { 682 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 683 u8 buffer[VIDEO_DIP_DATA_SIZE]; 684 int ret; 685 686 if ((crtc_state->infoframes.enable & 687 intel_hdmi_infoframe_enable(type)) == 0) 688 return; 689 690 dig_port->read_infoframe(encoder, crtc_state, 691 type, buffer, sizeof(buffer)); 692 693 /* Fill the 'hole' (see big comment above) at position 3 */ 694 memmove(&buffer[1], &buffer[0], 3); 695 696 /* see comment above for the reason for this offset */ 697 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 698 if (ret) { 699 drm_dbg_kms(encoder->base.dev, 700 "Failed to unpack infoframe type 0x%02x\n", type); 701 return; 702 } 703 704 if (frame->any.type != type) 705 drm_dbg_kms(encoder->base.dev, 706 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 707 frame->any.type, type); 708 } 709 710 static bool 711 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 712 struct intel_crtc_state *crtc_state, 713 struct drm_connector_state *conn_state) 714 { 715 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 716 const struct drm_display_mode *adjusted_mode = 717 &crtc_state->hw.adjusted_mode; 718 struct intel_connector *connector = to_intel_connector(conn_state->connector); 719 int ret; 720 721 if (!crtc_state->has_infoframe) 722 return true; 723 724 crtc_state->infoframes.enable |= 725 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 726 727 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base, 728 adjusted_mode); 729 if (ret) 730 return false; 731 732 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 733 frame->colorspace = HDMI_COLORSPACE_YUV420; 734 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 735 frame->colorspace = HDMI_COLORSPACE_YUV444; 736 else 737 frame->colorspace = HDMI_COLORSPACE_RGB; 738 739 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 740 741 /* nonsense combination */ 742 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 743 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 744 745 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 746 drm_hdmi_avi_infoframe_quant_range(frame, &connector->base, 747 adjusted_mode, 748 crtc_state->limited_color_range ? 749 HDMI_QUANTIZATION_RANGE_LIMITED : 750 HDMI_QUANTIZATION_RANGE_FULL); 751 } else { 752 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 753 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 754 } 755 756 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 757 758 /* TODO: handle pixel repetition for YCBCR420 outputs */ 759 760 ret = hdmi_avi_infoframe_check(frame); 761 if (drm_WARN_ON(encoder->base.dev, ret)) 762 return false; 763 764 return true; 765 } 766 767 static bool 768 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 769 struct intel_crtc_state *crtc_state, 770 struct drm_connector_state *conn_state) 771 { 772 struct intel_display *display = to_intel_display(crtc_state); 773 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 774 int ret; 775 776 if (!crtc_state->has_infoframe) 777 return true; 778 779 crtc_state->infoframes.enable |= 780 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 781 782 if (display->platform.dgfx) 783 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 784 else 785 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 786 787 if (drm_WARN_ON(encoder->base.dev, ret)) 788 return false; 789 790 frame->sdi = HDMI_SPD_SDI_PC; 791 792 ret = hdmi_spd_infoframe_check(frame); 793 if (drm_WARN_ON(encoder->base.dev, ret)) 794 return false; 795 796 return true; 797 } 798 799 static bool 800 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 801 struct intel_crtc_state *crtc_state, 802 struct drm_connector_state *conn_state) 803 { 804 struct hdmi_vendor_infoframe *frame = 805 &crtc_state->infoframes.hdmi.vendor.hdmi; 806 const struct drm_display_info *info = 807 &conn_state->connector->display_info; 808 int ret; 809 810 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 811 return true; 812 813 crtc_state->infoframes.enable |= 814 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 815 816 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 817 conn_state->connector, 818 &crtc_state->hw.adjusted_mode); 819 if (drm_WARN_ON(encoder->base.dev, ret)) 820 return false; 821 822 ret = hdmi_vendor_infoframe_check(frame); 823 if (drm_WARN_ON(encoder->base.dev, ret)) 824 return false; 825 826 return true; 827 } 828 829 static bool 830 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 831 struct intel_crtc_state *crtc_state, 832 struct drm_connector_state *conn_state) 833 { 834 struct intel_display *display = to_intel_display(encoder); 835 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 836 int ret; 837 838 if (DISPLAY_VER(display) < 10) 839 return true; 840 841 if (!crtc_state->has_infoframe) 842 return true; 843 844 if (!conn_state->hdr_output_metadata) 845 return true; 846 847 crtc_state->infoframes.enable |= 848 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 849 850 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 851 if (ret < 0) { 852 drm_dbg_kms(display->drm, 853 "couldn't set HDR metadata in infoframe\n"); 854 return false; 855 } 856 857 ret = hdmi_drm_infoframe_check(frame); 858 if (drm_WARN_ON(display->drm, ret)) 859 return false; 860 861 return true; 862 } 863 864 static void g4x_set_infoframes(struct intel_encoder *encoder, 865 bool enable, 866 const struct intel_crtc_state *crtc_state, 867 const struct drm_connector_state *conn_state) 868 { 869 struct intel_display *display = to_intel_display(encoder); 870 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 871 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 872 i915_reg_t reg = VIDEO_DIP_CTL; 873 u32 val = intel_de_read(display, reg); 874 u32 port = VIDEO_DIP_PORT(encoder->port); 875 876 assert_hdmi_port_disabled(intel_hdmi); 877 878 /* If the registers were not initialized yet, they might be zeroes, 879 * which means we're selecting the AVI DIP and we're setting its 880 * frequency to once. This seems to really confuse the HW and make 881 * things stop working (the register spec says the AVI always needs to 882 * be sent every VSync). So here we avoid writing to the register more 883 * than we need and also explicitly select the AVI DIP and explicitly 884 * set its frequency to every VSync. Avoiding to write it twice seems to 885 * be enough to solve the problem, but being defensive shouldn't hurt us 886 * either. */ 887 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 888 889 if (!enable) { 890 if (!(val & VIDEO_DIP_ENABLE)) 891 return; 892 if (port != (val & VIDEO_DIP_PORT_MASK)) { 893 drm_dbg_kms(display->drm, 894 "video DIP still enabled on port %c\n", 895 (val & VIDEO_DIP_PORT_MASK) >> 29); 896 return; 897 } 898 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 899 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 900 intel_de_write(display, reg, val); 901 intel_de_posting_read(display, reg); 902 return; 903 } 904 905 if (port != (val & VIDEO_DIP_PORT_MASK)) { 906 if (val & VIDEO_DIP_ENABLE) { 907 drm_dbg_kms(display->drm, 908 "video DIP already enabled on port %c\n", 909 (val & VIDEO_DIP_PORT_MASK) >> 29); 910 return; 911 } 912 val &= ~VIDEO_DIP_PORT_MASK; 913 val |= port; 914 } 915 916 val |= VIDEO_DIP_ENABLE; 917 val &= ~(VIDEO_DIP_ENABLE_AVI | 918 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 919 920 intel_de_write(display, reg, val); 921 intel_de_posting_read(display, reg); 922 923 intel_write_infoframe(encoder, crtc_state, 924 HDMI_INFOFRAME_TYPE_AVI, 925 &crtc_state->infoframes.avi); 926 intel_write_infoframe(encoder, crtc_state, 927 HDMI_INFOFRAME_TYPE_SPD, 928 &crtc_state->infoframes.spd); 929 intel_write_infoframe(encoder, crtc_state, 930 HDMI_INFOFRAME_TYPE_VENDOR, 931 &crtc_state->infoframes.hdmi); 932 } 933 934 /* 935 * Determine if default_phase=1 can be indicated in the GCP infoframe. 936 * 937 * From HDMI specification 1.4a: 938 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 939 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 940 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 941 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 942 * phase of 0 943 */ 944 static bool gcp_default_phase_possible(int pipe_bpp, 945 const struct drm_display_mode *mode) 946 { 947 unsigned int pixels_per_group; 948 949 switch (pipe_bpp) { 950 case 30: 951 /* 4 pixels in 5 clocks */ 952 pixels_per_group = 4; 953 break; 954 case 36: 955 /* 2 pixels in 3 clocks */ 956 pixels_per_group = 2; 957 break; 958 case 48: 959 /* 1 pixel in 2 clocks */ 960 pixels_per_group = 1; 961 break; 962 default: 963 /* phase information not relevant for 8bpc */ 964 return false; 965 } 966 967 return mode->crtc_hdisplay % pixels_per_group == 0 && 968 mode->crtc_htotal % pixels_per_group == 0 && 969 mode->crtc_hblank_start % pixels_per_group == 0 && 970 mode->crtc_hblank_end % pixels_per_group == 0 && 971 mode->crtc_hsync_start % pixels_per_group == 0 && 972 mode->crtc_hsync_end % pixels_per_group == 0 && 973 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 974 mode->crtc_htotal/2 % pixels_per_group == 0); 975 } 976 977 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 978 const struct intel_crtc_state *crtc_state, 979 const struct drm_connector_state *conn_state) 980 { 981 struct intel_display *display = to_intel_display(encoder); 982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 983 i915_reg_t reg; 984 985 if ((crtc_state->infoframes.enable & 986 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 987 return false; 988 989 if (HAS_DDI(display)) 990 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 991 else if (display->platform.valleyview || display->platform.cherryview) 992 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 993 else if (HAS_PCH_SPLIT(display)) 994 reg = TVIDEO_DIP_GCP(crtc->pipe); 995 else 996 return false; 997 998 intel_de_write(display, reg, crtc_state->infoframes.gcp); 999 1000 return true; 1001 } 1002 1003 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1004 struct intel_crtc_state *crtc_state) 1005 { 1006 struct intel_display *display = to_intel_display(encoder); 1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1008 i915_reg_t reg; 1009 1010 if ((crtc_state->infoframes.enable & 1011 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1012 return; 1013 1014 if (HAS_DDI(display)) 1015 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1016 else if (display->platform.valleyview || display->platform.cherryview) 1017 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1018 else if (HAS_PCH_SPLIT(display)) 1019 reg = TVIDEO_DIP_GCP(crtc->pipe); 1020 else 1021 return; 1022 1023 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1024 } 1025 1026 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1027 struct intel_crtc_state *crtc_state, 1028 struct drm_connector_state *conn_state) 1029 { 1030 struct intel_display *display = to_intel_display(encoder); 1031 1032 if (display->platform.g4x || !crtc_state->has_infoframe) 1033 return; 1034 1035 crtc_state->infoframes.enable |= 1036 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1037 1038 /* Indicate color indication for deep color mode */ 1039 if (crtc_state->pipe_bpp > 24) 1040 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1041 1042 /* Enable default_phase whenever the display mode is suitably aligned */ 1043 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1044 &crtc_state->hw.adjusted_mode)) 1045 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1046 } 1047 1048 static void ibx_set_infoframes(struct intel_encoder *encoder, 1049 bool enable, 1050 const struct intel_crtc_state *crtc_state, 1051 const struct drm_connector_state *conn_state) 1052 { 1053 struct intel_display *display = to_intel_display(encoder); 1054 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1055 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1056 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1057 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1058 u32 val = intel_de_read(display, reg); 1059 u32 port = VIDEO_DIP_PORT(encoder->port); 1060 1061 assert_hdmi_port_disabled(intel_hdmi); 1062 1063 /* See the big comment in g4x_set_infoframes() */ 1064 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1065 1066 if (!enable) { 1067 if (!(val & VIDEO_DIP_ENABLE)) 1068 return; 1069 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1070 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1071 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1072 intel_de_write(display, reg, val); 1073 intel_de_posting_read(display, reg); 1074 return; 1075 } 1076 1077 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1078 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1079 "DIP already enabled on port %c\n", 1080 (val & VIDEO_DIP_PORT_MASK) >> 29); 1081 val &= ~VIDEO_DIP_PORT_MASK; 1082 val |= port; 1083 } 1084 1085 val |= VIDEO_DIP_ENABLE; 1086 val &= ~(VIDEO_DIP_ENABLE_AVI | 1087 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1088 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1089 1090 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1091 val |= VIDEO_DIP_ENABLE_GCP; 1092 1093 intel_de_write(display, reg, val); 1094 intel_de_posting_read(display, reg); 1095 1096 intel_write_infoframe(encoder, crtc_state, 1097 HDMI_INFOFRAME_TYPE_AVI, 1098 &crtc_state->infoframes.avi); 1099 intel_write_infoframe(encoder, crtc_state, 1100 HDMI_INFOFRAME_TYPE_SPD, 1101 &crtc_state->infoframes.spd); 1102 intel_write_infoframe(encoder, crtc_state, 1103 HDMI_INFOFRAME_TYPE_VENDOR, 1104 &crtc_state->infoframes.hdmi); 1105 } 1106 1107 static void cpt_set_infoframes(struct intel_encoder *encoder, 1108 bool enable, 1109 const struct intel_crtc_state *crtc_state, 1110 const struct drm_connector_state *conn_state) 1111 { 1112 struct intel_display *display = to_intel_display(encoder); 1113 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1114 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1115 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1116 u32 val = intel_de_read(display, reg); 1117 1118 assert_hdmi_port_disabled(intel_hdmi); 1119 1120 /* See the big comment in g4x_set_infoframes() */ 1121 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1122 1123 if (!enable) { 1124 if (!(val & VIDEO_DIP_ENABLE)) 1125 return; 1126 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1127 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1128 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1129 intel_de_write(display, reg, val); 1130 intel_de_posting_read(display, reg); 1131 return; 1132 } 1133 1134 /* Set both together, unset both together: see the spec. */ 1135 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1136 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1137 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1138 1139 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1140 val |= VIDEO_DIP_ENABLE_GCP; 1141 1142 intel_de_write(display, reg, val); 1143 intel_de_posting_read(display, reg); 1144 1145 intel_write_infoframe(encoder, crtc_state, 1146 HDMI_INFOFRAME_TYPE_AVI, 1147 &crtc_state->infoframes.avi); 1148 intel_write_infoframe(encoder, crtc_state, 1149 HDMI_INFOFRAME_TYPE_SPD, 1150 &crtc_state->infoframes.spd); 1151 intel_write_infoframe(encoder, crtc_state, 1152 HDMI_INFOFRAME_TYPE_VENDOR, 1153 &crtc_state->infoframes.hdmi); 1154 } 1155 1156 static void vlv_set_infoframes(struct intel_encoder *encoder, 1157 bool enable, 1158 const struct intel_crtc_state *crtc_state, 1159 const struct drm_connector_state *conn_state) 1160 { 1161 struct intel_display *display = to_intel_display(encoder); 1162 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1163 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1164 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1165 u32 val = intel_de_read(display, reg); 1166 u32 port = VIDEO_DIP_PORT(encoder->port); 1167 1168 assert_hdmi_port_disabled(intel_hdmi); 1169 1170 /* See the big comment in g4x_set_infoframes() */ 1171 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1172 1173 if (!enable) { 1174 if (!(val & VIDEO_DIP_ENABLE)) 1175 return; 1176 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1177 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1178 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1179 intel_de_write(display, reg, val); 1180 intel_de_posting_read(display, reg); 1181 return; 1182 } 1183 1184 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1185 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1186 "DIP already enabled on port %c\n", 1187 (val & VIDEO_DIP_PORT_MASK) >> 29); 1188 val &= ~VIDEO_DIP_PORT_MASK; 1189 val |= port; 1190 } 1191 1192 val |= VIDEO_DIP_ENABLE; 1193 val &= ~(VIDEO_DIP_ENABLE_AVI | 1194 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1195 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1196 1197 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1198 val |= VIDEO_DIP_ENABLE_GCP; 1199 1200 intel_de_write(display, reg, val); 1201 intel_de_posting_read(display, reg); 1202 1203 intel_write_infoframe(encoder, crtc_state, 1204 HDMI_INFOFRAME_TYPE_AVI, 1205 &crtc_state->infoframes.avi); 1206 intel_write_infoframe(encoder, crtc_state, 1207 HDMI_INFOFRAME_TYPE_SPD, 1208 &crtc_state->infoframes.spd); 1209 intel_write_infoframe(encoder, crtc_state, 1210 HDMI_INFOFRAME_TYPE_VENDOR, 1211 &crtc_state->infoframes.hdmi); 1212 } 1213 1214 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, 1215 const struct intel_crtc_state *crtc_state, 1216 const struct drm_connector_state *conn_state) 1217 { 1218 struct intel_display *display = to_intel_display(encoder); 1219 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1220 crtc_state->cpu_transcoder); 1221 u32 val = intel_de_read(display, reg); 1222 1223 if ((crtc_state->infoframes.enable & 1224 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 && 1225 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0) 1226 return; 1227 1228 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK); 1229 1230 intel_de_write(display, reg, val); 1231 intel_de_posting_read(display, reg); 1232 1233 intel_write_infoframe(encoder, crtc_state, 1234 HDMI_INFOFRAME_TYPE_DRM, 1235 &crtc_state->infoframes.drm); 1236 } 1237 1238 static void hsw_set_infoframes(struct intel_encoder *encoder, 1239 bool enable, 1240 const struct intel_crtc_state *crtc_state, 1241 const struct drm_connector_state *conn_state) 1242 { 1243 struct intel_display *display = to_intel_display(encoder); 1244 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1245 crtc_state->cpu_transcoder); 1246 u32 val = intel_de_read(display, reg); 1247 1248 assert_hdmi_transcoder_func_disabled(display, 1249 crtc_state->cpu_transcoder); 1250 1251 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1252 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1253 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1254 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1255 1256 if (!enable) { 1257 intel_de_write(display, reg, val); 1258 intel_de_posting_read(display, reg); 1259 return; 1260 } 1261 1262 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1263 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1264 1265 intel_de_write(display, reg, val); 1266 intel_de_posting_read(display, reg); 1267 1268 intel_write_infoframe(encoder, crtc_state, 1269 HDMI_INFOFRAME_TYPE_AVI, 1270 &crtc_state->infoframes.avi); 1271 intel_write_infoframe(encoder, crtc_state, 1272 HDMI_INFOFRAME_TYPE_SPD, 1273 &crtc_state->infoframes.spd); 1274 intel_write_infoframe(encoder, crtc_state, 1275 HDMI_INFOFRAME_TYPE_VENDOR, 1276 &crtc_state->infoframes.hdmi); 1277 intel_write_infoframe(encoder, crtc_state, 1278 HDMI_INFOFRAME_TYPE_DRM, 1279 &crtc_state->infoframes.drm); 1280 } 1281 1282 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1283 { 1284 struct intel_display *display = to_intel_display(hdmi); 1285 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1286 1287 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1288 return; 1289 1290 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1291 enable ? "Enabling" : "Disabling"); 1292 1293 drm_dp_dual_mode_set_tmds_output(display->drm, 1294 hdmi->dp_dual_mode.type, ddc, enable); 1295 } 1296 1297 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1298 unsigned int offset, void *buffer, size_t size) 1299 { 1300 struct intel_hdmi *hdmi = &dig_port->hdmi; 1301 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1302 int ret; 1303 u8 start = offset & 0xff; 1304 struct i2c_msg msgs[] = { 1305 { 1306 .addr = DRM_HDCP_DDC_ADDR, 1307 .flags = 0, 1308 .len = 1, 1309 .buf = &start, 1310 }, 1311 { 1312 .addr = DRM_HDCP_DDC_ADDR, 1313 .flags = I2C_M_RD, 1314 .len = size, 1315 .buf = buffer 1316 } 1317 }; 1318 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1319 if (ret == ARRAY_SIZE(msgs)) 1320 return 0; 1321 return ret >= 0 ? -EIO : ret; 1322 } 1323 1324 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1325 unsigned int offset, void *buffer, size_t size) 1326 { 1327 struct intel_hdmi *hdmi = &dig_port->hdmi; 1328 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1329 int ret; 1330 u8 *write_buf; 1331 struct i2c_msg msg; 1332 1333 write_buf = kzalloc(size + 1, GFP_KERNEL); 1334 if (!write_buf) 1335 return -ENOMEM; 1336 1337 write_buf[0] = offset & 0xff; 1338 memcpy(&write_buf[1], buffer, size); 1339 1340 msg.addr = DRM_HDCP_DDC_ADDR; 1341 msg.flags = 0; 1342 msg.len = size + 1; 1343 msg.buf = write_buf; 1344 1345 ret = i2c_transfer(ddc, &msg, 1); 1346 if (ret == 1) 1347 ret = 0; 1348 else if (ret >= 0) 1349 ret = -EIO; 1350 1351 kfree(write_buf); 1352 return ret; 1353 } 1354 1355 static 1356 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1357 u8 *an) 1358 { 1359 struct intel_display *display = to_intel_display(dig_port); 1360 struct intel_hdmi *hdmi = &dig_port->hdmi; 1361 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1362 int ret; 1363 1364 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1365 DRM_HDCP_AN_LEN); 1366 if (ret) { 1367 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1368 ret); 1369 return ret; 1370 } 1371 1372 ret = intel_gmbus_output_aksv(ddc); 1373 if (ret < 0) { 1374 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1375 return ret; 1376 } 1377 return 0; 1378 } 1379 1380 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1381 u8 *bksv) 1382 { 1383 struct intel_display *display = to_intel_display(dig_port); 1384 1385 int ret; 1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1387 DRM_HDCP_KSV_LEN); 1388 if (ret) 1389 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1390 ret); 1391 return ret; 1392 } 1393 1394 static 1395 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1396 u8 *bstatus) 1397 { 1398 struct intel_display *display = to_intel_display(dig_port); 1399 1400 int ret; 1401 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1402 bstatus, DRM_HDCP_BSTATUS_LEN); 1403 if (ret) 1404 drm_dbg_kms(display->drm, 1405 "Read bstatus over DDC failed (%d)\n", 1406 ret); 1407 return ret; 1408 } 1409 1410 static 1411 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1412 bool *repeater_present) 1413 { 1414 struct intel_display *display = to_intel_display(dig_port); 1415 int ret; 1416 u8 val; 1417 1418 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1419 if (ret) { 1420 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1421 ret); 1422 return ret; 1423 } 1424 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1425 return 0; 1426 } 1427 1428 static 1429 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1430 u8 *ri_prime) 1431 { 1432 struct intel_display *display = to_intel_display(dig_port); 1433 1434 int ret; 1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1436 ri_prime, DRM_HDCP_RI_LEN); 1437 if (ret) 1438 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1439 ret); 1440 return ret; 1441 } 1442 1443 static 1444 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1445 bool *ksv_ready) 1446 { 1447 struct intel_display *display = to_intel_display(dig_port); 1448 int ret; 1449 u8 val; 1450 1451 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1452 if (ret) { 1453 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1454 ret); 1455 return ret; 1456 } 1457 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1458 return 0; 1459 } 1460 1461 static 1462 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1463 int num_downstream, u8 *ksv_fifo) 1464 { 1465 struct intel_display *display = to_intel_display(dig_port); 1466 int ret; 1467 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1468 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1469 if (ret) { 1470 drm_dbg_kms(display->drm, 1471 "Read ksv fifo over DDC failed (%d)\n", ret); 1472 return ret; 1473 } 1474 return 0; 1475 } 1476 1477 static 1478 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1479 int i, u32 *part) 1480 { 1481 struct intel_display *display = to_intel_display(dig_port); 1482 int ret; 1483 1484 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1485 return -EINVAL; 1486 1487 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1488 part, DRM_HDCP_V_PRIME_PART_LEN); 1489 if (ret) 1490 drm_dbg_kms(display->drm, 1491 "Read V'[%d] over DDC failed (%d)\n", 1492 i, ret); 1493 return ret; 1494 } 1495 1496 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1497 enum transcoder cpu_transcoder) 1498 { 1499 struct intel_display *display = to_intel_display(connector); 1500 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1501 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1502 u32 scanline; 1503 int ret; 1504 1505 for (;;) { 1506 scanline = intel_de_read(display, 1507 PIPEDSL(display, crtc->pipe)); 1508 if (scanline > 100 && scanline < 200) 1509 break; 1510 usleep_range(25, 50); 1511 } 1512 1513 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1514 false, TRANS_DDI_HDCP_SIGNALLING); 1515 if (ret) { 1516 drm_err(display->drm, 1517 "Disable HDCP signalling failed (%d)\n", ret); 1518 return ret; 1519 } 1520 1521 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1522 true, TRANS_DDI_HDCP_SIGNALLING); 1523 if (ret) { 1524 drm_err(display->drm, 1525 "Enable HDCP signalling failed (%d)\n", ret); 1526 return ret; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static 1533 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1534 enum transcoder cpu_transcoder, 1535 bool enable) 1536 { 1537 struct intel_display *display = to_intel_display(dig_port); 1538 struct intel_hdmi *hdmi = &dig_port->hdmi; 1539 struct intel_connector *connector = hdmi->attached_connector; 1540 int ret; 1541 1542 if (!enable) 1543 usleep_range(6, 60); /* Bspec says >= 6us */ 1544 1545 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1546 cpu_transcoder, enable, 1547 TRANS_DDI_HDCP_SIGNALLING); 1548 if (ret) { 1549 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1550 enable ? "Enable" : "Disable", ret); 1551 return ret; 1552 } 1553 1554 /* 1555 * WA: To fix incorrect positioning of the window of 1556 * opportunity and enc_en signalling in KABYLAKE. 1557 */ 1558 if (display->platform.kabylake && enable) 1559 return kbl_repositioning_enc_en_signal(connector, 1560 cpu_transcoder); 1561 1562 return 0; 1563 } 1564 1565 static 1566 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1567 struct intel_connector *connector) 1568 { 1569 struct intel_display *display = to_intel_display(dig_port); 1570 enum port port = dig_port->base.port; 1571 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1572 int ret; 1573 union { 1574 u32 reg; 1575 u8 shim[DRM_HDCP_RI_LEN]; 1576 } ri; 1577 1578 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1579 if (ret) 1580 return false; 1581 1582 intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg); 1583 1584 /* Wait for Ri prime match */ 1585 if (wait_for((intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 1586 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1587 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1588 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1589 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, 1590 port))); 1591 return false; 1592 } 1593 return true; 1594 } 1595 1596 static 1597 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1598 struct intel_connector *connector) 1599 { 1600 int retry; 1601 1602 for (retry = 0; retry < 3; retry++) 1603 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1604 return true; 1605 1606 return false; 1607 } 1608 1609 struct hdcp2_hdmi_msg_timeout { 1610 u8 msg_id; 1611 u16 timeout; 1612 }; 1613 1614 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1615 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1616 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1617 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1618 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1619 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1620 }; 1621 1622 static 1623 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1624 u8 *rx_status) 1625 { 1626 return intel_hdmi_hdcp_read(dig_port, 1627 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1628 rx_status, 1629 HDCP_2_2_HDMI_RXSTATUS_LEN); 1630 } 1631 1632 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1633 { 1634 int i; 1635 1636 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1637 if (is_paired) 1638 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1639 else 1640 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1641 } 1642 1643 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1644 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1645 return hdcp2_msg_timeout[i].timeout; 1646 } 1647 1648 return -EINVAL; 1649 } 1650 1651 static int 1652 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1653 u8 msg_id, bool *msg_ready, 1654 ssize_t *msg_sz) 1655 { 1656 struct intel_display *display = to_intel_display(dig_port); 1657 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1658 int ret; 1659 1660 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1661 if (ret < 0) { 1662 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1663 ret); 1664 return ret; 1665 } 1666 1667 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1668 rx_status[0]); 1669 1670 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1671 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1672 *msg_sz); 1673 else 1674 *msg_ready = *msg_sz; 1675 1676 return 0; 1677 } 1678 1679 static ssize_t 1680 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1681 u8 msg_id, bool paired) 1682 { 1683 struct intel_display *display = to_intel_display(dig_port); 1684 bool msg_ready = false; 1685 int timeout, ret; 1686 ssize_t msg_sz = 0; 1687 1688 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1689 if (timeout < 0) 1690 return timeout; 1691 1692 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1693 msg_id, &msg_ready, 1694 &msg_sz), 1695 !ret && msg_ready && msg_sz, timeout * 1000, 1696 1000, 5 * 1000); 1697 if (ret) 1698 drm_dbg_kms(display->drm, 1699 "msg_id: %d, ret: %d, timeout: %d\n", 1700 msg_id, ret, timeout); 1701 1702 return ret ? ret : msg_sz; 1703 } 1704 1705 static 1706 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1707 void *buf, size_t size) 1708 { 1709 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1710 unsigned int offset; 1711 1712 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1713 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1714 } 1715 1716 static 1717 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1718 u8 msg_id, void *buf, size_t size) 1719 { 1720 struct intel_display *display = to_intel_display(connector); 1721 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1722 struct intel_hdmi *hdmi = &dig_port->hdmi; 1723 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1724 unsigned int offset; 1725 ssize_t ret; 1726 1727 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1728 hdcp->is_paired); 1729 if (ret < 0) 1730 return ret; 1731 1732 /* 1733 * Available msg size should be equal to or lesser than the 1734 * available buffer. 1735 */ 1736 if (ret > size) { 1737 drm_dbg_kms(display->drm, 1738 "msg_sz(%zd) is more than exp size(%zu)\n", 1739 ret, size); 1740 return -EINVAL; 1741 } 1742 1743 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1744 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1745 if (ret) 1746 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1747 msg_id, ret); 1748 1749 return ret; 1750 } 1751 1752 static 1753 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1754 struct intel_connector *connector) 1755 { 1756 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1757 int ret; 1758 1759 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1760 if (ret) 1761 return ret; 1762 1763 /* 1764 * Re-auth request and Link Integrity Failures are represented by 1765 * same bit. i.e reauth_req. 1766 */ 1767 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1768 ret = HDCP_REAUTH_REQUEST; 1769 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1770 ret = HDCP_TOPOLOGY_CHANGE; 1771 1772 return ret; 1773 } 1774 1775 static 1776 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1777 bool *capable) 1778 { 1779 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1780 u8 hdcp2_version; 1781 int ret; 1782 1783 *capable = false; 1784 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1785 &hdcp2_version, sizeof(hdcp2_version)); 1786 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1787 *capable = true; 1788 1789 return ret; 1790 } 1791 1792 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1793 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1794 .read_bksv = intel_hdmi_hdcp_read_bksv, 1795 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1796 .repeater_present = intel_hdmi_hdcp_repeater_present, 1797 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1798 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1799 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1800 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1801 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1802 .check_link = intel_hdmi_hdcp_check_link, 1803 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1804 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1805 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1806 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1807 .protocol = HDCP_PROTOCOL_HDMI, 1808 }; 1809 1810 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1811 { 1812 struct intel_display *display = to_intel_display(encoder); 1813 int max_tmds_clock, vbt_max_tmds_clock; 1814 1815 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s) 1816 max_tmds_clock = 600000; 1817 else if (DISPLAY_VER(display) >= 10) 1818 max_tmds_clock = 594000; 1819 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) 1820 max_tmds_clock = 300000; 1821 else if (DISPLAY_VER(display) >= 5) 1822 max_tmds_clock = 225000; 1823 else 1824 max_tmds_clock = 165000; 1825 1826 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1827 if (vbt_max_tmds_clock) 1828 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1829 1830 return max_tmds_clock; 1831 } 1832 1833 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1834 const struct drm_connector_state *conn_state) 1835 { 1836 struct intel_connector *connector = hdmi->attached_connector; 1837 1838 return connector->base.display_info.is_hdmi && 1839 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1840 } 1841 1842 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1843 { 1844 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1845 } 1846 1847 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1848 bool respect_downstream_limits, 1849 bool has_hdmi_sink) 1850 { 1851 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1852 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1853 1854 if (respect_downstream_limits) { 1855 struct intel_connector *connector = hdmi->attached_connector; 1856 const struct drm_display_info *info = &connector->base.display_info; 1857 1858 if (hdmi->dp_dual_mode.max_tmds_clock) 1859 max_tmds_clock = min(max_tmds_clock, 1860 hdmi->dp_dual_mode.max_tmds_clock); 1861 1862 if (info->max_tmds_clock) 1863 max_tmds_clock = min(max_tmds_clock, 1864 info->max_tmds_clock); 1865 else if (!has_hdmi_sink) 1866 max_tmds_clock = min(max_tmds_clock, 165000); 1867 } 1868 1869 return max_tmds_clock; 1870 } 1871 1872 static enum drm_mode_status 1873 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1874 int clock, bool respect_downstream_limits, 1875 bool has_hdmi_sink) 1876 { 1877 struct intel_display *display = to_intel_display(hdmi); 1878 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1879 1880 if (clock < 25000) 1881 return MODE_CLOCK_LOW; 1882 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1883 has_hdmi_sink)) 1884 return MODE_CLOCK_HIGH; 1885 1886 /* GLK DPLL can't generate 446-480 MHz */ 1887 if (display->platform.geminilake && clock > 446666 && clock < 480000) 1888 return MODE_CLOCK_RANGE; 1889 1890 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1891 if ((display->platform.geminilake || display->platform.broxton) && 1892 clock > 223333 && clock < 240000) 1893 return MODE_CLOCK_RANGE; 1894 1895 /* CHV DPLL can't generate 216-240 MHz */ 1896 if (display->platform.cherryview && clock > 216000 && clock < 240000) 1897 return MODE_CLOCK_RANGE; 1898 1899 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1900 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1901 return MODE_CLOCK_RANGE; 1902 1903 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1904 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1905 return MODE_CLOCK_RANGE; 1906 1907 return MODE_OK; 1908 } 1909 1910 int intel_hdmi_tmds_clock(int clock, int bpc, 1911 enum intel_output_format sink_format) 1912 { 1913 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1914 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1915 clock /= 2; 1916 1917 /* 1918 * Need to adjust the port link by: 1919 * 1.5x for 12bpc 1920 * 1.25x for 10bpc 1921 */ 1922 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1923 } 1924 1925 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1926 { 1927 switch (bpc) { 1928 case 12: 1929 return !HAS_GMCH(display); 1930 case 10: 1931 return DISPLAY_VER(display) >= 11; 1932 case 8: 1933 return true; 1934 default: 1935 MISSING_CASE(bpc); 1936 return false; 1937 } 1938 } 1939 1940 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector, 1941 int bpc, bool has_hdmi_sink, 1942 enum intel_output_format sink_format) 1943 { 1944 struct intel_connector *connector = to_intel_connector(_connector); 1945 const struct drm_display_info *info = &connector->base.display_info; 1946 const struct drm_hdmi_info *hdmi = &info->hdmi; 1947 1948 switch (bpc) { 1949 case 12: 1950 if (!has_hdmi_sink) 1951 return false; 1952 1953 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1954 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1955 else 1956 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1957 case 10: 1958 if (!has_hdmi_sink) 1959 return false; 1960 1961 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1962 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1963 else 1964 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1965 case 8: 1966 return true; 1967 default: 1968 MISSING_CASE(bpc); 1969 return false; 1970 } 1971 } 1972 1973 static enum drm_mode_status 1974 intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, 1975 bool has_hdmi_sink, 1976 enum intel_output_format sink_format) 1977 { 1978 struct intel_connector *connector = to_intel_connector(_connector); 1979 struct intel_display *display = to_intel_display(connector); 1980 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1981 enum drm_mode_status status = MODE_OK; 1982 int bpc; 1983 1984 /* 1985 * Try all color depths since valid port clock range 1986 * can have holes. Any mode that can be used with at 1987 * least one color depth is accepted. 1988 */ 1989 for (bpc = 12; bpc >= 8; bpc -= 2) { 1990 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1991 1992 if (!intel_hdmi_source_bpc_possible(display, bpc)) 1993 continue; 1994 1995 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 1996 sink_format)) 1997 continue; 1998 1999 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 2000 if (status == MODE_OK) 2001 return MODE_OK; 2002 } 2003 2004 /* can never happen */ 2005 drm_WARN_ON(display->drm, status == MODE_OK); 2006 2007 return status; 2008 } 2009 2010 static enum drm_mode_status 2011 intel_hdmi_mode_valid(struct drm_connector *_connector, 2012 const struct drm_display_mode *mode) 2013 { 2014 struct intel_connector *connector = to_intel_connector(_connector); 2015 struct intel_display *display = to_intel_display(connector); 2016 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2017 enum drm_mode_status status; 2018 int clock = mode->clock; 2019 int max_dotclk = display->cdclk.max_dotclk_freq; 2020 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); 2021 bool ycbcr_420_only; 2022 enum intel_output_format sink_format; 2023 2024 status = intel_cpu_transcoder_mode_valid(display, mode); 2025 if (status != MODE_OK) 2026 return status; 2027 2028 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2029 clock *= 2; 2030 2031 if (clock > max_dotclk) 2032 return MODE_CLOCK_HIGH; 2033 2034 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2035 if (!has_hdmi_sink) 2036 return MODE_CLOCK_LOW; 2037 clock *= 2; 2038 } 2039 2040 /* 2041 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2042 * enumerated only if FRL is supported. Current platforms do not support 2043 * FRL so prune the higher resolution modes that require doctclock more 2044 * than 600MHz. 2045 */ 2046 if (clock > 600000) 2047 return MODE_CLOCK_HIGH; 2048 2049 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); 2050 2051 if (ycbcr_420_only) 2052 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2053 else 2054 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2055 2056 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); 2057 if (status != MODE_OK) { 2058 if (ycbcr_420_only || 2059 !connector->base.ycbcr_420_allowed || 2060 !drm_mode_is_420_also(&connector->base.display_info, mode)) 2061 return status; 2062 2063 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2064 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, 2065 sink_format); 2066 if (status != MODE_OK) 2067 return status; 2068 } 2069 2070 return intel_mode_valid_max_plane_size(display, mode, 1); 2071 } 2072 2073 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2074 int bpc, bool has_hdmi_sink) 2075 { 2076 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 2077 struct intel_digital_connector_state *connector_state; 2078 struct intel_connector *connector; 2079 int i; 2080 2081 for_each_new_intel_connector_in_state(state, connector, connector_state, i) { 2082 if (connector_state->base.crtc != crtc_state->uapi.crtc) 2083 continue; 2084 2085 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2086 crtc_state->sink_format)) 2087 return false; 2088 } 2089 2090 return true; 2091 } 2092 2093 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2094 { 2095 struct intel_display *display = to_intel_display(crtc_state); 2096 const struct drm_display_mode *adjusted_mode = 2097 &crtc_state->hw.adjusted_mode; 2098 2099 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2100 return false; 2101 2102 /* Display Wa_1405510057:icl,ehl */ 2103 if (intel_hdmi_is_ycbcr420(crtc_state) && 2104 bpc == 10 && DISPLAY_VER(display) == 11 && 2105 (adjusted_mode->crtc_hblank_end - 2106 adjusted_mode->crtc_hblank_start) % 8 == 2) 2107 return false; 2108 2109 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2110 } 2111 2112 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2113 struct intel_crtc_state *crtc_state, 2114 int clock, bool respect_downstream_limits) 2115 { 2116 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2117 int bpc; 2118 2119 /* 2120 * pipe_bpp could already be below 8bpc due to FDI 2121 * bandwidth constraints. HDMI minimum is 8bpc however. 2122 */ 2123 bpc = max(crtc_state->pipe_bpp / 3, 8); 2124 2125 /* 2126 * We will never exceed downstream TMDS clock limits while 2127 * attempting deep color. If the user insists on forcing an 2128 * out of spec mode they will have to be satisfied with 8bpc. 2129 */ 2130 if (!respect_downstream_limits) 2131 bpc = 8; 2132 2133 for (; bpc >= 8; bpc -= 2) { 2134 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2135 crtc_state->sink_format); 2136 2137 if (hdmi_bpc_possible(crtc_state, bpc) && 2138 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2139 respect_downstream_limits, 2140 crtc_state->has_hdmi_sink) == MODE_OK) 2141 return bpc; 2142 } 2143 2144 return -EINVAL; 2145 } 2146 2147 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2148 struct intel_crtc_state *crtc_state, 2149 bool respect_downstream_limits) 2150 { 2151 struct intel_display *display = to_intel_display(encoder); 2152 const struct drm_display_mode *adjusted_mode = 2153 &crtc_state->hw.adjusted_mode; 2154 int bpc, clock = adjusted_mode->crtc_clock; 2155 2156 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2157 clock *= 2; 2158 2159 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2160 respect_downstream_limits); 2161 if (bpc < 0) 2162 return bpc; 2163 2164 crtc_state->port_clock = 2165 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2166 2167 /* 2168 * pipe_bpp could already be below 8bpc due to 2169 * FDI bandwidth constraints. We shouldn't bump it 2170 * back up to the HDMI minimum 8bpc in that case. 2171 */ 2172 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2173 2174 drm_dbg_kms(display->drm, 2175 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2176 bpc, crtc_state->pipe_bpp); 2177 2178 return 0; 2179 } 2180 2181 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2182 const struct drm_connector_state *conn_state) 2183 { 2184 const struct intel_digital_connector_state *intel_conn_state = 2185 to_intel_digital_connector_state(conn_state); 2186 const struct drm_display_mode *adjusted_mode = 2187 &crtc_state->hw.adjusted_mode; 2188 2189 /* 2190 * Our YCbCr output is always limited range. 2191 * crtc_state->limited_color_range only applies to RGB, 2192 * and it must never be set for YCbCr or we risk setting 2193 * some conflicting bits in TRANSCONF which will mess up 2194 * the colors on the monitor. 2195 */ 2196 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2197 return false; 2198 2199 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2200 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2201 return crtc_state->has_hdmi_sink && 2202 drm_default_rgb_quant_range(adjusted_mode) == 2203 HDMI_QUANTIZATION_RANGE_LIMITED; 2204 } else { 2205 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2206 } 2207 } 2208 2209 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2210 const struct intel_crtc_state *crtc_state, 2211 const struct drm_connector_state *conn_state) 2212 { 2213 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2214 const struct intel_digital_connector_state *intel_conn_state = 2215 to_intel_digital_connector_state(conn_state); 2216 2217 if (!crtc_state->has_hdmi_sink) 2218 return false; 2219 2220 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2221 return connector->base.display_info.has_audio; 2222 else 2223 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2224 } 2225 2226 static enum intel_output_format 2227 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2228 struct intel_connector *connector, 2229 bool ycbcr_420_output) 2230 { 2231 if (!crtc_state->has_hdmi_sink) 2232 return INTEL_OUTPUT_FORMAT_RGB; 2233 2234 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2235 return INTEL_OUTPUT_FORMAT_YCBCR420; 2236 else 2237 return INTEL_OUTPUT_FORMAT_RGB; 2238 } 2239 2240 static enum intel_output_format 2241 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2242 { 2243 return crtc_state->sink_format; 2244 } 2245 2246 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2247 struct intel_crtc_state *crtc_state, 2248 const struct drm_connector_state *conn_state, 2249 bool respect_downstream_limits) 2250 { 2251 struct intel_display *display = to_intel_display(encoder); 2252 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2253 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2254 const struct drm_display_info *info = &connector->base.display_info; 2255 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2256 int ret; 2257 2258 crtc_state->sink_format = 2259 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2260 2261 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2262 drm_dbg_kms(display->drm, 2263 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2264 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2265 } 2266 2267 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2268 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2269 if (ret) { 2270 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2271 !crtc_state->has_hdmi_sink || 2272 !connector->base.ycbcr_420_allowed || 2273 !drm_mode_is_420_also(info, adjusted_mode)) 2274 return ret; 2275 2276 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2277 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2278 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2279 } 2280 2281 return ret; 2282 } 2283 2284 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2285 { 2286 return crtc_state->uapi.encoder_mask && 2287 !is_power_of_2(crtc_state->uapi.encoder_mask); 2288 } 2289 2290 static bool source_supports_scrambling(struct intel_encoder *encoder) 2291 { 2292 /* 2293 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2294 * scrambling is supported. 2295 * But there seem to be cases where certain platforms that support 2296 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2297 * capped by VBT to less than 340MHz. 2298 * 2299 * In such cases when an HDMI2.0 sink is connected, it creates a 2300 * problem : the platform and the sink both support scrambling but the 2301 * HDMI 1.4 retimer chip doesn't. 2302 * 2303 * So go for scrambling, based on the max tmds clock taking into account, 2304 * restrictions coming from VBT. 2305 */ 2306 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2307 } 2308 2309 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2310 const struct intel_crtc_state *crtc_state, 2311 const struct drm_connector_state *conn_state) 2312 { 2313 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2314 2315 return intel_has_hdmi_sink(hdmi, conn_state) && 2316 !intel_hdmi_is_cloned(crtc_state); 2317 } 2318 2319 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2320 struct intel_crtc_state *pipe_config, 2321 struct drm_connector_state *conn_state) 2322 { 2323 struct intel_display *display = to_intel_display(encoder); 2324 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2325 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2326 struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc; 2327 int ret; 2328 2329 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2330 return -EINVAL; 2331 2332 if (!connector->base.interlace_allowed && 2333 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2334 return -EINVAL; 2335 2336 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2337 2338 if (pipe_config->has_hdmi_sink) 2339 pipe_config->has_infoframe = true; 2340 2341 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2342 pipe_config->pixel_multiplier = 2; 2343 2344 pipe_config->has_audio = 2345 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2346 intel_audio_compute_config(encoder, pipe_config, conn_state); 2347 2348 /* 2349 * Try to respect downstream TMDS clock limits first, if 2350 * that fails assume the user might know something we don't. 2351 */ 2352 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2353 if (ret) 2354 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2355 if (ret) { 2356 drm_dbg_kms(display->drm, 2357 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2358 pipe_config->hw.adjusted_mode.crtc_clock); 2359 return ret; 2360 } 2361 2362 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2363 ret = intel_pfit_compute_config(pipe_config, conn_state); 2364 if (ret) 2365 return ret; 2366 } 2367 2368 pipe_config->limited_color_range = 2369 intel_hdmi_limited_color_range(pipe_config, conn_state); 2370 2371 if (conn_state->picture_aspect_ratio) 2372 adjusted_mode->picture_aspect_ratio = 2373 conn_state->picture_aspect_ratio; 2374 2375 pipe_config->lane_count = 4; 2376 2377 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2378 if (scdc->scrambling.low_rates) 2379 pipe_config->hdmi_scrambling = true; 2380 2381 if (pipe_config->port_clock > 340000) { 2382 pipe_config->hdmi_scrambling = true; 2383 pipe_config->hdmi_high_tmds_clock_ratio = true; 2384 } 2385 } 2386 2387 intel_vrr_compute_config(pipe_config, conn_state); 2388 2389 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2390 conn_state); 2391 2392 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2393 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2394 return -EINVAL; 2395 } 2396 2397 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2398 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2403 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2404 return -EINVAL; 2405 } 2406 2407 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2408 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2409 return -EINVAL; 2410 } 2411 2412 return 0; 2413 } 2414 2415 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2416 { 2417 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2418 2419 /* 2420 * Give a hand to buggy BIOSen which forget to turn 2421 * the TMDS output buffers back on after a reboot. 2422 */ 2423 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2424 } 2425 2426 static void 2427 intel_hdmi_unset_edid(struct drm_connector *_connector) 2428 { 2429 struct intel_connector *connector = to_intel_connector(_connector); 2430 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2431 2432 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2433 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2434 2435 drm_edid_free(connector->detect_edid); 2436 connector->detect_edid = NULL; 2437 } 2438 2439 static void 2440 intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector) 2441 { 2442 struct intel_connector *connector = to_intel_connector(_connector); 2443 struct intel_display *display = to_intel_display(connector); 2444 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2445 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2446 struct i2c_adapter *ddc = connector->base.ddc; 2447 enum drm_dp_dual_mode_type type; 2448 2449 type = drm_dp_dual_mode_detect(display->drm, ddc); 2450 2451 /* 2452 * Type 1 DVI adaptors are not required to implement any 2453 * registers, so we can't always detect their presence. 2454 * Ideally we should be able to check the state of the 2455 * CONFIG1 pin, but no such luck on our hardware. 2456 * 2457 * The only method left to us is to check the VBT to see 2458 * if the port is a dual mode capable DP port. 2459 */ 2460 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2461 if (!connector->base.force && 2462 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2463 drm_dbg_kms(display->drm, 2464 "Assuming DP dual mode adaptor presence based on VBT\n"); 2465 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2466 } else { 2467 type = DRM_DP_DUAL_MODE_NONE; 2468 } 2469 } 2470 2471 if (type == DRM_DP_DUAL_MODE_NONE) 2472 return; 2473 2474 hdmi->dp_dual_mode.type = type; 2475 hdmi->dp_dual_mode.max_tmds_clock = 2476 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2477 2478 drm_dbg_kms(display->drm, 2479 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2480 drm_dp_get_dual_mode_type_name(type), 2481 hdmi->dp_dual_mode.max_tmds_clock); 2482 2483 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2484 if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) && 2485 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2486 drm_dbg_kms(display->drm, 2487 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2488 hdmi->dp_dual_mode.max_tmds_clock = 0; 2489 } 2490 } 2491 2492 static bool 2493 intel_hdmi_set_edid(struct drm_connector *_connector) 2494 { 2495 struct intel_connector *connector = to_intel_connector(_connector); 2496 struct intel_display *display = to_intel_display(connector); 2497 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2498 struct i2c_adapter *ddc = connector->base.ddc; 2499 intel_wakeref_t wakeref; 2500 const struct drm_edid *drm_edid; 2501 bool connected = false; 2502 2503 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2504 2505 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2506 2507 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2508 drm_dbg_kms(display->drm, 2509 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2510 intel_gmbus_force_bit(ddc, true); 2511 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2512 intel_gmbus_force_bit(ddc, false); 2513 } 2514 2515 /* Below we depend on display info having been updated */ 2516 drm_edid_connector_update(&connector->base, drm_edid); 2517 2518 connector->detect_edid = drm_edid; 2519 2520 if (drm_edid_is_digital(drm_edid)) { 2521 intel_hdmi_dp_dual_mode_detect(&connector->base); 2522 2523 connected = true; 2524 } 2525 2526 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2527 2528 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2529 connector->base.display_info.source_physical_address); 2530 2531 return connected; 2532 } 2533 2534 static enum drm_connector_status 2535 intel_hdmi_detect(struct drm_connector *_connector, bool force) 2536 { 2537 struct intel_connector *connector = to_intel_connector(_connector); 2538 struct intel_display *display = to_intel_display(connector); 2539 enum drm_connector_status status = connector_status_disconnected; 2540 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2541 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2542 intel_wakeref_t wakeref; 2543 2544 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2545 connector->base.base.id, connector->base.name); 2546 2547 if (!intel_display_device_enabled(display)) 2548 return connector_status_disconnected; 2549 2550 if (!intel_display_driver_check_access(display)) 2551 return connector->base.status; 2552 2553 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2554 2555 if (DISPLAY_VER(display) >= 11 && 2556 !intel_digital_port_connected(encoder)) 2557 goto out; 2558 2559 intel_hdmi_unset_edid(&connector->base); 2560 2561 if (intel_hdmi_set_edid(&connector->base)) 2562 status = connector_status_connected; 2563 2564 out: 2565 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2566 2567 if (status != connector_status_connected) 2568 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2569 2570 return status; 2571 } 2572 2573 static void 2574 intel_hdmi_force(struct drm_connector *_connector) 2575 { 2576 struct intel_connector *connector = to_intel_connector(_connector); 2577 struct intel_display *display = to_intel_display(connector); 2578 2579 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2580 connector->base.base.id, connector->base.name); 2581 2582 if (!intel_display_driver_check_access(display)) 2583 return; 2584 2585 intel_hdmi_unset_edid(&connector->base); 2586 2587 if (connector->base.status != connector_status_connected) 2588 return; 2589 2590 intel_hdmi_set_edid(&connector->base); 2591 } 2592 2593 static int intel_hdmi_get_modes(struct drm_connector *_connector) 2594 { 2595 struct intel_connector *connector = to_intel_connector(_connector); 2596 2597 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2598 return drm_edid_connector_add_modes(&connector->base); 2599 } 2600 2601 static int 2602 intel_hdmi_connector_register(struct drm_connector *_connector) 2603 { 2604 struct intel_connector *connector = to_intel_connector(_connector); 2605 int ret; 2606 2607 ret = intel_connector_register(&connector->base); 2608 if (ret) 2609 return ret; 2610 2611 return ret; 2612 } 2613 2614 static void intel_hdmi_connector_unregister(struct drm_connector *_connector) 2615 { 2616 struct intel_connector *connector = to_intel_connector(_connector); 2617 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; 2618 2619 cec_notifier_conn_unregister(n); 2620 2621 intel_connector_unregister(&connector->base); 2622 } 2623 2624 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2625 .detect = intel_hdmi_detect, 2626 .force = intel_hdmi_force, 2627 .fill_modes = drm_helper_probe_single_connector_modes, 2628 .atomic_get_property = intel_digital_connector_atomic_get_property, 2629 .atomic_set_property = intel_digital_connector_atomic_set_property, 2630 .late_register = intel_hdmi_connector_register, 2631 .early_unregister = intel_hdmi_connector_unregister, 2632 .destroy = intel_connector_destroy, 2633 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2634 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2635 }; 2636 2637 static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, 2638 struct drm_atomic_state *state) 2639 { 2640 struct intel_connector *connector = to_intel_connector(_connector); 2641 struct intel_display *display = to_intel_display(connector); 2642 2643 if (HAS_DDI(display)) 2644 return intel_digital_connector_atomic_check(&connector->base, state); 2645 else 2646 return g4x_hdmi_connector_atomic_check(&connector->base, state); 2647 } 2648 2649 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2650 .get_modes = intel_hdmi_get_modes, 2651 .mode_valid = intel_hdmi_mode_valid, 2652 .atomic_check = intel_hdmi_connector_atomic_check, 2653 }; 2654 2655 static void 2656 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_connector) 2657 { 2658 struct intel_connector *connector = to_intel_connector(_connector); 2659 struct intel_display *display = to_intel_display(intel_hdmi); 2660 2661 intel_attach_force_audio_property(&connector->base); 2662 intel_attach_broadcast_rgb_property(&connector->base); 2663 intel_attach_aspect_ratio_property(&connector->base); 2664 2665 intel_attach_hdmi_colorspace_property(&connector->base); 2666 drm_connector_attach_content_type_property(&connector->base); 2667 2668 if (DISPLAY_VER(display) >= 10) 2669 drm_connector_attach_hdr_output_metadata_property(&connector->base); 2670 2671 if (!HAS_GMCH(display)) 2672 drm_connector_attach_max_bpc_property(&connector->base, 8, 12); 2673 } 2674 2675 /* 2676 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2677 * @encoder: intel_encoder 2678 * @connector: drm_connector 2679 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2680 * or reset the high tmds clock ratio for scrambling 2681 * @scrambling: bool to Indicate if the function needs to set or reset 2682 * sink scrambling 2683 * 2684 * This function handles scrambling on HDMI 2.0 capable sinks. 2685 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2686 * it enables scrambling. This should be called before enabling the HDMI 2687 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2688 * detect a scrambled clock within 100 ms. 2689 * 2690 * Returns: 2691 * True on success, false on failure. 2692 */ 2693 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2694 struct drm_connector *_connector, 2695 bool high_tmds_clock_ratio, 2696 bool scrambling) 2697 { 2698 struct intel_connector *connector = to_intel_connector(_connector); 2699 struct intel_display *display = to_intel_display(encoder); 2700 struct drm_scrambling *sink_scrambling = 2701 &connector->base.display_info.hdmi.scdc.scrambling; 2702 2703 if (!sink_scrambling->supported) 2704 return true; 2705 2706 drm_dbg_kms(display->drm, 2707 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2708 connector->base.base.id, connector->base.name, 2709 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2710 2711 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2712 return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) && 2713 drm_scdc_set_scrambling(&connector->base, scrambling); 2714 } 2715 2716 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2717 { 2718 enum port port = encoder->port; 2719 u8 ddc_pin; 2720 2721 switch (port) { 2722 case PORT_B: 2723 ddc_pin = GMBUS_PIN_DPB; 2724 break; 2725 case PORT_C: 2726 ddc_pin = GMBUS_PIN_DPC; 2727 break; 2728 case PORT_D: 2729 ddc_pin = GMBUS_PIN_DPD_CHV; 2730 break; 2731 default: 2732 MISSING_CASE(port); 2733 ddc_pin = GMBUS_PIN_DPB; 2734 break; 2735 } 2736 return ddc_pin; 2737 } 2738 2739 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2740 { 2741 enum port port = encoder->port; 2742 u8 ddc_pin; 2743 2744 switch (port) { 2745 case PORT_B: 2746 ddc_pin = GMBUS_PIN_1_BXT; 2747 break; 2748 case PORT_C: 2749 ddc_pin = GMBUS_PIN_2_BXT; 2750 break; 2751 default: 2752 MISSING_CASE(port); 2753 ddc_pin = GMBUS_PIN_1_BXT; 2754 break; 2755 } 2756 return ddc_pin; 2757 } 2758 2759 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2760 { 2761 enum port port = encoder->port; 2762 u8 ddc_pin; 2763 2764 switch (port) { 2765 case PORT_B: 2766 ddc_pin = GMBUS_PIN_1_BXT; 2767 break; 2768 case PORT_C: 2769 ddc_pin = GMBUS_PIN_2_BXT; 2770 break; 2771 case PORT_D: 2772 ddc_pin = GMBUS_PIN_4_CNP; 2773 break; 2774 case PORT_F: 2775 ddc_pin = GMBUS_PIN_3_BXT; 2776 break; 2777 default: 2778 MISSING_CASE(port); 2779 ddc_pin = GMBUS_PIN_1_BXT; 2780 break; 2781 } 2782 return ddc_pin; 2783 } 2784 2785 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2786 { 2787 struct intel_display *display = to_intel_display(encoder); 2788 enum port port = encoder->port; 2789 2790 if (intel_encoder_is_combo(encoder)) 2791 return GMBUS_PIN_1_BXT + port; 2792 else if (intel_encoder_is_tc(encoder)) 2793 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2794 2795 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2796 return GMBUS_PIN_2_BXT; 2797 } 2798 2799 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2800 { 2801 enum phy phy = intel_encoder_to_phy(encoder); 2802 u8 ddc_pin; 2803 2804 switch (phy) { 2805 case PHY_A: 2806 ddc_pin = GMBUS_PIN_1_BXT; 2807 break; 2808 case PHY_B: 2809 ddc_pin = GMBUS_PIN_2_BXT; 2810 break; 2811 case PHY_C: 2812 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2813 break; 2814 default: 2815 MISSING_CASE(phy); 2816 ddc_pin = GMBUS_PIN_1_BXT; 2817 break; 2818 } 2819 return ddc_pin; 2820 } 2821 2822 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2823 { 2824 struct intel_display *display = to_intel_display(encoder); 2825 enum phy phy = intel_encoder_to_phy(encoder); 2826 2827 WARN_ON(encoder->port == PORT_C); 2828 2829 /* 2830 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2831 * final two outputs use type-c pins, even though they're actually 2832 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2833 * all outputs. 2834 */ 2835 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2836 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2837 2838 return GMBUS_PIN_1_BXT + phy; 2839 } 2840 2841 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2842 { 2843 struct intel_display *display = to_intel_display(encoder); 2844 enum phy phy = intel_encoder_to_phy(encoder); 2845 2846 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2847 2848 /* 2849 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2850 * final two outputs use type-c pins, even though they're actually 2851 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2852 * all outputs. 2853 */ 2854 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2855 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2856 2857 return GMBUS_PIN_1_BXT + phy; 2858 } 2859 2860 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2861 { 2862 return intel_encoder_to_phy(encoder) + 1; 2863 } 2864 2865 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2866 { 2867 enum phy phy = intel_encoder_to_phy(encoder); 2868 2869 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2870 2871 /* 2872 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2873 * except first combo output. 2874 */ 2875 if (phy == PHY_A) 2876 return GMBUS_PIN_1_BXT; 2877 2878 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2879 } 2880 2881 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2882 { 2883 enum port port = encoder->port; 2884 u8 ddc_pin; 2885 2886 switch (port) { 2887 case PORT_B: 2888 ddc_pin = GMBUS_PIN_DPB; 2889 break; 2890 case PORT_C: 2891 ddc_pin = GMBUS_PIN_DPC; 2892 break; 2893 case PORT_D: 2894 ddc_pin = GMBUS_PIN_DPD; 2895 break; 2896 default: 2897 MISSING_CASE(port); 2898 ddc_pin = GMBUS_PIN_DPB; 2899 break; 2900 } 2901 return ddc_pin; 2902 } 2903 2904 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2905 { 2906 struct intel_display *display = to_intel_display(encoder); 2907 u8 ddc_pin; 2908 2909 if (display->platform.alderlake_s) 2910 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2911 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 2912 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2913 else if (display->platform.rocketlake) 2914 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2915 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display)) 2916 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2917 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 2918 HAS_PCH_TGP(display)) 2919 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2920 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2921 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2922 else if (HAS_PCH_CNP(display)) 2923 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2924 else if (display->platform.geminilake || display->platform.broxton) 2925 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2926 else if (display->platform.cherryview) 2927 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2928 else 2929 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2930 2931 return ddc_pin; 2932 } 2933 2934 static struct intel_encoder * 2935 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2936 { 2937 struct intel_display *display = to_intel_display(encoder); 2938 struct intel_encoder *other; 2939 2940 for_each_intel_encoder(display->drm, other) { 2941 struct intel_connector *connector; 2942 2943 if (other == encoder) 2944 continue; 2945 2946 if (!intel_encoder_is_dig_port(other)) 2947 continue; 2948 2949 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2950 2951 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) 2952 return other; 2953 } 2954 2955 return NULL; 2956 } 2957 2958 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2959 { 2960 struct intel_display *display = to_intel_display(encoder); 2961 struct intel_encoder *other; 2962 const char *source; 2963 u8 ddc_pin; 2964 2965 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2966 source = "VBT"; 2967 2968 if (!ddc_pin) { 2969 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2970 source = "platform default"; 2971 } 2972 2973 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { 2974 drm_dbg_kms(display->drm, 2975 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2976 encoder->base.base.id, encoder->base.name, ddc_pin); 2977 return 0; 2978 } 2979 2980 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2981 if (other) { 2982 drm_dbg_kms(display->drm, 2983 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2984 encoder->base.base.id, encoder->base.name, ddc_pin, 2985 other->base.base.id, other->base.name); 2986 return 0; 2987 } 2988 2989 drm_dbg_kms(display->drm, 2990 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2991 encoder->base.base.id, encoder->base.name, 2992 ddc_pin, source); 2993 2994 return ddc_pin; 2995 } 2996 2997 void intel_infoframe_init(struct intel_digital_port *dig_port) 2998 { 2999 struct intel_display *display = to_intel_display(dig_port); 3000 3001 if (display->platform.valleyview || display->platform.cherryview) { 3002 dig_port->write_infoframe = vlv_write_infoframe; 3003 dig_port->read_infoframe = vlv_read_infoframe; 3004 dig_port->set_infoframes = vlv_set_infoframes; 3005 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3006 } else if (display->platform.g4x) { 3007 dig_port->write_infoframe = g4x_write_infoframe; 3008 dig_port->read_infoframe = g4x_read_infoframe; 3009 dig_port->set_infoframes = g4x_set_infoframes; 3010 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3011 } else if (HAS_DDI(display)) { 3012 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 3013 dig_port->write_infoframe = lspcon_write_infoframe; 3014 dig_port->read_infoframe = lspcon_read_infoframe; 3015 dig_port->set_infoframes = lspcon_set_infoframes; 3016 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3017 } else { 3018 dig_port->write_infoframe = hsw_write_infoframe; 3019 dig_port->read_infoframe = hsw_read_infoframe; 3020 dig_port->set_infoframes = hsw_set_infoframes; 3021 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3022 } 3023 } else if (HAS_PCH_IBX(display)) { 3024 dig_port->write_infoframe = ibx_write_infoframe; 3025 dig_port->read_infoframe = ibx_read_infoframe; 3026 dig_port->set_infoframes = ibx_set_infoframes; 3027 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3028 } else { 3029 dig_port->write_infoframe = cpt_write_infoframe; 3030 dig_port->read_infoframe = cpt_read_infoframe; 3031 dig_port->set_infoframes = cpt_set_infoframes; 3032 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3033 } 3034 } 3035 3036 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3037 struct intel_connector *intel_connector) 3038 { 3039 struct intel_display *display = to_intel_display(dig_port); 3040 struct drm_connector *connector = &intel_connector->base; 3041 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3042 struct intel_encoder *intel_encoder = &dig_port->base; 3043 struct drm_device *dev = intel_encoder->base.dev; 3044 enum port port = intel_encoder->port; 3045 struct cec_connector_info conn_info; 3046 u8 ddc_pin; 3047 3048 drm_dbg_kms(display->drm, 3049 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3050 intel_encoder->base.base.id, intel_encoder->base.name); 3051 3052 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3053 return false; 3054 3055 if (drm_WARN(dev, dig_port->max_lanes < 4, 3056 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3057 dig_port->max_lanes, intel_encoder->base.base.id, 3058 intel_encoder->base.name)) 3059 return false; 3060 3061 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3062 if (!ddc_pin) 3063 return false; 3064 3065 drm_connector_init_with_ddc(dev, connector, 3066 &intel_hdmi_connector_funcs, 3067 DRM_MODE_CONNECTOR_HDMIA, 3068 intel_gmbus_get_adapter(display, ddc_pin)); 3069 3070 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3071 3072 if (DISPLAY_VER(display) < 12) 3073 connector->interlace_allowed = true; 3074 3075 connector->stereo_allowed = true; 3076 3077 if (DISPLAY_VER(display) >= 10) 3078 connector->ycbcr_420_allowed = true; 3079 3080 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3081 intel_connector->base.polled = intel_connector->polled; 3082 3083 if (HAS_DDI(display)) 3084 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3085 else 3086 intel_connector->get_hw_state = intel_connector_get_hw_state; 3087 3088 intel_hdmi_add_properties(intel_hdmi, connector); 3089 3090 intel_connector_attach_encoder(intel_connector, intel_encoder); 3091 intel_hdmi->attached_connector = intel_connector; 3092 3093 if (is_hdcp_supported(display, port)) { 3094 int ret = intel_hdcp_init(intel_connector, dig_port, 3095 &intel_hdmi_hdcp_shim); 3096 if (ret) 3097 drm_dbg_kms(display->drm, 3098 "HDCP init failed, skipping.\n"); 3099 } 3100 3101 cec_fill_conn_info_from_drm(&conn_info, connector); 3102 3103 intel_hdmi->cec_notifier = 3104 cec_notifier_conn_register(dev->dev, port_identifier(port), 3105 &conn_info); 3106 if (!intel_hdmi->cec_notifier) 3107 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3108 3109 return true; 3110 } 3111 3112 /* 3113 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3114 * @vactive: Vactive of a display mode 3115 * 3116 * @return: appropriate dsc slice height for a given mode. 3117 */ 3118 int intel_hdmi_dsc_get_slice_height(int vactive) 3119 { 3120 int slice_height; 3121 3122 /* 3123 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3124 * Select smallest slice height >=96, that results in a valid PPS and 3125 * requires minimum padding lines required for final slice. 3126 * 3127 * Assumption : Vactive is even. 3128 */ 3129 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3130 if (vactive % slice_height == 0) 3131 return slice_height; 3132 3133 return 0; 3134 } 3135 3136 /* 3137 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3138 * and dsc decoder capabilities 3139 * 3140 * @crtc_state: intel crtc_state 3141 * @src_max_slices: maximum slices supported by the DSC encoder 3142 * @src_max_slice_width: maximum slice width supported by DSC encoder 3143 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3144 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3145 * 3146 * @return: num of dsc slices that can be supported by the dsc encoder 3147 * and decoder. 3148 */ 3149 int 3150 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3151 int src_max_slices, int src_max_slice_width, 3152 int hdmi_max_slices, int hdmi_throughput) 3153 { 3154 /* Pixel rates in KPixels/sec */ 3155 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3156 /* 3157 * Rates at which the source and sink are required to process pixels in each 3158 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3159 */ 3160 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3161 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3162 3163 /* Spec limits the slice width to 2720 pixels */ 3164 #define MAX_HDMI_SLICE_WIDTH 2720 3165 int kslice_adjust; 3166 int adjusted_clk_khz; 3167 int min_slices; 3168 int target_slices; 3169 int max_throughput; /* max clock freq. in khz per slice */ 3170 int max_slice_width; 3171 int slice_width; 3172 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3173 3174 if (!hdmi_throughput) 3175 return 0; 3176 3177 /* 3178 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3179 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3180 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3181 * dividing adjusted clock value by 10. 3182 */ 3183 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3184 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3185 kslice_adjust = 10; 3186 else 3187 kslice_adjust = 5; 3188 3189 /* 3190 * As per spec, the rate at which the source and the sink process 3191 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3192 * This depends upon the pixel clock rate and output formats 3193 * (kslice adjust). 3194 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3195 * at max 340MHz, otherwise they can be processed at max 400MHz. 3196 */ 3197 3198 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3199 3200 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3201 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3202 else 3203 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3204 3205 /* 3206 * Taking into account the sink's capability for maximum 3207 * clock per slice (in MHz) as read from HF-VSDB. 3208 */ 3209 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3210 3211 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3212 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3213 3214 /* 3215 * Keep on increasing the num of slices/line, starting from min_slices 3216 * per line till we get such a number, for which the slice_width is 3217 * just less than max_slice_width. The slices/line selected should be 3218 * less than or equal to the max horizontal slices that the combination 3219 * of PCON encoder and HDMI decoder can support. 3220 */ 3221 slice_width = max_slice_width; 3222 3223 do { 3224 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3225 target_slices = 1; 3226 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3227 target_slices = 2; 3228 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3229 target_slices = 4; 3230 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3231 target_slices = 8; 3232 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3233 target_slices = 12; 3234 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3235 target_slices = 16; 3236 else 3237 return 0; 3238 3239 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3240 if (slice_width >= max_slice_width) 3241 min_slices = target_slices + 1; 3242 } while (slice_width >= max_slice_width); 3243 3244 return target_slices; 3245 } 3246 3247 /* 3248 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3249 * source and sink capabilities. 3250 * 3251 * @src_fraction_bpp: fractional bpp supported by the source 3252 * @slice_width: dsc slice width supported by the source and sink 3253 * @num_slices: num of slices supported by the source and sink 3254 * @output_format: video output format 3255 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3256 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3257 * 3258 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3259 */ 3260 int 3261 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3262 int output_format, bool hdmi_all_bpp, 3263 int hdmi_max_chunk_bytes) 3264 { 3265 int max_dsc_bpp, min_dsc_bpp; 3266 int target_bytes; 3267 bool bpp_found = false; 3268 int bpp_decrement_x16; 3269 int bpp_target; 3270 int bpp_target_x16; 3271 3272 /* 3273 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3274 * Start with the max bpp and keep on decrementing with 3275 * fractional bpp, if supported by PCON DSC encoder 3276 * 3277 * for each bpp we check if no of bytes can be supported by HDMI sink 3278 */ 3279 3280 /* Assuming: bpc as 8*/ 3281 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3282 min_dsc_bpp = 6; 3283 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3284 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3285 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3286 min_dsc_bpp = 8; 3287 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3288 } else { 3289 /* Assuming 4:2:2 encoding */ 3290 min_dsc_bpp = 7; 3291 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3292 } 3293 3294 /* 3295 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3296 * Section 7.7.34 : Source shall not enable compressed Video 3297 * Transport with bpp_target settings above 12 bpp unless 3298 * DSC_all_bpp is set to 1. 3299 */ 3300 if (!hdmi_all_bpp) 3301 max_dsc_bpp = min(max_dsc_bpp, 12); 3302 3303 /* 3304 * The Sink has a limit of compressed data in bytes for a scanline, 3305 * as described in max_chunk_bytes field in HFVSDB block of edid. 3306 * The no. of bytes depend on the target bits per pixel that the 3307 * source configures. So we start with the max_bpp and calculate 3308 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3309 * till we get the target_chunk_bytes just less than what the sink's 3310 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3311 * 3312 * The decrement is according to the fractional support from PCON DSC 3313 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3314 * 3315 * bpp_target_x16 = bpp_target * 16 3316 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3317 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3318 */ 3319 3320 bpp_target = max_dsc_bpp; 3321 3322 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3323 if (!src_fractional_bpp) 3324 src_fractional_bpp = 1; 3325 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3326 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3327 3328 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3329 int bpp; 3330 3331 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3332 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3333 if (target_bytes <= hdmi_max_chunk_bytes) { 3334 bpp_found = true; 3335 break; 3336 } 3337 bpp_target_x16 -= bpp_decrement_x16; 3338 } 3339 if (bpp_found) 3340 return bpp_target_x16; 3341 3342 return 0; 3343 } 3344