1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/slab.h> 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_hdcp.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <drm/intel_lpe_audio.h> 40 41 #include "i915_debugfs.h" 42 #include "i915_drv.h" 43 #include "intel_atomic.h" 44 #include "intel_connector.h" 45 #include "intel_ddi.h" 46 #include "intel_de.h" 47 #include "intel_display_types.h" 48 #include "intel_dp.h" 49 #include "intel_gmbus.h" 50 #include "intel_hdcp.h" 51 #include "intel_hdmi.h" 52 #include "intel_lspcon.h" 53 #include "intel_panel.h" 54 55 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) 56 { 57 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; 58 } 59 60 static void 61 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 62 { 63 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); 64 struct drm_i915_private *dev_priv = to_i915(dev); 65 u32 enabled_bits; 66 67 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 68 69 drm_WARN(dev, 70 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, 71 "HDMI port enabled, expecting disabled\n"); 72 } 73 74 static void 75 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, 76 enum transcoder cpu_transcoder) 77 { 78 drm_WARN(&dev_priv->drm, 79 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & 80 TRANS_DDI_FUNC_ENABLE, 81 "HDMI transcoder function enabled, expecting disabled\n"); 82 } 83 84 static u32 g4x_infoframe_index(unsigned int type) 85 { 86 switch (type) { 87 case HDMI_PACKET_TYPE_GAMUT_METADATA: 88 return VIDEO_DIP_SELECT_GAMUT; 89 case HDMI_INFOFRAME_TYPE_AVI: 90 return VIDEO_DIP_SELECT_AVI; 91 case HDMI_INFOFRAME_TYPE_SPD: 92 return VIDEO_DIP_SELECT_SPD; 93 case HDMI_INFOFRAME_TYPE_VENDOR: 94 return VIDEO_DIP_SELECT_VENDOR; 95 default: 96 MISSING_CASE(type); 97 return 0; 98 } 99 } 100 101 static u32 g4x_infoframe_enable(unsigned int type) 102 { 103 switch (type) { 104 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 105 return VIDEO_DIP_ENABLE_GCP; 106 case HDMI_PACKET_TYPE_GAMUT_METADATA: 107 return VIDEO_DIP_ENABLE_GAMUT; 108 case DP_SDP_VSC: 109 return 0; 110 case HDMI_INFOFRAME_TYPE_AVI: 111 return VIDEO_DIP_ENABLE_AVI; 112 case HDMI_INFOFRAME_TYPE_SPD: 113 return VIDEO_DIP_ENABLE_SPD; 114 case HDMI_INFOFRAME_TYPE_VENDOR: 115 return VIDEO_DIP_ENABLE_VENDOR; 116 case HDMI_INFOFRAME_TYPE_DRM: 117 return 0; 118 default: 119 MISSING_CASE(type); 120 return 0; 121 } 122 } 123 124 static u32 hsw_infoframe_enable(unsigned int type) 125 { 126 switch (type) { 127 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 128 return VIDEO_DIP_ENABLE_GCP_HSW; 129 case HDMI_PACKET_TYPE_GAMUT_METADATA: 130 return VIDEO_DIP_ENABLE_GMP_HSW; 131 case DP_SDP_VSC: 132 return VIDEO_DIP_ENABLE_VSC_HSW; 133 case DP_SDP_PPS: 134 return VDIP_ENABLE_PPS; 135 case HDMI_INFOFRAME_TYPE_AVI: 136 return VIDEO_DIP_ENABLE_AVI_HSW; 137 case HDMI_INFOFRAME_TYPE_SPD: 138 return VIDEO_DIP_ENABLE_SPD_HSW; 139 case HDMI_INFOFRAME_TYPE_VENDOR: 140 return VIDEO_DIP_ENABLE_VS_HSW; 141 case HDMI_INFOFRAME_TYPE_DRM: 142 return VIDEO_DIP_ENABLE_DRM_GLK; 143 default: 144 MISSING_CASE(type); 145 return 0; 146 } 147 } 148 149 static i915_reg_t 150 hsw_dip_data_reg(struct drm_i915_private *dev_priv, 151 enum transcoder cpu_transcoder, 152 unsigned int type, 153 int i) 154 { 155 switch (type) { 156 case HDMI_PACKET_TYPE_GAMUT_METADATA: 157 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); 158 case DP_SDP_VSC: 159 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); 160 case DP_SDP_PPS: 161 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); 162 case HDMI_INFOFRAME_TYPE_AVI: 163 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); 164 case HDMI_INFOFRAME_TYPE_SPD: 165 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); 166 case HDMI_INFOFRAME_TYPE_VENDOR: 167 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); 168 case HDMI_INFOFRAME_TYPE_DRM: 169 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); 170 default: 171 MISSING_CASE(type); 172 return INVALID_MMIO_REG; 173 } 174 } 175 176 static int hsw_dip_data_size(struct drm_i915_private *dev_priv, 177 unsigned int type) 178 { 179 switch (type) { 180 case DP_SDP_VSC: 181 return VIDEO_DIP_VSC_DATA_SIZE; 182 case DP_SDP_PPS: 183 return VIDEO_DIP_PPS_DATA_SIZE; 184 case HDMI_PACKET_TYPE_GAMUT_METADATA: 185 if (DISPLAY_VER(dev_priv) >= 11) 186 return VIDEO_DIP_GMP_DATA_SIZE; 187 else 188 return VIDEO_DIP_DATA_SIZE; 189 default: 190 return VIDEO_DIP_DATA_SIZE; 191 } 192 } 193 194 static void g4x_write_infoframe(struct intel_encoder *encoder, 195 const struct intel_crtc_state *crtc_state, 196 unsigned int type, 197 const void *frame, ssize_t len) 198 { 199 const u32 *data = frame; 200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 201 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 202 int i; 203 204 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 205 "Writing DIP with CTL reg disabled\n"); 206 207 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 208 val |= g4x_infoframe_index(type); 209 210 val &= ~g4x_infoframe_enable(type); 211 212 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 213 214 for (i = 0; i < len; i += 4) { 215 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); 216 data++; 217 } 218 /* Write every possible data byte to force correct ECC calculation. */ 219 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 220 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); 221 222 val |= g4x_infoframe_enable(type); 223 val &= ~VIDEO_DIP_FREQ_MASK; 224 val |= VIDEO_DIP_FREQ_VSYNC; 225 226 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 227 intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); 228 } 229 230 static void g4x_read_infoframe(struct intel_encoder *encoder, 231 const struct intel_crtc_state *crtc_state, 232 unsigned int type, 233 void *frame, ssize_t len) 234 { 235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 236 u32 val, *data = frame; 237 int i; 238 239 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 240 241 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 242 val |= g4x_infoframe_index(type); 243 244 intel_de_write(dev_priv, VIDEO_DIP_CTL, val); 245 246 for (i = 0; i < len; i += 4) 247 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); 248 } 249 250 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 251 const struct intel_crtc_state *pipe_config) 252 { 253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 254 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); 255 256 if ((val & VIDEO_DIP_ENABLE) == 0) 257 return 0; 258 259 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 260 return 0; 261 262 return val & (VIDEO_DIP_ENABLE_AVI | 263 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 264 } 265 266 static void ibx_write_infoframe(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state, 268 unsigned int type, 269 const void *frame, ssize_t len) 270 { 271 const u32 *data = frame; 272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 273 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 274 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 275 u32 val = intel_de_read(dev_priv, reg); 276 int i; 277 278 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 279 "Writing DIP with CTL reg disabled\n"); 280 281 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 282 val |= g4x_infoframe_index(type); 283 284 val &= ~g4x_infoframe_enable(type); 285 286 intel_de_write(dev_priv, reg, val); 287 288 for (i = 0; i < len; i += 4) { 289 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 290 *data); 291 data++; 292 } 293 /* Write every possible data byte to force correct ECC calculation. */ 294 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 295 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 296 297 val |= g4x_infoframe_enable(type); 298 val &= ~VIDEO_DIP_FREQ_MASK; 299 val |= VIDEO_DIP_FREQ_VSYNC; 300 301 intel_de_write(dev_priv, reg, val); 302 intel_de_posting_read(dev_priv, reg); 303 } 304 305 static void ibx_read_infoframe(struct intel_encoder *encoder, 306 const struct intel_crtc_state *crtc_state, 307 unsigned int type, 308 void *frame, ssize_t len) 309 { 310 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 311 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 312 u32 val, *data = frame; 313 int i; 314 315 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 316 317 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 318 val |= g4x_infoframe_index(type); 319 320 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 321 322 for (i = 0; i < len; i += 4) 323 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 324 } 325 326 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 327 const struct intel_crtc_state *pipe_config) 328 { 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 331 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 332 u32 val = intel_de_read(dev_priv, reg); 333 334 if ((val & VIDEO_DIP_ENABLE) == 0) 335 return 0; 336 337 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 338 return 0; 339 340 return val & (VIDEO_DIP_ENABLE_AVI | 341 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 342 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 343 } 344 345 static void cpt_write_infoframe(struct intel_encoder *encoder, 346 const struct intel_crtc_state *crtc_state, 347 unsigned int type, 348 const void *frame, ssize_t len) 349 { 350 const u32 *data = frame; 351 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 353 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 354 u32 val = intel_de_read(dev_priv, reg); 355 int i; 356 357 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 358 "Writing DIP with CTL reg disabled\n"); 359 360 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 361 val |= g4x_infoframe_index(type); 362 363 /* The DIP control register spec says that we need to update the AVI 364 * infoframe without clearing its enable bit */ 365 if (type != HDMI_INFOFRAME_TYPE_AVI) 366 val &= ~g4x_infoframe_enable(type); 367 368 intel_de_write(dev_priv, reg, val); 369 370 for (i = 0; i < len; i += 4) { 371 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 372 *data); 373 data++; 374 } 375 /* Write every possible data byte to force correct ECC calculation. */ 376 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 377 intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0); 378 379 val |= g4x_infoframe_enable(type); 380 val &= ~VIDEO_DIP_FREQ_MASK; 381 val |= VIDEO_DIP_FREQ_VSYNC; 382 383 intel_de_write(dev_priv, reg, val); 384 intel_de_posting_read(dev_priv, reg); 385 } 386 387 static void cpt_read_infoframe(struct intel_encoder *encoder, 388 const struct intel_crtc_state *crtc_state, 389 unsigned int type, 390 void *frame, ssize_t len) 391 { 392 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 393 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 394 u32 val, *data = frame; 395 int i; 396 397 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); 398 399 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 400 val |= g4x_infoframe_index(type); 401 402 intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); 403 404 for (i = 0; i < len; i += 4) 405 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); 406 } 407 408 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 409 const struct intel_crtc_state *pipe_config) 410 { 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 412 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 413 u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); 414 415 if ((val & VIDEO_DIP_ENABLE) == 0) 416 return 0; 417 418 return val & (VIDEO_DIP_ENABLE_AVI | 419 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 420 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 421 } 422 423 static void vlv_write_infoframe(struct intel_encoder *encoder, 424 const struct intel_crtc_state *crtc_state, 425 unsigned int type, 426 const void *frame, ssize_t len) 427 { 428 const u32 *data = frame; 429 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 431 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 432 u32 val = intel_de_read(dev_priv, reg); 433 int i; 434 435 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), 436 "Writing DIP with CTL reg disabled\n"); 437 438 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 439 val |= g4x_infoframe_index(type); 440 441 val &= ~g4x_infoframe_enable(type); 442 443 intel_de_write(dev_priv, reg, val); 444 445 for (i = 0; i < len; i += 4) { 446 intel_de_write(dev_priv, 447 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 448 data++; 449 } 450 /* Write every possible data byte to force correct ECC calculation. */ 451 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 452 intel_de_write(dev_priv, 453 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 454 455 val |= g4x_infoframe_enable(type); 456 val &= ~VIDEO_DIP_FREQ_MASK; 457 val |= VIDEO_DIP_FREQ_VSYNC; 458 459 intel_de_write(dev_priv, reg, val); 460 intel_de_posting_read(dev_priv, reg); 461 } 462 463 static void vlv_read_infoframe(struct intel_encoder *encoder, 464 const struct intel_crtc_state *crtc_state, 465 unsigned int type, 466 void *frame, ssize_t len) 467 { 468 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 469 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 470 u32 val, *data = frame; 471 int i; 472 473 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); 474 475 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 476 val |= g4x_infoframe_index(type); 477 478 intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); 479 480 for (i = 0; i < len; i += 4) 481 *data++ = intel_de_read(dev_priv, 482 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 483 } 484 485 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 486 const struct intel_crtc_state *pipe_config) 487 { 488 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 489 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 490 u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); 491 492 if ((val & VIDEO_DIP_ENABLE) == 0) 493 return 0; 494 495 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 496 return 0; 497 498 return val & (VIDEO_DIP_ENABLE_AVI | 499 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 500 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 501 } 502 503 void hsw_write_infoframe(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state, 505 unsigned int type, 506 const void *frame, ssize_t len) 507 { 508 const u32 *data = frame; 509 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 510 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 511 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); 512 int data_size; 513 int i; 514 u32 val = intel_de_read(dev_priv, ctl_reg); 515 516 data_size = hsw_dip_data_size(dev_priv, type); 517 518 drm_WARN_ON(&dev_priv->drm, len > data_size); 519 520 val &= ~hsw_infoframe_enable(type); 521 intel_de_write(dev_priv, ctl_reg, val); 522 523 for (i = 0; i < len; i += 4) { 524 intel_de_write(dev_priv, 525 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 526 *data); 527 data++; 528 } 529 /* Write every possible data byte to force correct ECC calculation. */ 530 for (; i < data_size; i += 4) 531 intel_de_write(dev_priv, 532 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), 533 0); 534 535 /* Wa_14013475917 */ 536 if (DISPLAY_VER(dev_priv) == 13 && crtc_state->has_psr && 537 type == DP_SDP_VSC) 538 return; 539 540 val |= hsw_infoframe_enable(type); 541 intel_de_write(dev_priv, ctl_reg, val); 542 intel_de_posting_read(dev_priv, ctl_reg); 543 } 544 545 void hsw_read_infoframe(struct intel_encoder *encoder, 546 const struct intel_crtc_state *crtc_state, 547 unsigned int type, void *frame, ssize_t len) 548 { 549 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 550 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 551 u32 *data = frame; 552 int i; 553 554 for (i = 0; i < len; i += 4) 555 *data++ = intel_de_read(dev_priv, 556 hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); 557 } 558 559 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 560 const struct intel_crtc_state *pipe_config) 561 { 562 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 563 u32 val = intel_de_read(dev_priv, 564 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); 565 u32 mask; 566 567 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 568 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 569 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 570 571 if (DISPLAY_VER(dev_priv) >= 10) 572 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 573 574 return val & mask; 575 } 576 577 static const u8 infoframe_type_to_idx[] = { 578 HDMI_PACKET_TYPE_GENERAL_CONTROL, 579 HDMI_PACKET_TYPE_GAMUT_METADATA, 580 DP_SDP_VSC, 581 HDMI_INFOFRAME_TYPE_AVI, 582 HDMI_INFOFRAME_TYPE_SPD, 583 HDMI_INFOFRAME_TYPE_VENDOR, 584 HDMI_INFOFRAME_TYPE_DRM, 585 }; 586 587 u32 intel_hdmi_infoframe_enable(unsigned int type) 588 { 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 592 if (infoframe_type_to_idx[i] == type) 593 return BIT(i); 594 } 595 596 return 0; 597 } 598 599 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 600 const struct intel_crtc_state *crtc_state) 601 { 602 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 603 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 604 u32 val, ret = 0; 605 int i; 606 607 val = dig_port->infoframes_enabled(encoder, crtc_state); 608 609 /* map from hardware bits to dip idx */ 610 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 611 unsigned int type = infoframe_type_to_idx[i]; 612 613 if (HAS_DDI(dev_priv)) { 614 if (val & hsw_infoframe_enable(type)) 615 ret |= BIT(i); 616 } else { 617 if (val & g4x_infoframe_enable(type)) 618 ret |= BIT(i); 619 } 620 } 621 622 return ret; 623 } 624 625 /* 626 * The data we write to the DIP data buffer registers is 1 byte bigger than the 627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 628 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 629 * used for both technologies. 630 * 631 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 632 * DW1: DB3 | DB2 | DB1 | DB0 633 * DW2: DB7 | DB6 | DB5 | DB4 634 * DW3: ... 635 * 636 * (HB is Header Byte, DB is Data Byte) 637 * 638 * The hdmi pack() functions don't know about that hardware specific hole so we 639 * trick them by giving an offset into the buffer and moving back the header 640 * bytes by one. 641 */ 642 static void intel_write_infoframe(struct intel_encoder *encoder, 643 const struct intel_crtc_state *crtc_state, 644 enum hdmi_infoframe_type type, 645 const union hdmi_infoframe *frame) 646 { 647 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 648 u8 buffer[VIDEO_DIP_DATA_SIZE]; 649 ssize_t len; 650 651 if ((crtc_state->infoframes.enable & 652 intel_hdmi_infoframe_enable(type)) == 0) 653 return; 654 655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 656 return; 657 658 /* see comment above for the reason for this offset */ 659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 660 if (drm_WARN_ON(encoder->base.dev, len < 0)) 661 return; 662 663 /* Insert the 'hole' (see big comment above) at position 3 */ 664 memmove(&buffer[0], &buffer[1], 3); 665 buffer[3] = 0; 666 len++; 667 668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 669 } 670 671 void intel_read_infoframe(struct intel_encoder *encoder, 672 const struct intel_crtc_state *crtc_state, 673 enum hdmi_infoframe_type type, 674 union hdmi_infoframe *frame) 675 { 676 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 677 u8 buffer[VIDEO_DIP_DATA_SIZE]; 678 int ret; 679 680 if ((crtc_state->infoframes.enable & 681 intel_hdmi_infoframe_enable(type)) == 0) 682 return; 683 684 dig_port->read_infoframe(encoder, crtc_state, 685 type, buffer, sizeof(buffer)); 686 687 /* Fill the 'hole' (see big comment above) at position 3 */ 688 memmove(&buffer[1], &buffer[0], 3); 689 690 /* see comment above for the reason for this offset */ 691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 692 if (ret) { 693 drm_dbg_kms(encoder->base.dev, 694 "Failed to unpack infoframe type 0x%02x\n", type); 695 return; 696 } 697 698 if (frame->any.type != type) 699 drm_dbg_kms(encoder->base.dev, 700 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 701 frame->any.type, type); 702 } 703 704 static bool 705 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 706 struct intel_crtc_state *crtc_state, 707 struct drm_connector_state *conn_state) 708 { 709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 710 const struct drm_display_mode *adjusted_mode = 711 &crtc_state->hw.adjusted_mode; 712 struct drm_connector *connector = conn_state->connector; 713 int ret; 714 715 if (!crtc_state->has_infoframe) 716 return true; 717 718 crtc_state->infoframes.enable |= 719 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 720 721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, 722 adjusted_mode); 723 if (ret) 724 return false; 725 726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 727 frame->colorspace = HDMI_COLORSPACE_YUV420; 728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 729 frame->colorspace = HDMI_COLORSPACE_YUV444; 730 else 731 frame->colorspace = HDMI_COLORSPACE_RGB; 732 733 drm_hdmi_avi_infoframe_colorspace(frame, conn_state); 734 735 /* nonsense combination */ 736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 738 739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 740 drm_hdmi_avi_infoframe_quant_range(frame, connector, 741 adjusted_mode, 742 crtc_state->limited_color_range ? 743 HDMI_QUANTIZATION_RANGE_LIMITED : 744 HDMI_QUANTIZATION_RANGE_FULL); 745 } else { 746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 748 } 749 750 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 751 752 /* TODO: handle pixel repetition for YCBCR420 outputs */ 753 754 ret = hdmi_avi_infoframe_check(frame); 755 if (drm_WARN_ON(encoder->base.dev, ret)) 756 return false; 757 758 return true; 759 } 760 761 static bool 762 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 763 struct intel_crtc_state *crtc_state, 764 struct drm_connector_state *conn_state) 765 { 766 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 767 int ret; 768 769 if (!crtc_state->has_infoframe) 770 return true; 771 772 crtc_state->infoframes.enable |= 773 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 774 775 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 776 if (drm_WARN_ON(encoder->base.dev, ret)) 777 return false; 778 779 frame->sdi = HDMI_SPD_SDI_PC; 780 781 ret = hdmi_spd_infoframe_check(frame); 782 if (drm_WARN_ON(encoder->base.dev, ret)) 783 return false; 784 785 return true; 786 } 787 788 static bool 789 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 790 struct intel_crtc_state *crtc_state, 791 struct drm_connector_state *conn_state) 792 { 793 struct hdmi_vendor_infoframe *frame = 794 &crtc_state->infoframes.hdmi.vendor.hdmi; 795 const struct drm_display_info *info = 796 &conn_state->connector->display_info; 797 int ret; 798 799 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 800 return true; 801 802 crtc_state->infoframes.enable |= 803 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 804 805 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 806 conn_state->connector, 807 &crtc_state->hw.adjusted_mode); 808 if (drm_WARN_ON(encoder->base.dev, ret)) 809 return false; 810 811 ret = hdmi_vendor_infoframe_check(frame); 812 if (drm_WARN_ON(encoder->base.dev, ret)) 813 return false; 814 815 return true; 816 } 817 818 static bool 819 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 820 struct intel_crtc_state *crtc_state, 821 struct drm_connector_state *conn_state) 822 { 823 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 824 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 825 int ret; 826 827 if (DISPLAY_VER(dev_priv) < 10) 828 return true; 829 830 if (!crtc_state->has_infoframe) 831 return true; 832 833 if (!conn_state->hdr_output_metadata) 834 return true; 835 836 crtc_state->infoframes.enable |= 837 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 838 839 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 840 if (ret < 0) { 841 drm_dbg_kms(&dev_priv->drm, 842 "couldn't set HDR metadata in infoframe\n"); 843 return false; 844 } 845 846 ret = hdmi_drm_infoframe_check(frame); 847 if (drm_WARN_ON(&dev_priv->drm, ret)) 848 return false; 849 850 return true; 851 } 852 853 static void g4x_set_infoframes(struct intel_encoder *encoder, 854 bool enable, 855 const struct intel_crtc_state *crtc_state, 856 const struct drm_connector_state *conn_state) 857 { 858 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 859 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 860 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 861 i915_reg_t reg = VIDEO_DIP_CTL; 862 u32 val = intel_de_read(dev_priv, reg); 863 u32 port = VIDEO_DIP_PORT(encoder->port); 864 865 assert_hdmi_port_disabled(intel_hdmi); 866 867 /* If the registers were not initialized yet, they might be zeroes, 868 * which means we're selecting the AVI DIP and we're setting its 869 * frequency to once. This seems to really confuse the HW and make 870 * things stop working (the register spec says the AVI always needs to 871 * be sent every VSync). So here we avoid writing to the register more 872 * than we need and also explicitly select the AVI DIP and explicitly 873 * set its frequency to every VSync. Avoiding to write it twice seems to 874 * be enough to solve the problem, but being defensive shouldn't hurt us 875 * either. */ 876 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 877 878 if (!enable) { 879 if (!(val & VIDEO_DIP_ENABLE)) 880 return; 881 if (port != (val & VIDEO_DIP_PORT_MASK)) { 882 drm_dbg_kms(&dev_priv->drm, 883 "video DIP still enabled on port %c\n", 884 (val & VIDEO_DIP_PORT_MASK) >> 29); 885 return; 886 } 887 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 888 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 889 intel_de_write(dev_priv, reg, val); 890 intel_de_posting_read(dev_priv, reg); 891 return; 892 } 893 894 if (port != (val & VIDEO_DIP_PORT_MASK)) { 895 if (val & VIDEO_DIP_ENABLE) { 896 drm_dbg_kms(&dev_priv->drm, 897 "video DIP already enabled on port %c\n", 898 (val & VIDEO_DIP_PORT_MASK) >> 29); 899 return; 900 } 901 val &= ~VIDEO_DIP_PORT_MASK; 902 val |= port; 903 } 904 905 val |= VIDEO_DIP_ENABLE; 906 val &= ~(VIDEO_DIP_ENABLE_AVI | 907 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 908 909 intel_de_write(dev_priv, reg, val); 910 intel_de_posting_read(dev_priv, reg); 911 912 intel_write_infoframe(encoder, crtc_state, 913 HDMI_INFOFRAME_TYPE_AVI, 914 &crtc_state->infoframes.avi); 915 intel_write_infoframe(encoder, crtc_state, 916 HDMI_INFOFRAME_TYPE_SPD, 917 &crtc_state->infoframes.spd); 918 intel_write_infoframe(encoder, crtc_state, 919 HDMI_INFOFRAME_TYPE_VENDOR, 920 &crtc_state->infoframes.hdmi); 921 } 922 923 /* 924 * Determine if default_phase=1 can be indicated in the GCP infoframe. 925 * 926 * From HDMI specification 1.4a: 927 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 928 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 929 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 930 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 931 * phase of 0 932 */ 933 static bool gcp_default_phase_possible(int pipe_bpp, 934 const struct drm_display_mode *mode) 935 { 936 unsigned int pixels_per_group; 937 938 switch (pipe_bpp) { 939 case 30: 940 /* 4 pixels in 5 clocks */ 941 pixels_per_group = 4; 942 break; 943 case 36: 944 /* 2 pixels in 3 clocks */ 945 pixels_per_group = 2; 946 break; 947 case 48: 948 /* 1 pixel in 2 clocks */ 949 pixels_per_group = 1; 950 break; 951 default: 952 /* phase information not relevant for 8bpc */ 953 return false; 954 } 955 956 return mode->crtc_hdisplay % pixels_per_group == 0 && 957 mode->crtc_htotal % pixels_per_group == 0 && 958 mode->crtc_hblank_start % pixels_per_group == 0 && 959 mode->crtc_hblank_end % pixels_per_group == 0 && 960 mode->crtc_hsync_start % pixels_per_group == 0 && 961 mode->crtc_hsync_end % pixels_per_group == 0 && 962 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 963 mode->crtc_htotal/2 % pixels_per_group == 0); 964 } 965 966 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 967 const struct intel_crtc_state *crtc_state, 968 const struct drm_connector_state *conn_state) 969 { 970 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 971 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 972 i915_reg_t reg; 973 974 if ((crtc_state->infoframes.enable & 975 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 976 return false; 977 978 if (HAS_DDI(dev_priv)) 979 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 980 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 981 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 982 else if (HAS_PCH_SPLIT(dev_priv)) 983 reg = TVIDEO_DIP_GCP(crtc->pipe); 984 else 985 return false; 986 987 intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); 988 989 return true; 990 } 991 992 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 993 struct intel_crtc_state *crtc_state) 994 { 995 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 996 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 997 i915_reg_t reg; 998 999 if ((crtc_state->infoframes.enable & 1000 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1001 return; 1002 1003 if (HAS_DDI(dev_priv)) 1004 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); 1005 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 1006 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1007 else if (HAS_PCH_SPLIT(dev_priv)) 1008 reg = TVIDEO_DIP_GCP(crtc->pipe); 1009 else 1010 return; 1011 1012 crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); 1013 } 1014 1015 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1016 struct intel_crtc_state *crtc_state, 1017 struct drm_connector_state *conn_state) 1018 { 1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1020 1021 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) 1022 return; 1023 1024 crtc_state->infoframes.enable |= 1025 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1026 1027 /* Indicate color indication for deep color mode */ 1028 if (crtc_state->pipe_bpp > 24) 1029 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1030 1031 /* Enable default_phase whenever the display mode is suitably aligned */ 1032 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1033 &crtc_state->hw.adjusted_mode)) 1034 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1035 } 1036 1037 static void ibx_set_infoframes(struct intel_encoder *encoder, 1038 bool enable, 1039 const struct intel_crtc_state *crtc_state, 1040 const struct drm_connector_state *conn_state) 1041 { 1042 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1043 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1044 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1045 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1046 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1047 u32 val = intel_de_read(dev_priv, reg); 1048 u32 port = VIDEO_DIP_PORT(encoder->port); 1049 1050 assert_hdmi_port_disabled(intel_hdmi); 1051 1052 /* See the big comment in g4x_set_infoframes() */ 1053 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1054 1055 if (!enable) { 1056 if (!(val & VIDEO_DIP_ENABLE)) 1057 return; 1058 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1059 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1060 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1061 intel_de_write(dev_priv, reg, val); 1062 intel_de_posting_read(dev_priv, reg); 1063 return; 1064 } 1065 1066 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1067 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1068 "DIP already enabled on port %c\n", 1069 (val & VIDEO_DIP_PORT_MASK) >> 29); 1070 val &= ~VIDEO_DIP_PORT_MASK; 1071 val |= port; 1072 } 1073 1074 val |= VIDEO_DIP_ENABLE; 1075 val &= ~(VIDEO_DIP_ENABLE_AVI | 1076 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1077 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1078 1079 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1080 val |= VIDEO_DIP_ENABLE_GCP; 1081 1082 intel_de_write(dev_priv, reg, val); 1083 intel_de_posting_read(dev_priv, reg); 1084 1085 intel_write_infoframe(encoder, crtc_state, 1086 HDMI_INFOFRAME_TYPE_AVI, 1087 &crtc_state->infoframes.avi); 1088 intel_write_infoframe(encoder, crtc_state, 1089 HDMI_INFOFRAME_TYPE_SPD, 1090 &crtc_state->infoframes.spd); 1091 intel_write_infoframe(encoder, crtc_state, 1092 HDMI_INFOFRAME_TYPE_VENDOR, 1093 &crtc_state->infoframes.hdmi); 1094 } 1095 1096 static void cpt_set_infoframes(struct intel_encoder *encoder, 1097 bool enable, 1098 const struct intel_crtc_state *crtc_state, 1099 const struct drm_connector_state *conn_state) 1100 { 1101 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1103 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1104 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1105 u32 val = intel_de_read(dev_priv, reg); 1106 1107 assert_hdmi_port_disabled(intel_hdmi); 1108 1109 /* See the big comment in g4x_set_infoframes() */ 1110 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1111 1112 if (!enable) { 1113 if (!(val & VIDEO_DIP_ENABLE)) 1114 return; 1115 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1116 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1117 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1118 intel_de_write(dev_priv, reg, val); 1119 intel_de_posting_read(dev_priv, reg); 1120 return; 1121 } 1122 1123 /* Set both together, unset both together: see the spec. */ 1124 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1125 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1126 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1127 1128 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1129 val |= VIDEO_DIP_ENABLE_GCP; 1130 1131 intel_de_write(dev_priv, reg, val); 1132 intel_de_posting_read(dev_priv, reg); 1133 1134 intel_write_infoframe(encoder, crtc_state, 1135 HDMI_INFOFRAME_TYPE_AVI, 1136 &crtc_state->infoframes.avi); 1137 intel_write_infoframe(encoder, crtc_state, 1138 HDMI_INFOFRAME_TYPE_SPD, 1139 &crtc_state->infoframes.spd); 1140 intel_write_infoframe(encoder, crtc_state, 1141 HDMI_INFOFRAME_TYPE_VENDOR, 1142 &crtc_state->infoframes.hdmi); 1143 } 1144 1145 static void vlv_set_infoframes(struct intel_encoder *encoder, 1146 bool enable, 1147 const struct intel_crtc_state *crtc_state, 1148 const struct drm_connector_state *conn_state) 1149 { 1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1152 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1153 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1154 u32 val = intel_de_read(dev_priv, reg); 1155 u32 port = VIDEO_DIP_PORT(encoder->port); 1156 1157 assert_hdmi_port_disabled(intel_hdmi); 1158 1159 /* See the big comment in g4x_set_infoframes() */ 1160 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1161 1162 if (!enable) { 1163 if (!(val & VIDEO_DIP_ENABLE)) 1164 return; 1165 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1166 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1167 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1168 intel_de_write(dev_priv, reg, val); 1169 intel_de_posting_read(dev_priv, reg); 1170 return; 1171 } 1172 1173 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1174 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, 1175 "DIP already enabled on port %c\n", 1176 (val & VIDEO_DIP_PORT_MASK) >> 29); 1177 val &= ~VIDEO_DIP_PORT_MASK; 1178 val |= port; 1179 } 1180 1181 val |= VIDEO_DIP_ENABLE; 1182 val &= ~(VIDEO_DIP_ENABLE_AVI | 1183 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1184 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1185 1186 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1187 val |= VIDEO_DIP_ENABLE_GCP; 1188 1189 intel_de_write(dev_priv, reg, val); 1190 intel_de_posting_read(dev_priv, reg); 1191 1192 intel_write_infoframe(encoder, crtc_state, 1193 HDMI_INFOFRAME_TYPE_AVI, 1194 &crtc_state->infoframes.avi); 1195 intel_write_infoframe(encoder, crtc_state, 1196 HDMI_INFOFRAME_TYPE_SPD, 1197 &crtc_state->infoframes.spd); 1198 intel_write_infoframe(encoder, crtc_state, 1199 HDMI_INFOFRAME_TYPE_VENDOR, 1200 &crtc_state->infoframes.hdmi); 1201 } 1202 1203 static void hsw_set_infoframes(struct intel_encoder *encoder, 1204 bool enable, 1205 const struct intel_crtc_state *crtc_state, 1206 const struct drm_connector_state *conn_state) 1207 { 1208 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1209 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 1210 u32 val = intel_de_read(dev_priv, reg); 1211 1212 assert_hdmi_transcoder_func_disabled(dev_priv, 1213 crtc_state->cpu_transcoder); 1214 1215 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1216 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1217 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1218 VIDEO_DIP_ENABLE_DRM_GLK); 1219 1220 if (!enable) { 1221 intel_de_write(dev_priv, reg, val); 1222 intel_de_posting_read(dev_priv, reg); 1223 return; 1224 } 1225 1226 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1227 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1228 1229 intel_de_write(dev_priv, reg, val); 1230 intel_de_posting_read(dev_priv, reg); 1231 1232 intel_write_infoframe(encoder, crtc_state, 1233 HDMI_INFOFRAME_TYPE_AVI, 1234 &crtc_state->infoframes.avi); 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_SPD, 1237 &crtc_state->infoframes.spd); 1238 intel_write_infoframe(encoder, crtc_state, 1239 HDMI_INFOFRAME_TYPE_VENDOR, 1240 &crtc_state->infoframes.hdmi); 1241 intel_write_infoframe(encoder, crtc_state, 1242 HDMI_INFOFRAME_TYPE_DRM, 1243 &crtc_state->infoframes.drm); 1244 } 1245 1246 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1247 { 1248 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1249 struct i2c_adapter *adapter = 1250 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 1251 1252 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1253 return; 1254 1255 drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n", 1256 enable ? "Enabling" : "Disabling"); 1257 1258 drm_dp_dual_mode_set_tmds_output(&dev_priv->drm, hdmi->dp_dual_mode.type, adapter, enable); 1259 } 1260 1261 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1262 unsigned int offset, void *buffer, size_t size) 1263 { 1264 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1265 struct intel_hdmi *hdmi = &dig_port->hdmi; 1266 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1267 hdmi->ddc_bus); 1268 int ret; 1269 u8 start = offset & 0xff; 1270 struct i2c_msg msgs[] = { 1271 { 1272 .addr = DRM_HDCP_DDC_ADDR, 1273 .flags = 0, 1274 .len = 1, 1275 .buf = &start, 1276 }, 1277 { 1278 .addr = DRM_HDCP_DDC_ADDR, 1279 .flags = I2C_M_RD, 1280 .len = size, 1281 .buf = buffer 1282 } 1283 }; 1284 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); 1285 if (ret == ARRAY_SIZE(msgs)) 1286 return 0; 1287 return ret >= 0 ? -EIO : ret; 1288 } 1289 1290 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1291 unsigned int offset, void *buffer, size_t size) 1292 { 1293 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1294 struct intel_hdmi *hdmi = &dig_port->hdmi; 1295 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1296 hdmi->ddc_bus); 1297 int ret; 1298 u8 *write_buf; 1299 struct i2c_msg msg; 1300 1301 write_buf = kzalloc(size + 1, GFP_KERNEL); 1302 if (!write_buf) 1303 return -ENOMEM; 1304 1305 write_buf[0] = offset & 0xff; 1306 memcpy(&write_buf[1], buffer, size); 1307 1308 msg.addr = DRM_HDCP_DDC_ADDR; 1309 msg.flags = 0, 1310 msg.len = size + 1, 1311 msg.buf = write_buf; 1312 1313 ret = i2c_transfer(adapter, &msg, 1); 1314 if (ret == 1) 1315 ret = 0; 1316 else if (ret >= 0) 1317 ret = -EIO; 1318 1319 kfree(write_buf); 1320 return ret; 1321 } 1322 1323 static 1324 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1325 u8 *an) 1326 { 1327 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1328 struct intel_hdmi *hdmi = &dig_port->hdmi; 1329 struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, 1330 hdmi->ddc_bus); 1331 int ret; 1332 1333 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1334 DRM_HDCP_AN_LEN); 1335 if (ret) { 1336 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n", 1337 ret); 1338 return ret; 1339 } 1340 1341 ret = intel_gmbus_output_aksv(adapter); 1342 if (ret < 0) { 1343 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret); 1344 return ret; 1345 } 1346 return 0; 1347 } 1348 1349 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1350 u8 *bksv) 1351 { 1352 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1353 1354 int ret; 1355 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1356 DRM_HDCP_KSV_LEN); 1357 if (ret) 1358 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n", 1359 ret); 1360 return ret; 1361 } 1362 1363 static 1364 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1365 u8 *bstatus) 1366 { 1367 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1368 1369 int ret; 1370 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1371 bstatus, DRM_HDCP_BSTATUS_LEN); 1372 if (ret) 1373 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n", 1374 ret); 1375 return ret; 1376 } 1377 1378 static 1379 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1380 bool *repeater_present) 1381 { 1382 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1383 int ret; 1384 u8 val; 1385 1386 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1387 if (ret) { 1388 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1389 ret); 1390 return ret; 1391 } 1392 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1393 return 0; 1394 } 1395 1396 static 1397 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1398 u8 *ri_prime) 1399 { 1400 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1401 1402 int ret; 1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1404 ri_prime, DRM_HDCP_RI_LEN); 1405 if (ret) 1406 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n", 1407 ret); 1408 return ret; 1409 } 1410 1411 static 1412 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1413 bool *ksv_ready) 1414 { 1415 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1416 int ret; 1417 u8 val; 1418 1419 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1420 if (ret) { 1421 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n", 1422 ret); 1423 return ret; 1424 } 1425 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1426 return 0; 1427 } 1428 1429 static 1430 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1431 int num_downstream, u8 *ksv_fifo) 1432 { 1433 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1434 int ret; 1435 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1436 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1437 if (ret) { 1438 drm_dbg_kms(&i915->drm, 1439 "Read ksv fifo over DDC failed (%d)\n", ret); 1440 return ret; 1441 } 1442 return 0; 1443 } 1444 1445 static 1446 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1447 int i, u32 *part) 1448 { 1449 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1450 int ret; 1451 1452 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1453 return -EINVAL; 1454 1455 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1456 part, DRM_HDCP_V_PRIME_PART_LEN); 1457 if (ret) 1458 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n", 1459 i, ret); 1460 return ret; 1461 } 1462 1463 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1464 enum transcoder cpu_transcoder) 1465 { 1466 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1468 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1469 u32 scanline; 1470 int ret; 1471 1472 for (;;) { 1473 scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); 1474 if (scanline > 100 && scanline < 200) 1475 break; 1476 usleep_range(25, 50); 1477 } 1478 1479 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1480 false, TRANS_DDI_HDCP_SIGNALLING); 1481 if (ret) { 1482 drm_err(&dev_priv->drm, 1483 "Disable HDCP signalling failed (%d)\n", ret); 1484 return ret; 1485 } 1486 1487 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1488 true, TRANS_DDI_HDCP_SIGNALLING); 1489 if (ret) { 1490 drm_err(&dev_priv->drm, 1491 "Enable HDCP signalling failed (%d)\n", ret); 1492 return ret; 1493 } 1494 1495 return 0; 1496 } 1497 1498 static 1499 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1500 enum transcoder cpu_transcoder, 1501 bool enable) 1502 { 1503 struct intel_hdmi *hdmi = &dig_port->hdmi; 1504 struct intel_connector *connector = hdmi->attached_connector; 1505 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 1506 int ret; 1507 1508 if (!enable) 1509 usleep_range(6, 60); /* Bspec says >= 6us */ 1510 1511 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1512 cpu_transcoder, enable, 1513 TRANS_DDI_HDCP_SIGNALLING); 1514 if (ret) { 1515 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n", 1516 enable ? "Enable" : "Disable", ret); 1517 return ret; 1518 } 1519 1520 /* 1521 * WA: To fix incorrect positioning of the window of 1522 * opportunity and enc_en signalling in KABYLAKE. 1523 */ 1524 if (IS_KABYLAKE(dev_priv) && enable) 1525 return kbl_repositioning_enc_en_signal(connector, 1526 cpu_transcoder); 1527 1528 return 0; 1529 } 1530 1531 static 1532 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1533 struct intel_connector *connector) 1534 { 1535 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1536 enum port port = dig_port->base.port; 1537 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1538 int ret; 1539 union { 1540 u32 reg; 1541 u8 shim[DRM_HDCP_RI_LEN]; 1542 } ri; 1543 1544 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1545 if (ret) 1546 return false; 1547 1548 intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); 1549 1550 /* Wait for Ri prime match */ 1551 if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & 1552 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == 1553 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { 1554 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n", 1555 intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, 1556 port))); 1557 return false; 1558 } 1559 return true; 1560 } 1561 1562 static 1563 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1564 struct intel_connector *connector) 1565 { 1566 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1567 int retry; 1568 1569 for (retry = 0; retry < 3; retry++) 1570 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1571 return true; 1572 1573 drm_err(&i915->drm, "Link check failed\n"); 1574 return false; 1575 } 1576 1577 struct hdcp2_hdmi_msg_timeout { 1578 u8 msg_id; 1579 u16 timeout; 1580 }; 1581 1582 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1583 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1584 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1585 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1586 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1587 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1588 }; 1589 1590 static 1591 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1592 u8 *rx_status) 1593 { 1594 return intel_hdmi_hdcp_read(dig_port, 1595 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1596 rx_status, 1597 HDCP_2_2_HDMI_RXSTATUS_LEN); 1598 } 1599 1600 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1601 { 1602 int i; 1603 1604 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1605 if (is_paired) 1606 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1607 else 1608 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1609 } 1610 1611 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1612 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1613 return hdcp2_msg_timeout[i].timeout; 1614 } 1615 1616 return -EINVAL; 1617 } 1618 1619 static int 1620 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1621 u8 msg_id, bool *msg_ready, 1622 ssize_t *msg_sz) 1623 { 1624 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1625 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1626 int ret; 1627 1628 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1629 if (ret < 0) { 1630 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n", 1631 ret); 1632 return ret; 1633 } 1634 1635 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1636 rx_status[0]); 1637 1638 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1639 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1640 *msg_sz); 1641 else 1642 *msg_ready = *msg_sz; 1643 1644 return 0; 1645 } 1646 1647 static ssize_t 1648 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1649 u8 msg_id, bool paired) 1650 { 1651 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1652 bool msg_ready = false; 1653 int timeout, ret; 1654 ssize_t msg_sz = 0; 1655 1656 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1657 if (timeout < 0) 1658 return timeout; 1659 1660 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port, 1661 msg_id, &msg_ready, 1662 &msg_sz), 1663 !ret && msg_ready && msg_sz, timeout * 1000, 1664 1000, 5 * 1000); 1665 if (ret) 1666 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n", 1667 msg_id, ret, timeout); 1668 1669 return ret ? ret : msg_sz; 1670 } 1671 1672 static 1673 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port, 1674 void *buf, size_t size) 1675 { 1676 unsigned int offset; 1677 1678 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1679 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1680 } 1681 1682 static 1683 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port, 1684 u8 msg_id, void *buf, size_t size) 1685 { 1686 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1687 struct intel_hdmi *hdmi = &dig_port->hdmi; 1688 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1689 unsigned int offset; 1690 ssize_t ret; 1691 1692 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1693 hdcp->is_paired); 1694 if (ret < 0) 1695 return ret; 1696 1697 /* 1698 * Available msg size should be equal to or lesser than the 1699 * available buffer. 1700 */ 1701 if (ret > size) { 1702 drm_dbg_kms(&i915->drm, 1703 "msg_sz(%zd) is more than exp size(%zu)\n", 1704 ret, size); 1705 return -1; 1706 } 1707 1708 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1709 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1710 if (ret) 1711 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n", 1712 msg_id, ret); 1713 1714 return ret; 1715 } 1716 1717 static 1718 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1719 struct intel_connector *connector) 1720 { 1721 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1722 int ret; 1723 1724 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1725 if (ret) 1726 return ret; 1727 1728 /* 1729 * Re-auth request and Link Integrity Failures are represented by 1730 * same bit. i.e reauth_req. 1731 */ 1732 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1733 ret = HDCP_REAUTH_REQUEST; 1734 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1735 ret = HDCP_TOPOLOGY_CHANGE; 1736 1737 return ret; 1738 } 1739 1740 static 1741 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port, 1742 bool *capable) 1743 { 1744 u8 hdcp2_version; 1745 int ret; 1746 1747 *capable = false; 1748 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1749 &hdcp2_version, sizeof(hdcp2_version)); 1750 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1751 *capable = true; 1752 1753 return ret; 1754 } 1755 1756 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1757 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1758 .read_bksv = intel_hdmi_hdcp_read_bksv, 1759 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1760 .repeater_present = intel_hdmi_hdcp_repeater_present, 1761 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1762 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1763 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1764 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1765 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1766 .check_link = intel_hdmi_hdcp_check_link, 1767 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1768 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1769 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1770 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, 1771 .protocol = HDCP_PROTOCOL_HDMI, 1772 }; 1773 1774 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1775 { 1776 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1777 int max_tmds_clock, vbt_max_tmds_clock; 1778 1779 if (DISPLAY_VER(dev_priv) >= 10) 1780 max_tmds_clock = 594000; 1781 else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) 1782 max_tmds_clock = 300000; 1783 else if (DISPLAY_VER(dev_priv) >= 5) 1784 max_tmds_clock = 225000; 1785 else 1786 max_tmds_clock = 165000; 1787 1788 vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); 1789 if (vbt_max_tmds_clock) 1790 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1791 1792 return max_tmds_clock; 1793 } 1794 1795 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1796 const struct drm_connector_state *conn_state) 1797 { 1798 return hdmi->has_hdmi_sink && 1799 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1800 } 1801 1802 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1803 bool respect_downstream_limits, 1804 bool has_hdmi_sink) 1805 { 1806 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1807 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1808 1809 if (respect_downstream_limits) { 1810 struct intel_connector *connector = hdmi->attached_connector; 1811 const struct drm_display_info *info = &connector->base.display_info; 1812 1813 if (hdmi->dp_dual_mode.max_tmds_clock) 1814 max_tmds_clock = min(max_tmds_clock, 1815 hdmi->dp_dual_mode.max_tmds_clock); 1816 1817 if (info->max_tmds_clock) 1818 max_tmds_clock = min(max_tmds_clock, 1819 info->max_tmds_clock); 1820 else if (!has_hdmi_sink) 1821 max_tmds_clock = min(max_tmds_clock, 165000); 1822 } 1823 1824 return max_tmds_clock; 1825 } 1826 1827 static enum drm_mode_status 1828 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1829 int clock, bool respect_downstream_limits, 1830 bool has_hdmi_sink) 1831 { 1832 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); 1833 1834 if (clock < 25000) 1835 return MODE_CLOCK_LOW; 1836 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1837 has_hdmi_sink)) 1838 return MODE_CLOCK_HIGH; 1839 1840 /* GLK DPLL can't generate 446-480 MHz */ 1841 if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) 1842 return MODE_CLOCK_RANGE; 1843 1844 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1845 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && 1846 clock > 223333 && clock < 240000) 1847 return MODE_CLOCK_RANGE; 1848 1849 /* CHV DPLL can't generate 216-240 MHz */ 1850 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) 1851 return MODE_CLOCK_RANGE; 1852 1853 return MODE_OK; 1854 } 1855 1856 static int intel_hdmi_port_clock(int clock, int bpc) 1857 { 1858 /* 1859 * Need to adjust the port link by: 1860 * 1.5x for 12bpc 1861 * 1.25x for 10bpc 1862 */ 1863 return clock * bpc / 8; 1864 } 1865 1866 static bool intel_hdmi_bpc_possible(struct drm_connector *connector, 1867 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1868 { 1869 struct drm_i915_private *i915 = to_i915(connector->dev); 1870 const struct drm_display_info *info = &connector->display_info; 1871 const struct drm_hdmi_info *hdmi = &info->hdmi; 1872 1873 switch (bpc) { 1874 case 12: 1875 if (HAS_GMCH(i915)) 1876 return false; 1877 1878 if (!has_hdmi_sink) 1879 return false; 1880 1881 if (ycbcr420_output) 1882 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1883 else 1884 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36; 1885 case 10: 1886 if (DISPLAY_VER(i915) < 11) 1887 return false; 1888 1889 if (!has_hdmi_sink) 1890 return false; 1891 1892 if (ycbcr420_output) 1893 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1894 else 1895 return info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30; 1896 case 8: 1897 return true; 1898 default: 1899 MISSING_CASE(bpc); 1900 return false; 1901 } 1902 } 1903 1904 static enum drm_mode_status 1905 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, 1906 bool has_hdmi_sink, bool ycbcr420_output) 1907 { 1908 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1909 enum drm_mode_status status; 1910 1911 if (ycbcr420_output) 1912 clock /= 2; 1913 1914 /* check if we can do 8bpc */ 1915 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 8), 1916 true, has_hdmi_sink); 1917 1918 /* if we can't do 8bpc we may still be able to do 12bpc */ 1919 if (status != MODE_OK && 1920 intel_hdmi_bpc_possible(connector, 12, has_hdmi_sink, ycbcr420_output)) 1921 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 12), 1922 true, has_hdmi_sink); 1923 1924 /* if we can't do 8,12bpc we may still be able to do 10bpc */ 1925 if (status != MODE_OK && 1926 intel_hdmi_bpc_possible(connector, 10, has_hdmi_sink, ycbcr420_output)) 1927 status = hdmi_port_clock_valid(hdmi, intel_hdmi_port_clock(clock, 10), 1928 true, has_hdmi_sink); 1929 1930 return status; 1931 } 1932 1933 static enum drm_mode_status 1934 intel_hdmi_mode_valid(struct drm_connector *connector, 1935 struct drm_display_mode *mode) 1936 { 1937 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 1938 struct drm_device *dev = intel_hdmi_to_dev(hdmi); 1939 struct drm_i915_private *dev_priv = to_i915(dev); 1940 enum drm_mode_status status; 1941 int clock = mode->clock; 1942 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 1943 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); 1944 bool ycbcr_420_only; 1945 1946 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1947 return MODE_NO_DBLESCAN; 1948 1949 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 1950 clock *= 2; 1951 1952 if (clock > max_dotclk) 1953 return MODE_CLOCK_HIGH; 1954 1955 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1956 if (!has_hdmi_sink) 1957 return MODE_CLOCK_LOW; 1958 clock *= 2; 1959 } 1960 1961 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); 1962 1963 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, ycbcr_420_only); 1964 if (status != MODE_OK) { 1965 if (ycbcr_420_only || 1966 !connector->ycbcr_420_allowed || 1967 !drm_mode_is_420_also(&connector->display_info, mode)) 1968 return status; 1969 1970 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, true); 1971 if (status != MODE_OK) 1972 return status; 1973 } 1974 1975 return intel_mode_valid_max_plane_size(dev_priv, mode, false); 1976 } 1977 1978 bool intel_hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 1979 int bpc, bool has_hdmi_sink, bool ycbcr420_output) 1980 { 1981 struct drm_atomic_state *state = crtc_state->uapi.state; 1982 struct drm_connector_state *connector_state; 1983 struct drm_connector *connector; 1984 int i; 1985 1986 if (crtc_state->pipe_bpp < bpc * 3) 1987 return false; 1988 1989 for_each_new_connector_in_state(state, connector, connector_state, i) { 1990 if (connector_state->crtc != crtc_state->uapi.crtc) 1991 continue; 1992 1993 if (!intel_hdmi_bpc_possible(connector, bpc, has_hdmi_sink, ycbcr420_output)) 1994 return false; 1995 } 1996 1997 return true; 1998 } 1999 2000 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, 2001 int bpc) 2002 { 2003 struct drm_i915_private *dev_priv = 2004 to_i915(crtc_state->uapi.crtc->dev); 2005 const struct drm_display_mode *adjusted_mode = 2006 &crtc_state->hw.adjusted_mode; 2007 2008 /* 2009 * HDMI deep color affects the clocks, so it's only possible 2010 * when not cloning with other encoder types. 2011 */ 2012 if (crtc_state->output_types != BIT(INTEL_OUTPUT_HDMI)) 2013 return false; 2014 2015 /* Display Wa_1405510057:icl,ehl */ 2016 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && 2017 bpc == 10 && DISPLAY_VER(dev_priv) == 11 && 2018 (adjusted_mode->crtc_hblank_end - 2019 adjusted_mode->crtc_hblank_start) % 8 == 2) 2020 return false; 2021 2022 return intel_hdmi_deep_color_possible(crtc_state, bpc, 2023 crtc_state->has_hdmi_sink, 2024 crtc_state->output_format == 2025 INTEL_OUTPUT_FORMAT_YCBCR420); 2026 } 2027 2028 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2029 struct intel_crtc_state *crtc_state, 2030 int clock) 2031 { 2032 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2033 int bpc; 2034 2035 for (bpc = 12; bpc >= 10; bpc -= 2) { 2036 if (hdmi_deep_color_possible(crtc_state, bpc) && 2037 hdmi_port_clock_valid(intel_hdmi, 2038 intel_hdmi_port_clock(clock, bpc), 2039 true, crtc_state->has_hdmi_sink) == MODE_OK) 2040 return bpc; 2041 } 2042 2043 return 8; 2044 } 2045 2046 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2047 struct intel_crtc_state *crtc_state) 2048 { 2049 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 2050 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2051 const struct drm_display_mode *adjusted_mode = 2052 &crtc_state->hw.adjusted_mode; 2053 int bpc, clock = adjusted_mode->crtc_clock; 2054 2055 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2056 clock *= 2; 2057 2058 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 2059 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2060 clock /= 2; 2061 2062 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); 2063 2064 crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); 2065 2066 /* 2067 * pipe_bpp could already be below 8bpc due to 2068 * FDI bandwidth constraints. We shouldn't bump it 2069 * back up to 8bpc in that case. 2070 */ 2071 if (crtc_state->pipe_bpp > bpc * 3) 2072 crtc_state->pipe_bpp = bpc * 3; 2073 2074 drm_dbg_kms(&i915->drm, 2075 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2076 bpc, crtc_state->pipe_bpp); 2077 2078 if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, 2079 false, crtc_state->has_hdmi_sink) != MODE_OK) { 2080 drm_dbg_kms(&i915->drm, 2081 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2082 crtc_state->port_clock); 2083 return -EINVAL; 2084 } 2085 2086 return 0; 2087 } 2088 2089 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2090 const struct drm_connector_state *conn_state) 2091 { 2092 const struct intel_digital_connector_state *intel_conn_state = 2093 to_intel_digital_connector_state(conn_state); 2094 const struct drm_display_mode *adjusted_mode = 2095 &crtc_state->hw.adjusted_mode; 2096 2097 /* 2098 * Our YCbCr output is always limited range. 2099 * crtc_state->limited_color_range only applies to RGB, 2100 * and it must never be set for YCbCr or we risk setting 2101 * some conflicting bits in PIPECONF which will mess up 2102 * the colors on the monitor. 2103 */ 2104 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2105 return false; 2106 2107 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2108 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2109 return crtc_state->has_hdmi_sink && 2110 drm_default_rgb_quant_range(adjusted_mode) == 2111 HDMI_QUANTIZATION_RANGE_LIMITED; 2112 } else { 2113 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2114 } 2115 } 2116 2117 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2118 const struct intel_crtc_state *crtc_state, 2119 const struct drm_connector_state *conn_state) 2120 { 2121 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2122 const struct intel_digital_connector_state *intel_conn_state = 2123 to_intel_digital_connector_state(conn_state); 2124 2125 if (!crtc_state->has_hdmi_sink) 2126 return false; 2127 2128 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2129 return intel_hdmi->has_audio; 2130 else 2131 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2132 } 2133 2134 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2135 struct intel_crtc_state *crtc_state, 2136 const struct drm_connector_state *conn_state) 2137 { 2138 struct drm_connector *connector = conn_state->connector; 2139 struct drm_i915_private *i915 = to_i915(connector->dev); 2140 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2141 int ret; 2142 bool ycbcr_420_only; 2143 2144 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, adjusted_mode); 2145 if (connector->ycbcr_420_allowed && ycbcr_420_only) { 2146 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2147 } else { 2148 if (!connector->ycbcr_420_allowed && ycbcr_420_only) 2149 drm_dbg_kms(&i915->drm, 2150 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2151 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; 2152 } 2153 2154 ret = intel_hdmi_compute_clock(encoder, crtc_state); 2155 if (ret) { 2156 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420 && 2157 connector->ycbcr_420_allowed && 2158 drm_mode_is_420_also(&connector->display_info, adjusted_mode)) { 2159 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2160 ret = intel_hdmi_compute_clock(encoder, crtc_state); 2161 } 2162 } 2163 2164 return ret; 2165 } 2166 2167 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2168 struct intel_crtc_state *pipe_config, 2169 struct drm_connector_state *conn_state) 2170 { 2171 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2172 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2173 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2174 struct drm_connector *connector = conn_state->connector; 2175 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; 2176 int ret; 2177 2178 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2179 return -EINVAL; 2180 2181 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2182 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, 2183 conn_state); 2184 2185 if (pipe_config->has_hdmi_sink) 2186 pipe_config->has_infoframe = true; 2187 2188 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2189 pipe_config->pixel_multiplier = 2; 2190 2191 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) 2192 pipe_config->has_pch_encoder = true; 2193 2194 pipe_config->has_audio = 2195 intel_hdmi_has_audio(encoder, pipe_config, conn_state); 2196 2197 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state); 2198 if (ret) 2199 return ret; 2200 2201 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 2202 ret = intel_pch_panel_fitting(pipe_config, conn_state); 2203 if (ret) 2204 return ret; 2205 } 2206 2207 pipe_config->limited_color_range = 2208 intel_hdmi_limited_color_range(pipe_config, conn_state); 2209 2210 if (conn_state->picture_aspect_ratio) 2211 adjusted_mode->picture_aspect_ratio = 2212 conn_state->picture_aspect_ratio; 2213 2214 pipe_config->lane_count = 4; 2215 2216 if (scdc->scrambling.supported && DISPLAY_VER(dev_priv) >= 10) { 2217 if (scdc->scrambling.low_rates) 2218 pipe_config->hdmi_scrambling = true; 2219 2220 if (pipe_config->port_clock > 340000) { 2221 pipe_config->hdmi_scrambling = true; 2222 pipe_config->hdmi_high_tmds_clock_ratio = true; 2223 } 2224 } 2225 2226 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2227 conn_state); 2228 2229 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2230 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n"); 2231 return -EINVAL; 2232 } 2233 2234 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2235 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n"); 2236 return -EINVAL; 2237 } 2238 2239 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2240 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n"); 2241 return -EINVAL; 2242 } 2243 2244 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2245 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n"); 2246 return -EINVAL; 2247 } 2248 2249 return 0; 2250 } 2251 2252 static void 2253 intel_hdmi_unset_edid(struct drm_connector *connector) 2254 { 2255 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2256 2257 intel_hdmi->has_hdmi_sink = false; 2258 intel_hdmi->has_audio = false; 2259 2260 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2261 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2262 2263 kfree(to_intel_connector(connector)->detect_edid); 2264 to_intel_connector(connector)->detect_edid = NULL; 2265 } 2266 2267 static void 2268 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) 2269 { 2270 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2271 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2272 enum port port = hdmi_to_dig_port(hdmi)->base.port; 2273 struct i2c_adapter *adapter = 2274 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); 2275 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(&dev_priv->drm, adapter); 2276 2277 /* 2278 * Type 1 DVI adaptors are not required to implement any 2279 * registers, so we can't always detect their presence. 2280 * Ideally we should be able to check the state of the 2281 * CONFIG1 pin, but no such luck on our hardware. 2282 * 2283 * The only method left to us is to check the VBT to see 2284 * if the port is a dual mode capable DP port. But let's 2285 * only do that when we sucesfully read the EDID, to avoid 2286 * confusing log messages about DP dual mode adaptors when 2287 * there's nothing connected to the port. 2288 */ 2289 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2290 /* An overridden EDID imply that we want this port for testing. 2291 * Make sure not to set limits for that port. 2292 */ 2293 if (has_edid && !connector->override_edid && 2294 intel_bios_is_port_dp_dual_mode(dev_priv, port)) { 2295 drm_dbg_kms(&dev_priv->drm, 2296 "Assuming DP dual mode adaptor presence based on VBT\n"); 2297 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2298 } else { 2299 type = DRM_DP_DUAL_MODE_NONE; 2300 } 2301 } 2302 2303 if (type == DRM_DP_DUAL_MODE_NONE) 2304 return; 2305 2306 hdmi->dp_dual_mode.type = type; 2307 hdmi->dp_dual_mode.max_tmds_clock = 2308 drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, adapter); 2309 2310 drm_dbg_kms(&dev_priv->drm, 2311 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2312 drm_dp_get_dual_mode_type_name(type), 2313 hdmi->dp_dual_mode.max_tmds_clock); 2314 } 2315 2316 static bool 2317 intel_hdmi_set_edid(struct drm_connector *connector) 2318 { 2319 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2320 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2321 intel_wakeref_t wakeref; 2322 struct edid *edid; 2323 bool connected = false; 2324 struct i2c_adapter *i2c; 2325 2326 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2327 2328 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2329 2330 edid = drm_get_edid(connector, i2c); 2331 2332 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 2333 drm_dbg_kms(&dev_priv->drm, 2334 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2335 intel_gmbus_force_bit(i2c, true); 2336 edid = drm_get_edid(connector, i2c); 2337 intel_gmbus_force_bit(i2c, false); 2338 } 2339 2340 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); 2341 2342 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2343 2344 to_intel_connector(connector)->detect_edid = edid; 2345 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 2346 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 2347 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 2348 2349 connected = true; 2350 } 2351 2352 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); 2353 2354 return connected; 2355 } 2356 2357 static enum drm_connector_status 2358 intel_hdmi_detect(struct drm_connector *connector, bool force) 2359 { 2360 enum drm_connector_status status = connector_status_disconnected; 2361 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2362 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2363 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2364 intel_wakeref_t wakeref; 2365 2366 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 2367 connector->base.id, connector->name); 2368 2369 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 2370 return connector_status_disconnected; 2371 2372 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 2373 2374 if (DISPLAY_VER(dev_priv) >= 11 && 2375 !intel_digital_port_connected(encoder)) 2376 goto out; 2377 2378 intel_hdmi_unset_edid(connector); 2379 2380 if (intel_hdmi_set_edid(connector)) 2381 status = connector_status_connected; 2382 2383 out: 2384 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 2385 2386 if (status != connector_status_connected) 2387 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2388 2389 /* 2390 * Make sure the refs for power wells enabled during detect are 2391 * dropped to avoid a new detect cycle triggered by HPD polling. 2392 */ 2393 intel_display_power_flush_work(dev_priv); 2394 2395 return status; 2396 } 2397 2398 static void 2399 intel_hdmi_force(struct drm_connector *connector) 2400 { 2401 struct drm_i915_private *i915 = to_i915(connector->dev); 2402 2403 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n", 2404 connector->base.id, connector->name); 2405 2406 intel_hdmi_unset_edid(connector); 2407 2408 if (connector->status != connector_status_connected) 2409 return; 2410 2411 intel_hdmi_set_edid(connector); 2412 } 2413 2414 static int intel_hdmi_get_modes(struct drm_connector *connector) 2415 { 2416 struct edid *edid; 2417 2418 edid = to_intel_connector(connector)->detect_edid; 2419 if (edid == NULL) 2420 return 0; 2421 2422 return intel_connector_update_modes(connector, edid); 2423 } 2424 2425 static struct i2c_adapter * 2426 intel_hdmi_get_i2c_adapter(struct drm_connector *connector) 2427 { 2428 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2429 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); 2430 2431 return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2432 } 2433 2434 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) 2435 { 2436 struct drm_i915_private *i915 = to_i915(connector->dev); 2437 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2438 struct kobject *i2c_kobj = &adapter->dev.kobj; 2439 struct kobject *connector_kobj = &connector->kdev->kobj; 2440 int ret; 2441 2442 ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); 2443 if (ret) 2444 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret); 2445 } 2446 2447 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) 2448 { 2449 struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); 2450 struct kobject *i2c_kobj = &adapter->dev.kobj; 2451 struct kobject *connector_kobj = &connector->kdev->kobj; 2452 2453 sysfs_remove_link(connector_kobj, i2c_kobj->name); 2454 } 2455 2456 static int 2457 intel_hdmi_connector_register(struct drm_connector *connector) 2458 { 2459 int ret; 2460 2461 ret = intel_connector_register(connector); 2462 if (ret) 2463 return ret; 2464 2465 intel_hdmi_create_i2c_symlink(connector); 2466 2467 return ret; 2468 } 2469 2470 static void intel_hdmi_connector_unregister(struct drm_connector *connector) 2471 { 2472 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; 2473 2474 cec_notifier_conn_unregister(n); 2475 2476 intel_hdmi_remove_i2c_symlink(connector); 2477 intel_connector_unregister(connector); 2478 } 2479 2480 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2481 .detect = intel_hdmi_detect, 2482 .force = intel_hdmi_force, 2483 .fill_modes = drm_helper_probe_single_connector_modes, 2484 .atomic_get_property = intel_digital_connector_atomic_get_property, 2485 .atomic_set_property = intel_digital_connector_atomic_set_property, 2486 .late_register = intel_hdmi_connector_register, 2487 .early_unregister = intel_hdmi_connector_unregister, 2488 .destroy = intel_connector_destroy, 2489 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2490 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2491 }; 2492 2493 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2494 .get_modes = intel_hdmi_get_modes, 2495 .mode_valid = intel_hdmi_mode_valid, 2496 .atomic_check = intel_digital_connector_atomic_check, 2497 }; 2498 2499 static void 2500 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 2501 { 2502 struct drm_i915_private *dev_priv = to_i915(connector->dev); 2503 2504 intel_attach_force_audio_property(connector); 2505 intel_attach_broadcast_rgb_property(connector); 2506 intel_attach_aspect_ratio_property(connector); 2507 2508 intel_attach_hdmi_colorspace_property(connector); 2509 drm_connector_attach_content_type_property(connector); 2510 2511 if (DISPLAY_VER(dev_priv) >= 10) 2512 drm_connector_attach_hdr_output_metadata_property(connector); 2513 2514 if (!HAS_GMCH(dev_priv)) 2515 drm_connector_attach_max_bpc_property(connector, 8, 12); 2516 } 2517 2518 /* 2519 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2520 * @encoder: intel_encoder 2521 * @connector: drm_connector 2522 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2523 * or reset the high tmds clock ratio for scrambling 2524 * @scrambling: bool to Indicate if the function needs to set or reset 2525 * sink scrambling 2526 * 2527 * This function handles scrambling on HDMI 2.0 capable sinks. 2528 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2529 * it enables scrambling. This should be called before enabling the HDMI 2530 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2531 * detect a scrambled clock within 100 ms. 2532 * 2533 * Returns: 2534 * True on success, false on failure. 2535 */ 2536 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2537 struct drm_connector *connector, 2538 bool high_tmds_clock_ratio, 2539 bool scrambling) 2540 { 2541 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2542 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2543 struct drm_scrambling *sink_scrambling = 2544 &connector->display_info.hdmi.scdc.scrambling; 2545 struct i2c_adapter *adapter = 2546 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2547 2548 if (!sink_scrambling->supported) 2549 return true; 2550 2551 drm_dbg_kms(&dev_priv->drm, 2552 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2553 connector->base.id, connector->name, 2554 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); 2555 2556 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2557 return drm_scdc_set_high_tmds_clock_ratio(adapter, 2558 high_tmds_clock_ratio) && 2559 drm_scdc_set_scrambling(adapter, scrambling); 2560 } 2561 2562 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2563 { 2564 u8 ddc_pin; 2565 2566 switch (port) { 2567 case PORT_B: 2568 ddc_pin = GMBUS_PIN_DPB; 2569 break; 2570 case PORT_C: 2571 ddc_pin = GMBUS_PIN_DPC; 2572 break; 2573 case PORT_D: 2574 ddc_pin = GMBUS_PIN_DPD_CHV; 2575 break; 2576 default: 2577 MISSING_CASE(port); 2578 ddc_pin = GMBUS_PIN_DPB; 2579 break; 2580 } 2581 return ddc_pin; 2582 } 2583 2584 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2585 { 2586 u8 ddc_pin; 2587 2588 switch (port) { 2589 case PORT_B: 2590 ddc_pin = GMBUS_PIN_1_BXT; 2591 break; 2592 case PORT_C: 2593 ddc_pin = GMBUS_PIN_2_BXT; 2594 break; 2595 default: 2596 MISSING_CASE(port); 2597 ddc_pin = GMBUS_PIN_1_BXT; 2598 break; 2599 } 2600 return ddc_pin; 2601 } 2602 2603 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2604 enum port port) 2605 { 2606 u8 ddc_pin; 2607 2608 switch (port) { 2609 case PORT_B: 2610 ddc_pin = GMBUS_PIN_1_BXT; 2611 break; 2612 case PORT_C: 2613 ddc_pin = GMBUS_PIN_2_BXT; 2614 break; 2615 case PORT_D: 2616 ddc_pin = GMBUS_PIN_4_CNP; 2617 break; 2618 case PORT_F: 2619 ddc_pin = GMBUS_PIN_3_BXT; 2620 break; 2621 default: 2622 MISSING_CASE(port); 2623 ddc_pin = GMBUS_PIN_1_BXT; 2624 break; 2625 } 2626 return ddc_pin; 2627 } 2628 2629 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2630 { 2631 enum phy phy = intel_port_to_phy(dev_priv, port); 2632 2633 if (intel_phy_is_combo(dev_priv, phy)) 2634 return GMBUS_PIN_1_BXT + port; 2635 else if (intel_phy_is_tc(dev_priv, phy)) 2636 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); 2637 2638 drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); 2639 return GMBUS_PIN_2_BXT; 2640 } 2641 2642 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2643 { 2644 enum phy phy = intel_port_to_phy(dev_priv, port); 2645 u8 ddc_pin; 2646 2647 switch (phy) { 2648 case PHY_A: 2649 ddc_pin = GMBUS_PIN_1_BXT; 2650 break; 2651 case PHY_B: 2652 ddc_pin = GMBUS_PIN_2_BXT; 2653 break; 2654 case PHY_C: 2655 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2656 break; 2657 default: 2658 MISSING_CASE(phy); 2659 ddc_pin = GMBUS_PIN_1_BXT; 2660 break; 2661 } 2662 return ddc_pin; 2663 } 2664 2665 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2666 { 2667 enum phy phy = intel_port_to_phy(dev_priv, port); 2668 2669 WARN_ON(port == PORT_C); 2670 2671 /* 2672 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2673 * final two outputs use type-c pins, even though they're actually 2674 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2675 * all outputs. 2676 */ 2677 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C) 2678 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2679 2680 return GMBUS_PIN_1_BXT + phy; 2681 } 2682 2683 static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port) 2684 { 2685 enum phy phy = intel_port_to_phy(i915, port); 2686 2687 drm_WARN_ON(&i915->drm, port == PORT_A); 2688 2689 /* 2690 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2691 * final two outputs use type-c pins, even though they're actually 2692 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2693 * all outputs. 2694 */ 2695 if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C) 2696 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2697 2698 return GMBUS_PIN_1_BXT + phy; 2699 } 2700 2701 static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2702 { 2703 return intel_port_to_phy(dev_priv, port) + 1; 2704 } 2705 2706 static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 2707 { 2708 enum phy phy = intel_port_to_phy(dev_priv, port); 2709 2710 WARN_ON(port == PORT_B || port == PORT_C); 2711 2712 /* 2713 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2714 * except first combo output. 2715 */ 2716 if (phy == PHY_A) 2717 return GMBUS_PIN_1_BXT; 2718 2719 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2720 } 2721 2722 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, 2723 enum port port) 2724 { 2725 u8 ddc_pin; 2726 2727 switch (port) { 2728 case PORT_B: 2729 ddc_pin = GMBUS_PIN_DPB; 2730 break; 2731 case PORT_C: 2732 ddc_pin = GMBUS_PIN_DPC; 2733 break; 2734 case PORT_D: 2735 ddc_pin = GMBUS_PIN_DPD; 2736 break; 2737 default: 2738 MISSING_CASE(port); 2739 ddc_pin = GMBUS_PIN_DPB; 2740 break; 2741 } 2742 return ddc_pin; 2743 } 2744 2745 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2746 { 2747 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2748 enum port port = encoder->port; 2749 u8 ddc_pin; 2750 2751 ddc_pin = intel_bios_alternate_ddc_pin(encoder); 2752 if (ddc_pin) { 2753 drm_dbg_kms(&dev_priv->drm, 2754 "Using DDC pin 0x%x for port %c (VBT)\n", 2755 ddc_pin, port_name(port)); 2756 return ddc_pin; 2757 } 2758 2759 if (IS_ALDERLAKE_S(dev_priv)) 2760 ddc_pin = adls_port_to_ddc_pin(dev_priv, port); 2761 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 2762 ddc_pin = dg1_port_to_ddc_pin(dev_priv, port); 2763 else if (IS_ROCKETLAKE(dev_priv)) 2764 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port); 2765 else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv)) 2766 ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port); 2767 else if (HAS_PCH_MCC(dev_priv)) 2768 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); 2769 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 2770 ddc_pin = icl_port_to_ddc_pin(dev_priv, port); 2771 else if (HAS_PCH_CNP(dev_priv)) 2772 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); 2773 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 2774 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); 2775 else if (IS_CHERRYVIEW(dev_priv)) 2776 ddc_pin = chv_port_to_ddc_pin(dev_priv, port); 2777 else 2778 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); 2779 2780 drm_dbg_kms(&dev_priv->drm, 2781 "Using DDC pin 0x%x for port %c (platform default)\n", 2782 ddc_pin, port_name(port)); 2783 2784 return ddc_pin; 2785 } 2786 2787 void intel_infoframe_init(struct intel_digital_port *dig_port) 2788 { 2789 struct drm_i915_private *dev_priv = 2790 to_i915(dig_port->base.base.dev); 2791 2792 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 2793 dig_port->write_infoframe = vlv_write_infoframe; 2794 dig_port->read_infoframe = vlv_read_infoframe; 2795 dig_port->set_infoframes = vlv_set_infoframes; 2796 dig_port->infoframes_enabled = vlv_infoframes_enabled; 2797 } else if (IS_G4X(dev_priv)) { 2798 dig_port->write_infoframe = g4x_write_infoframe; 2799 dig_port->read_infoframe = g4x_read_infoframe; 2800 dig_port->set_infoframes = g4x_set_infoframes; 2801 dig_port->infoframes_enabled = g4x_infoframes_enabled; 2802 } else if (HAS_DDI(dev_priv)) { 2803 if (intel_bios_is_lspcon_present(dev_priv, dig_port->base.port)) { 2804 dig_port->write_infoframe = lspcon_write_infoframe; 2805 dig_port->read_infoframe = lspcon_read_infoframe; 2806 dig_port->set_infoframes = lspcon_set_infoframes; 2807 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 2808 } else { 2809 dig_port->write_infoframe = hsw_write_infoframe; 2810 dig_port->read_infoframe = hsw_read_infoframe; 2811 dig_port->set_infoframes = hsw_set_infoframes; 2812 dig_port->infoframes_enabled = hsw_infoframes_enabled; 2813 } 2814 } else if (HAS_PCH_IBX(dev_priv)) { 2815 dig_port->write_infoframe = ibx_write_infoframe; 2816 dig_port->read_infoframe = ibx_read_infoframe; 2817 dig_port->set_infoframes = ibx_set_infoframes; 2818 dig_port->infoframes_enabled = ibx_infoframes_enabled; 2819 } else { 2820 dig_port->write_infoframe = cpt_write_infoframe; 2821 dig_port->read_infoframe = cpt_read_infoframe; 2822 dig_port->set_infoframes = cpt_set_infoframes; 2823 dig_port->infoframes_enabled = cpt_infoframes_enabled; 2824 } 2825 } 2826 2827 void intel_hdmi_init_connector(struct intel_digital_port *dig_port, 2828 struct intel_connector *intel_connector) 2829 { 2830 struct drm_connector *connector = &intel_connector->base; 2831 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 2832 struct intel_encoder *intel_encoder = &dig_port->base; 2833 struct drm_device *dev = intel_encoder->base.dev; 2834 struct drm_i915_private *dev_priv = to_i915(dev); 2835 struct i2c_adapter *ddc; 2836 enum port port = intel_encoder->port; 2837 struct cec_connector_info conn_info; 2838 2839 drm_dbg_kms(&dev_priv->drm, 2840 "Adding HDMI connector on [ENCODER:%d:%s]\n", 2841 intel_encoder->base.base.id, intel_encoder->base.name); 2842 2843 if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) 2844 return; 2845 2846 if (drm_WARN(dev, dig_port->max_lanes < 4, 2847 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 2848 dig_port->max_lanes, intel_encoder->base.base.id, 2849 intel_encoder->base.name)) 2850 return; 2851 2852 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); 2853 ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); 2854 2855 drm_connector_init_with_ddc(dev, connector, 2856 &intel_hdmi_connector_funcs, 2857 DRM_MODE_CONNECTOR_HDMIA, 2858 ddc); 2859 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 2860 2861 connector->interlace_allowed = 1; 2862 connector->doublescan_allowed = 0; 2863 connector->stereo_allowed = 1; 2864 2865 if (DISPLAY_VER(dev_priv) >= 10) 2866 connector->ycbcr_420_allowed = true; 2867 2868 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 2869 2870 if (HAS_DDI(dev_priv)) 2871 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2872 else 2873 intel_connector->get_hw_state = intel_connector_get_hw_state; 2874 2875 intel_hdmi_add_properties(intel_hdmi, connector); 2876 2877 intel_connector_attach_encoder(intel_connector, intel_encoder); 2878 intel_hdmi->attached_connector = intel_connector; 2879 2880 if (is_hdcp_supported(dev_priv, port)) { 2881 int ret = intel_hdcp_init(intel_connector, dig_port, 2882 &intel_hdmi_hdcp_shim); 2883 if (ret) 2884 drm_dbg_kms(&dev_priv->drm, 2885 "HDCP init failed, skipping.\n"); 2886 } 2887 2888 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2889 * 0xd. Failure to do so will result in spurious interrupts being 2890 * generated on the port when a cable is not attached. 2891 */ 2892 if (IS_G45(dev_priv)) { 2893 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 2894 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 2895 (temp & ~0xf) | 0xd); 2896 } 2897 2898 cec_fill_conn_info_from_drm(&conn_info, connector); 2899 2900 intel_hdmi->cec_notifier = 2901 cec_notifier_conn_register(dev->dev, port_identifier(port), 2902 &conn_info); 2903 if (!intel_hdmi->cec_notifier) 2904 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n"); 2905 } 2906 2907 /* 2908 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 2909 * @vactive: Vactive of a display mode 2910 * 2911 * @return: appropriate dsc slice height for a given mode. 2912 */ 2913 int intel_hdmi_dsc_get_slice_height(int vactive) 2914 { 2915 int slice_height; 2916 2917 /* 2918 * Slice Height determination : HDMI2.1 Section 7.7.5.2 2919 * Select smallest slice height >=96, that results in a valid PPS and 2920 * requires minimum padding lines required for final slice. 2921 * 2922 * Assumption : Vactive is even. 2923 */ 2924 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 2925 if (vactive % slice_height == 0) 2926 return slice_height; 2927 2928 return 0; 2929 } 2930 2931 /* 2932 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 2933 * and dsc decoder capabilities 2934 * 2935 * @crtc_state: intel crtc_state 2936 * @src_max_slices: maximum slices supported by the DSC encoder 2937 * @src_max_slice_width: maximum slice width supported by DSC encoder 2938 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 2939 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 2940 * 2941 * @return: num of dsc slices that can be supported by the dsc encoder 2942 * and decoder. 2943 */ 2944 int 2945 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 2946 int src_max_slices, int src_max_slice_width, 2947 int hdmi_max_slices, int hdmi_throughput) 2948 { 2949 /* Pixel rates in KPixels/sec */ 2950 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 2951 /* 2952 * Rates at which the source and sink are required to process pixels in each 2953 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 2954 */ 2955 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 2956 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 2957 2958 /* Spec limits the slice width to 2720 pixels */ 2959 #define MAX_HDMI_SLICE_WIDTH 2720 2960 int kslice_adjust; 2961 int adjusted_clk_khz; 2962 int min_slices; 2963 int target_slices; 2964 int max_throughput; /* max clock freq. in khz per slice */ 2965 int max_slice_width; 2966 int slice_width; 2967 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 2968 2969 if (!hdmi_throughput) 2970 return 0; 2971 2972 /* 2973 * Slice Width determination : HDMI2.1 Section 7.7.5.1 2974 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 2975 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 2976 * dividing adjusted clock value by 10. 2977 */ 2978 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 2979 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 2980 kslice_adjust = 10; 2981 else 2982 kslice_adjust = 5; 2983 2984 /* 2985 * As per spec, the rate at which the source and the sink process 2986 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 2987 * This depends upon the pixel clock rate and output formats 2988 * (kslice adjust). 2989 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 2990 * at max 340MHz, otherwise they can be processed at max 400MHz. 2991 */ 2992 2993 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 2994 2995 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 2996 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 2997 else 2998 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 2999 3000 /* 3001 * Taking into account the sink's capability for maximum 3002 * clock per slice (in MHz) as read from HF-VSDB. 3003 */ 3004 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3005 3006 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3007 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3008 3009 /* 3010 * Keep on increasing the num of slices/line, starting from min_slices 3011 * per line till we get such a number, for which the slice_width is 3012 * just less than max_slice_width. The slices/line selected should be 3013 * less than or equal to the max horizontal slices that the combination 3014 * of PCON encoder and HDMI decoder can support. 3015 */ 3016 slice_width = max_slice_width; 3017 3018 do { 3019 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3020 target_slices = 1; 3021 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3022 target_slices = 2; 3023 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3024 target_slices = 4; 3025 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3026 target_slices = 8; 3027 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3028 target_slices = 12; 3029 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3030 target_slices = 16; 3031 else 3032 return 0; 3033 3034 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3035 if (slice_width >= max_slice_width) 3036 min_slices = target_slices + 1; 3037 } while (slice_width >= max_slice_width); 3038 3039 return target_slices; 3040 } 3041 3042 /* 3043 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3044 * source and sink capabilities. 3045 * 3046 * @src_fraction_bpp: fractional bpp supported by the source 3047 * @slice_width: dsc slice width supported by the source and sink 3048 * @num_slices: num of slices supported by the source and sink 3049 * @output_format: video output format 3050 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3051 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3052 * 3053 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3054 */ 3055 int 3056 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3057 int output_format, bool hdmi_all_bpp, 3058 int hdmi_max_chunk_bytes) 3059 { 3060 int max_dsc_bpp, min_dsc_bpp; 3061 int target_bytes; 3062 bool bpp_found = false; 3063 int bpp_decrement_x16; 3064 int bpp_target; 3065 int bpp_target_x16; 3066 3067 /* 3068 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3069 * Start with the max bpp and keep on decrementing with 3070 * fractional bpp, if supported by PCON DSC encoder 3071 * 3072 * for each bpp we check if no of bytes can be supported by HDMI sink 3073 */ 3074 3075 /* Assuming: bpc as 8*/ 3076 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3077 min_dsc_bpp = 6; 3078 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3079 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3080 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3081 min_dsc_bpp = 8; 3082 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3083 } else { 3084 /* Assuming 4:2:2 encoding */ 3085 min_dsc_bpp = 7; 3086 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3087 } 3088 3089 /* 3090 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3091 * Section 7.7.34 : Source shall not enable compressed Video 3092 * Transport with bpp_target settings above 12 bpp unless 3093 * DSC_all_bpp is set to 1. 3094 */ 3095 if (!hdmi_all_bpp) 3096 max_dsc_bpp = min(max_dsc_bpp, 12); 3097 3098 /* 3099 * The Sink has a limit of compressed data in bytes for a scanline, 3100 * as described in max_chunk_bytes field in HFVSDB block of edid. 3101 * The no. of bytes depend on the target bits per pixel that the 3102 * source configures. So we start with the max_bpp and calculate 3103 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3104 * till we get the target_chunk_bytes just less than what the sink's 3105 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3106 * 3107 * The decrement is according to the fractional support from PCON DSC 3108 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3109 * 3110 * bpp_target_x16 = bpp_target * 16 3111 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3112 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3113 */ 3114 3115 bpp_target = max_dsc_bpp; 3116 3117 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3118 if (!src_fractional_bpp) 3119 src_fractional_bpp = 1; 3120 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3121 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3122 3123 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3124 int bpp; 3125 3126 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3127 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3128 if (target_bytes <= hdmi_max_chunk_bytes) { 3129 bpp_found = true; 3130 break; 3131 } 3132 bpp_target_x16 -= bpp_decrement_x16; 3133 } 3134 if (bpp_found) 3135 return bpp_target_x16; 3136 3137 return 0; 3138 } 3139