1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 */ 28 29 #include <linux/delay.h> 30 #include <linux/hdmi.h> 31 #include <linux/i2c.h> 32 #include <linux/iopoll.h> 33 #include <linux/slab.h> 34 #include <linux/string_helpers.h> 35 36 #include <drm/display/drm_hdcp_helper.h> 37 #include <drm/display/drm_hdmi_helper.h> 38 #include <drm/display/drm_scdc_helper.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_crtc.h> 41 #include <drm/drm_edid.h> 42 #include <drm/drm_print.h> 43 #include <drm/drm_probe_helper.h> 44 #include <drm/intel/intel_lpe_audio.h> 45 #include <media/cec-notifier.h> 46 47 #include "g4x_hdmi.h" 48 #include "i915_utils.h" 49 #include "intel_atomic.h" 50 #include "intel_audio.h" 51 #include "intel_connector.h" 52 #include "intel_cx0_phy.h" 53 #include "intel_ddi.h" 54 #include "intel_de.h" 55 #include "intel_display_driver.h" 56 #include "intel_display_regs.h" 57 #include "intel_display_types.h" 58 #include "intel_dp.h" 59 #include "intel_gmbus.h" 60 #include "intel_hdcp.h" 61 #include "intel_hdcp_regs.h" 62 #include "intel_hdcp_shim.h" 63 #include "intel_hdmi.h" 64 #include "intel_link_bw.h" 65 #include "intel_lspcon.h" 66 #include "intel_panel.h" 67 #include "intel_pfit.h" 68 #include "intel_snps_phy.h" 69 #include "intel_vrr.h" 70 71 static void 72 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) 73 { 74 struct intel_display *display = to_intel_display(intel_hdmi); 75 u32 enabled_bits; 76 77 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; 78 79 drm_WARN(display->drm, 80 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, 81 "HDMI port enabled, expecting disabled\n"); 82 } 83 84 static void 85 assert_hdmi_transcoder_func_disabled(struct intel_display *display, 86 enum transcoder cpu_transcoder) 87 { 88 drm_WARN(display->drm, 89 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & 90 TRANS_DDI_FUNC_ENABLE, 91 "HDMI transcoder function enabled, expecting disabled\n"); 92 } 93 94 static u32 g4x_infoframe_index(unsigned int type) 95 { 96 switch (type) { 97 case HDMI_PACKET_TYPE_GAMUT_METADATA: 98 return VIDEO_DIP_SELECT_GAMUT; 99 case HDMI_INFOFRAME_TYPE_AVI: 100 return VIDEO_DIP_SELECT_AVI; 101 case HDMI_INFOFRAME_TYPE_SPD: 102 return VIDEO_DIP_SELECT_SPD; 103 case HDMI_INFOFRAME_TYPE_VENDOR: 104 return VIDEO_DIP_SELECT_VENDOR; 105 default: 106 MISSING_CASE(type); 107 return 0; 108 } 109 } 110 111 static u32 g4x_infoframe_enable(unsigned int type) 112 { 113 switch (type) { 114 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 115 return VIDEO_DIP_ENABLE_GCP; 116 case HDMI_PACKET_TYPE_GAMUT_METADATA: 117 return VIDEO_DIP_ENABLE_GAMUT; 118 case DP_SDP_VSC: 119 return 0; 120 case DP_SDP_ADAPTIVE_SYNC: 121 return 0; 122 case HDMI_INFOFRAME_TYPE_AVI: 123 return VIDEO_DIP_ENABLE_AVI; 124 case HDMI_INFOFRAME_TYPE_SPD: 125 return VIDEO_DIP_ENABLE_SPD; 126 case HDMI_INFOFRAME_TYPE_VENDOR: 127 return VIDEO_DIP_ENABLE_VENDOR; 128 case HDMI_INFOFRAME_TYPE_DRM: 129 return 0; 130 default: 131 MISSING_CASE(type); 132 return 0; 133 } 134 } 135 136 static u32 hsw_infoframe_enable(unsigned int type) 137 { 138 switch (type) { 139 case HDMI_PACKET_TYPE_GENERAL_CONTROL: 140 return VIDEO_DIP_ENABLE_GCP_HSW; 141 case HDMI_PACKET_TYPE_GAMUT_METADATA: 142 return VIDEO_DIP_ENABLE_GMP_HSW; 143 case DP_SDP_VSC: 144 return VIDEO_DIP_ENABLE_VSC_HSW; 145 case DP_SDP_ADAPTIVE_SYNC: 146 return VIDEO_DIP_ENABLE_AS_ADL; 147 case DP_SDP_PPS: 148 return VDIP_ENABLE_PPS; 149 case HDMI_INFOFRAME_TYPE_AVI: 150 return VIDEO_DIP_ENABLE_AVI_HSW; 151 case HDMI_INFOFRAME_TYPE_SPD: 152 return VIDEO_DIP_ENABLE_SPD_HSW; 153 case HDMI_INFOFRAME_TYPE_VENDOR: 154 return VIDEO_DIP_ENABLE_VS_HSW; 155 case HDMI_INFOFRAME_TYPE_DRM: 156 return VIDEO_DIP_ENABLE_DRM_GLK; 157 default: 158 MISSING_CASE(type); 159 return 0; 160 } 161 } 162 163 static i915_reg_t 164 hsw_dip_data_reg(struct intel_display *display, 165 enum transcoder cpu_transcoder, 166 unsigned int type, 167 int i) 168 { 169 switch (type) { 170 case HDMI_PACKET_TYPE_GAMUT_METADATA: 171 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); 172 case DP_SDP_VSC: 173 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); 174 case DP_SDP_ADAPTIVE_SYNC: 175 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); 176 case DP_SDP_PPS: 177 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); 178 case HDMI_INFOFRAME_TYPE_AVI: 179 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); 180 case HDMI_INFOFRAME_TYPE_SPD: 181 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); 182 case HDMI_INFOFRAME_TYPE_VENDOR: 183 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); 184 case HDMI_INFOFRAME_TYPE_DRM: 185 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); 186 default: 187 MISSING_CASE(type); 188 return INVALID_MMIO_REG; 189 } 190 } 191 192 static int hsw_dip_data_size(struct intel_display *display, 193 unsigned int type) 194 { 195 switch (type) { 196 case DP_SDP_VSC: 197 return VIDEO_DIP_VSC_DATA_SIZE; 198 case DP_SDP_ADAPTIVE_SYNC: 199 return VIDEO_DIP_ASYNC_DATA_SIZE; 200 case DP_SDP_PPS: 201 return VIDEO_DIP_PPS_DATA_SIZE; 202 case HDMI_PACKET_TYPE_GAMUT_METADATA: 203 if (DISPLAY_VER(display) >= 11) 204 return VIDEO_DIP_GMP_DATA_SIZE; 205 else 206 return VIDEO_DIP_DATA_SIZE; 207 default: 208 return VIDEO_DIP_DATA_SIZE; 209 } 210 } 211 212 static void g4x_write_infoframe(struct intel_encoder *encoder, 213 const struct intel_crtc_state *crtc_state, 214 unsigned int type, 215 const void *frame, ssize_t len) 216 { 217 struct intel_display *display = to_intel_display(encoder); 218 const u32 *data = frame; 219 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 220 int i; 221 222 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 223 "Writing DIP with CTL reg disabled\n"); 224 225 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 226 val |= g4x_infoframe_index(type); 227 228 val &= ~g4x_infoframe_enable(type); 229 230 intel_de_write(display, VIDEO_DIP_CTL, val); 231 232 for (i = 0; i < len; i += 4) { 233 intel_de_write(display, VIDEO_DIP_DATA, *data); 234 data++; 235 } 236 /* Write every possible data byte to force correct ECC calculation. */ 237 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 238 intel_de_write(display, VIDEO_DIP_DATA, 0); 239 240 val |= g4x_infoframe_enable(type); 241 val &= ~VIDEO_DIP_FREQ_MASK; 242 val |= VIDEO_DIP_FREQ_VSYNC; 243 244 intel_de_write(display, VIDEO_DIP_CTL, val); 245 intel_de_posting_read(display, VIDEO_DIP_CTL); 246 } 247 248 static void g4x_read_infoframe(struct intel_encoder *encoder, 249 const struct intel_crtc_state *crtc_state, 250 unsigned int type, 251 void *frame, ssize_t len) 252 { 253 struct intel_display *display = to_intel_display(encoder); 254 u32 *data = frame; 255 int i; 256 257 intel_de_rmw(display, VIDEO_DIP_CTL, 258 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 259 260 for (i = 0; i < len; i += 4) 261 *data++ = intel_de_read(display, VIDEO_DIP_DATA); 262 } 263 264 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, 265 const struct intel_crtc_state *pipe_config) 266 { 267 struct intel_display *display = to_intel_display(encoder); 268 u32 val = intel_de_read(display, VIDEO_DIP_CTL); 269 270 if ((val & VIDEO_DIP_ENABLE) == 0) 271 return 0; 272 273 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 274 return 0; 275 276 return val & (VIDEO_DIP_ENABLE_AVI | 277 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 278 } 279 280 static void ibx_write_infoframe(struct intel_encoder *encoder, 281 const struct intel_crtc_state *crtc_state, 282 unsigned int type, 283 const void *frame, ssize_t len) 284 { 285 struct intel_display *display = to_intel_display(encoder); 286 const u32 *data = frame; 287 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 288 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 289 u32 val = intel_de_read(display, reg); 290 int i; 291 292 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 293 "Writing DIP with CTL reg disabled\n"); 294 295 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 296 val |= g4x_infoframe_index(type); 297 298 val &= ~g4x_infoframe_enable(type); 299 300 intel_de_write(display, reg, val); 301 302 for (i = 0; i < len; i += 4) { 303 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 304 *data); 305 data++; 306 } 307 /* Write every possible data byte to force correct ECC calculation. */ 308 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 309 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 310 311 val |= g4x_infoframe_enable(type); 312 val &= ~VIDEO_DIP_FREQ_MASK; 313 val |= VIDEO_DIP_FREQ_VSYNC; 314 315 intel_de_write(display, reg, val); 316 intel_de_posting_read(display, reg); 317 } 318 319 static void ibx_read_infoframe(struct intel_encoder *encoder, 320 const struct intel_crtc_state *crtc_state, 321 unsigned int type, 322 void *frame, ssize_t len) 323 { 324 struct intel_display *display = to_intel_display(encoder); 325 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 326 u32 *data = frame; 327 int i; 328 329 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 330 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 331 332 for (i = 0; i < len; i += 4) 333 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 334 } 335 336 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, 337 const struct intel_crtc_state *pipe_config) 338 { 339 struct intel_display *display = to_intel_display(encoder); 340 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 341 i915_reg_t reg = TVIDEO_DIP_CTL(pipe); 342 u32 val = intel_de_read(display, reg); 343 344 if ((val & VIDEO_DIP_ENABLE) == 0) 345 return 0; 346 347 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 348 return 0; 349 350 return val & (VIDEO_DIP_ENABLE_AVI | 351 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 352 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 353 } 354 355 static void cpt_write_infoframe(struct intel_encoder *encoder, 356 const struct intel_crtc_state *crtc_state, 357 unsigned int type, 358 const void *frame, ssize_t len) 359 { 360 struct intel_display *display = to_intel_display(encoder); 361 const u32 *data = frame; 362 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 363 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 364 u32 val = intel_de_read(display, reg); 365 int i; 366 367 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 368 "Writing DIP with CTL reg disabled\n"); 369 370 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 371 val |= g4x_infoframe_index(type); 372 373 /* The DIP control register spec says that we need to update the AVI 374 * infoframe without clearing its enable bit */ 375 if (type != HDMI_INFOFRAME_TYPE_AVI) 376 val &= ~g4x_infoframe_enable(type); 377 378 intel_de_write(display, reg, val); 379 380 for (i = 0; i < len; i += 4) { 381 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 382 *data); 383 data++; 384 } 385 /* Write every possible data byte to force correct ECC calculation. */ 386 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 387 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); 388 389 val |= g4x_infoframe_enable(type); 390 val &= ~VIDEO_DIP_FREQ_MASK; 391 val |= VIDEO_DIP_FREQ_VSYNC; 392 393 intel_de_write(display, reg, val); 394 intel_de_posting_read(display, reg); 395 } 396 397 static void cpt_read_infoframe(struct intel_encoder *encoder, 398 const struct intel_crtc_state *crtc_state, 399 unsigned int type, 400 void *frame, ssize_t len) 401 { 402 struct intel_display *display = to_intel_display(encoder); 403 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 404 u32 *data = frame; 405 int i; 406 407 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), 408 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 409 410 for (i = 0; i < len; i += 4) 411 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); 412 } 413 414 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, 415 const struct intel_crtc_state *pipe_config) 416 { 417 struct intel_display *display = to_intel_display(encoder); 418 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 419 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); 420 421 if ((val & VIDEO_DIP_ENABLE) == 0) 422 return 0; 423 424 return val & (VIDEO_DIP_ENABLE_AVI | 425 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 426 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 427 } 428 429 static void vlv_write_infoframe(struct intel_encoder *encoder, 430 const struct intel_crtc_state *crtc_state, 431 unsigned int type, 432 const void *frame, ssize_t len) 433 { 434 struct intel_display *display = to_intel_display(encoder); 435 const u32 *data = frame; 436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 437 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 438 u32 val = intel_de_read(display, reg); 439 int i; 440 441 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), 442 "Writing DIP with CTL reg disabled\n"); 443 444 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 445 val |= g4x_infoframe_index(type); 446 447 val &= ~g4x_infoframe_enable(type); 448 449 intel_de_write(display, reg, val); 450 451 for (i = 0; i < len; i += 4) { 452 intel_de_write(display, 453 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); 454 data++; 455 } 456 /* Write every possible data byte to force correct ECC calculation. */ 457 for (; i < VIDEO_DIP_DATA_SIZE; i += 4) 458 intel_de_write(display, 459 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); 460 461 val |= g4x_infoframe_enable(type); 462 val &= ~VIDEO_DIP_FREQ_MASK; 463 val |= VIDEO_DIP_FREQ_VSYNC; 464 465 intel_de_write(display, reg, val); 466 intel_de_posting_read(display, reg); 467 } 468 469 static void vlv_read_infoframe(struct intel_encoder *encoder, 470 const struct intel_crtc_state *crtc_state, 471 unsigned int type, 472 void *frame, ssize_t len) 473 { 474 struct intel_display *display = to_intel_display(encoder); 475 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 476 u32 *data = frame; 477 int i; 478 479 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), 480 VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type)); 481 482 for (i = 0; i < len; i += 4) 483 *data++ = intel_de_read(display, 484 VLV_TVIDEO_DIP_DATA(crtc->pipe)); 485 } 486 487 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, 488 const struct intel_crtc_state *pipe_config) 489 { 490 struct intel_display *display = to_intel_display(encoder); 491 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; 492 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); 493 494 if ((val & VIDEO_DIP_ENABLE) == 0) 495 return 0; 496 497 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) 498 return 0; 499 500 return val & (VIDEO_DIP_ENABLE_AVI | 501 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 502 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 503 } 504 505 void hsw_write_infoframe(struct intel_encoder *encoder, 506 const struct intel_crtc_state *crtc_state, 507 unsigned int type, 508 const void *frame, ssize_t len) 509 { 510 struct intel_display *display = to_intel_display(encoder); 511 const u32 *data = frame; 512 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 513 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); 514 int data_size; 515 int i; 516 u32 val = intel_de_read(display, ctl_reg); 517 518 data_size = hsw_dip_data_size(display, type); 519 520 drm_WARN_ON(display->drm, len > data_size); 521 522 val &= ~hsw_infoframe_enable(type); 523 intel_de_write(display, ctl_reg, val); 524 525 for (i = 0; i < len; i += 4) { 526 intel_de_write(display, 527 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 528 *data); 529 data++; 530 } 531 /* Write every possible data byte to force correct ECC calculation. */ 532 for (; i < data_size; i += 4) 533 intel_de_write(display, 534 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), 535 0); 536 537 /* Wa_14013475917 */ 538 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && 539 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) 540 val |= hsw_infoframe_enable(type); 541 542 if (type == DP_SDP_VSC) 543 val |= VSC_DIP_HW_DATA_SW_HEA; 544 545 intel_de_write(display, ctl_reg, val); 546 intel_de_posting_read(display, ctl_reg); 547 } 548 549 void hsw_read_infoframe(struct intel_encoder *encoder, 550 const struct intel_crtc_state *crtc_state, 551 unsigned int type, void *frame, ssize_t len) 552 { 553 struct intel_display *display = to_intel_display(encoder); 554 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 555 u32 *data = frame; 556 int i; 557 558 for (i = 0; i < len; i += 4) 559 *data++ = intel_de_read(display, 560 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); 561 } 562 563 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, 564 const struct intel_crtc_state *pipe_config) 565 { 566 struct intel_display *display = to_intel_display(encoder); 567 u32 val = intel_de_read(display, 568 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 569 u32 mask; 570 571 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 572 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 573 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); 574 575 if (DISPLAY_VER(display) >= 10) 576 mask |= VIDEO_DIP_ENABLE_DRM_GLK; 577 578 if (HAS_AS_SDP(display)) 579 mask |= VIDEO_DIP_ENABLE_AS_ADL; 580 581 return val & mask; 582 } 583 584 static const u8 infoframe_type_to_idx[] = { 585 HDMI_PACKET_TYPE_GENERAL_CONTROL, 586 HDMI_PACKET_TYPE_GAMUT_METADATA, 587 DP_SDP_VSC, 588 DP_SDP_ADAPTIVE_SYNC, 589 HDMI_INFOFRAME_TYPE_AVI, 590 HDMI_INFOFRAME_TYPE_SPD, 591 HDMI_INFOFRAME_TYPE_VENDOR, 592 HDMI_INFOFRAME_TYPE_DRM, 593 }; 594 595 u32 intel_hdmi_infoframe_enable(unsigned int type) 596 { 597 int i; 598 599 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 600 if (infoframe_type_to_idx[i] == type) 601 return BIT(i); 602 } 603 604 return 0; 605 } 606 607 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, 608 const struct intel_crtc_state *crtc_state) 609 { 610 struct intel_display *display = to_intel_display(encoder); 611 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 612 u32 val, ret = 0; 613 int i; 614 615 val = dig_port->infoframes_enabled(encoder, crtc_state); 616 617 /* map from hardware bits to dip idx */ 618 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { 619 unsigned int type = infoframe_type_to_idx[i]; 620 621 if (HAS_DDI(display)) { 622 if (val & hsw_infoframe_enable(type)) 623 ret |= BIT(i); 624 } else { 625 if (val & g4x_infoframe_enable(type)) 626 ret |= BIT(i); 627 } 628 } 629 630 return ret; 631 } 632 633 /* 634 * The data we write to the DIP data buffer registers is 1 byte bigger than the 635 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting 636 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be 637 * used for both technologies. 638 * 639 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 640 * DW1: DB3 | DB2 | DB1 | DB0 641 * DW2: DB7 | DB6 | DB5 | DB4 642 * DW3: ... 643 * 644 * (HB is Header Byte, DB is Data Byte) 645 * 646 * The hdmi pack() functions don't know about that hardware specific hole so we 647 * trick them by giving an offset into the buffer and moving back the header 648 * bytes by one. 649 */ 650 static void intel_write_infoframe(struct intel_encoder *encoder, 651 const struct intel_crtc_state *crtc_state, 652 enum hdmi_infoframe_type type, 653 const union hdmi_infoframe *frame) 654 { 655 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 656 u8 buffer[VIDEO_DIP_DATA_SIZE]; 657 ssize_t len; 658 659 if ((crtc_state->infoframes.enable & 660 intel_hdmi_infoframe_enable(type)) == 0) 661 return; 662 663 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) 664 return; 665 666 /* see comment above for the reason for this offset */ 667 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); 668 if (drm_WARN_ON(encoder->base.dev, len < 0)) 669 return; 670 671 /* Insert the 'hole' (see big comment above) at position 3 */ 672 memmove(&buffer[0], &buffer[1], 3); 673 buffer[3] = 0; 674 len++; 675 676 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); 677 } 678 679 void intel_read_infoframe(struct intel_encoder *encoder, 680 const struct intel_crtc_state *crtc_state, 681 enum hdmi_infoframe_type type, 682 union hdmi_infoframe *frame) 683 { 684 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 685 u8 buffer[VIDEO_DIP_DATA_SIZE]; 686 int ret; 687 688 if ((crtc_state->infoframes.enable & 689 intel_hdmi_infoframe_enable(type)) == 0) 690 return; 691 692 dig_port->read_infoframe(encoder, crtc_state, 693 type, buffer, sizeof(buffer)); 694 695 /* Fill the 'hole' (see big comment above) at position 3 */ 696 memmove(&buffer[1], &buffer[0], 3); 697 698 /* see comment above for the reason for this offset */ 699 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); 700 if (ret) { 701 drm_dbg_kms(encoder->base.dev, 702 "Failed to unpack infoframe type 0x%02x\n", type); 703 return; 704 } 705 706 if (frame->any.type != type) 707 drm_dbg_kms(encoder->base.dev, 708 "Found the wrong infoframe type 0x%x (expected 0x%02x)\n", 709 frame->any.type, type); 710 } 711 712 static bool 713 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, 714 struct intel_crtc_state *crtc_state, 715 struct drm_connector_state *conn_state) 716 { 717 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; 718 const struct drm_display_mode *adjusted_mode = 719 &crtc_state->hw.adjusted_mode; 720 struct intel_connector *connector = to_intel_connector(conn_state->connector); 721 int ret; 722 723 if (!crtc_state->has_infoframe) 724 return true; 725 726 crtc_state->infoframes.enable |= 727 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 728 729 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base, 730 adjusted_mode); 731 if (ret) 732 return false; 733 734 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 735 frame->colorspace = HDMI_COLORSPACE_YUV420; 736 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) 737 frame->colorspace = HDMI_COLORSPACE_YUV444; 738 else 739 frame->colorspace = HDMI_COLORSPACE_RGB; 740 741 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); 742 743 /* nonsense combination */ 744 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && 745 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); 746 747 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { 748 drm_hdmi_avi_infoframe_quant_range(frame, &connector->base, 749 adjusted_mode, 750 crtc_state->limited_color_range ? 751 HDMI_QUANTIZATION_RANGE_LIMITED : 752 HDMI_QUANTIZATION_RANGE_FULL); 753 } else { 754 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 755 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 756 } 757 758 drm_hdmi_avi_infoframe_content_type(frame, conn_state); 759 760 /* TODO: handle pixel repetition for YCBCR420 outputs */ 761 762 ret = hdmi_avi_infoframe_check(frame); 763 if (drm_WARN_ON(encoder->base.dev, ret)) 764 return false; 765 766 return true; 767 } 768 769 static bool 770 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, 771 struct intel_crtc_state *crtc_state, 772 struct drm_connector_state *conn_state) 773 { 774 struct intel_display *display = to_intel_display(crtc_state); 775 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; 776 int ret; 777 778 if (!crtc_state->has_infoframe) 779 return true; 780 781 crtc_state->infoframes.enable |= 782 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); 783 784 if (display->platform.dgfx) 785 ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx"); 786 else 787 ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); 788 789 if (drm_WARN_ON(encoder->base.dev, ret)) 790 return false; 791 792 frame->sdi = HDMI_SPD_SDI_PC; 793 794 ret = hdmi_spd_infoframe_check(frame); 795 if (drm_WARN_ON(encoder->base.dev, ret)) 796 return false; 797 798 return true; 799 } 800 801 static bool 802 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, 803 struct intel_crtc_state *crtc_state, 804 struct drm_connector_state *conn_state) 805 { 806 struct hdmi_vendor_infoframe *frame = 807 &crtc_state->infoframes.hdmi.vendor.hdmi; 808 const struct drm_display_info *info = 809 &conn_state->connector->display_info; 810 int ret; 811 812 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) 813 return true; 814 815 crtc_state->infoframes.enable |= 816 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); 817 818 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, 819 conn_state->connector, 820 &crtc_state->hw.adjusted_mode); 821 if (drm_WARN_ON(encoder->base.dev, ret)) 822 return false; 823 824 ret = hdmi_vendor_infoframe_check(frame); 825 if (drm_WARN_ON(encoder->base.dev, ret)) 826 return false; 827 828 return true; 829 } 830 831 static bool 832 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, 833 struct intel_crtc_state *crtc_state, 834 struct drm_connector_state *conn_state) 835 { 836 struct intel_display *display = to_intel_display(encoder); 837 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; 838 int ret; 839 840 if (DISPLAY_VER(display) < 10) 841 return true; 842 843 if (!crtc_state->has_infoframe) 844 return true; 845 846 if (!conn_state->hdr_output_metadata) 847 return true; 848 849 crtc_state->infoframes.enable |= 850 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); 851 852 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); 853 if (ret < 0) { 854 drm_dbg_kms(display->drm, 855 "couldn't set HDR metadata in infoframe\n"); 856 return false; 857 } 858 859 ret = hdmi_drm_infoframe_check(frame); 860 if (drm_WARN_ON(display->drm, ret)) 861 return false; 862 863 return true; 864 } 865 866 static void g4x_set_infoframes(struct intel_encoder *encoder, 867 bool enable, 868 const struct intel_crtc_state *crtc_state, 869 const struct drm_connector_state *conn_state) 870 { 871 struct intel_display *display = to_intel_display(encoder); 872 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 873 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 874 i915_reg_t reg = VIDEO_DIP_CTL; 875 u32 val = intel_de_read(display, reg); 876 u32 port = VIDEO_DIP_PORT(encoder->port); 877 878 assert_hdmi_port_disabled(intel_hdmi); 879 880 /* If the registers were not initialized yet, they might be zeroes, 881 * which means we're selecting the AVI DIP and we're setting its 882 * frequency to once. This seems to really confuse the HW and make 883 * things stop working (the register spec says the AVI always needs to 884 * be sent every VSync). So here we avoid writing to the register more 885 * than we need and also explicitly select the AVI DIP and explicitly 886 * set its frequency to every VSync. Avoiding to write it twice seems to 887 * be enough to solve the problem, but being defensive shouldn't hurt us 888 * either. */ 889 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 890 891 if (!enable) { 892 if (!(val & VIDEO_DIP_ENABLE)) 893 return; 894 if (port != (val & VIDEO_DIP_PORT_MASK)) { 895 drm_dbg_kms(display->drm, 896 "video DIP still enabled on port %c\n", 897 (val & VIDEO_DIP_PORT_MASK) >> 29); 898 return; 899 } 900 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 901 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 902 intel_de_write(display, reg, val); 903 intel_de_posting_read(display, reg); 904 return; 905 } 906 907 if (port != (val & VIDEO_DIP_PORT_MASK)) { 908 if (val & VIDEO_DIP_ENABLE) { 909 drm_dbg_kms(display->drm, 910 "video DIP already enabled on port %c\n", 911 (val & VIDEO_DIP_PORT_MASK) >> 29); 912 return; 913 } 914 val &= ~VIDEO_DIP_PORT_MASK; 915 val |= port; 916 } 917 918 val |= VIDEO_DIP_ENABLE; 919 val &= ~(VIDEO_DIP_ENABLE_AVI | 920 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); 921 922 intel_de_write(display, reg, val); 923 intel_de_posting_read(display, reg); 924 925 intel_write_infoframe(encoder, crtc_state, 926 HDMI_INFOFRAME_TYPE_AVI, 927 &crtc_state->infoframes.avi); 928 intel_write_infoframe(encoder, crtc_state, 929 HDMI_INFOFRAME_TYPE_SPD, 930 &crtc_state->infoframes.spd); 931 intel_write_infoframe(encoder, crtc_state, 932 HDMI_INFOFRAME_TYPE_VENDOR, 933 &crtc_state->infoframes.hdmi); 934 } 935 936 /* 937 * Determine if default_phase=1 can be indicated in the GCP infoframe. 938 * 939 * From HDMI specification 1.4a: 940 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 941 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 942 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase 943 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing 944 * phase of 0 945 */ 946 static bool gcp_default_phase_possible(int pipe_bpp, 947 const struct drm_display_mode *mode) 948 { 949 unsigned int pixels_per_group; 950 951 switch (pipe_bpp) { 952 case 30: 953 /* 4 pixels in 5 clocks */ 954 pixels_per_group = 4; 955 break; 956 case 36: 957 /* 2 pixels in 3 clocks */ 958 pixels_per_group = 2; 959 break; 960 case 48: 961 /* 1 pixel in 2 clocks */ 962 pixels_per_group = 1; 963 break; 964 default: 965 /* phase information not relevant for 8bpc */ 966 return false; 967 } 968 969 return mode->crtc_hdisplay % pixels_per_group == 0 && 970 mode->crtc_htotal % pixels_per_group == 0 && 971 mode->crtc_hblank_start % pixels_per_group == 0 && 972 mode->crtc_hblank_end % pixels_per_group == 0 && 973 mode->crtc_hsync_start % pixels_per_group == 0 && 974 mode->crtc_hsync_end % pixels_per_group == 0 && 975 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || 976 mode->crtc_htotal/2 % pixels_per_group == 0); 977 } 978 979 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, 980 const struct intel_crtc_state *crtc_state, 981 const struct drm_connector_state *conn_state) 982 { 983 struct intel_display *display = to_intel_display(encoder); 984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 985 i915_reg_t reg; 986 987 if ((crtc_state->infoframes.enable & 988 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 989 return false; 990 991 if (HAS_DDI(display)) 992 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 993 else if (display->platform.valleyview || display->platform.cherryview) 994 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 995 else if (HAS_PCH_SPLIT(display)) 996 reg = TVIDEO_DIP_GCP(crtc->pipe); 997 else 998 return false; 999 1000 intel_de_write(display, reg, crtc_state->infoframes.gcp); 1001 1002 return true; 1003 } 1004 1005 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, 1006 struct intel_crtc_state *crtc_state) 1007 { 1008 struct intel_display *display = to_intel_display(encoder); 1009 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1010 i915_reg_t reg; 1011 1012 if ((crtc_state->infoframes.enable & 1013 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) 1014 return; 1015 1016 if (HAS_DDI(display)) 1017 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); 1018 else if (display->platform.valleyview || display->platform.cherryview) 1019 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); 1020 else if (HAS_PCH_SPLIT(display)) 1021 reg = TVIDEO_DIP_GCP(crtc->pipe); 1022 else 1023 return; 1024 1025 crtc_state->infoframes.gcp = intel_de_read(display, reg); 1026 } 1027 1028 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, 1029 struct intel_crtc_state *crtc_state, 1030 struct drm_connector_state *conn_state) 1031 { 1032 struct intel_display *display = to_intel_display(encoder); 1033 1034 if (display->platform.g4x || !crtc_state->has_infoframe) 1035 return; 1036 1037 crtc_state->infoframes.enable |= 1038 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); 1039 1040 /* Indicate color indication for deep color mode */ 1041 if (crtc_state->pipe_bpp > 24) 1042 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; 1043 1044 /* Enable default_phase whenever the display mode is suitably aligned */ 1045 if (gcp_default_phase_possible(crtc_state->pipe_bpp, 1046 &crtc_state->hw.adjusted_mode)) 1047 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; 1048 } 1049 1050 static void ibx_set_infoframes(struct intel_encoder *encoder, 1051 bool enable, 1052 const struct intel_crtc_state *crtc_state, 1053 const struct drm_connector_state *conn_state) 1054 { 1055 struct intel_display *display = to_intel_display(encoder); 1056 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1057 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1058 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 1059 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1060 u32 val = intel_de_read(display, reg); 1061 u32 port = VIDEO_DIP_PORT(encoder->port); 1062 1063 assert_hdmi_port_disabled(intel_hdmi); 1064 1065 /* See the big comment in g4x_set_infoframes() */ 1066 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1067 1068 if (!enable) { 1069 if (!(val & VIDEO_DIP_ENABLE)) 1070 return; 1071 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1072 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1073 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1074 intel_de_write(display, reg, val); 1075 intel_de_posting_read(display, reg); 1076 return; 1077 } 1078 1079 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1080 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1081 "DIP already enabled on port %c\n", 1082 (val & VIDEO_DIP_PORT_MASK) >> 29); 1083 val &= ~VIDEO_DIP_PORT_MASK; 1084 val |= port; 1085 } 1086 1087 val |= VIDEO_DIP_ENABLE; 1088 val &= ~(VIDEO_DIP_ENABLE_AVI | 1089 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1090 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1091 1092 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1093 val |= VIDEO_DIP_ENABLE_GCP; 1094 1095 intel_de_write(display, reg, val); 1096 intel_de_posting_read(display, reg); 1097 1098 intel_write_infoframe(encoder, crtc_state, 1099 HDMI_INFOFRAME_TYPE_AVI, 1100 &crtc_state->infoframes.avi); 1101 intel_write_infoframe(encoder, crtc_state, 1102 HDMI_INFOFRAME_TYPE_SPD, 1103 &crtc_state->infoframes.spd); 1104 intel_write_infoframe(encoder, crtc_state, 1105 HDMI_INFOFRAME_TYPE_VENDOR, 1106 &crtc_state->infoframes.hdmi); 1107 } 1108 1109 static void cpt_set_infoframes(struct intel_encoder *encoder, 1110 bool enable, 1111 const struct intel_crtc_state *crtc_state, 1112 const struct drm_connector_state *conn_state) 1113 { 1114 struct intel_display *display = to_intel_display(encoder); 1115 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1116 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1117 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); 1118 u32 val = intel_de_read(display, reg); 1119 1120 assert_hdmi_port_disabled(intel_hdmi); 1121 1122 /* See the big comment in g4x_set_infoframes() */ 1123 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1124 1125 if (!enable) { 1126 if (!(val & VIDEO_DIP_ENABLE)) 1127 return; 1128 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1129 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1130 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1131 intel_de_write(display, reg, val); 1132 intel_de_posting_read(display, reg); 1133 return; 1134 } 1135 1136 /* Set both together, unset both together: see the spec. */ 1137 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; 1138 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1139 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1140 1141 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1142 val |= VIDEO_DIP_ENABLE_GCP; 1143 1144 intel_de_write(display, reg, val); 1145 intel_de_posting_read(display, reg); 1146 1147 intel_write_infoframe(encoder, crtc_state, 1148 HDMI_INFOFRAME_TYPE_AVI, 1149 &crtc_state->infoframes.avi); 1150 intel_write_infoframe(encoder, crtc_state, 1151 HDMI_INFOFRAME_TYPE_SPD, 1152 &crtc_state->infoframes.spd); 1153 intel_write_infoframe(encoder, crtc_state, 1154 HDMI_INFOFRAME_TYPE_VENDOR, 1155 &crtc_state->infoframes.hdmi); 1156 } 1157 1158 static void vlv_set_infoframes(struct intel_encoder *encoder, 1159 bool enable, 1160 const struct intel_crtc_state *crtc_state, 1161 const struct drm_connector_state *conn_state) 1162 { 1163 struct intel_display *display = to_intel_display(encoder); 1164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1165 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 1166 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); 1167 u32 val = intel_de_read(display, reg); 1168 u32 port = VIDEO_DIP_PORT(encoder->port); 1169 1170 assert_hdmi_port_disabled(intel_hdmi); 1171 1172 /* See the big comment in g4x_set_infoframes() */ 1173 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; 1174 1175 if (!enable) { 1176 if (!(val & VIDEO_DIP_ENABLE)) 1177 return; 1178 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | 1179 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1180 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1181 intel_de_write(display, reg, val); 1182 intel_de_posting_read(display, reg); 1183 return; 1184 } 1185 1186 if (port != (val & VIDEO_DIP_PORT_MASK)) { 1187 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, 1188 "DIP already enabled on port %c\n", 1189 (val & VIDEO_DIP_PORT_MASK) >> 29); 1190 val &= ~VIDEO_DIP_PORT_MASK; 1191 val |= port; 1192 } 1193 1194 val |= VIDEO_DIP_ENABLE; 1195 val &= ~(VIDEO_DIP_ENABLE_AVI | 1196 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | 1197 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); 1198 1199 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1200 val |= VIDEO_DIP_ENABLE_GCP; 1201 1202 intel_de_write(display, reg, val); 1203 intel_de_posting_read(display, reg); 1204 1205 intel_write_infoframe(encoder, crtc_state, 1206 HDMI_INFOFRAME_TYPE_AVI, 1207 &crtc_state->infoframes.avi); 1208 intel_write_infoframe(encoder, crtc_state, 1209 HDMI_INFOFRAME_TYPE_SPD, 1210 &crtc_state->infoframes.spd); 1211 intel_write_infoframe(encoder, crtc_state, 1212 HDMI_INFOFRAME_TYPE_VENDOR, 1213 &crtc_state->infoframes.hdmi); 1214 } 1215 1216 void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder, 1217 const struct intel_crtc_state *crtc_state, 1218 const struct drm_connector_state *conn_state) 1219 { 1220 struct intel_display *display = to_intel_display(encoder); 1221 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1222 crtc_state->cpu_transcoder); 1223 u32 val = intel_de_read(display, reg); 1224 1225 if ((crtc_state->infoframes.enable & 1226 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 && 1227 (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0) 1228 return; 1229 1230 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK); 1231 1232 intel_de_write(display, reg, val); 1233 intel_de_posting_read(display, reg); 1234 1235 intel_write_infoframe(encoder, crtc_state, 1236 HDMI_INFOFRAME_TYPE_DRM, 1237 &crtc_state->infoframes.drm); 1238 } 1239 1240 static void hsw_set_infoframes(struct intel_encoder *encoder, 1241 bool enable, 1242 const struct intel_crtc_state *crtc_state, 1243 const struct drm_connector_state *conn_state) 1244 { 1245 struct intel_display *display = to_intel_display(encoder); 1246 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, 1247 crtc_state->cpu_transcoder); 1248 u32 val = intel_de_read(display, reg); 1249 1250 assert_hdmi_transcoder_func_disabled(display, 1251 crtc_state->cpu_transcoder); 1252 1253 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | 1254 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | 1255 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | 1256 VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL); 1257 1258 if (!enable) { 1259 intel_de_write(display, reg, val); 1260 intel_de_posting_read(display, reg); 1261 return; 1262 } 1263 1264 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) 1265 val |= VIDEO_DIP_ENABLE_GCP_HSW; 1266 1267 intel_de_write(display, reg, val); 1268 intel_de_posting_read(display, reg); 1269 1270 intel_write_infoframe(encoder, crtc_state, 1271 HDMI_INFOFRAME_TYPE_AVI, 1272 &crtc_state->infoframes.avi); 1273 intel_write_infoframe(encoder, crtc_state, 1274 HDMI_INFOFRAME_TYPE_SPD, 1275 &crtc_state->infoframes.spd); 1276 intel_write_infoframe(encoder, crtc_state, 1277 HDMI_INFOFRAME_TYPE_VENDOR, 1278 &crtc_state->infoframes.hdmi); 1279 intel_write_infoframe(encoder, crtc_state, 1280 HDMI_INFOFRAME_TYPE_DRM, 1281 &crtc_state->infoframes.drm); 1282 } 1283 1284 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) 1285 { 1286 struct intel_display *display = to_intel_display(hdmi); 1287 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1288 1289 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) 1290 return; 1291 1292 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", 1293 enable ? "Enabling" : "Disabling"); 1294 1295 drm_dp_dual_mode_set_tmds_output(display->drm, 1296 hdmi->dp_dual_mode.type, ddc, enable); 1297 } 1298 1299 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port, 1300 unsigned int offset, void *buffer, size_t size) 1301 { 1302 struct intel_hdmi *hdmi = &dig_port->hdmi; 1303 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1304 int ret; 1305 u8 start = offset & 0xff; 1306 struct i2c_msg msgs[] = { 1307 { 1308 .addr = DRM_HDCP_DDC_ADDR, 1309 .flags = 0, 1310 .len = 1, 1311 .buf = &start, 1312 }, 1313 { 1314 .addr = DRM_HDCP_DDC_ADDR, 1315 .flags = I2C_M_RD, 1316 .len = size, 1317 .buf = buffer 1318 } 1319 }; 1320 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs)); 1321 if (ret == ARRAY_SIZE(msgs)) 1322 return 0; 1323 return ret >= 0 ? -EIO : ret; 1324 } 1325 1326 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port, 1327 unsigned int offset, void *buffer, size_t size) 1328 { 1329 struct intel_hdmi *hdmi = &dig_port->hdmi; 1330 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1331 int ret; 1332 u8 *write_buf; 1333 struct i2c_msg msg; 1334 1335 write_buf = kzalloc(size + 1, GFP_KERNEL); 1336 if (!write_buf) 1337 return -ENOMEM; 1338 1339 write_buf[0] = offset & 0xff; 1340 memcpy(&write_buf[1], buffer, size); 1341 1342 msg.addr = DRM_HDCP_DDC_ADDR; 1343 msg.flags = 0; 1344 msg.len = size + 1; 1345 msg.buf = write_buf; 1346 1347 ret = i2c_transfer(ddc, &msg, 1); 1348 if (ret == 1) 1349 ret = 0; 1350 else if (ret >= 0) 1351 ret = -EIO; 1352 1353 kfree(write_buf); 1354 return ret; 1355 } 1356 1357 static 1358 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 1359 u8 *an) 1360 { 1361 struct intel_display *display = to_intel_display(dig_port); 1362 struct intel_hdmi *hdmi = &dig_port->hdmi; 1363 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; 1364 int ret; 1365 1366 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an, 1367 DRM_HDCP_AN_LEN); 1368 if (ret) { 1369 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", 1370 ret); 1371 return ret; 1372 } 1373 1374 ret = intel_gmbus_output_aksv(ddc); 1375 if (ret < 0) { 1376 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); 1377 return ret; 1378 } 1379 return 0; 1380 } 1381 1382 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port, 1383 u8 *bksv) 1384 { 1385 struct intel_display *display = to_intel_display(dig_port); 1386 1387 int ret; 1388 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv, 1389 DRM_HDCP_KSV_LEN); 1390 if (ret) 1391 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", 1392 ret); 1393 return ret; 1394 } 1395 1396 static 1397 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port, 1398 u8 *bstatus) 1399 { 1400 struct intel_display *display = to_intel_display(dig_port); 1401 1402 int ret; 1403 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS, 1404 bstatus, DRM_HDCP_BSTATUS_LEN); 1405 if (ret) 1406 drm_dbg_kms(display->drm, 1407 "Read bstatus over DDC failed (%d)\n", 1408 ret); 1409 return ret; 1410 } 1411 1412 static 1413 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port, 1414 bool *repeater_present) 1415 { 1416 struct intel_display *display = to_intel_display(dig_port); 1417 int ret; 1418 u8 val; 1419 1420 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1421 if (ret) { 1422 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1423 ret); 1424 return ret; 1425 } 1426 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; 1427 return 0; 1428 } 1429 1430 static 1431 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 1432 u8 *ri_prime) 1433 { 1434 struct intel_display *display = to_intel_display(dig_port); 1435 1436 int ret; 1437 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME, 1438 ri_prime, DRM_HDCP_RI_LEN); 1439 if (ret) 1440 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", 1441 ret); 1442 return ret; 1443 } 1444 1445 static 1446 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 1447 bool *ksv_ready) 1448 { 1449 struct intel_display *display = to_intel_display(dig_port); 1450 int ret; 1451 u8 val; 1452 1453 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); 1454 if (ret) { 1455 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", 1456 ret); 1457 return ret; 1458 } 1459 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; 1460 return 0; 1461 } 1462 1463 static 1464 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 1465 int num_downstream, u8 *ksv_fifo) 1466 { 1467 struct intel_display *display = to_intel_display(dig_port); 1468 int ret; 1469 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO, 1470 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); 1471 if (ret) { 1472 drm_dbg_kms(display->drm, 1473 "Read ksv fifo over DDC failed (%d)\n", ret); 1474 return ret; 1475 } 1476 return 0; 1477 } 1478 1479 static 1480 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 1481 int i, u32 *part) 1482 { 1483 struct intel_display *display = to_intel_display(dig_port); 1484 int ret; 1485 1486 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 1487 return -EINVAL; 1488 1489 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i), 1490 part, DRM_HDCP_V_PRIME_PART_LEN); 1491 if (ret) 1492 drm_dbg_kms(display->drm, 1493 "Read V'[%d] over DDC failed (%d)\n", 1494 i, ret); 1495 return ret; 1496 } 1497 1498 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, 1499 enum transcoder cpu_transcoder) 1500 { 1501 struct intel_display *display = to_intel_display(connector); 1502 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1503 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); 1504 u32 scanline; 1505 int ret; 1506 1507 for (;;) { 1508 scanline = intel_de_read(display, 1509 PIPEDSL(display, crtc->pipe)); 1510 if (scanline > 100 && scanline < 200) 1511 break; 1512 usleep_range(25, 50); 1513 } 1514 1515 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1516 false, TRANS_DDI_HDCP_SIGNALLING); 1517 if (ret) { 1518 drm_err(display->drm, 1519 "Disable HDCP signalling failed (%d)\n", ret); 1520 return ret; 1521 } 1522 1523 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, 1524 true, TRANS_DDI_HDCP_SIGNALLING); 1525 if (ret) { 1526 drm_err(display->drm, 1527 "Enable HDCP signalling failed (%d)\n", ret); 1528 return ret; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static 1535 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 1536 enum transcoder cpu_transcoder, 1537 bool enable) 1538 { 1539 struct intel_display *display = to_intel_display(dig_port); 1540 struct intel_hdmi *hdmi = &dig_port->hdmi; 1541 struct intel_connector *connector = hdmi->attached_connector; 1542 int ret; 1543 1544 if (!enable) 1545 usleep_range(6, 60); /* Bspec says >= 6us */ 1546 1547 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 1548 cpu_transcoder, enable, 1549 TRANS_DDI_HDCP_SIGNALLING); 1550 if (ret) { 1551 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", 1552 enable ? "Enable" : "Disable", ret); 1553 return ret; 1554 } 1555 1556 /* 1557 * WA: To fix incorrect positioning of the window of 1558 * opportunity and enc_en signalling in KABYLAKE. 1559 */ 1560 if (display->platform.kabylake && enable) 1561 return kbl_repositioning_enc_en_signal(connector, 1562 cpu_transcoder); 1563 1564 return 0; 1565 } 1566 1567 static 1568 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port, 1569 struct intel_connector *connector) 1570 { 1571 struct intel_display *display = to_intel_display(dig_port); 1572 enum port port = dig_port->base.port; 1573 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 1574 int ret; 1575 union { 1576 u32 reg; 1577 u8 shim[DRM_HDCP_RI_LEN]; 1578 } ri; 1579 1580 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim); 1581 if (ret) 1582 return false; 1583 1584 intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg); 1585 1586 /* Wait for Ri prime match */ 1587 ret = intel_de_wait_for_set(display, HDCP_STATUS(display, cpu_transcoder, port), 1588 HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC, 1); 1589 if (ret) { 1590 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", 1591 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, 1592 port))); 1593 return false; 1594 } 1595 return true; 1596 } 1597 1598 static 1599 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port, 1600 struct intel_connector *connector) 1601 { 1602 int retry; 1603 1604 for (retry = 0; retry < 3; retry++) 1605 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) 1606 return true; 1607 1608 return false; 1609 } 1610 1611 struct hdcp2_hdmi_msg_timeout { 1612 u8 msg_id; 1613 u16 timeout; 1614 }; 1615 1616 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { 1617 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, 1618 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, 1619 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, 1620 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, 1621 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, 1622 }; 1623 1624 static 1625 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 1626 u8 *rx_status) 1627 { 1628 return intel_hdmi_hdcp_read(dig_port, 1629 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, 1630 rx_status, 1631 HDCP_2_2_HDMI_RXSTATUS_LEN); 1632 } 1633 1634 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) 1635 { 1636 int i; 1637 1638 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { 1639 if (is_paired) 1640 return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; 1641 else 1642 return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; 1643 } 1644 1645 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { 1646 if (hdcp2_msg_timeout[i].msg_id == msg_id) 1647 return hdcp2_msg_timeout[i].timeout; 1648 } 1649 1650 return -EINVAL; 1651 } 1652 1653 static int 1654 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 1655 u8 msg_id, bool *msg_ready, 1656 ssize_t *msg_sz) 1657 { 1658 struct intel_display *display = to_intel_display(dig_port); 1659 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1660 int ret; 1661 1662 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1663 if (ret < 0) { 1664 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", 1665 ret); 1666 return ret; 1667 } 1668 1669 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | 1670 rx_status[0]); 1671 1672 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) 1673 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && 1674 *msg_sz); 1675 else 1676 *msg_ready = *msg_sz; 1677 1678 return 0; 1679 } 1680 1681 static ssize_t 1682 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 1683 u8 msg_id, bool paired) 1684 { 1685 struct intel_display *display = to_intel_display(dig_port); 1686 bool msg_ready = false; 1687 int timeout, ret; 1688 ssize_t msg_sz = 0; 1689 1690 timeout = get_hdcp2_msg_timeout(msg_id, paired); 1691 if (timeout < 0) 1692 return timeout; 1693 1694 ret = poll_timeout_us(ret = hdcp2_detect_msg_availability(dig_port, msg_id, 1695 &msg_ready, &msg_sz), 1696 !ret && msg_ready && msg_sz, 1697 4000, timeout * 1000, false); 1698 if (ret) 1699 drm_dbg_kms(display->drm, 1700 "msg_id: %d, ret: %d, timeout: %d\n", 1701 msg_id, ret, timeout); 1702 1703 return ret ? ret : msg_sz; 1704 } 1705 1706 static 1707 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, 1708 void *buf, size_t size) 1709 { 1710 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1711 unsigned int offset; 1712 1713 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; 1714 return intel_hdmi_hdcp_write(dig_port, offset, buf, size); 1715 } 1716 1717 static 1718 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, 1719 u8 msg_id, void *buf, size_t size) 1720 { 1721 struct intel_display *display = to_intel_display(connector); 1722 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1723 struct intel_hdmi *hdmi = &dig_port->hdmi; 1724 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; 1725 unsigned int offset; 1726 ssize_t ret; 1727 1728 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id, 1729 hdcp->is_paired); 1730 if (ret < 0) 1731 return ret; 1732 1733 /* 1734 * Available msg size should be equal to or lesser than the 1735 * available buffer. 1736 */ 1737 if (ret > size) { 1738 drm_dbg_kms(display->drm, 1739 "msg_sz(%zd) is more than exp size(%zu)\n", 1740 ret, size); 1741 return -EINVAL; 1742 } 1743 1744 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; 1745 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret); 1746 if (ret) 1747 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", 1748 msg_id, ret); 1749 1750 return ret; 1751 } 1752 1753 static 1754 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, 1755 struct intel_connector *connector) 1756 { 1757 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; 1758 int ret; 1759 1760 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status); 1761 if (ret) 1762 return ret; 1763 1764 /* 1765 * Re-auth request and Link Integrity Failures are represented by 1766 * same bit. i.e reauth_req. 1767 */ 1768 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) 1769 ret = HDCP_REAUTH_REQUEST; 1770 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) 1771 ret = HDCP_TOPOLOGY_CHANGE; 1772 1773 return ret; 1774 } 1775 1776 static 1777 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, 1778 bool *capable) 1779 { 1780 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1781 u8 hdcp2_version; 1782 int ret; 1783 1784 *capable = false; 1785 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, 1786 &hdcp2_version, sizeof(hdcp2_version)); 1787 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) 1788 *capable = true; 1789 1790 return ret; 1791 } 1792 1793 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { 1794 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, 1795 .read_bksv = intel_hdmi_hdcp_read_bksv, 1796 .read_bstatus = intel_hdmi_hdcp_read_bstatus, 1797 .repeater_present = intel_hdmi_hdcp_repeater_present, 1798 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, 1799 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, 1800 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, 1801 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, 1802 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, 1803 .check_link = intel_hdmi_hdcp_check_link, 1804 .write_2_2_msg = intel_hdmi_hdcp2_write_msg, 1805 .read_2_2_msg = intel_hdmi_hdcp2_read_msg, 1806 .check_2_2_link = intel_hdmi_hdcp2_check_link, 1807 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability, 1808 .protocol = HDCP_PROTOCOL_HDMI, 1809 }; 1810 1811 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) 1812 { 1813 struct intel_display *display = to_intel_display(encoder); 1814 int max_tmds_clock, vbt_max_tmds_clock; 1815 1816 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s) 1817 max_tmds_clock = 600000; 1818 else if (DISPLAY_VER(display) >= 10) 1819 max_tmds_clock = 594000; 1820 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) 1821 max_tmds_clock = 300000; 1822 else if (DISPLAY_VER(display) >= 5) 1823 max_tmds_clock = 225000; 1824 else 1825 max_tmds_clock = 165000; 1826 1827 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); 1828 if (vbt_max_tmds_clock) 1829 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); 1830 1831 return max_tmds_clock; 1832 } 1833 1834 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, 1835 const struct drm_connector_state *conn_state) 1836 { 1837 struct intel_connector *connector = hdmi->attached_connector; 1838 1839 return connector->base.display_info.is_hdmi && 1840 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; 1841 } 1842 1843 static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state) 1844 { 1845 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; 1846 } 1847 1848 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, 1849 bool respect_downstream_limits, 1850 bool has_hdmi_sink) 1851 { 1852 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1853 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); 1854 1855 if (respect_downstream_limits) { 1856 struct intel_connector *connector = hdmi->attached_connector; 1857 const struct drm_display_info *info = &connector->base.display_info; 1858 1859 if (hdmi->dp_dual_mode.max_tmds_clock) 1860 max_tmds_clock = min(max_tmds_clock, 1861 hdmi->dp_dual_mode.max_tmds_clock); 1862 1863 if (info->max_tmds_clock) 1864 max_tmds_clock = min(max_tmds_clock, 1865 info->max_tmds_clock); 1866 else if (!has_hdmi_sink) 1867 max_tmds_clock = min(max_tmds_clock, 165000); 1868 } 1869 1870 return max_tmds_clock; 1871 } 1872 1873 static enum drm_mode_status 1874 hdmi_port_clock_valid(struct intel_hdmi *hdmi, 1875 int clock, bool respect_downstream_limits, 1876 bool has_hdmi_sink) 1877 { 1878 struct intel_display *display = to_intel_display(hdmi); 1879 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 1880 1881 if (clock < 25000) 1882 return MODE_CLOCK_LOW; 1883 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, 1884 has_hdmi_sink)) 1885 return MODE_CLOCK_HIGH; 1886 1887 /* GLK DPLL can't generate 446-480 MHz */ 1888 if (display->platform.geminilake && clock > 446666 && clock < 480000) 1889 return MODE_CLOCK_RANGE; 1890 1891 /* BXT/GLK DPLL can't generate 223-240 MHz */ 1892 if ((display->platform.geminilake || display->platform.broxton) && 1893 clock > 223333 && clock < 240000) 1894 return MODE_CLOCK_RANGE; 1895 1896 /* CHV DPLL can't generate 216-240 MHz */ 1897 if (display->platform.cherryview && clock > 216000 && clock < 240000) 1898 return MODE_CLOCK_RANGE; 1899 1900 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ 1901 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200) 1902 return MODE_CLOCK_RANGE; 1903 1904 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ 1905 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800) 1906 return MODE_CLOCK_RANGE; 1907 1908 return MODE_OK; 1909 } 1910 1911 int intel_hdmi_tmds_clock(int clock, int bpc, 1912 enum intel_output_format sink_format) 1913 { 1914 /* YCBCR420 TMDS rate requirement is half the pixel clock */ 1915 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1916 clock /= 2; 1917 1918 /* 1919 * Need to adjust the port link by: 1920 * 1.5x for 12bpc 1921 * 1.25x for 10bpc 1922 */ 1923 return DIV_ROUND_CLOSEST(clock * bpc, 8); 1924 } 1925 1926 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) 1927 { 1928 switch (bpc) { 1929 case 12: 1930 return !HAS_GMCH(display); 1931 case 10: 1932 return DISPLAY_VER(display) >= 11; 1933 case 8: 1934 return true; 1935 default: 1936 MISSING_CASE(bpc); 1937 return false; 1938 } 1939 } 1940 1941 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector, 1942 int bpc, bool has_hdmi_sink, 1943 enum intel_output_format sink_format) 1944 { 1945 struct intel_connector *connector = to_intel_connector(_connector); 1946 const struct drm_display_info *info = &connector->base.display_info; 1947 const struct drm_hdmi_info *hdmi = &info->hdmi; 1948 1949 switch (bpc) { 1950 case 12: 1951 if (!has_hdmi_sink) 1952 return false; 1953 1954 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1955 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; 1956 else 1957 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; 1958 case 10: 1959 if (!has_hdmi_sink) 1960 return false; 1961 1962 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1963 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; 1964 else 1965 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; 1966 case 8: 1967 return true; 1968 default: 1969 MISSING_CASE(bpc); 1970 return false; 1971 } 1972 } 1973 1974 static enum drm_mode_status 1975 intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock, 1976 bool has_hdmi_sink, 1977 enum intel_output_format sink_format) 1978 { 1979 struct intel_connector *connector = to_intel_connector(_connector); 1980 struct intel_display *display = to_intel_display(connector); 1981 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 1982 enum drm_mode_status status = MODE_OK; 1983 int bpc; 1984 1985 /* 1986 * Try all color depths since valid port clock range 1987 * can have holes. Any mode that can be used with at 1988 * least one color depth is accepted. 1989 */ 1990 for (bpc = 12; bpc >= 8; bpc -= 2) { 1991 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format); 1992 1993 if (!intel_hdmi_source_bpc_possible(display, bpc)) 1994 continue; 1995 1996 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 1997 sink_format)) 1998 continue; 1999 2000 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); 2001 if (status == MODE_OK) 2002 return MODE_OK; 2003 } 2004 2005 /* can never happen */ 2006 drm_WARN_ON(display->drm, status == MODE_OK); 2007 2008 return status; 2009 } 2010 2011 static enum drm_mode_status 2012 intel_hdmi_mode_valid(struct drm_connector *_connector, 2013 const struct drm_display_mode *mode) 2014 { 2015 struct intel_connector *connector = to_intel_connector(_connector); 2016 struct intel_display *display = to_intel_display(connector); 2017 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2018 enum drm_mode_status status; 2019 int clock = mode->clock; 2020 int max_dotclk = display->cdclk.max_dotclk_freq; 2021 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state); 2022 bool ycbcr_420_only; 2023 enum intel_output_format sink_format; 2024 2025 status = intel_cpu_transcoder_mode_valid(display, mode); 2026 if (status != MODE_OK) 2027 return status; 2028 2029 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) 2030 clock *= 2; 2031 2032 if (clock > max_dotclk) 2033 return MODE_CLOCK_HIGH; 2034 2035 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2036 if (!has_hdmi_sink) 2037 return MODE_CLOCK_LOW; 2038 clock *= 2; 2039 } 2040 2041 /* 2042 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be 2043 * enumerated only if FRL is supported. Current platforms do not support 2044 * FRL so prune the higher resolution modes that require doctclock more 2045 * than 600MHz. 2046 */ 2047 if (clock > 600000) 2048 return MODE_CLOCK_HIGH; 2049 2050 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode); 2051 2052 if (ycbcr_420_only) 2053 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2054 else 2055 sink_format = INTEL_OUTPUT_FORMAT_RGB; 2056 2057 status = intel_pfit_mode_valid(display, mode, sink_format, 0); 2058 if (status != MODE_OK) 2059 return status; 2060 2061 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format); 2062 if (status != MODE_OK) { 2063 if (ycbcr_420_only || 2064 !connector->base.ycbcr_420_allowed || 2065 !drm_mode_is_420_also(&connector->base.display_info, mode)) 2066 return status; 2067 2068 sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2069 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, 2070 sink_format); 2071 if (status != MODE_OK) 2072 return status; 2073 } 2074 2075 return intel_mode_valid_max_plane_size(display, mode, 1); 2076 } 2077 2078 bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, 2079 int bpc, bool has_hdmi_sink) 2080 { 2081 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); 2082 struct intel_digital_connector_state *connector_state; 2083 struct intel_connector *connector; 2084 int i; 2085 2086 for_each_new_intel_connector_in_state(state, connector, connector_state, i) { 2087 if (connector_state->base.crtc != crtc_state->uapi.crtc) 2088 continue; 2089 2090 if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink, 2091 crtc_state->sink_format)) 2092 return false; 2093 } 2094 2095 return true; 2096 } 2097 2098 static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc) 2099 { 2100 struct intel_display *display = to_intel_display(crtc_state); 2101 const struct drm_display_mode *adjusted_mode = 2102 &crtc_state->hw.adjusted_mode; 2103 2104 if (!intel_hdmi_source_bpc_possible(display, bpc)) 2105 return false; 2106 2107 /* Display Wa_1405510057:icl,ehl */ 2108 if (intel_hdmi_is_ycbcr420(crtc_state) && 2109 bpc == 10 && DISPLAY_VER(display) == 11 && 2110 (adjusted_mode->crtc_hblank_end - 2111 adjusted_mode->crtc_hblank_start) % 8 == 2) 2112 return false; 2113 2114 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); 2115 } 2116 2117 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, 2118 struct intel_crtc_state *crtc_state, 2119 int clock, bool respect_downstream_limits) 2120 { 2121 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2122 int bpc; 2123 2124 /* 2125 * pipe_bpp could already be below 8bpc due to FDI 2126 * bandwidth constraints. HDMI minimum is 8bpc however. 2127 */ 2128 bpc = max(crtc_state->pipe_bpp / 3, 8); 2129 2130 /* 2131 * We will never exceed downstream TMDS clock limits while 2132 * attempting deep color. If the user insists on forcing an 2133 * out of spec mode they will have to be satisfied with 8bpc. 2134 */ 2135 if (!respect_downstream_limits) 2136 bpc = 8; 2137 2138 for (; bpc >= 8; bpc -= 2) { 2139 int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, 2140 crtc_state->sink_format); 2141 2142 if (hdmi_bpc_possible(crtc_state, bpc) && 2143 hdmi_port_clock_valid(intel_hdmi, tmds_clock, 2144 respect_downstream_limits, 2145 crtc_state->has_hdmi_sink) == MODE_OK) 2146 return bpc; 2147 } 2148 2149 return -EINVAL; 2150 } 2151 2152 static int intel_hdmi_compute_clock(struct intel_encoder *encoder, 2153 struct intel_crtc_state *crtc_state, 2154 bool respect_downstream_limits) 2155 { 2156 struct intel_display *display = to_intel_display(encoder); 2157 const struct drm_display_mode *adjusted_mode = 2158 &crtc_state->hw.adjusted_mode; 2159 int bpc, clock = adjusted_mode->crtc_clock; 2160 2161 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2162 clock *= 2; 2163 2164 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock, 2165 respect_downstream_limits); 2166 if (bpc < 0) 2167 return bpc; 2168 2169 crtc_state->port_clock = 2170 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); 2171 2172 /* 2173 * pipe_bpp could already be below 8bpc due to 2174 * FDI bandwidth constraints. We shouldn't bump it 2175 * back up to the HDMI minimum 8bpc in that case. 2176 */ 2177 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); 2178 2179 drm_dbg_kms(display->drm, 2180 "picking %d bpc for HDMI output (pipe bpp: %d)\n", 2181 bpc, crtc_state->pipe_bpp); 2182 2183 return 0; 2184 } 2185 2186 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, 2187 const struct drm_connector_state *conn_state) 2188 { 2189 const struct intel_digital_connector_state *intel_conn_state = 2190 to_intel_digital_connector_state(conn_state); 2191 const struct drm_display_mode *adjusted_mode = 2192 &crtc_state->hw.adjusted_mode; 2193 2194 /* 2195 * Our YCbCr output is always limited range. 2196 * crtc_state->limited_color_range only applies to RGB, 2197 * and it must never be set for YCbCr or we risk setting 2198 * some conflicting bits in TRANSCONF which will mess up 2199 * the colors on the monitor. 2200 */ 2201 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 2202 return false; 2203 2204 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2205 /* See CEA-861-E - 5.1 Default Encoding Parameters */ 2206 return crtc_state->has_hdmi_sink && 2207 drm_default_rgb_quant_range(adjusted_mode) == 2208 HDMI_QUANTIZATION_RANGE_LIMITED; 2209 } else { 2210 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; 2211 } 2212 } 2213 2214 static bool intel_hdmi_has_audio(struct intel_encoder *encoder, 2215 const struct intel_crtc_state *crtc_state, 2216 const struct drm_connector_state *conn_state) 2217 { 2218 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2219 const struct intel_digital_connector_state *intel_conn_state = 2220 to_intel_digital_connector_state(conn_state); 2221 2222 if (!crtc_state->has_hdmi_sink) 2223 return false; 2224 2225 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2226 return connector->base.display_info.has_audio; 2227 else 2228 return intel_conn_state->force_audio == HDMI_AUDIO_ON; 2229 } 2230 2231 static enum intel_output_format 2232 intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state, 2233 struct intel_connector *connector, 2234 bool ycbcr_420_output) 2235 { 2236 if (!crtc_state->has_hdmi_sink) 2237 return INTEL_OUTPUT_FORMAT_RGB; 2238 2239 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) 2240 return INTEL_OUTPUT_FORMAT_YCBCR420; 2241 else 2242 return INTEL_OUTPUT_FORMAT_RGB; 2243 } 2244 2245 static enum intel_output_format 2246 intel_hdmi_output_format(const struct intel_crtc_state *crtc_state) 2247 { 2248 return crtc_state->sink_format; 2249 } 2250 2251 static int intel_hdmi_compute_output_format(struct intel_encoder *encoder, 2252 struct intel_crtc_state *crtc_state, 2253 const struct drm_connector_state *conn_state, 2254 bool respect_downstream_limits) 2255 { 2256 struct intel_display *display = to_intel_display(encoder); 2257 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2258 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 2259 const struct drm_display_info *info = &connector->base.display_info; 2260 bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode); 2261 int ret; 2262 2263 crtc_state->sink_format = 2264 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); 2265 2266 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { 2267 drm_dbg_kms(display->drm, 2268 "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n"); 2269 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; 2270 } 2271 2272 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2273 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2274 if (ret) { 2275 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 2276 !crtc_state->has_hdmi_sink || 2277 !connector->base.ycbcr_420_allowed || 2278 !drm_mode_is_420_also(info, adjusted_mode)) 2279 return ret; 2280 2281 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2282 crtc_state->output_format = intel_hdmi_output_format(crtc_state); 2283 ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits); 2284 } 2285 2286 return ret; 2287 } 2288 2289 static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state) 2290 { 2291 return crtc_state->uapi.encoder_mask && 2292 !is_power_of_2(crtc_state->uapi.encoder_mask); 2293 } 2294 2295 static bool source_supports_scrambling(struct intel_encoder *encoder) 2296 { 2297 /* 2298 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and 2299 * scrambling is supported. 2300 * But there seem to be cases where certain platforms that support 2301 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is 2302 * capped by VBT to less than 340MHz. 2303 * 2304 * In such cases when an HDMI2.0 sink is connected, it creates a 2305 * problem : the platform and the sink both support scrambling but the 2306 * HDMI 1.4 retimer chip doesn't. 2307 * 2308 * So go for scrambling, based on the max tmds clock taking into account, 2309 * restrictions coming from VBT. 2310 */ 2311 return intel_hdmi_source_max_tmds_clock(encoder) > 340000; 2312 } 2313 2314 bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder, 2315 const struct intel_crtc_state *crtc_state, 2316 const struct drm_connector_state *conn_state) 2317 { 2318 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); 2319 2320 return intel_has_hdmi_sink(hdmi, conn_state) && 2321 !intel_hdmi_is_cloned(crtc_state); 2322 } 2323 2324 int intel_hdmi_compute_config(struct intel_encoder *encoder, 2325 struct intel_crtc_state *pipe_config, 2326 struct drm_connector_state *conn_state) 2327 { 2328 struct intel_display *display = to_intel_display(encoder); 2329 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 2330 struct intel_connector *connector = to_intel_connector(conn_state->connector); 2331 struct drm_scdc *scdc = &connector->base.display_info.hdmi.scdc; 2332 int ret; 2333 2334 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2335 return -EINVAL; 2336 2337 if (!connector->base.interlace_allowed && 2338 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2339 return -EINVAL; 2340 2341 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2342 2343 if (pipe_config->has_hdmi_sink) 2344 pipe_config->has_infoframe = true; 2345 2346 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2347 pipe_config->pixel_multiplier = 2; 2348 2349 if (!intel_link_bw_compute_pipe_bpp(pipe_config)) 2350 return -EINVAL; 2351 2352 pipe_config->has_audio = 2353 intel_hdmi_has_audio(encoder, pipe_config, conn_state) && 2354 intel_audio_compute_config(encoder, pipe_config, conn_state); 2355 2356 /* 2357 * Try to respect downstream TMDS clock limits first, if 2358 * that fails assume the user might know something we don't. 2359 */ 2360 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true); 2361 if (ret) 2362 ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false); 2363 if (ret) { 2364 drm_dbg_kms(display->drm, 2365 "unsupported HDMI clock (%d kHz), rejecting mode\n", 2366 pipe_config->hw.adjusted_mode.crtc_clock); 2367 return ret; 2368 } 2369 2370 if (intel_hdmi_is_ycbcr420(pipe_config)) { 2371 ret = intel_pfit_compute_config(pipe_config, conn_state); 2372 if (ret) 2373 return ret; 2374 } 2375 2376 pipe_config->limited_color_range = 2377 intel_hdmi_limited_color_range(pipe_config, conn_state); 2378 2379 if (conn_state->picture_aspect_ratio) 2380 adjusted_mode->picture_aspect_ratio = 2381 conn_state->picture_aspect_ratio; 2382 2383 pipe_config->lane_count = 4; 2384 2385 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { 2386 if (scdc->scrambling.low_rates) 2387 pipe_config->hdmi_scrambling = true; 2388 2389 if (pipe_config->port_clock > 340000) { 2390 pipe_config->hdmi_scrambling = true; 2391 pipe_config->hdmi_high_tmds_clock_ratio = true; 2392 } 2393 } 2394 2395 intel_vrr_compute_config(pipe_config, conn_state); 2396 2397 intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, 2398 conn_state); 2399 2400 if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { 2401 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); 2402 return -EINVAL; 2403 } 2404 2405 if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { 2406 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); 2407 return -EINVAL; 2408 } 2409 2410 if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { 2411 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); 2412 return -EINVAL; 2413 } 2414 2415 if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { 2416 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); 2417 return -EINVAL; 2418 } 2419 2420 return 0; 2421 } 2422 2423 void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder) 2424 { 2425 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2426 2427 /* 2428 * Give a hand to buggy BIOSen which forget to turn 2429 * the TMDS output buffers back on after a reboot. 2430 */ 2431 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); 2432 } 2433 2434 static void 2435 intel_hdmi_unset_edid(struct drm_connector *_connector) 2436 { 2437 struct intel_connector *connector = to_intel_connector(_connector); 2438 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2439 2440 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; 2441 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; 2442 2443 drm_edid_free(connector->detect_edid); 2444 connector->detect_edid = NULL; 2445 } 2446 2447 static void 2448 intel_hdmi_dp_dual_mode_detect(struct drm_connector *_connector) 2449 { 2450 struct intel_connector *connector = to_intel_connector(_connector); 2451 struct intel_display *display = to_intel_display(connector); 2452 struct intel_hdmi *hdmi = intel_attached_hdmi(connector); 2453 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; 2454 struct i2c_adapter *ddc = connector->base.ddc; 2455 enum drm_dp_dual_mode_type type; 2456 2457 type = drm_dp_dual_mode_detect(display->drm, ddc); 2458 2459 /* 2460 * Type 1 DVI adaptors are not required to implement any 2461 * registers, so we can't always detect their presence. 2462 * Ideally we should be able to check the state of the 2463 * CONFIG1 pin, but no such luck on our hardware. 2464 * 2465 * The only method left to us is to check the VBT to see 2466 * if the port is a dual mode capable DP port. 2467 */ 2468 if (type == DRM_DP_DUAL_MODE_UNKNOWN) { 2469 if (!connector->base.force && 2470 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2471 drm_dbg_kms(display->drm, 2472 "Assuming DP dual mode adaptor presence based on VBT\n"); 2473 type = DRM_DP_DUAL_MODE_TYPE1_DVI; 2474 } else { 2475 type = DRM_DP_DUAL_MODE_NONE; 2476 } 2477 } 2478 2479 if (type == DRM_DP_DUAL_MODE_NONE) 2480 return; 2481 2482 hdmi->dp_dual_mode.type = type; 2483 hdmi->dp_dual_mode.max_tmds_clock = 2484 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); 2485 2486 drm_dbg_kms(display->drm, 2487 "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", 2488 drm_dp_get_dual_mode_type_name(type), 2489 hdmi->dp_dual_mode.max_tmds_clock); 2490 2491 /* Older VBTs are often buggy and can't be trusted :( Play it safe. */ 2492 if ((DISPLAY_VER(display) >= 8 || display->platform.haswell) && 2493 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { 2494 drm_dbg_kms(display->drm, 2495 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); 2496 hdmi->dp_dual_mode.max_tmds_clock = 0; 2497 } 2498 } 2499 2500 static bool 2501 intel_hdmi_set_edid(struct drm_connector *_connector) 2502 { 2503 struct intel_connector *connector = to_intel_connector(_connector); 2504 struct intel_display *display = to_intel_display(connector); 2505 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2506 struct i2c_adapter *ddc = connector->base.ddc; 2507 intel_wakeref_t wakeref; 2508 const struct drm_edid *drm_edid; 2509 bool connected = false; 2510 2511 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2512 2513 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2514 2515 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { 2516 drm_dbg_kms(display->drm, 2517 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); 2518 intel_gmbus_force_bit(ddc, true); 2519 drm_edid = drm_edid_read_ddc(&connector->base, ddc); 2520 intel_gmbus_force_bit(ddc, false); 2521 } 2522 2523 /* Below we depend on display info having been updated */ 2524 drm_edid_connector_update(&connector->base, drm_edid); 2525 2526 connector->detect_edid = drm_edid; 2527 2528 if (drm_edid_is_digital(drm_edid)) { 2529 intel_hdmi_dp_dual_mode_detect(&connector->base); 2530 2531 connected = true; 2532 } 2533 2534 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2535 2536 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, 2537 connector->base.display_info.source_physical_address); 2538 2539 return connected; 2540 } 2541 2542 static enum drm_connector_status 2543 intel_hdmi_detect(struct drm_connector *_connector, bool force) 2544 { 2545 struct intel_connector *connector = to_intel_connector(_connector); 2546 struct intel_display *display = to_intel_display(connector); 2547 enum drm_connector_status status = connector_status_disconnected; 2548 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 2549 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; 2550 intel_wakeref_t wakeref; 2551 2552 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2553 connector->base.base.id, connector->base.name); 2554 2555 if (!intel_display_device_enabled(display)) 2556 return connector_status_disconnected; 2557 2558 if (!intel_display_driver_check_access(display)) 2559 return connector->base.status; 2560 2561 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 2562 2563 if (DISPLAY_VER(display) >= 11 && 2564 !intel_digital_port_connected(encoder)) 2565 goto out; 2566 2567 intel_hdmi_unset_edid(&connector->base); 2568 2569 if (intel_hdmi_set_edid(&connector->base)) 2570 status = connector_status_connected; 2571 2572 out: 2573 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 2574 2575 if (status != connector_status_connected) 2576 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); 2577 2578 return status; 2579 } 2580 2581 static void 2582 intel_hdmi_force(struct drm_connector *_connector) 2583 { 2584 struct intel_connector *connector = to_intel_connector(_connector); 2585 struct intel_display *display = to_intel_display(connector); 2586 2587 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", 2588 connector->base.base.id, connector->base.name); 2589 2590 if (!intel_display_driver_check_access(display)) 2591 return; 2592 2593 intel_hdmi_unset_edid(&connector->base); 2594 2595 if (connector->base.status != connector_status_connected) 2596 return; 2597 2598 intel_hdmi_set_edid(&connector->base); 2599 } 2600 2601 static int intel_hdmi_get_modes(struct drm_connector *_connector) 2602 { 2603 struct intel_connector *connector = to_intel_connector(_connector); 2604 2605 /* drm_edid_connector_update() done in ->detect() or ->force() */ 2606 return drm_edid_connector_add_modes(&connector->base); 2607 } 2608 2609 static int 2610 intel_hdmi_connector_register(struct drm_connector *_connector) 2611 { 2612 struct intel_connector *connector = to_intel_connector(_connector); 2613 int ret; 2614 2615 ret = intel_connector_register(&connector->base); 2616 if (ret) 2617 return ret; 2618 2619 return ret; 2620 } 2621 2622 static void intel_hdmi_connector_unregister(struct drm_connector *_connector) 2623 { 2624 struct intel_connector *connector = to_intel_connector(_connector); 2625 struct cec_notifier *n = intel_attached_hdmi(connector)->cec_notifier; 2626 2627 cec_notifier_conn_unregister(n); 2628 2629 intel_connector_unregister(&connector->base); 2630 } 2631 2632 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 2633 .detect = intel_hdmi_detect, 2634 .force = intel_hdmi_force, 2635 .fill_modes = drm_helper_probe_single_connector_modes, 2636 .atomic_get_property = intel_digital_connector_atomic_get_property, 2637 .atomic_set_property = intel_digital_connector_atomic_set_property, 2638 .late_register = intel_hdmi_connector_register, 2639 .early_unregister = intel_hdmi_connector_unregister, 2640 .destroy = intel_connector_destroy, 2641 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2642 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 2643 }; 2644 2645 static int intel_hdmi_connector_atomic_check(struct drm_connector *_connector, 2646 struct drm_atomic_state *state) 2647 { 2648 struct intel_connector *connector = to_intel_connector(_connector); 2649 struct intel_display *display = to_intel_display(connector); 2650 2651 if (HAS_DDI(display)) 2652 return intel_digital_connector_atomic_check(&connector->base, state); 2653 else 2654 return g4x_hdmi_connector_atomic_check(&connector->base, state); 2655 } 2656 2657 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 2658 .get_modes = intel_hdmi_get_modes, 2659 .mode_valid = intel_hdmi_mode_valid, 2660 .atomic_check = intel_hdmi_connector_atomic_check, 2661 }; 2662 2663 static void 2664 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *_connector) 2665 { 2666 struct intel_connector *connector = to_intel_connector(_connector); 2667 struct intel_display *display = to_intel_display(intel_hdmi); 2668 2669 intel_attach_force_audio_property(&connector->base); 2670 intel_attach_broadcast_rgb_property(&connector->base); 2671 intel_attach_aspect_ratio_property(&connector->base); 2672 2673 intel_attach_hdmi_colorspace_property(&connector->base); 2674 drm_connector_attach_content_type_property(&connector->base); 2675 2676 if (DISPLAY_VER(display) >= 10) 2677 drm_connector_attach_hdr_output_metadata_property(&connector->base); 2678 2679 if (!HAS_GMCH(display)) 2680 drm_connector_attach_max_bpc_property(&connector->base, 8, 12); 2681 } 2682 2683 /* 2684 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup 2685 * @encoder: intel_encoder 2686 * @connector: drm_connector 2687 * @high_tmds_clock_ratio = bool to indicate if the function needs to set 2688 * or reset the high tmds clock ratio for scrambling 2689 * @scrambling: bool to Indicate if the function needs to set or reset 2690 * sink scrambling 2691 * 2692 * This function handles scrambling on HDMI 2.0 capable sinks. 2693 * If required clock rate is > 340 Mhz && scrambling is supported by sink 2694 * it enables scrambling. This should be called before enabling the HDMI 2695 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't 2696 * detect a scrambled clock within 100 ms. 2697 * 2698 * Returns: 2699 * True on success, false on failure. 2700 */ 2701 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, 2702 struct drm_connector *_connector, 2703 bool high_tmds_clock_ratio, 2704 bool scrambling) 2705 { 2706 struct intel_connector *connector = to_intel_connector(_connector); 2707 struct intel_display *display = to_intel_display(encoder); 2708 struct drm_scrambling *sink_scrambling = 2709 &connector->base.display_info.hdmi.scdc.scrambling; 2710 2711 if (!sink_scrambling->supported) 2712 return true; 2713 2714 drm_dbg_kms(display->drm, 2715 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", 2716 connector->base.base.id, connector->base.name, 2717 str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10); 2718 2719 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ 2720 return drm_scdc_set_high_tmds_clock_ratio(&connector->base, high_tmds_clock_ratio) && 2721 drm_scdc_set_scrambling(&connector->base, scrambling); 2722 } 2723 2724 static u8 chv_encoder_to_ddc_pin(struct intel_encoder *encoder) 2725 { 2726 enum port port = encoder->port; 2727 u8 ddc_pin; 2728 2729 switch (port) { 2730 case PORT_B: 2731 ddc_pin = GMBUS_PIN_DPB; 2732 break; 2733 case PORT_C: 2734 ddc_pin = GMBUS_PIN_DPC; 2735 break; 2736 case PORT_D: 2737 ddc_pin = GMBUS_PIN_DPD_CHV; 2738 break; 2739 default: 2740 MISSING_CASE(port); 2741 ddc_pin = GMBUS_PIN_DPB; 2742 break; 2743 } 2744 return ddc_pin; 2745 } 2746 2747 static u8 bxt_encoder_to_ddc_pin(struct intel_encoder *encoder) 2748 { 2749 enum port port = encoder->port; 2750 u8 ddc_pin; 2751 2752 switch (port) { 2753 case PORT_B: 2754 ddc_pin = GMBUS_PIN_1_BXT; 2755 break; 2756 case PORT_C: 2757 ddc_pin = GMBUS_PIN_2_BXT; 2758 break; 2759 default: 2760 MISSING_CASE(port); 2761 ddc_pin = GMBUS_PIN_1_BXT; 2762 break; 2763 } 2764 return ddc_pin; 2765 } 2766 2767 static u8 cnp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2768 { 2769 enum port port = encoder->port; 2770 u8 ddc_pin; 2771 2772 switch (port) { 2773 case PORT_B: 2774 ddc_pin = GMBUS_PIN_1_BXT; 2775 break; 2776 case PORT_C: 2777 ddc_pin = GMBUS_PIN_2_BXT; 2778 break; 2779 case PORT_D: 2780 ddc_pin = GMBUS_PIN_4_CNP; 2781 break; 2782 case PORT_F: 2783 ddc_pin = GMBUS_PIN_3_BXT; 2784 break; 2785 default: 2786 MISSING_CASE(port); 2787 ddc_pin = GMBUS_PIN_1_BXT; 2788 break; 2789 } 2790 return ddc_pin; 2791 } 2792 2793 static u8 icl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2794 { 2795 struct intel_display *display = to_intel_display(encoder); 2796 enum port port = encoder->port; 2797 2798 if (intel_encoder_is_combo(encoder)) 2799 return GMBUS_PIN_1_BXT + port; 2800 else if (intel_encoder_is_tc(encoder)) 2801 return GMBUS_PIN_9_TC1_ICP + intel_encoder_to_tc(encoder); 2802 2803 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); 2804 return GMBUS_PIN_2_BXT; 2805 } 2806 2807 static u8 mcc_encoder_to_ddc_pin(struct intel_encoder *encoder) 2808 { 2809 enum phy phy = intel_encoder_to_phy(encoder); 2810 u8 ddc_pin; 2811 2812 switch (phy) { 2813 case PHY_A: 2814 ddc_pin = GMBUS_PIN_1_BXT; 2815 break; 2816 case PHY_B: 2817 ddc_pin = GMBUS_PIN_2_BXT; 2818 break; 2819 case PHY_C: 2820 ddc_pin = GMBUS_PIN_9_TC1_ICP; 2821 break; 2822 default: 2823 MISSING_CASE(phy); 2824 ddc_pin = GMBUS_PIN_1_BXT; 2825 break; 2826 } 2827 return ddc_pin; 2828 } 2829 2830 static u8 rkl_encoder_to_ddc_pin(struct intel_encoder *encoder) 2831 { 2832 struct intel_display *display = to_intel_display(encoder); 2833 enum phy phy = intel_encoder_to_phy(encoder); 2834 2835 WARN_ON(encoder->port == PORT_C); 2836 2837 /* 2838 * Pin mapping for RKL depends on which PCH is present. With TGP, the 2839 * final two outputs use type-c pins, even though they're actually 2840 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2841 * all outputs. 2842 */ 2843 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2844 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2845 2846 return GMBUS_PIN_1_BXT + phy; 2847 } 2848 2849 static u8 gen9bc_tgp_encoder_to_ddc_pin(struct intel_encoder *encoder) 2850 { 2851 struct intel_display *display = to_intel_display(encoder); 2852 enum phy phy = intel_encoder_to_phy(encoder); 2853 2854 drm_WARN_ON(display->drm, encoder->port == PORT_A); 2855 2856 /* 2857 * Pin mapping for GEN9 BC depends on which PCH is present. With TGP, 2858 * final two outputs use type-c pins, even though they're actually 2859 * combo outputs. With CMP, the traditional DDI A-D pins are used for 2860 * all outputs. 2861 */ 2862 if (INTEL_PCH_TYPE(display) >= PCH_TGP && phy >= PHY_C) 2863 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; 2864 2865 return GMBUS_PIN_1_BXT + phy; 2866 } 2867 2868 static u8 dg1_encoder_to_ddc_pin(struct intel_encoder *encoder) 2869 { 2870 return intel_encoder_to_phy(encoder) + 1; 2871 } 2872 2873 static u8 adls_encoder_to_ddc_pin(struct intel_encoder *encoder) 2874 { 2875 enum phy phy = intel_encoder_to_phy(encoder); 2876 2877 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); 2878 2879 /* 2880 * Pin mapping for ADL-S requires TC pins for all combo phy outputs 2881 * except first combo output. 2882 */ 2883 if (phy == PHY_A) 2884 return GMBUS_PIN_1_BXT; 2885 2886 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; 2887 } 2888 2889 static u8 g4x_encoder_to_ddc_pin(struct intel_encoder *encoder) 2890 { 2891 enum port port = encoder->port; 2892 u8 ddc_pin; 2893 2894 switch (port) { 2895 case PORT_B: 2896 ddc_pin = GMBUS_PIN_DPB; 2897 break; 2898 case PORT_C: 2899 ddc_pin = GMBUS_PIN_DPC; 2900 break; 2901 case PORT_D: 2902 ddc_pin = GMBUS_PIN_DPD; 2903 break; 2904 default: 2905 MISSING_CASE(port); 2906 ddc_pin = GMBUS_PIN_DPB; 2907 break; 2908 } 2909 return ddc_pin; 2910 } 2911 2912 static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder) 2913 { 2914 struct intel_display *display = to_intel_display(encoder); 2915 u8 ddc_pin; 2916 2917 if (display->platform.alderlake_s) 2918 ddc_pin = adls_encoder_to_ddc_pin(encoder); 2919 else if (INTEL_PCH_TYPE(display) >= PCH_DG1) 2920 ddc_pin = dg1_encoder_to_ddc_pin(encoder); 2921 else if (display->platform.rocketlake) 2922 ddc_pin = rkl_encoder_to_ddc_pin(encoder); 2923 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(display)) 2924 ddc_pin = gen9bc_tgp_encoder_to_ddc_pin(encoder); 2925 else if ((display->platform.jasperlake || display->platform.elkhartlake) && 2926 HAS_PCH_TGP(display)) 2927 ddc_pin = mcc_encoder_to_ddc_pin(encoder); 2928 else if (INTEL_PCH_TYPE(display) >= PCH_ICP) 2929 ddc_pin = icl_encoder_to_ddc_pin(encoder); 2930 else if (HAS_PCH_CNP(display)) 2931 ddc_pin = cnp_encoder_to_ddc_pin(encoder); 2932 else if (display->platform.geminilake || display->platform.broxton) 2933 ddc_pin = bxt_encoder_to_ddc_pin(encoder); 2934 else if (display->platform.cherryview) 2935 ddc_pin = chv_encoder_to_ddc_pin(encoder); 2936 else 2937 ddc_pin = g4x_encoder_to_ddc_pin(encoder); 2938 2939 return ddc_pin; 2940 } 2941 2942 static struct intel_encoder * 2943 get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin) 2944 { 2945 struct intel_display *display = to_intel_display(encoder); 2946 struct intel_encoder *other; 2947 2948 for_each_intel_encoder(display->drm, other) { 2949 struct intel_connector *connector; 2950 2951 if (other == encoder) 2952 continue; 2953 2954 if (!intel_encoder_is_dig_port(other)) 2955 continue; 2956 2957 connector = enc_to_dig_port(other)->hdmi.attached_connector; 2958 2959 if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin)) 2960 return other; 2961 } 2962 2963 return NULL; 2964 } 2965 2966 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 2967 { 2968 struct intel_display *display = to_intel_display(encoder); 2969 struct intel_encoder *other; 2970 const char *source; 2971 u8 ddc_pin; 2972 2973 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); 2974 source = "VBT"; 2975 2976 if (!ddc_pin) { 2977 ddc_pin = intel_hdmi_default_ddc_pin(encoder); 2978 source = "platform default"; 2979 } 2980 2981 if (!intel_gmbus_is_valid_pin(display, ddc_pin)) { 2982 drm_dbg_kms(display->drm, 2983 "[ENCODER:%d:%s] Invalid DDC pin %d\n", 2984 encoder->base.base.id, encoder->base.name, ddc_pin); 2985 return 0; 2986 } 2987 2988 other = get_encoder_by_ddc_pin(encoder, ddc_pin); 2989 if (other) { 2990 drm_dbg_kms(display->drm, 2991 "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n", 2992 encoder->base.base.id, encoder->base.name, ddc_pin, 2993 other->base.base.id, other->base.name); 2994 return 0; 2995 } 2996 2997 drm_dbg_kms(display->drm, 2998 "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n", 2999 encoder->base.base.id, encoder->base.name, 3000 ddc_pin, source); 3001 3002 return ddc_pin; 3003 } 3004 3005 void intel_infoframe_init(struct intel_digital_port *dig_port) 3006 { 3007 struct intel_display *display = to_intel_display(dig_port); 3008 3009 if (display->platform.valleyview || display->platform.cherryview) { 3010 dig_port->write_infoframe = vlv_write_infoframe; 3011 dig_port->read_infoframe = vlv_read_infoframe; 3012 dig_port->set_infoframes = vlv_set_infoframes; 3013 dig_port->infoframes_enabled = vlv_infoframes_enabled; 3014 } else if (display->platform.g4x) { 3015 dig_port->write_infoframe = g4x_write_infoframe; 3016 dig_port->read_infoframe = g4x_read_infoframe; 3017 dig_port->set_infoframes = g4x_set_infoframes; 3018 dig_port->infoframes_enabled = g4x_infoframes_enabled; 3019 } else if (HAS_DDI(display)) { 3020 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { 3021 dig_port->write_infoframe = lspcon_write_infoframe; 3022 dig_port->read_infoframe = lspcon_read_infoframe; 3023 dig_port->set_infoframes = lspcon_set_infoframes; 3024 dig_port->infoframes_enabled = lspcon_infoframes_enabled; 3025 } else { 3026 dig_port->write_infoframe = hsw_write_infoframe; 3027 dig_port->read_infoframe = hsw_read_infoframe; 3028 dig_port->set_infoframes = hsw_set_infoframes; 3029 dig_port->infoframes_enabled = hsw_infoframes_enabled; 3030 } 3031 } else if (HAS_PCH_IBX(display)) { 3032 dig_port->write_infoframe = ibx_write_infoframe; 3033 dig_port->read_infoframe = ibx_read_infoframe; 3034 dig_port->set_infoframes = ibx_set_infoframes; 3035 dig_port->infoframes_enabled = ibx_infoframes_enabled; 3036 } else { 3037 dig_port->write_infoframe = cpt_write_infoframe; 3038 dig_port->read_infoframe = cpt_read_infoframe; 3039 dig_port->set_infoframes = cpt_set_infoframes; 3040 dig_port->infoframes_enabled = cpt_infoframes_enabled; 3041 } 3042 } 3043 3044 bool intel_hdmi_init_connector(struct intel_digital_port *dig_port, 3045 struct intel_connector *intel_connector) 3046 { 3047 struct intel_display *display = to_intel_display(dig_port); 3048 struct drm_connector *connector = &intel_connector->base; 3049 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; 3050 struct intel_encoder *intel_encoder = &dig_port->base; 3051 struct drm_device *dev = intel_encoder->base.dev; 3052 enum port port = intel_encoder->port; 3053 struct cec_connector_info conn_info; 3054 u8 ddc_pin; 3055 3056 drm_dbg_kms(display->drm, 3057 "Adding HDMI connector on [ENCODER:%d:%s]\n", 3058 intel_encoder->base.base.id, intel_encoder->base.name); 3059 3060 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) 3061 return false; 3062 3063 if (drm_WARN(dev, dig_port->max_lanes < 4, 3064 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", 3065 dig_port->max_lanes, intel_encoder->base.base.id, 3066 intel_encoder->base.name)) 3067 return false; 3068 3069 ddc_pin = intel_hdmi_ddc_pin(intel_encoder); 3070 if (!ddc_pin) 3071 return false; 3072 3073 drm_connector_init_with_ddc(dev, connector, 3074 &intel_hdmi_connector_funcs, 3075 DRM_MODE_CONNECTOR_HDMIA, 3076 intel_gmbus_get_adapter(display, ddc_pin)); 3077 3078 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 3079 3080 if (DISPLAY_VER(display) < 12) 3081 connector->interlace_allowed = true; 3082 3083 connector->stereo_allowed = true; 3084 3085 if (DISPLAY_VER(display) >= 10) 3086 connector->ycbcr_420_allowed = true; 3087 3088 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 3089 intel_connector->base.polled = intel_connector->polled; 3090 3091 if (HAS_DDI(display)) 3092 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 3093 else 3094 intel_connector->get_hw_state = intel_connector_get_hw_state; 3095 3096 intel_hdmi_add_properties(intel_hdmi, connector); 3097 3098 intel_connector_attach_encoder(intel_connector, intel_encoder); 3099 intel_hdmi->attached_connector = intel_connector; 3100 3101 if (is_hdcp_supported(display, port)) { 3102 int ret = intel_hdcp_init(intel_connector, dig_port, 3103 &intel_hdmi_hdcp_shim); 3104 if (ret) 3105 drm_dbg_kms(display->drm, 3106 "HDCP init failed, skipping.\n"); 3107 } 3108 3109 cec_fill_conn_info_from_drm(&conn_info, connector); 3110 3111 intel_hdmi->cec_notifier = 3112 cec_notifier_conn_register(dev->dev, port_identifier(port), 3113 &conn_info); 3114 if (!intel_hdmi->cec_notifier) 3115 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); 3116 3117 return true; 3118 } 3119 3120 /* 3121 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height 3122 * @vactive: Vactive of a display mode 3123 * 3124 * @return: appropriate dsc slice height for a given mode. 3125 */ 3126 int intel_hdmi_dsc_get_slice_height(int vactive) 3127 { 3128 int slice_height; 3129 3130 /* 3131 * Slice Height determination : HDMI2.1 Section 7.7.5.2 3132 * Select smallest slice height >=96, that results in a valid PPS and 3133 * requires minimum padding lines required for final slice. 3134 * 3135 * Assumption : Vactive is even. 3136 */ 3137 for (slice_height = 96; slice_height <= vactive; slice_height += 2) 3138 if (vactive % slice_height == 0) 3139 return slice_height; 3140 3141 return 0; 3142 } 3143 3144 /* 3145 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder 3146 * and dsc decoder capabilities 3147 * 3148 * @crtc_state: intel crtc_state 3149 * @src_max_slices: maximum slices supported by the DSC encoder 3150 * @src_max_slice_width: maximum slice width supported by DSC encoder 3151 * @hdmi_max_slices: maximum slices supported by sink DSC decoder 3152 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink 3153 * 3154 * @return: num of dsc slices that can be supported by the dsc encoder 3155 * and decoder. 3156 */ 3157 int 3158 intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state, 3159 int src_max_slices, int src_max_slice_width, 3160 int hdmi_max_slices, int hdmi_throughput) 3161 { 3162 /* Pixel rates in KPixels/sec */ 3163 #define HDMI_DSC_PEAK_PIXEL_RATE 2720000 3164 /* 3165 * Rates at which the source and sink are required to process pixels in each 3166 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz. 3167 */ 3168 #define HDMI_DSC_MAX_ENC_THROUGHPUT_0 340000 3169 #define HDMI_DSC_MAX_ENC_THROUGHPUT_1 400000 3170 3171 /* Spec limits the slice width to 2720 pixels */ 3172 #define MAX_HDMI_SLICE_WIDTH 2720 3173 int kslice_adjust; 3174 int adjusted_clk_khz; 3175 int min_slices; 3176 int target_slices; 3177 int max_throughput; /* max clock freq. in khz per slice */ 3178 int max_slice_width; 3179 int slice_width; 3180 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; 3181 3182 if (!hdmi_throughput) 3183 return 0; 3184 3185 /* 3186 * Slice Width determination : HDMI2.1 Section 7.7.5.1 3187 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as 3188 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later 3189 * dividing adjusted clock value by 10. 3190 */ 3191 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3192 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 3193 kslice_adjust = 10; 3194 else 3195 kslice_adjust = 5; 3196 3197 /* 3198 * As per spec, the rate at which the source and the sink process 3199 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz. 3200 * This depends upon the pixel clock rate and output formats 3201 * (kslice adjust). 3202 * If pixel clock * kslice adjust >= 2720MHz slices can be processed 3203 * at max 340MHz, otherwise they can be processed at max 400MHz. 3204 */ 3205 3206 adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10); 3207 3208 if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE) 3209 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0; 3210 else 3211 max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1; 3212 3213 /* 3214 * Taking into account the sink's capability for maximum 3215 * clock per slice (in MHz) as read from HF-VSDB. 3216 */ 3217 max_throughput = min(max_throughput, hdmi_throughput * 1000); 3218 3219 min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput); 3220 max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width); 3221 3222 /* 3223 * Keep on increasing the num of slices/line, starting from min_slices 3224 * per line till we get such a number, for which the slice_width is 3225 * just less than max_slice_width. The slices/line selected should be 3226 * less than or equal to the max horizontal slices that the combination 3227 * of PCON encoder and HDMI decoder can support. 3228 */ 3229 slice_width = max_slice_width; 3230 3231 do { 3232 if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1) 3233 target_slices = 1; 3234 else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2) 3235 target_slices = 2; 3236 else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4) 3237 target_slices = 4; 3238 else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8) 3239 target_slices = 8; 3240 else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12) 3241 target_slices = 12; 3242 else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16) 3243 target_slices = 16; 3244 else 3245 return 0; 3246 3247 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); 3248 if (slice_width >= max_slice_width) 3249 min_slices = target_slices + 1; 3250 } while (slice_width >= max_slice_width); 3251 3252 return target_slices; 3253 } 3254 3255 /* 3256 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on 3257 * source and sink capabilities. 3258 * 3259 * @src_fraction_bpp: fractional bpp supported by the source 3260 * @slice_width: dsc slice width supported by the source and sink 3261 * @num_slices: num of slices supported by the source and sink 3262 * @output_format: video output format 3263 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting 3264 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink 3265 * 3266 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel 3267 */ 3268 int 3269 intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices, 3270 int output_format, bool hdmi_all_bpp, 3271 int hdmi_max_chunk_bytes) 3272 { 3273 int max_dsc_bpp, min_dsc_bpp; 3274 int target_bytes; 3275 bool bpp_found = false; 3276 int bpp_decrement_x16; 3277 int bpp_target; 3278 int bpp_target_x16; 3279 3280 /* 3281 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec 3282 * Start with the max bpp and keep on decrementing with 3283 * fractional bpp, if supported by PCON DSC encoder 3284 * 3285 * for each bpp we check if no of bytes can be supported by HDMI sink 3286 */ 3287 3288 /* Assuming: bpc as 8*/ 3289 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 3290 min_dsc_bpp = 6; 3291 max_dsc_bpp = 3 * 4; /* 3*bpc/2 */ 3292 } else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || 3293 output_format == INTEL_OUTPUT_FORMAT_RGB) { 3294 min_dsc_bpp = 8; 3295 max_dsc_bpp = 3 * 8; /* 3*bpc */ 3296 } else { 3297 /* Assuming 4:2:2 encoding */ 3298 min_dsc_bpp = 7; 3299 max_dsc_bpp = 2 * 8; /* 2*bpc */ 3300 } 3301 3302 /* 3303 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink 3304 * Section 7.7.34 : Source shall not enable compressed Video 3305 * Transport with bpp_target settings above 12 bpp unless 3306 * DSC_all_bpp is set to 1. 3307 */ 3308 if (!hdmi_all_bpp) 3309 max_dsc_bpp = min(max_dsc_bpp, 12); 3310 3311 /* 3312 * The Sink has a limit of compressed data in bytes for a scanline, 3313 * as described in max_chunk_bytes field in HFVSDB block of edid. 3314 * The no. of bytes depend on the target bits per pixel that the 3315 * source configures. So we start with the max_bpp and calculate 3316 * the target_chunk_bytes. We keep on decrementing the target_bpp, 3317 * till we get the target_chunk_bytes just less than what the sink's 3318 * max_chunk_bytes, or else till we reach the min_dsc_bpp. 3319 * 3320 * The decrement is according to the fractional support from PCON DSC 3321 * encoder. For fractional BPP we use bpp_target as a multiple of 16. 3322 * 3323 * bpp_target_x16 = bpp_target * 16 3324 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps 3325 * {1/16, 1/8, 1/4, 1/2, 1} respectively. 3326 */ 3327 3328 bpp_target = max_dsc_bpp; 3329 3330 /* src does not support fractional bpp implies decrement by 16 for bppx16 */ 3331 if (!src_fractional_bpp) 3332 src_fractional_bpp = 1; 3333 bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp); 3334 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; 3335 3336 while (bpp_target_x16 > (min_dsc_bpp * 16)) { 3337 int bpp; 3338 3339 bpp = DIV_ROUND_UP(bpp_target_x16, 16); 3340 target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8); 3341 if (target_bytes <= hdmi_max_chunk_bytes) { 3342 bpp_found = true; 3343 break; 3344 } 3345 bpp_target_x16 -= bpp_decrement_x16; 3346 } 3347 if (bpp_found) 3348 return bpp_target_x16; 3349 3350 return 0; 3351 } 3352