xref: /linux/drivers/gpu/drm/i915/display/intel_hdcp_shim.h (revision 79d2e1919a2728ef49d938eb20ebd5903c14dfb0)
1 /* SPDX-License-Identifier: MIT */
2 /* Copyright © 2024 Intel Corporation */
3 
4 #ifndef __INTEL_HDCP_SHIM_H__
5 #define __INTEL_HDCP_SHIM_H__
6 
7 #include <linux/types.h>
8 
9 #include <drm/intel/i915_hdcp_interface.h>
10 
11 enum transcoder;
12 struct intel_connector;
13 struct intel_digital_port;
14 
15 enum check_link_response {
16 	HDCP_LINK_PROTECTED	= 0,
17 	HDCP_TOPOLOGY_CHANGE,
18 	HDCP_LINK_INTEGRITY_FAILURE,
19 	HDCP_REAUTH_REQUEST
20 };
21 
22 /*
23  * This structure serves as a translation layer between the generic HDCP code
24  * and the bus-specific code. What that means is that HDCP over HDMI differs
25  * from HDCP over DP, so to account for these differences, we need to
26  * communicate with the receiver through this shim.
27  *
28  * For completeness, the 2 buses differ in the following ways:
29  *	- DP AUX vs. DDC
30  *		HDCP registers on the receiver are set via DP AUX for DP, and
31  *		they are set via DDC for HDMI.
32  *	- Receiver register offsets
33  *		The offsets of the registers are different for DP vs. HDMI
34  *	- Receiver register masks/offsets
35  *		For instance, the ready bit for the KSV fifo is in a different
36  *		place on DP vs HDMI
37  *	- Receiver register names
38  *		Seriously. In the DP spec, the 16-bit register containing
39  *		downstream information is called BINFO, on HDMI it's called
40  *		BSTATUS. To confuse matters further, DP has a BSTATUS register
41  *		with a completely different definition.
42  *	- KSV FIFO
43  *		On HDMI, the ksv fifo is read all at once, whereas on DP it must
44  *		be read 3 keys at a time
45  *	- Aksv output
46  *		Since Aksv is hidden in hardware, there's different procedures
47  *		to send it over DP AUX vs DDC
48  */
49 struct intel_hdcp_shim {
50 	/* Outputs the transmitter's An and Aksv values to the receiver. */
51 	int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an);
52 
53 	/* Reads the receiver's key selection vector */
54 	int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv);
55 
56 	/*
57 	 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
58 	 * definitions are the same in the respective specs, but the names are
59 	 * different. Call it BSTATUS since that's the name the HDMI spec
60 	 * uses and it was there first.
61 	 */
62 	int (*read_bstatus)(struct intel_digital_port *dig_port,
63 			    u8 *bstatus);
64 
65 	/* Determines whether a repeater is present downstream */
66 	int (*repeater_present)(struct intel_digital_port *dig_port,
67 				bool *repeater_present);
68 
69 	/* Reads the receiver's Ri' value */
70 	int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri);
71 
72 	/* Determines if the receiver's KSV FIFO is ready for consumption */
73 	int (*read_ksv_ready)(struct intel_digital_port *dig_port,
74 			      bool *ksv_ready);
75 
76 	/* Reads the ksv fifo for num_downstream devices */
77 	int (*read_ksv_fifo)(struct intel_digital_port *dig_port,
78 			     int num_downstream, u8 *ksv_fifo);
79 
80 	/* Reads a 32-bit part of V' from the receiver */
81 	int (*read_v_prime_part)(struct intel_digital_port *dig_port,
82 				 int i, u32 *part);
83 
84 	/* Enables HDCP signalling on the port */
85 	int (*toggle_signalling)(struct intel_digital_port *dig_port,
86 				 enum transcoder cpu_transcoder,
87 				 bool enable);
88 
89 	/* Enable/Disable stream encryption on DP MST Transport Link */
90 	int (*stream_encryption)(struct intel_connector *connector,
91 				 bool enable);
92 
93 	/* Ensures the link is still protected */
94 	bool (*check_link)(struct intel_digital_port *dig_port,
95 			   struct intel_connector *connector);
96 
97 	/* Detects panel's hdcp capability. This is optional for HDMI. */
98 	int (*hdcp_get_capability)(struct intel_digital_port *dig_port,
99 				   bool *hdcp_capable);
100 
101 	/* HDCP adaptation(DP/HDMI) required on the port */
102 	enum hdcp_wired_protocol protocol;
103 
104 	/* Detects whether sink is HDCP2.2 capable */
105 	int (*hdcp_2_2_get_capability)(struct intel_connector *connector,
106 				       bool *capable);
107 
108 	/* Write HDCP2.2 messages */
109 	int (*write_2_2_msg)(struct intel_connector *connector,
110 			     void *buf, size_t size);
111 
112 	/* Read HDCP2.2 messages */
113 	int (*read_2_2_msg)(struct intel_connector *connector,
114 			    u8 msg_id, void *buf, size_t size);
115 
116 	/*
117 	 * Implementation of DP HDCP2.2 Errata for the communication of stream
118 	 * type to Receivers. In DP HDCP2.2 Stream type is one of the input to
119 	 * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI.
120 	 */
121 	int (*config_stream_type)(struct intel_connector *connector,
122 				  bool is_repeater, u8 type);
123 
124 	/* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
125 	int (*stream_2_2_encryption)(struct intel_connector *connector,
126 				     bool enable);
127 
128 	/* HDCP2.2 Link Integrity Check */
129 	int (*check_2_2_link)(struct intel_digital_port *dig_port,
130 			      struct intel_connector *connector);
131 
132 	/* HDCP remote sink cap */
133 	int (*get_remote_hdcp_capability)(struct intel_connector *connector,
134 					  bool *hdcp_capable, bool *hdcp2_capable);
135 };
136 
137 #endif /* __INTEL_HDCP_SHIM_H__ */
138