1*c0e08c20SJani Nikula /* SPDX-License-Identifier: MIT */ 2*c0e08c20SJani Nikula /* Copyright © 2024 Intel Corporation */ 3*c0e08c20SJani Nikula 4*c0e08c20SJani Nikula #ifndef __INTEL_HDCP_SHIM_H__ 5*c0e08c20SJani Nikula #define __INTEL_HDCP_SHIM_H__ 6*c0e08c20SJani Nikula 7*c0e08c20SJani Nikula #include <linux/types.h> 8*c0e08c20SJani Nikula 9*c0e08c20SJani Nikula #include <drm/intel/i915_hdcp_interface.h> 10*c0e08c20SJani Nikula 11*c0e08c20SJani Nikula enum transcoder; 12*c0e08c20SJani Nikula struct intel_connector; 13*c0e08c20SJani Nikula struct intel_digital_port; 14*c0e08c20SJani Nikula 15*c0e08c20SJani Nikula enum check_link_response { 16*c0e08c20SJani Nikula HDCP_LINK_PROTECTED = 0, 17*c0e08c20SJani Nikula HDCP_TOPOLOGY_CHANGE, 18*c0e08c20SJani Nikula HDCP_LINK_INTEGRITY_FAILURE, 19*c0e08c20SJani Nikula HDCP_REAUTH_REQUEST 20*c0e08c20SJani Nikula }; 21*c0e08c20SJani Nikula 22*c0e08c20SJani Nikula /* 23*c0e08c20SJani Nikula * This structure serves as a translation layer between the generic HDCP code 24*c0e08c20SJani Nikula * and the bus-specific code. What that means is that HDCP over HDMI differs 25*c0e08c20SJani Nikula * from HDCP over DP, so to account for these differences, we need to 26*c0e08c20SJani Nikula * communicate with the receiver through this shim. 27*c0e08c20SJani Nikula * 28*c0e08c20SJani Nikula * For completeness, the 2 buses differ in the following ways: 29*c0e08c20SJani Nikula * - DP AUX vs. DDC 30*c0e08c20SJani Nikula * HDCP registers on the receiver are set via DP AUX for DP, and 31*c0e08c20SJani Nikula * they are set via DDC for HDMI. 32*c0e08c20SJani Nikula * - Receiver register offsets 33*c0e08c20SJani Nikula * The offsets of the registers are different for DP vs. HDMI 34*c0e08c20SJani Nikula * - Receiver register masks/offsets 35*c0e08c20SJani Nikula * For instance, the ready bit for the KSV fifo is in a different 36*c0e08c20SJani Nikula * place on DP vs HDMI 37*c0e08c20SJani Nikula * - Receiver register names 38*c0e08c20SJani Nikula * Seriously. In the DP spec, the 16-bit register containing 39*c0e08c20SJani Nikula * downstream information is called BINFO, on HDMI it's called 40*c0e08c20SJani Nikula * BSTATUS. To confuse matters further, DP has a BSTATUS register 41*c0e08c20SJani Nikula * with a completely different definition. 42*c0e08c20SJani Nikula * - KSV FIFO 43*c0e08c20SJani Nikula * On HDMI, the ksv fifo is read all at once, whereas on DP it must 44*c0e08c20SJani Nikula * be read 3 keys at a time 45*c0e08c20SJani Nikula * - Aksv output 46*c0e08c20SJani Nikula * Since Aksv is hidden in hardware, there's different procedures 47*c0e08c20SJani Nikula * to send it over DP AUX vs DDC 48*c0e08c20SJani Nikula */ 49*c0e08c20SJani Nikula struct intel_hdcp_shim { 50*c0e08c20SJani Nikula /* Outputs the transmitter's An and Aksv values to the receiver. */ 51*c0e08c20SJani Nikula int (*write_an_aksv)(struct intel_digital_port *dig_port, u8 *an); 52*c0e08c20SJani Nikula 53*c0e08c20SJani Nikula /* Reads the receiver's key selection vector */ 54*c0e08c20SJani Nikula int (*read_bksv)(struct intel_digital_port *dig_port, u8 *bksv); 55*c0e08c20SJani Nikula 56*c0e08c20SJani Nikula /* 57*c0e08c20SJani Nikula * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The 58*c0e08c20SJani Nikula * definitions are the same in the respective specs, but the names are 59*c0e08c20SJani Nikula * different. Call it BSTATUS since that's the name the HDMI spec 60*c0e08c20SJani Nikula * uses and it was there first. 61*c0e08c20SJani Nikula */ 62*c0e08c20SJani Nikula int (*read_bstatus)(struct intel_digital_port *dig_port, 63*c0e08c20SJani Nikula u8 *bstatus); 64*c0e08c20SJani Nikula 65*c0e08c20SJani Nikula /* Determines whether a repeater is present downstream */ 66*c0e08c20SJani Nikula int (*repeater_present)(struct intel_digital_port *dig_port, 67*c0e08c20SJani Nikula bool *repeater_present); 68*c0e08c20SJani Nikula 69*c0e08c20SJani Nikula /* Reads the receiver's Ri' value */ 70*c0e08c20SJani Nikula int (*read_ri_prime)(struct intel_digital_port *dig_port, u8 *ri); 71*c0e08c20SJani Nikula 72*c0e08c20SJani Nikula /* Determines if the receiver's KSV FIFO is ready for consumption */ 73*c0e08c20SJani Nikula int (*read_ksv_ready)(struct intel_digital_port *dig_port, 74*c0e08c20SJani Nikula bool *ksv_ready); 75*c0e08c20SJani Nikula 76*c0e08c20SJani Nikula /* Reads the ksv fifo for num_downstream devices */ 77*c0e08c20SJani Nikula int (*read_ksv_fifo)(struct intel_digital_port *dig_port, 78*c0e08c20SJani Nikula int num_downstream, u8 *ksv_fifo); 79*c0e08c20SJani Nikula 80*c0e08c20SJani Nikula /* Reads a 32-bit part of V' from the receiver */ 81*c0e08c20SJani Nikula int (*read_v_prime_part)(struct intel_digital_port *dig_port, 82*c0e08c20SJani Nikula int i, u32 *part); 83*c0e08c20SJani Nikula 84*c0e08c20SJani Nikula /* Enables HDCP signalling on the port */ 85*c0e08c20SJani Nikula int (*toggle_signalling)(struct intel_digital_port *dig_port, 86*c0e08c20SJani Nikula enum transcoder cpu_transcoder, 87*c0e08c20SJani Nikula bool enable); 88*c0e08c20SJani Nikula 89*c0e08c20SJani Nikula /* Enable/Disable stream encryption on DP MST Transport Link */ 90*c0e08c20SJani Nikula int (*stream_encryption)(struct intel_connector *connector, 91*c0e08c20SJani Nikula bool enable); 92*c0e08c20SJani Nikula 93*c0e08c20SJani Nikula /* Ensures the link is still protected */ 94*c0e08c20SJani Nikula bool (*check_link)(struct intel_digital_port *dig_port, 95*c0e08c20SJani Nikula struct intel_connector *connector); 96*c0e08c20SJani Nikula 97*c0e08c20SJani Nikula /* Detects panel's hdcp capability. This is optional for HDMI. */ 98*c0e08c20SJani Nikula int (*hdcp_get_capability)(struct intel_digital_port *dig_port, 99*c0e08c20SJani Nikula bool *hdcp_capable); 100*c0e08c20SJani Nikula 101*c0e08c20SJani Nikula /* HDCP adaptation(DP/HDMI) required on the port */ 102*c0e08c20SJani Nikula enum hdcp_wired_protocol protocol; 103*c0e08c20SJani Nikula 104*c0e08c20SJani Nikula /* Detects whether sink is HDCP2.2 capable */ 105*c0e08c20SJani Nikula int (*hdcp_2_2_get_capability)(struct intel_connector *connector, 106*c0e08c20SJani Nikula bool *capable); 107*c0e08c20SJani Nikula 108*c0e08c20SJani Nikula /* Write HDCP2.2 messages */ 109*c0e08c20SJani Nikula int (*write_2_2_msg)(struct intel_connector *connector, 110*c0e08c20SJani Nikula void *buf, size_t size); 111*c0e08c20SJani Nikula 112*c0e08c20SJani Nikula /* Read HDCP2.2 messages */ 113*c0e08c20SJani Nikula int (*read_2_2_msg)(struct intel_connector *connector, 114*c0e08c20SJani Nikula u8 msg_id, void *buf, size_t size); 115*c0e08c20SJani Nikula 116*c0e08c20SJani Nikula /* 117*c0e08c20SJani Nikula * Implementation of DP HDCP2.2 Errata for the communication of stream 118*c0e08c20SJani Nikula * type to Receivers. In DP HDCP2.2 Stream type is one of the input to 119*c0e08c20SJani Nikula * the HDCP2.2 Cipher for En/De-Cryption. Not applicable for HDMI. 120*c0e08c20SJani Nikula */ 121*c0e08c20SJani Nikula int (*config_stream_type)(struct intel_connector *connector, 122*c0e08c20SJani Nikula bool is_repeater, u8 type); 123*c0e08c20SJani Nikula 124*c0e08c20SJani Nikula /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */ 125*c0e08c20SJani Nikula int (*stream_2_2_encryption)(struct intel_connector *connector, 126*c0e08c20SJani Nikula bool enable); 127*c0e08c20SJani Nikula 128*c0e08c20SJani Nikula /* HDCP2.2 Link Integrity Check */ 129*c0e08c20SJani Nikula int (*check_2_2_link)(struct intel_digital_port *dig_port, 130*c0e08c20SJani Nikula struct intel_connector *connector); 131*c0e08c20SJani Nikula 132*c0e08c20SJani Nikula /* HDCP remote sink cap */ 133*c0e08c20SJani Nikula int (*get_remote_hdcp_capability)(struct intel_connector *connector, 134*c0e08c20SJani Nikula bool *hdcp_capable, bool *hdcp2_capable); 135*c0e08c20SJani Nikula }; 136*c0e08c20SJani Nikula 137*c0e08c20SJani Nikula #endif /* __INTEL_HDCP_SHIM_H__ */ 138