1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/i2c.h> 13 #include <linux/random.h> 14 15 #include <drm/display/drm_hdcp_helper.h> 16 #include <drm/intel/i915_component.h> 17 18 #include "i915_drv.h" 19 #include "i915_reg.h" 20 #include "intel_connector.h" 21 #include "intel_de.h" 22 #include "intel_display_power.h" 23 #include "intel_display_power_well.h" 24 #include "intel_display_types.h" 25 #include "intel_hdcp.h" 26 #include "intel_hdcp_gsc.h" 27 #include "intel_hdcp_regs.h" 28 #include "intel_hdcp_shim.h" 29 #include "intel_pcode.h" 30 31 #define KEY_LOAD_TRIES 5 32 #define HDCP2_LC_RETRY_CNT 3 33 34 static void 35 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 36 struct intel_hdcp *hdcp, 37 bool enable) 38 { 39 struct intel_display *display = to_intel_display(encoder); 40 i915_reg_t rekey_reg; 41 u32 rekey_bit = 0; 42 43 /* Here we assume HDMI is in TMDS mode of operation */ 44 if (encoder->type != INTEL_OUTPUT_HDMI) 45 return; 46 47 if (DISPLAY_VER(display) >= 30) { 48 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 49 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 50 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 51 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 52 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 53 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 54 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 55 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 56 rekey_bit = HDCP_LINE_REKEY_DISABLE; 57 } 58 59 if (rekey_bit) 60 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 61 } 62 63 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 64 struct intel_connector *connector) 65 { 66 struct drm_dp_mst_topology_mgr *mgr; 67 struct drm_dp_mst_atomic_payload *payload; 68 struct drm_dp_mst_topology_state *mst_state; 69 int vcpi = 0; 70 71 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 72 if (!connector->port) 73 return 0; 74 mgr = connector->port->mgr; 75 76 drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); 77 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 78 payload = drm_atomic_get_mst_payload_state(mst_state, connector->port); 79 if (drm_WARN_ON(mgr->dev, !payload)) 80 goto out; 81 82 vcpi = payload->vcpi; 83 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 84 vcpi = 0; 85 goto out; 86 } 87 out: 88 return vcpi; 89 } 90 91 /* 92 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 93 * content_type for all streams in DP MST topology because security f/w doesn't 94 * have any provision to mark content_type for each stream separately, it marks 95 * all available streams with the content_type proivided at the time of port 96 * authentication. This may prohibit the userspace to use type1 content on 97 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 98 * DP MST topology. Though it is not compulsory, security fw should change its 99 * policy to mark different content_types for different streams. 100 */ 101 static int 102 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 103 struct intel_digital_port *dig_port) 104 { 105 struct intel_display *display = to_intel_display(state); 106 struct drm_connector_list_iter conn_iter; 107 struct intel_digital_port *conn_dig_port; 108 struct intel_connector *connector; 109 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 110 bool enforce_type0 = false; 111 int k; 112 113 if (dig_port->hdcp_auth_status) 114 return 0; 115 116 data->k = 0; 117 118 if (!dig_port->hdcp_mst_type1_capable) 119 enforce_type0 = true; 120 121 drm_connector_list_iter_begin(display->drm, &conn_iter); 122 for_each_intel_connector_iter(connector, &conn_iter) { 123 if (connector->base.status == connector_status_disconnected) 124 continue; 125 126 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 127 continue; 128 129 conn_dig_port = intel_attached_dig_port(connector); 130 if (conn_dig_port != dig_port) 131 continue; 132 133 data->streams[data->k].stream_id = 134 intel_conn_to_vcpi(state, connector); 135 data->k++; 136 137 /* if there is only one active stream */ 138 if (dig_port->dp.active_mst_links <= 1) 139 break; 140 } 141 drm_connector_list_iter_end(&conn_iter); 142 143 if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0)) 144 return -EINVAL; 145 146 /* 147 * Apply common protection level across all streams in DP MST Topology. 148 * Use highest supported content type for all streams in DP MST Topology. 149 */ 150 for (k = 0; k < data->k; k++) 151 data->streams[k].stream_type = 152 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 153 154 return 0; 155 } 156 157 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 158 struct intel_connector *connector) 159 { 160 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 161 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 162 struct intel_hdcp *hdcp = &connector->hdcp; 163 164 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 165 return intel_hdcp_required_content_stream(state, dig_port); 166 167 data->k = 1; 168 data->streams[0].stream_id = 0; 169 data->streams[0].stream_type = hdcp->content_type; 170 171 return 0; 172 } 173 174 static 175 bool intel_hdcp_is_ksv_valid(u8 *ksv) 176 { 177 int i, ones = 0; 178 /* KSV has 20 1's and 20 0's */ 179 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 180 ones += hweight8(ksv[i]); 181 if (ones != 20) 182 return false; 183 184 return true; 185 } 186 187 static 188 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 189 const struct intel_hdcp_shim *shim, u8 *bksv) 190 { 191 struct intel_display *display = to_intel_display(dig_port); 192 int ret, i, tries = 2; 193 194 /* HDCP spec states that we must retry the bksv if it is invalid */ 195 for (i = 0; i < tries; i++) { 196 ret = shim->read_bksv(dig_port, bksv); 197 if (ret) 198 return ret; 199 if (intel_hdcp_is_ksv_valid(bksv)) 200 break; 201 } 202 if (i == tries) { 203 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 204 return -ENODEV; 205 } 206 207 return 0; 208 } 209 210 /* Is HDCP1.4 capable on Platform and Sink */ 211 bool intel_hdcp_get_capability(struct intel_connector *connector) 212 { 213 struct intel_digital_port *dig_port; 214 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 215 bool capable = false; 216 u8 bksv[5]; 217 218 if (!intel_attached_encoder(connector)) 219 return capable; 220 221 dig_port = intel_attached_dig_port(connector); 222 223 if (!shim) 224 return capable; 225 226 if (shim->hdcp_get_capability) { 227 shim->hdcp_get_capability(dig_port, &capable); 228 } else { 229 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 230 capable = true; 231 } 232 233 return capable; 234 } 235 236 /* 237 * Check if the source has all the building blocks ready to make 238 * HDCP 2.2 work 239 */ 240 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 241 { 242 struct intel_display *display = to_intel_display(connector); 243 struct intel_hdcp *hdcp = &connector->hdcp; 244 245 /* I915 support for HDCP2.2 */ 246 if (!hdcp->hdcp2_supported) 247 return false; 248 249 /* If MTL+ make sure gsc is loaded and proxy is setup */ 250 if (intel_hdcp_gsc_cs_required(display)) { 251 if (!intel_hdcp_gsc_check_status(display)) 252 return false; 253 } 254 255 /* MEI/GSC interface is solid depending on which is used */ 256 mutex_lock(&display->hdcp.hdcp_mutex); 257 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 258 mutex_unlock(&display->hdcp.hdcp_mutex); 259 return false; 260 } 261 mutex_unlock(&display->hdcp.hdcp_mutex); 262 263 return true; 264 } 265 266 /* Is HDCP2.2 capable on Platform and Sink */ 267 bool intel_hdcp2_get_capability(struct intel_connector *connector) 268 { 269 struct intel_hdcp *hdcp = &connector->hdcp; 270 bool capable = false; 271 272 if (!intel_hdcp2_prerequisite(connector)) 273 return false; 274 275 /* Sink's capability for HDCP2.2 */ 276 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 277 278 return capable; 279 } 280 281 void intel_hdcp_get_remote_capability(struct intel_connector *connector, 282 bool *hdcp_capable, 283 bool *hdcp2_capable) 284 { 285 struct intel_hdcp *hdcp = &connector->hdcp; 286 287 if (!hdcp->shim->get_remote_hdcp_capability) 288 return; 289 290 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 291 hdcp2_capable); 292 293 if (!intel_hdcp2_prerequisite(connector)) 294 *hdcp2_capable = false; 295 } 296 297 static bool intel_hdcp_in_use(struct intel_display *display, 298 enum transcoder cpu_transcoder, enum port port) 299 { 300 return intel_de_read(display, 301 HDCP_STATUS(display, cpu_transcoder, port)) & 302 HDCP_STATUS_ENC; 303 } 304 305 static bool intel_hdcp2_in_use(struct intel_display *display, 306 enum transcoder cpu_transcoder, enum port port) 307 { 308 return intel_de_read(display, 309 HDCP2_STATUS(display, cpu_transcoder, port)) & 310 LINK_ENCRYPTION_STATUS; 311 } 312 313 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 314 const struct intel_hdcp_shim *shim) 315 { 316 int ret, read_ret; 317 bool ksv_ready; 318 319 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 320 ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, 321 &ksv_ready), 322 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 323 100 * 1000); 324 if (ret) 325 return ret; 326 if (read_ret) 327 return read_ret; 328 if (!ksv_ready) 329 return -ETIMEDOUT; 330 331 return 0; 332 } 333 334 static bool hdcp_key_loadable(struct intel_display *display) 335 { 336 struct drm_i915_private *i915 = to_i915(display->drm); 337 enum i915_power_well_id id; 338 intel_wakeref_t wakeref; 339 bool enabled = false; 340 341 /* 342 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 343 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 344 */ 345 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 346 id = HSW_DISP_PW_GLOBAL; 347 else 348 id = SKL_DISP_PW_1; 349 350 /* PG1 (power well #1) needs to be enabled */ 351 with_intel_runtime_pm(&i915->runtime_pm, wakeref) 352 enabled = intel_display_power_well_is_enabled(display, id); 353 354 /* 355 * Another req for hdcp key loadability is enabled state of pll for 356 * cdclk. Without active crtc we wont land here. So we are assuming that 357 * cdclk is already on. 358 */ 359 360 return enabled; 361 } 362 363 static void intel_hdcp_clear_keys(struct intel_display *display) 364 { 365 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 366 intel_de_write(display, HDCP_KEY_STATUS, 367 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 368 } 369 370 static int intel_hdcp_load_keys(struct intel_display *display) 371 { 372 struct drm_i915_private *i915 = to_i915(display->drm); 373 int ret; 374 u32 val; 375 376 val = intel_de_read(display, HDCP_KEY_STATUS); 377 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 378 return 0; 379 380 /* 381 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 382 * out of reset. So if Key is not already loaded, its an error state. 383 */ 384 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) 385 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 386 return -ENXIO; 387 388 /* 389 * Initiate loading the HDCP key from fuses. 390 * 391 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 392 * version 9 platforms (minus BXT) differ in the key load trigger 393 * process from other platforms. These platforms use the GT Driver 394 * Mailbox interface. 395 */ 396 if (DISPLAY_VER(display) == 9 && !IS_BROXTON(i915)) { 397 ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); 398 if (ret) { 399 drm_err(display->drm, 400 "Failed to initiate HDCP key load (%d)\n", 401 ret); 402 return ret; 403 } 404 } else { 405 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 406 } 407 408 /* Wait for the keys to load (500us) */ 409 ret = intel_de_wait_custom(display, HDCP_KEY_STATUS, 410 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 411 10, 1, &val); 412 if (ret) 413 return ret; 414 else if (!(val & HDCP_KEY_LOAD_STATUS)) 415 return -ENXIO; 416 417 /* Send Aksv over to PCH display for use in authentication */ 418 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 419 420 return 0; 421 } 422 423 /* Returns updated SHA-1 index */ 424 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 425 { 426 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 427 if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 428 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 429 return -ETIMEDOUT; 430 } 431 return 0; 432 } 433 434 static 435 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 436 enum transcoder cpu_transcoder, enum port port) 437 { 438 if (DISPLAY_VER(display) >= 12) { 439 switch (cpu_transcoder) { 440 case TRANSCODER_A: 441 return HDCP_TRANSA_REP_PRESENT | 442 HDCP_TRANSA_SHA1_M0; 443 case TRANSCODER_B: 444 return HDCP_TRANSB_REP_PRESENT | 445 HDCP_TRANSB_SHA1_M0; 446 case TRANSCODER_C: 447 return HDCP_TRANSC_REP_PRESENT | 448 HDCP_TRANSC_SHA1_M0; 449 case TRANSCODER_D: 450 return HDCP_TRANSD_REP_PRESENT | 451 HDCP_TRANSD_SHA1_M0; 452 default: 453 drm_err(display->drm, "Unknown transcoder %d\n", 454 cpu_transcoder); 455 return 0; 456 } 457 } 458 459 switch (port) { 460 case PORT_A: 461 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 462 case PORT_B: 463 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 464 case PORT_C: 465 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 466 case PORT_D: 467 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 468 case PORT_E: 469 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 470 default: 471 drm_err(display->drm, "Unknown port %d\n", port); 472 return 0; 473 } 474 } 475 476 static 477 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 478 const struct intel_hdcp_shim *shim, 479 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 480 { 481 struct intel_display *display = to_intel_display(connector); 482 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 483 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 484 enum port port = dig_port->base.port; 485 u32 vprime, sha_text, sha_leftovers, rep_ctl; 486 int ret, i, j, sha_idx; 487 488 /* Process V' values from the receiver */ 489 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 490 ret = shim->read_v_prime_part(dig_port, i, &vprime); 491 if (ret) 492 return ret; 493 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 494 } 495 496 /* 497 * We need to write the concatenation of all device KSVs, BINFO (DP) || 498 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 499 * stream is written via the HDCP_SHA_TEXT register in 32-bit 500 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 501 * index will keep track of our progress through the 64 bytes as well as 502 * helping us work the 40-bit KSVs through our 32-bit register. 503 * 504 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 505 */ 506 sha_idx = 0; 507 sha_text = 0; 508 sha_leftovers = 0; 509 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 510 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 511 for (i = 0; i < num_downstream; i++) { 512 unsigned int sha_empty; 513 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 514 515 /* Fill up the empty slots in sha_text and write it out */ 516 sha_empty = sizeof(sha_text) - sha_leftovers; 517 for (j = 0; j < sha_empty; j++) { 518 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 519 sha_text |= ksv[j] << off; 520 } 521 522 ret = intel_write_sha_text(display, sha_text); 523 if (ret < 0) 524 return ret; 525 526 /* Programming guide writes this every 64 bytes */ 527 sha_idx += sizeof(sha_text); 528 if (!(sha_idx % 64)) 529 intel_de_write(display, HDCP_REP_CTL, 530 rep_ctl | HDCP_SHA1_TEXT_32); 531 532 /* Store the leftover bytes from the ksv in sha_text */ 533 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 534 sha_text = 0; 535 for (j = 0; j < sha_leftovers; j++) 536 sha_text |= ksv[sha_empty + j] << 537 ((sizeof(sha_text) - j - 1) * 8); 538 539 /* 540 * If we still have room in sha_text for more data, continue. 541 * Otherwise, write it out immediately. 542 */ 543 if (sizeof(sha_text) > sha_leftovers) 544 continue; 545 546 ret = intel_write_sha_text(display, sha_text); 547 if (ret < 0) 548 return ret; 549 sha_leftovers = 0; 550 sha_text = 0; 551 sha_idx += sizeof(sha_text); 552 } 553 554 /* 555 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 556 * bytes are leftover from the last ksv, we might be able to fit them 557 * all in sha_text (first 2 cases), or we might need to split them up 558 * into 2 writes (last 2 cases). 559 */ 560 if (sha_leftovers == 0) { 561 /* Write 16 bits of text, 16 bits of M0 */ 562 intel_de_write(display, HDCP_REP_CTL, 563 rep_ctl | HDCP_SHA1_TEXT_16); 564 ret = intel_write_sha_text(display, 565 bstatus[0] << 8 | bstatus[1]); 566 if (ret < 0) 567 return ret; 568 sha_idx += sizeof(sha_text); 569 570 /* Write 32 bits of M0 */ 571 intel_de_write(display, HDCP_REP_CTL, 572 rep_ctl | HDCP_SHA1_TEXT_0); 573 ret = intel_write_sha_text(display, 0); 574 if (ret < 0) 575 return ret; 576 sha_idx += sizeof(sha_text); 577 578 /* Write 16 bits of M0 */ 579 intel_de_write(display, HDCP_REP_CTL, 580 rep_ctl | HDCP_SHA1_TEXT_16); 581 ret = intel_write_sha_text(display, 0); 582 if (ret < 0) 583 return ret; 584 sha_idx += sizeof(sha_text); 585 586 } else if (sha_leftovers == 1) { 587 /* Write 24 bits of text, 8 bits of M0 */ 588 intel_de_write(display, HDCP_REP_CTL, 589 rep_ctl | HDCP_SHA1_TEXT_24); 590 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 591 /* Only 24-bits of data, must be in the LSB */ 592 sha_text = (sha_text & 0xffffff00) >> 8; 593 ret = intel_write_sha_text(display, sha_text); 594 if (ret < 0) 595 return ret; 596 sha_idx += sizeof(sha_text); 597 598 /* Write 32 bits of M0 */ 599 intel_de_write(display, HDCP_REP_CTL, 600 rep_ctl | HDCP_SHA1_TEXT_0); 601 ret = intel_write_sha_text(display, 0); 602 if (ret < 0) 603 return ret; 604 sha_idx += sizeof(sha_text); 605 606 /* Write 24 bits of M0 */ 607 intel_de_write(display, HDCP_REP_CTL, 608 rep_ctl | HDCP_SHA1_TEXT_8); 609 ret = intel_write_sha_text(display, 0); 610 if (ret < 0) 611 return ret; 612 sha_idx += sizeof(sha_text); 613 614 } else if (sha_leftovers == 2) { 615 /* Write 32 bits of text */ 616 intel_de_write(display, HDCP_REP_CTL, 617 rep_ctl | HDCP_SHA1_TEXT_32); 618 sha_text |= bstatus[0] << 8 | bstatus[1]; 619 ret = intel_write_sha_text(display, sha_text); 620 if (ret < 0) 621 return ret; 622 sha_idx += sizeof(sha_text); 623 624 /* Write 64 bits of M0 */ 625 intel_de_write(display, HDCP_REP_CTL, 626 rep_ctl | HDCP_SHA1_TEXT_0); 627 for (i = 0; i < 2; i++) { 628 ret = intel_write_sha_text(display, 0); 629 if (ret < 0) 630 return ret; 631 sha_idx += sizeof(sha_text); 632 } 633 634 /* 635 * Terminate the SHA-1 stream by hand. For the other leftover 636 * cases this is appended by the hardware. 637 */ 638 intel_de_write(display, HDCP_REP_CTL, 639 rep_ctl | HDCP_SHA1_TEXT_32); 640 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 641 ret = intel_write_sha_text(display, sha_text); 642 if (ret < 0) 643 return ret; 644 sha_idx += sizeof(sha_text); 645 } else if (sha_leftovers == 3) { 646 /* Write 32 bits of text (filled from LSB) */ 647 intel_de_write(display, HDCP_REP_CTL, 648 rep_ctl | HDCP_SHA1_TEXT_32); 649 sha_text |= bstatus[0]; 650 ret = intel_write_sha_text(display, sha_text); 651 if (ret < 0) 652 return ret; 653 sha_idx += sizeof(sha_text); 654 655 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 656 intel_de_write(display, HDCP_REP_CTL, 657 rep_ctl | HDCP_SHA1_TEXT_8); 658 ret = intel_write_sha_text(display, bstatus[1]); 659 if (ret < 0) 660 return ret; 661 sha_idx += sizeof(sha_text); 662 663 /* Write 32 bits of M0 */ 664 intel_de_write(display, HDCP_REP_CTL, 665 rep_ctl | HDCP_SHA1_TEXT_0); 666 ret = intel_write_sha_text(display, 0); 667 if (ret < 0) 668 return ret; 669 sha_idx += sizeof(sha_text); 670 671 /* Write 8 bits of M0 */ 672 intel_de_write(display, HDCP_REP_CTL, 673 rep_ctl | HDCP_SHA1_TEXT_24); 674 ret = intel_write_sha_text(display, 0); 675 if (ret < 0) 676 return ret; 677 sha_idx += sizeof(sha_text); 678 } else { 679 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 680 sha_leftovers); 681 return -EINVAL; 682 } 683 684 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 685 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 686 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 687 ret = intel_write_sha_text(display, 0); 688 if (ret < 0) 689 return ret; 690 sha_idx += sizeof(sha_text); 691 } 692 693 /* 694 * Last write gets the length of the concatenation in bits. That is: 695 * - 5 bytes per device 696 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 697 */ 698 sha_text = (num_downstream * 5 + 10) * 8; 699 ret = intel_write_sha_text(display, sha_text); 700 if (ret < 0) 701 return ret; 702 703 /* Tell the HW we're done with the hash and wait for it to ACK */ 704 intel_de_write(display, HDCP_REP_CTL, 705 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 706 if (intel_de_wait_for_set(display, HDCP_REP_CTL, 707 HDCP_SHA1_COMPLETE, 1)) { 708 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 709 return -ETIMEDOUT; 710 } 711 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 712 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 713 return -ENXIO; 714 } 715 716 return 0; 717 } 718 719 /* Implements Part 2 of the HDCP authorization procedure */ 720 static 721 int intel_hdcp_auth_downstream(struct intel_connector *connector) 722 { 723 struct intel_display *display = to_intel_display(connector); 724 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 725 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 726 u8 bstatus[2], num_downstream, *ksv_fifo; 727 int ret, i, tries = 3; 728 729 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 730 if (ret) { 731 drm_dbg_kms(display->drm, 732 "KSV list failed to become ready (%d)\n", ret); 733 return ret; 734 } 735 736 ret = shim->read_bstatus(dig_port, bstatus); 737 if (ret) 738 return ret; 739 740 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 741 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 742 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 743 return -EPERM; 744 } 745 746 /* 747 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 748 * the HDCP encryption. That implies that repeater can't have its own 749 * display. As there is no consumption of encrypted content in the 750 * repeater with 0 downstream devices, we are failing the 751 * authentication. 752 */ 753 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 754 if (num_downstream == 0) { 755 drm_dbg_kms(display->drm, 756 "Repeater with zero downstream devices\n"); 757 return -EINVAL; 758 } 759 760 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 761 if (!ksv_fifo) { 762 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 763 return -ENOMEM; 764 } 765 766 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 767 if (ret) 768 goto err; 769 770 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 771 num_downstream) > 0) { 772 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 773 ret = -EPERM; 774 goto err; 775 } 776 777 /* 778 * When V prime mismatches, DP Spec mandates re-read of 779 * V prime atleast twice. 780 */ 781 for (i = 0; i < tries; i++) { 782 ret = intel_hdcp_validate_v_prime(connector, shim, 783 ksv_fifo, num_downstream, 784 bstatus); 785 if (!ret) 786 break; 787 } 788 789 if (i == tries) { 790 drm_dbg_kms(display->drm, 791 "V Prime validation failed.(%d)\n", ret); 792 goto err; 793 } 794 795 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 796 num_downstream); 797 ret = 0; 798 err: 799 kfree(ksv_fifo); 800 return ret; 801 } 802 803 /* Implements Part 1 of the HDCP authorization procedure */ 804 static int intel_hdcp_auth(struct intel_connector *connector) 805 { 806 struct intel_display *display = to_intel_display(connector); 807 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 808 struct intel_hdcp *hdcp = &connector->hdcp; 809 const struct intel_hdcp_shim *shim = hdcp->shim; 810 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 811 enum port port = dig_port->base.port; 812 unsigned long r0_prime_gen_start; 813 int ret, i, tries = 2; 814 union { 815 u32 reg[2]; 816 u8 shim[DRM_HDCP_AN_LEN]; 817 } an; 818 union { 819 u32 reg[2]; 820 u8 shim[DRM_HDCP_KSV_LEN]; 821 } bksv; 822 union { 823 u32 reg; 824 u8 shim[DRM_HDCP_RI_LEN]; 825 } ri; 826 bool repeater_present, hdcp_capable; 827 828 /* 829 * Detects whether the display is HDCP capable. Although we check for 830 * valid Bksv below, the HDCP over DP spec requires that we check 831 * whether the display supports HDCP before we write An. For HDMI 832 * displays, this is not necessary. 833 */ 834 if (shim->hdcp_get_capability) { 835 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 836 if (ret) 837 return ret; 838 if (!hdcp_capable) { 839 drm_dbg_kms(display->drm, 840 "Panel is not HDCP capable\n"); 841 return -EINVAL; 842 } 843 } 844 845 /* Initialize An with 2 random values and acquire it */ 846 for (i = 0; i < 2; i++) 847 intel_de_write(display, 848 HDCP_ANINIT(display, cpu_transcoder, port), 849 get_random_u32()); 850 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 851 HDCP_CONF_CAPTURE_AN); 852 853 /* Wait for An to be acquired */ 854 if (intel_de_wait_for_set(display, 855 HDCP_STATUS(display, cpu_transcoder, port), 856 HDCP_STATUS_AN_READY, 1)) { 857 drm_err(display->drm, "Timed out waiting for An\n"); 858 return -ETIMEDOUT; 859 } 860 861 an.reg[0] = intel_de_read(display, 862 HDCP_ANLO(display, cpu_transcoder, port)); 863 an.reg[1] = intel_de_read(display, 864 HDCP_ANHI(display, cpu_transcoder, port)); 865 ret = shim->write_an_aksv(dig_port, an.shim); 866 if (ret) 867 return ret; 868 869 r0_prime_gen_start = jiffies; 870 871 memset(&bksv, 0, sizeof(bksv)); 872 873 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 874 if (ret < 0) 875 return ret; 876 877 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 878 drm_err(display->drm, "BKSV is revoked\n"); 879 return -EPERM; 880 } 881 882 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 883 bksv.reg[0]); 884 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 885 bksv.reg[1]); 886 887 ret = shim->repeater_present(dig_port, &repeater_present); 888 if (ret) 889 return ret; 890 if (repeater_present) 891 intel_de_write(display, HDCP_REP_CTL, 892 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 893 894 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 895 if (ret) 896 return ret; 897 898 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 899 HDCP_CONF_AUTH_AND_ENC); 900 901 /* Wait for R0 ready */ 902 if (wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 903 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 904 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 905 return -ETIMEDOUT; 906 } 907 908 /* 909 * Wait for R0' to become available. The spec says 100ms from Aksv, but 910 * some monitors can take longer than this. We'll set the timeout at 911 * 300ms just to be sure. 912 * 913 * On DP, there's an R0_READY bit available but no such bit 914 * exists on HDMI. Since the upper-bound is the same, we'll just do 915 * the stupid thing instead of polling on one and not the other. 916 */ 917 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 918 919 tries = 3; 920 921 /* 922 * DP HDCP Spec mandates the two more reattempt to read R0, incase 923 * of R0 mismatch. 924 */ 925 for (i = 0; i < tries; i++) { 926 ri.reg = 0; 927 ret = shim->read_ri_prime(dig_port, ri.shim); 928 if (ret) 929 return ret; 930 intel_de_write(display, 931 HDCP_RPRIME(display, cpu_transcoder, port), 932 ri.reg); 933 934 /* Wait for Ri prime match */ 935 if (!wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 936 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 937 break; 938 } 939 940 if (i == tries) { 941 drm_dbg_kms(display->drm, 942 "Timed out waiting for Ri prime match (%x)\n", 943 intel_de_read(display, 944 HDCP_STATUS(display, cpu_transcoder, port))); 945 return -ETIMEDOUT; 946 } 947 948 /* Wait for encryption confirmation */ 949 if (intel_de_wait_for_set(display, 950 HDCP_STATUS(display, cpu_transcoder, port), 951 HDCP_STATUS_ENC, 952 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 953 drm_err(display->drm, "Timed out waiting for encryption\n"); 954 return -ETIMEDOUT; 955 } 956 957 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 958 if (shim->stream_encryption) { 959 ret = shim->stream_encryption(connector, true); 960 if (ret) { 961 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 962 connector->base.base.id, connector->base.name); 963 return ret; 964 } 965 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 966 transcoder_name(hdcp->stream_transcoder)); 967 } 968 969 if (repeater_present) 970 return intel_hdcp_auth_downstream(connector); 971 972 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 973 return 0; 974 } 975 976 static int _intel_hdcp_disable(struct intel_connector *connector) 977 { 978 struct intel_display *display = to_intel_display(connector); 979 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 980 struct intel_hdcp *hdcp = &connector->hdcp; 981 enum port port = dig_port->base.port; 982 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 983 u32 repeater_ctl; 984 int ret; 985 986 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 987 connector->base.base.id, connector->base.name); 988 989 if (hdcp->shim->stream_encryption) { 990 ret = hdcp->shim->stream_encryption(connector, false); 991 if (ret) { 992 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 993 connector->base.base.id, connector->base.name); 994 return ret; 995 } 996 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 997 transcoder_name(hdcp->stream_transcoder)); 998 /* 999 * If there are other connectors on this port using HDCP, 1000 * don't disable it until it disabled HDCP encryption for 1001 * all connectors in MST topology. 1002 */ 1003 if (dig_port->num_hdcp_streams > 0) 1004 return 0; 1005 } 1006 1007 hdcp->hdcp_encrypted = false; 1008 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1009 if (intel_de_wait_for_clear(display, 1010 HDCP_STATUS(display, cpu_transcoder, port), 1011 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1012 drm_err(display->drm, 1013 "Failed to disable HDCP, timeout clearing status\n"); 1014 return -ETIMEDOUT; 1015 } 1016 1017 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1018 port); 1019 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1020 1021 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1022 if (ret) { 1023 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1024 return ret; 1025 } 1026 1027 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1028 return 0; 1029 } 1030 1031 static int intel_hdcp1_enable(struct intel_connector *connector) 1032 { 1033 struct intel_display *display = to_intel_display(connector); 1034 struct intel_hdcp *hdcp = &connector->hdcp; 1035 int i, ret, tries = 3; 1036 1037 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1038 connector->base.base.id, connector->base.name); 1039 1040 if (!hdcp_key_loadable(display)) { 1041 drm_err(display->drm, "HDCP key Load is not possible\n"); 1042 return -ENXIO; 1043 } 1044 1045 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1046 ret = intel_hdcp_load_keys(display); 1047 if (!ret) 1048 break; 1049 intel_hdcp_clear_keys(display); 1050 } 1051 if (ret) { 1052 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1053 ret); 1054 return ret; 1055 } 1056 1057 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1058 1059 /* Incase of authentication failures, HDCP spec expects reauth. */ 1060 for (i = 0; i < tries; i++) { 1061 ret = intel_hdcp_auth(connector); 1062 if (!ret) { 1063 hdcp->hdcp_encrypted = true; 1064 return 0; 1065 } 1066 1067 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1068 1069 /* Ensuring HDCP encryption and signalling are stopped. */ 1070 _intel_hdcp_disable(connector); 1071 } 1072 1073 drm_dbg_kms(display->drm, 1074 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1075 return ret; 1076 } 1077 1078 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1079 { 1080 return container_of(hdcp, struct intel_connector, hdcp); 1081 } 1082 1083 static void intel_hdcp_update_value(struct intel_connector *connector, 1084 u64 value, bool update_property) 1085 { 1086 struct intel_display *display = to_intel_display(connector); 1087 struct drm_i915_private *i915 = to_i915(display->drm); 1088 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1089 struct intel_hdcp *hdcp = &connector->hdcp; 1090 1091 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1092 1093 if (hdcp->value == value) 1094 return; 1095 1096 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp_mutex)); 1097 1098 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1099 if (!drm_WARN_ON(display->drm, dig_port->num_hdcp_streams == 0)) 1100 dig_port->num_hdcp_streams--; 1101 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1102 dig_port->num_hdcp_streams++; 1103 } 1104 1105 hdcp->value = value; 1106 if (update_property) { 1107 drm_connector_get(&connector->base); 1108 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 1109 drm_connector_put(&connector->base); 1110 } 1111 } 1112 1113 /* Implements Part 3 of the HDCP authorization procedure */ 1114 static int intel_hdcp_check_link(struct intel_connector *connector) 1115 { 1116 struct intel_display *display = to_intel_display(connector); 1117 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1118 struct intel_hdcp *hdcp = &connector->hdcp; 1119 enum port port = dig_port->base.port; 1120 enum transcoder cpu_transcoder; 1121 int ret = 0; 1122 1123 mutex_lock(&hdcp->mutex); 1124 mutex_lock(&dig_port->hdcp_mutex); 1125 1126 cpu_transcoder = hdcp->cpu_transcoder; 1127 1128 /* Check_link valid only when HDCP1.4 is enabled */ 1129 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1130 !hdcp->hdcp_encrypted) { 1131 ret = -EINVAL; 1132 goto out; 1133 } 1134 1135 if (drm_WARN_ON(display->drm, 1136 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1137 drm_err(display->drm, 1138 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1139 connector->base.base.id, connector->base.name, 1140 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1141 ret = -ENXIO; 1142 intel_hdcp_update_value(connector, 1143 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1144 true); 1145 goto out; 1146 } 1147 1148 if (hdcp->shim->check_link(dig_port, connector)) { 1149 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1150 intel_hdcp_update_value(connector, 1151 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1152 } 1153 goto out; 1154 } 1155 1156 drm_dbg_kms(display->drm, 1157 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1158 connector->base.base.id, connector->base.name); 1159 1160 ret = _intel_hdcp_disable(connector); 1161 if (ret) { 1162 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1163 intel_hdcp_update_value(connector, 1164 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1165 true); 1166 goto out; 1167 } 1168 1169 ret = intel_hdcp1_enable(connector); 1170 if (ret) { 1171 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1172 intel_hdcp_update_value(connector, 1173 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1174 true); 1175 goto out; 1176 } 1177 1178 out: 1179 mutex_unlock(&dig_port->hdcp_mutex); 1180 mutex_unlock(&hdcp->mutex); 1181 return ret; 1182 } 1183 1184 static void intel_hdcp_prop_work(struct work_struct *work) 1185 { 1186 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1187 prop_work); 1188 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1189 struct intel_display *display = to_intel_display(connector); 1190 1191 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1192 mutex_lock(&hdcp->mutex); 1193 1194 /* 1195 * This worker is only used to flip between ENABLED/DESIRED. Either of 1196 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1197 * we're running just after hdcp has been disabled, so just exit 1198 */ 1199 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1200 drm_hdcp_update_content_protection(&connector->base, 1201 hdcp->value); 1202 1203 mutex_unlock(&hdcp->mutex); 1204 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1205 1206 drm_connector_put(&connector->base); 1207 } 1208 1209 bool is_hdcp_supported(struct intel_display *display, enum port port) 1210 { 1211 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1212 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1213 } 1214 1215 static int 1216 hdcp2_prepare_ake_init(struct intel_connector *connector, 1217 struct hdcp2_ake_init *ake_data) 1218 { 1219 struct intel_display *display = to_intel_display(connector); 1220 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1221 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1222 struct i915_hdcp_arbiter *arbiter; 1223 int ret; 1224 1225 mutex_lock(&display->hdcp.hdcp_mutex); 1226 arbiter = display->hdcp.arbiter; 1227 1228 if (!arbiter || !arbiter->ops) { 1229 mutex_unlock(&display->hdcp.hdcp_mutex); 1230 return -EINVAL; 1231 } 1232 1233 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1234 if (ret) 1235 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1236 ret); 1237 mutex_unlock(&display->hdcp.hdcp_mutex); 1238 1239 return ret; 1240 } 1241 1242 static int 1243 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1244 struct hdcp2_ake_send_cert *rx_cert, 1245 bool *paired, 1246 struct hdcp2_ake_no_stored_km *ek_pub_km, 1247 size_t *msg_sz) 1248 { 1249 struct intel_display *display = to_intel_display(connector); 1250 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1251 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1252 struct i915_hdcp_arbiter *arbiter; 1253 int ret; 1254 1255 mutex_lock(&display->hdcp.hdcp_mutex); 1256 arbiter = display->hdcp.arbiter; 1257 1258 if (!arbiter || !arbiter->ops) { 1259 mutex_unlock(&display->hdcp.hdcp_mutex); 1260 return -EINVAL; 1261 } 1262 1263 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1264 rx_cert, paired, 1265 ek_pub_km, msg_sz); 1266 if (ret < 0) 1267 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1268 ret); 1269 mutex_unlock(&display->hdcp.hdcp_mutex); 1270 1271 return ret; 1272 } 1273 1274 static int hdcp2_verify_hprime(struct intel_connector *connector, 1275 struct hdcp2_ake_send_hprime *rx_hprime) 1276 { 1277 struct intel_display *display = to_intel_display(connector); 1278 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1279 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1280 struct i915_hdcp_arbiter *arbiter; 1281 int ret; 1282 1283 mutex_lock(&display->hdcp.hdcp_mutex); 1284 arbiter = display->hdcp.arbiter; 1285 1286 if (!arbiter || !arbiter->ops) { 1287 mutex_unlock(&display->hdcp.hdcp_mutex); 1288 return -EINVAL; 1289 } 1290 1291 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1292 if (ret < 0) 1293 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1294 mutex_unlock(&display->hdcp.hdcp_mutex); 1295 1296 return ret; 1297 } 1298 1299 static int 1300 hdcp2_store_pairing_info(struct intel_connector *connector, 1301 struct hdcp2_ake_send_pairing_info *pairing_info) 1302 { 1303 struct intel_display *display = to_intel_display(connector); 1304 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1305 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1306 struct i915_hdcp_arbiter *arbiter; 1307 int ret; 1308 1309 mutex_lock(&display->hdcp.hdcp_mutex); 1310 arbiter = display->hdcp.arbiter; 1311 1312 if (!arbiter || !arbiter->ops) { 1313 mutex_unlock(&display->hdcp.hdcp_mutex); 1314 return -EINVAL; 1315 } 1316 1317 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1318 if (ret < 0) 1319 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1320 ret); 1321 mutex_unlock(&display->hdcp.hdcp_mutex); 1322 1323 return ret; 1324 } 1325 1326 static int 1327 hdcp2_prepare_lc_init(struct intel_connector *connector, 1328 struct hdcp2_lc_init *lc_init) 1329 { 1330 struct intel_display *display = to_intel_display(connector); 1331 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1332 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1333 struct i915_hdcp_arbiter *arbiter; 1334 int ret; 1335 1336 mutex_lock(&display->hdcp.hdcp_mutex); 1337 arbiter = display->hdcp.arbiter; 1338 1339 if (!arbiter || !arbiter->ops) { 1340 mutex_unlock(&display->hdcp.hdcp_mutex); 1341 return -EINVAL; 1342 } 1343 1344 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1345 if (ret < 0) 1346 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1347 ret); 1348 mutex_unlock(&display->hdcp.hdcp_mutex); 1349 1350 return ret; 1351 } 1352 1353 static int 1354 hdcp2_verify_lprime(struct intel_connector *connector, 1355 struct hdcp2_lc_send_lprime *rx_lprime) 1356 { 1357 struct intel_display *display = to_intel_display(connector); 1358 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1359 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1360 struct i915_hdcp_arbiter *arbiter; 1361 int ret; 1362 1363 mutex_lock(&display->hdcp.hdcp_mutex); 1364 arbiter = display->hdcp.arbiter; 1365 1366 if (!arbiter || !arbiter->ops) { 1367 mutex_unlock(&display->hdcp.hdcp_mutex); 1368 return -EINVAL; 1369 } 1370 1371 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1372 if (ret < 0) 1373 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1374 ret); 1375 mutex_unlock(&display->hdcp.hdcp_mutex); 1376 1377 return ret; 1378 } 1379 1380 static int hdcp2_prepare_skey(struct intel_connector *connector, 1381 struct hdcp2_ske_send_eks *ske_data) 1382 { 1383 struct intel_display *display = to_intel_display(connector); 1384 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1385 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1386 struct i915_hdcp_arbiter *arbiter; 1387 int ret; 1388 1389 mutex_lock(&display->hdcp.hdcp_mutex); 1390 arbiter = display->hdcp.arbiter; 1391 1392 if (!arbiter || !arbiter->ops) { 1393 mutex_unlock(&display->hdcp.hdcp_mutex); 1394 return -EINVAL; 1395 } 1396 1397 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1398 if (ret < 0) 1399 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1400 ret); 1401 mutex_unlock(&display->hdcp.hdcp_mutex); 1402 1403 return ret; 1404 } 1405 1406 static int 1407 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1408 struct hdcp2_rep_send_receiverid_list 1409 *rep_topology, 1410 struct hdcp2_rep_send_ack *rep_send_ack) 1411 { 1412 struct intel_display *display = to_intel_display(connector); 1413 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1414 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1415 struct i915_hdcp_arbiter *arbiter; 1416 int ret; 1417 1418 mutex_lock(&display->hdcp.hdcp_mutex); 1419 arbiter = display->hdcp.arbiter; 1420 1421 if (!arbiter || !arbiter->ops) { 1422 mutex_unlock(&display->hdcp.hdcp_mutex); 1423 return -EINVAL; 1424 } 1425 1426 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1427 data, 1428 rep_topology, 1429 rep_send_ack); 1430 if (ret < 0) 1431 drm_dbg_kms(display->drm, 1432 "Verify rep topology failed. %d\n", ret); 1433 mutex_unlock(&display->hdcp.hdcp_mutex); 1434 1435 return ret; 1436 } 1437 1438 static int 1439 hdcp2_verify_mprime(struct intel_connector *connector, 1440 struct hdcp2_rep_stream_ready *stream_ready) 1441 { 1442 struct intel_display *display = to_intel_display(connector); 1443 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1444 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1445 struct i915_hdcp_arbiter *arbiter; 1446 int ret; 1447 1448 mutex_lock(&display->hdcp.hdcp_mutex); 1449 arbiter = display->hdcp.arbiter; 1450 1451 if (!arbiter || !arbiter->ops) { 1452 mutex_unlock(&display->hdcp.hdcp_mutex); 1453 return -EINVAL; 1454 } 1455 1456 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1457 if (ret < 0) 1458 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1459 mutex_unlock(&display->hdcp.hdcp_mutex); 1460 1461 return ret; 1462 } 1463 1464 static int hdcp2_authenticate_port(struct intel_connector *connector) 1465 { 1466 struct intel_display *display = to_intel_display(connector); 1467 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1468 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1469 struct i915_hdcp_arbiter *arbiter; 1470 int ret; 1471 1472 mutex_lock(&display->hdcp.hdcp_mutex); 1473 arbiter = display->hdcp.arbiter; 1474 1475 if (!arbiter || !arbiter->ops) { 1476 mutex_unlock(&display->hdcp.hdcp_mutex); 1477 return -EINVAL; 1478 } 1479 1480 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1481 if (ret < 0) 1482 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1483 ret); 1484 mutex_unlock(&display->hdcp.hdcp_mutex); 1485 1486 return ret; 1487 } 1488 1489 static int hdcp2_close_session(struct intel_connector *connector) 1490 { 1491 struct intel_display *display = to_intel_display(connector); 1492 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1493 struct i915_hdcp_arbiter *arbiter; 1494 int ret; 1495 1496 mutex_lock(&display->hdcp.hdcp_mutex); 1497 arbiter = display->hdcp.arbiter; 1498 1499 if (!arbiter || !arbiter->ops) { 1500 mutex_unlock(&display->hdcp.hdcp_mutex); 1501 return -EINVAL; 1502 } 1503 1504 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1505 &dig_port->hdcp_port_data); 1506 mutex_unlock(&display->hdcp.hdcp_mutex); 1507 1508 return ret; 1509 } 1510 1511 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1512 { 1513 return hdcp2_close_session(connector); 1514 } 1515 1516 /* Authentication flow starts from here */ 1517 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1518 { 1519 struct intel_display *display = to_intel_display(connector); 1520 struct intel_digital_port *dig_port = 1521 intel_attached_dig_port(connector); 1522 struct intel_hdcp *hdcp = &connector->hdcp; 1523 union { 1524 struct hdcp2_ake_init ake_init; 1525 struct hdcp2_ake_send_cert send_cert; 1526 struct hdcp2_ake_no_stored_km no_stored_km; 1527 struct hdcp2_ake_send_hprime send_hprime; 1528 struct hdcp2_ake_send_pairing_info pairing_info; 1529 } msgs; 1530 const struct intel_hdcp_shim *shim = hdcp->shim; 1531 size_t size; 1532 int ret, i, max_retries; 1533 1534 /* Init for seq_num */ 1535 hdcp->seq_num_v = 0; 1536 hdcp->seq_num_m = 0; 1537 1538 if (intel_encoder_is_dp(&dig_port->base) || 1539 intel_encoder_is_mst(&dig_port->base)) 1540 max_retries = 10; 1541 else 1542 max_retries = 1; 1543 1544 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1545 if (ret < 0) 1546 return ret; 1547 1548 /* 1549 * Retry the first read and write to downstream at least 10 times 1550 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1551 * (dock decides to stop advertising hdcp2 capability for some reason). 1552 * The reason being that during suspend resume dock usually keeps the 1553 * HDCP2 registers inaccesible causing AUX error. This wouldn't be a 1554 * big problem if the userspace just kept retrying with some delay while 1555 * it continues to play low value content but most userpace applications 1556 * end up throwing an error when it receives one from KMD. This makes 1557 * sure we give the dock and the sink devices to complete its power cycle 1558 * and then try HDCP authentication. The values of 10 and delay of 50ms 1559 * was decided based on multiple trial and errors. 1560 */ 1561 for (i = 0; i < max_retries; i++) { 1562 if (!intel_hdcp2_get_capability(connector)) { 1563 msleep(50); 1564 continue; 1565 } 1566 1567 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1568 sizeof(msgs.ake_init)); 1569 if (ret < 0) 1570 continue; 1571 1572 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1573 &msgs.send_cert, sizeof(msgs.send_cert)); 1574 if (ret > 0) 1575 break; 1576 } 1577 1578 if (ret < 0) 1579 return ret; 1580 1581 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1582 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1583 return -EINVAL; 1584 } 1585 1586 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1587 1588 if (drm_hdcp_check_ksvs_revoked(display->drm, 1589 msgs.send_cert.cert_rx.receiver_id, 1590 1) > 0) { 1591 drm_err(display->drm, "Receiver ID is revoked\n"); 1592 return -EPERM; 1593 } 1594 1595 /* 1596 * Here msgs.no_stored_km will hold msgs corresponding to the km 1597 * stored also. 1598 */ 1599 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1600 &hdcp->is_paired, 1601 &msgs.no_stored_km, &size); 1602 if (ret < 0) 1603 return ret; 1604 1605 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1606 if (ret < 0) 1607 return ret; 1608 1609 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1610 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1611 if (ret < 0) 1612 return ret; 1613 1614 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1615 if (ret < 0) 1616 return ret; 1617 1618 if (!hdcp->is_paired) { 1619 /* Pairing is required */ 1620 ret = shim->read_2_2_msg(connector, 1621 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1622 &msgs.pairing_info, 1623 sizeof(msgs.pairing_info)); 1624 if (ret < 0) 1625 return ret; 1626 1627 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1628 if (ret < 0) 1629 return ret; 1630 hdcp->is_paired = true; 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int hdcp2_locality_check(struct intel_connector *connector) 1637 { 1638 struct intel_hdcp *hdcp = &connector->hdcp; 1639 union { 1640 struct hdcp2_lc_init lc_init; 1641 struct hdcp2_lc_send_lprime send_lprime; 1642 } msgs; 1643 const struct intel_hdcp_shim *shim = hdcp->shim; 1644 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1645 1646 for (i = 0; i < tries; i++) { 1647 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1648 if (ret < 0) 1649 continue; 1650 1651 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1652 sizeof(msgs.lc_init)); 1653 if (ret < 0) 1654 continue; 1655 1656 ret = shim->read_2_2_msg(connector, 1657 HDCP_2_2_LC_SEND_LPRIME, 1658 &msgs.send_lprime, 1659 sizeof(msgs.send_lprime)); 1660 if (ret < 0) 1661 continue; 1662 1663 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1664 if (!ret) 1665 break; 1666 } 1667 1668 return ret; 1669 } 1670 1671 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1672 { 1673 struct intel_hdcp *hdcp = &connector->hdcp; 1674 struct hdcp2_ske_send_eks send_eks; 1675 int ret; 1676 1677 ret = hdcp2_prepare_skey(connector, &send_eks); 1678 if (ret < 0) 1679 return ret; 1680 1681 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1682 sizeof(send_eks)); 1683 if (ret < 0) 1684 return ret; 1685 1686 return 0; 1687 } 1688 1689 static 1690 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1691 { 1692 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1693 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1694 struct intel_hdcp *hdcp = &connector->hdcp; 1695 union { 1696 struct hdcp2_rep_stream_manage stream_manage; 1697 struct hdcp2_rep_stream_ready stream_ready; 1698 } msgs; 1699 const struct intel_hdcp_shim *shim = hdcp->shim; 1700 int ret, streams_size_delta, i; 1701 1702 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1703 return -ERANGE; 1704 1705 /* Prepare RepeaterAuth_Stream_Manage msg */ 1706 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1707 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1708 1709 msgs.stream_manage.k = cpu_to_be16(data->k); 1710 1711 for (i = 0; i < data->k; i++) { 1712 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1713 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1714 } 1715 1716 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1717 sizeof(struct hdcp2_streamid_type); 1718 /* Send it to Repeater */ 1719 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1720 sizeof(msgs.stream_manage) - streams_size_delta); 1721 if (ret < 0) 1722 goto out; 1723 1724 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1725 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1726 if (ret < 0) 1727 goto out; 1728 1729 data->seq_num_m = hdcp->seq_num_m; 1730 1731 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1732 1733 out: 1734 hdcp->seq_num_m++; 1735 1736 return ret; 1737 } 1738 1739 static 1740 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1741 { 1742 struct intel_display *display = to_intel_display(connector); 1743 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1744 struct intel_hdcp *hdcp = &connector->hdcp; 1745 union { 1746 struct hdcp2_rep_send_receiverid_list recvid_list; 1747 struct hdcp2_rep_send_ack rep_ack; 1748 } msgs; 1749 const struct intel_hdcp_shim *shim = hdcp->shim; 1750 u32 seq_num_v, device_cnt; 1751 u8 *rx_info; 1752 int ret; 1753 1754 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1755 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1756 if (ret < 0) 1757 return ret; 1758 1759 rx_info = msgs.recvid_list.rx_info; 1760 1761 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1762 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1763 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1764 return -EINVAL; 1765 } 1766 1767 /* 1768 * MST topology is not Type 1 capable if it contains a downstream 1769 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1770 */ 1771 dig_port->hdcp_mst_type1_capable = 1772 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1773 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1774 1775 if (!dig_port->hdcp_mst_type1_capable && hdcp->content_type) { 1776 drm_dbg_kms(display->drm, 1777 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1778 return -EINVAL; 1779 } 1780 1781 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1782 seq_num_v = 1783 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1784 1785 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1786 drm_dbg_kms(display->drm, 1787 "Non zero Seq_num_v at first RecvId_List msg\n"); 1788 return -EINVAL; 1789 } 1790 1791 if (seq_num_v < hdcp->seq_num_v) { 1792 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1793 drm_dbg_kms(display->drm, "Seq_num_v roll over.\n"); 1794 return -EINVAL; 1795 } 1796 1797 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1798 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1799 if (drm_hdcp_check_ksvs_revoked(display->drm, 1800 msgs.recvid_list.receiver_ids, 1801 device_cnt) > 0) { 1802 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1803 return -EPERM; 1804 } 1805 1806 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1807 &msgs.recvid_list, 1808 &msgs.rep_ack); 1809 if (ret < 0) 1810 return ret; 1811 1812 hdcp->seq_num_v = seq_num_v; 1813 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1814 sizeof(msgs.rep_ack)); 1815 if (ret < 0) 1816 return ret; 1817 1818 return 0; 1819 } 1820 1821 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1822 { 1823 struct intel_display *display = to_intel_display(connector); 1824 struct intel_hdcp *hdcp = &connector->hdcp; 1825 const struct intel_hdcp_shim *shim = hdcp->shim; 1826 int ret; 1827 1828 ret = hdcp2_authentication_key_exchange(connector); 1829 if (ret < 0) { 1830 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1831 return ret; 1832 } 1833 1834 ret = hdcp2_locality_check(connector); 1835 if (ret < 0) { 1836 drm_dbg_kms(display->drm, 1837 "Locality Check failed. Err : %d\n", ret); 1838 return ret; 1839 } 1840 1841 ret = hdcp2_session_key_exchange(connector); 1842 if (ret < 0) { 1843 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1844 return ret; 1845 } 1846 1847 if (shim->config_stream_type) { 1848 ret = shim->config_stream_type(connector, 1849 hdcp->is_repeater, 1850 hdcp->content_type); 1851 if (ret < 0) 1852 return ret; 1853 } 1854 1855 if (hdcp->is_repeater) { 1856 ret = hdcp2_authenticate_repeater_topology(connector); 1857 if (ret < 0) { 1858 drm_dbg_kms(display->drm, 1859 "Repeater Auth Failed. Err: %d\n", ret); 1860 return ret; 1861 } 1862 } 1863 1864 return ret; 1865 } 1866 1867 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1868 { 1869 struct intel_display *display = to_intel_display(connector); 1870 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1871 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 1872 struct intel_hdcp *hdcp = &connector->hdcp; 1873 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1874 enum port port = dig_port->base.port; 1875 int ret = 0; 1876 1877 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1878 LINK_ENCRYPTION_STATUS)) { 1879 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1880 connector->base.base.id, connector->base.name); 1881 ret = -EPERM; 1882 goto link_recover; 1883 } 1884 1885 if (hdcp->shim->stream_2_2_encryption) { 1886 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1887 if (ret) { 1888 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1889 connector->base.base.id, connector->base.name); 1890 return ret; 1891 } 1892 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1893 transcoder_name(hdcp->stream_transcoder)); 1894 } 1895 1896 return 0; 1897 1898 link_recover: 1899 if (hdcp2_deauthenticate_port(connector) < 0) 1900 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1901 1902 dig_port->hdcp_auth_status = false; 1903 data->k = 0; 1904 1905 return ret; 1906 } 1907 1908 static int hdcp2_enable_encryption(struct intel_connector *connector) 1909 { 1910 struct intel_display *display = to_intel_display(connector); 1911 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1912 struct intel_hdcp *hdcp = &connector->hdcp; 1913 enum port port = dig_port->base.port; 1914 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1915 int ret; 1916 1917 drm_WARN_ON(display->drm, 1918 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1919 LINK_ENCRYPTION_STATUS); 1920 if (hdcp->shim->toggle_signalling) { 1921 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1922 true); 1923 if (ret) { 1924 drm_err(display->drm, 1925 "Failed to enable HDCP signalling. %d\n", 1926 ret); 1927 return ret; 1928 } 1929 } 1930 1931 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1932 LINK_AUTH_STATUS) 1933 /* Link is Authenticated. Now set for Encryption */ 1934 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1935 0, CTL_LINK_ENCRYPTION_REQ); 1936 1937 ret = intel_de_wait_for_set(display, 1938 HDCP2_STATUS(display, cpu_transcoder, 1939 port), 1940 LINK_ENCRYPTION_STATUS, 1941 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1942 dig_port->hdcp_auth_status = true; 1943 1944 return ret; 1945 } 1946 1947 static int hdcp2_disable_encryption(struct intel_connector *connector) 1948 { 1949 struct intel_display *display = to_intel_display(connector); 1950 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1951 struct intel_hdcp *hdcp = &connector->hdcp; 1952 enum port port = dig_port->base.port; 1953 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1954 int ret; 1955 1956 drm_WARN_ON(display->drm, 1957 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1958 LINK_ENCRYPTION_STATUS)); 1959 1960 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1961 CTL_LINK_ENCRYPTION_REQ, 0); 1962 1963 ret = intel_de_wait_for_clear(display, 1964 HDCP2_STATUS(display, cpu_transcoder, 1965 port), 1966 LINK_ENCRYPTION_STATUS, 1967 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1968 if (ret == -ETIMEDOUT) 1969 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1970 1971 if (hdcp->shim->toggle_signalling) { 1972 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1973 false); 1974 if (ret) { 1975 drm_err(display->drm, 1976 "Failed to disable HDCP signalling. %d\n", 1977 ret); 1978 return ret; 1979 } 1980 } 1981 1982 return ret; 1983 } 1984 1985 static int 1986 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1987 { 1988 struct intel_display *display = to_intel_display(connector); 1989 int i, tries = 3, ret; 1990 1991 if (!connector->hdcp.is_repeater) 1992 return 0; 1993 1994 for (i = 0; i < tries; i++) { 1995 ret = _hdcp2_propagate_stream_management_info(connector); 1996 if (!ret) 1997 break; 1998 1999 /* Lets restart the auth incase of seq_num_m roll over */ 2000 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2001 drm_dbg_kms(display->drm, 2002 "seq_num_m roll over.(%d)\n", ret); 2003 break; 2004 } 2005 2006 drm_dbg_kms(display->drm, 2007 "HDCP2 stream management %d of %d Failed.(%d)\n", 2008 i + 1, tries, ret); 2009 } 2010 2011 return ret; 2012 } 2013 2014 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2015 struct intel_connector *connector) 2016 { 2017 struct intel_display *display = to_intel_display(connector); 2018 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2019 int ret = 0, i, tries = 3; 2020 2021 for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { 2022 ret = hdcp2_authenticate_sink(connector); 2023 if (!ret) { 2024 ret = intel_hdcp_prepare_streams(state, connector); 2025 if (ret) { 2026 drm_dbg_kms(display->drm, 2027 "Prepare stream failed.(%d)\n", 2028 ret); 2029 break; 2030 } 2031 2032 ret = hdcp2_propagate_stream_management_info(connector); 2033 if (ret) { 2034 drm_dbg_kms(display->drm, 2035 "Stream management failed.(%d)\n", 2036 ret); 2037 break; 2038 } 2039 2040 ret = hdcp2_authenticate_port(connector); 2041 if (!ret) 2042 break; 2043 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2044 ret); 2045 } 2046 2047 /* Clearing the mei hdcp session */ 2048 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2049 i + 1, tries, ret); 2050 if (hdcp2_deauthenticate_port(connector) < 0) 2051 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2052 } 2053 2054 if (!ret && !dig_port->hdcp_auth_status) { 2055 /* 2056 * Ensuring the required 200mSec min time interval between 2057 * Session Key Exchange and encryption. 2058 */ 2059 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2060 ret = hdcp2_enable_encryption(connector); 2061 if (ret < 0) { 2062 drm_dbg_kms(display->drm, 2063 "Encryption Enable Failed.(%d)\n", ret); 2064 if (hdcp2_deauthenticate_port(connector) < 0) 2065 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2066 } 2067 } 2068 2069 if (!ret) 2070 ret = hdcp2_enable_stream_encryption(connector); 2071 2072 return ret; 2073 } 2074 2075 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2076 struct intel_connector *connector) 2077 { 2078 struct intel_display *display = to_intel_display(connector); 2079 struct intel_hdcp *hdcp = &connector->hdcp; 2080 int ret; 2081 2082 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2083 connector->base.base.id, connector->base.name, 2084 hdcp->content_type); 2085 2086 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2087 2088 ret = hdcp2_authenticate_and_encrypt(state, connector); 2089 if (ret) { 2090 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2091 hdcp->content_type, ret); 2092 return ret; 2093 } 2094 2095 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2096 connector->base.base.id, connector->base.name, 2097 hdcp->content_type); 2098 2099 hdcp->hdcp2_encrypted = true; 2100 return 0; 2101 } 2102 2103 static int 2104 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2105 { 2106 struct intel_display *display = to_intel_display(connector); 2107 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2108 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2109 struct intel_hdcp *hdcp = &connector->hdcp; 2110 int ret; 2111 2112 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2113 connector->base.base.id, connector->base.name); 2114 2115 if (hdcp->shim->stream_2_2_encryption) { 2116 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2117 if (ret) { 2118 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2119 connector->base.base.id, connector->base.name); 2120 return ret; 2121 } 2122 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2123 transcoder_name(hdcp->stream_transcoder)); 2124 2125 if (dig_port->num_hdcp_streams > 0 && !hdcp2_link_recovery) 2126 return 0; 2127 } 2128 2129 ret = hdcp2_disable_encryption(connector); 2130 2131 if (hdcp2_deauthenticate_port(connector) < 0) 2132 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2133 2134 connector->hdcp.hdcp2_encrypted = false; 2135 dig_port->hdcp_auth_status = false; 2136 data->k = 0; 2137 2138 return ret; 2139 } 2140 2141 /* Implements the Link Integrity Check for HDCP2.2 */ 2142 static int intel_hdcp2_check_link(struct intel_connector *connector) 2143 { 2144 struct intel_display *display = to_intel_display(connector); 2145 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2146 struct intel_hdcp *hdcp = &connector->hdcp; 2147 enum port port = dig_port->base.port; 2148 enum transcoder cpu_transcoder; 2149 int ret = 0; 2150 2151 mutex_lock(&hdcp->mutex); 2152 mutex_lock(&dig_port->hdcp_mutex); 2153 cpu_transcoder = hdcp->cpu_transcoder; 2154 2155 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2156 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2157 !hdcp->hdcp2_encrypted) { 2158 ret = -EINVAL; 2159 goto out; 2160 } 2161 2162 if (drm_WARN_ON(display->drm, 2163 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2164 drm_err(display->drm, 2165 "HDCP2.2 link stopped the encryption, %x\n", 2166 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2167 ret = -ENXIO; 2168 _intel_hdcp2_disable(connector, true); 2169 intel_hdcp_update_value(connector, 2170 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2171 true); 2172 goto out; 2173 } 2174 2175 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2176 if (ret == HDCP_LINK_PROTECTED) { 2177 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2178 intel_hdcp_update_value(connector, 2179 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2180 true); 2181 } 2182 goto out; 2183 } 2184 2185 if (ret == HDCP_TOPOLOGY_CHANGE) { 2186 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2187 goto out; 2188 2189 drm_dbg_kms(display->drm, 2190 "HDCP2.2 Downstream topology change\n"); 2191 } else { 2192 drm_dbg_kms(display->drm, 2193 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2194 connector->base.base.id, connector->base.name); 2195 } 2196 2197 ret = _intel_hdcp2_disable(connector, true); 2198 if (ret) { 2199 drm_err(display->drm, 2200 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2201 connector->base.base.id, connector->base.name, ret); 2202 intel_hdcp_update_value(connector, 2203 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2204 goto out; 2205 } 2206 2207 intel_hdcp_update_value(connector, 2208 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2209 out: 2210 mutex_unlock(&dig_port->hdcp_mutex); 2211 mutex_unlock(&hdcp->mutex); 2212 return ret; 2213 } 2214 2215 static void intel_hdcp_check_work(struct work_struct *work) 2216 { 2217 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2218 struct intel_hdcp, 2219 check_work); 2220 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2221 struct intel_display *display = to_intel_display(connector); 2222 struct drm_i915_private *i915 = to_i915(display->drm); 2223 2224 if (drm_connector_is_unregistered(&connector->base)) 2225 return; 2226 2227 if (!intel_hdcp2_check_link(connector)) 2228 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2229 DRM_HDCP2_CHECK_PERIOD_MS); 2230 else if (!intel_hdcp_check_link(connector)) 2231 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2232 DRM_HDCP_CHECK_PERIOD_MS); 2233 } 2234 2235 static int i915_hdcp_component_bind(struct device *drv_kdev, 2236 struct device *mei_kdev, void *data) 2237 { 2238 struct intel_display *display = to_intel_display(drv_kdev); 2239 2240 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2241 mutex_lock(&display->hdcp.hdcp_mutex); 2242 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2243 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2244 mutex_unlock(&display->hdcp.hdcp_mutex); 2245 2246 return 0; 2247 } 2248 2249 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2250 struct device *mei_kdev, void *data) 2251 { 2252 struct intel_display *display = to_intel_display(drv_kdev); 2253 2254 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2255 mutex_lock(&display->hdcp.hdcp_mutex); 2256 display->hdcp.arbiter = NULL; 2257 mutex_unlock(&display->hdcp.hdcp_mutex); 2258 } 2259 2260 static const struct component_ops i915_hdcp_ops = { 2261 .bind = i915_hdcp_component_bind, 2262 .unbind = i915_hdcp_component_unbind, 2263 }; 2264 2265 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2266 { 2267 switch (port) { 2268 case PORT_A: 2269 return HDCP_DDI_A; 2270 case PORT_B ... PORT_F: 2271 return (enum hdcp_ddi)port; 2272 default: 2273 return HDCP_DDI_INVALID_PORT; 2274 } 2275 } 2276 2277 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2278 { 2279 switch (cpu_transcoder) { 2280 case TRANSCODER_A ... TRANSCODER_D: 2281 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2282 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2283 return HDCP_INVALID_TRANSCODER; 2284 } 2285 } 2286 2287 static int initialize_hdcp_port_data(struct intel_connector *connector, 2288 struct intel_digital_port *dig_port, 2289 const struct intel_hdcp_shim *shim) 2290 { 2291 struct intel_display *display = to_intel_display(connector); 2292 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 2293 enum port port = dig_port->base.port; 2294 2295 if (DISPLAY_VER(display) < 12) 2296 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2297 else 2298 /* 2299 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2300 * with zero(INVALID PORT index). 2301 */ 2302 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2303 2304 /* 2305 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2306 * is initialized to zero (invalid transcoder index). This will be 2307 * retained for <Gen12 forever. 2308 */ 2309 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2310 2311 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2312 data->protocol = (u8)shim->protocol; 2313 2314 if (!data->streams) 2315 data->streams = kcalloc(INTEL_NUM_PIPES(display), 2316 sizeof(struct hdcp2_streamid_type), 2317 GFP_KERNEL); 2318 if (!data->streams) { 2319 drm_err(display->drm, "Out of Memory\n"); 2320 return -ENOMEM; 2321 } 2322 2323 return 0; 2324 } 2325 2326 static bool is_hdcp2_supported(struct intel_display *display) 2327 { 2328 struct drm_i915_private *i915 = to_i915(display->drm); 2329 2330 if (intel_hdcp_gsc_cs_required(display)) 2331 return true; 2332 2333 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2334 return false; 2335 2336 return (DISPLAY_VER(display) >= 10 || 2337 IS_KABYLAKE(i915) || 2338 IS_COFFEELAKE(i915) || 2339 IS_COMETLAKE(i915)); 2340 } 2341 2342 void intel_hdcp_component_init(struct intel_display *display) 2343 { 2344 int ret; 2345 2346 if (!is_hdcp2_supported(display)) 2347 return; 2348 2349 mutex_lock(&display->hdcp.hdcp_mutex); 2350 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2351 2352 display->hdcp.comp_added = true; 2353 mutex_unlock(&display->hdcp.hdcp_mutex); 2354 if (intel_hdcp_gsc_cs_required(display)) 2355 ret = intel_hdcp_gsc_init(display); 2356 else 2357 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2358 I915_COMPONENT_HDCP); 2359 2360 if (ret < 0) { 2361 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2362 ret); 2363 mutex_lock(&display->hdcp.hdcp_mutex); 2364 display->hdcp.comp_added = false; 2365 mutex_unlock(&display->hdcp.hdcp_mutex); 2366 return; 2367 } 2368 } 2369 2370 static void intel_hdcp2_init(struct intel_connector *connector, 2371 struct intel_digital_port *dig_port, 2372 const struct intel_hdcp_shim *shim) 2373 { 2374 struct intel_display *display = to_intel_display(connector); 2375 struct intel_hdcp *hdcp = &connector->hdcp; 2376 int ret; 2377 2378 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2379 if (ret) { 2380 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2381 return; 2382 } 2383 2384 hdcp->hdcp2_supported = true; 2385 } 2386 2387 int intel_hdcp_init(struct intel_connector *connector, 2388 struct intel_digital_port *dig_port, 2389 const struct intel_hdcp_shim *shim) 2390 { 2391 struct intel_display *display = to_intel_display(connector); 2392 struct intel_hdcp *hdcp = &connector->hdcp; 2393 int ret; 2394 2395 if (!shim) 2396 return -EINVAL; 2397 2398 if (is_hdcp2_supported(display)) 2399 intel_hdcp2_init(connector, dig_port, shim); 2400 2401 ret = drm_connector_attach_content_protection_property(&connector->base, 2402 hdcp->hdcp2_supported); 2403 if (ret) { 2404 hdcp->hdcp2_supported = false; 2405 kfree(dig_port->hdcp_port_data.streams); 2406 return ret; 2407 } 2408 2409 hdcp->shim = shim; 2410 mutex_init(&hdcp->mutex); 2411 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2412 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2413 init_waitqueue_head(&hdcp->cp_irq_queue); 2414 2415 return 0; 2416 } 2417 2418 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2419 struct intel_encoder *encoder, 2420 const struct intel_crtc_state *pipe_config, 2421 const struct drm_connector_state *conn_state) 2422 { 2423 struct intel_display *display = to_intel_display(encoder); 2424 struct drm_i915_private *i915 = to_i915(display->drm); 2425 struct intel_connector *connector = 2426 to_intel_connector(conn_state->connector); 2427 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2428 struct intel_hdcp *hdcp = &connector->hdcp; 2429 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2430 int ret = -EINVAL; 2431 2432 if (!hdcp->shim) 2433 return -ENOENT; 2434 2435 if (!connector->encoder) { 2436 drm_err(display->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n", 2437 connector->base.base.id, connector->base.name); 2438 return -ENODEV; 2439 } 2440 2441 mutex_lock(&hdcp->mutex); 2442 mutex_lock(&dig_port->hdcp_mutex); 2443 drm_WARN_ON(display->drm, 2444 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2445 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2446 2447 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2448 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2449 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2450 } else { 2451 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2452 hdcp->stream_transcoder = INVALID_TRANSCODER; 2453 } 2454 2455 if (DISPLAY_VER(display) >= 12) 2456 dig_port->hdcp_port_data.hdcp_transcoder = 2457 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2458 2459 /* 2460 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2461 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2462 */ 2463 if (intel_hdcp2_get_capability(connector)) { 2464 ret = _intel_hdcp2_enable(state, connector); 2465 if (!ret) 2466 check_link_interval = 2467 DRM_HDCP2_CHECK_PERIOD_MS; 2468 } 2469 2470 /* 2471 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2472 * be attempted. 2473 */ 2474 if (ret && intel_hdcp_get_capability(connector) && 2475 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2476 ret = intel_hdcp1_enable(connector); 2477 } 2478 2479 if (!ret) { 2480 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2481 check_link_interval); 2482 intel_hdcp_update_value(connector, 2483 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2484 true); 2485 } 2486 2487 mutex_unlock(&dig_port->hdcp_mutex); 2488 mutex_unlock(&hdcp->mutex); 2489 return ret; 2490 } 2491 2492 void intel_hdcp_enable(struct intel_atomic_state *state, 2493 struct intel_encoder *encoder, 2494 const struct intel_crtc_state *crtc_state, 2495 const struct drm_connector_state *conn_state) 2496 { 2497 struct intel_connector *connector = 2498 to_intel_connector(conn_state->connector); 2499 struct intel_hdcp *hdcp = &connector->hdcp; 2500 2501 /* 2502 * Enable hdcp if it's desired or if userspace is enabled and 2503 * driver set its state to undesired 2504 */ 2505 if (conn_state->content_protection == 2506 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2507 (conn_state->content_protection == 2508 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2509 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2510 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2511 } 2512 2513 int intel_hdcp_disable(struct intel_connector *connector) 2514 { 2515 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2516 struct intel_hdcp *hdcp = &connector->hdcp; 2517 int ret = 0; 2518 2519 if (!hdcp->shim) 2520 return -ENOENT; 2521 2522 mutex_lock(&hdcp->mutex); 2523 mutex_lock(&dig_port->hdcp_mutex); 2524 2525 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2526 goto out; 2527 2528 intel_hdcp_update_value(connector, 2529 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2530 if (hdcp->hdcp2_encrypted) 2531 ret = _intel_hdcp2_disable(connector, false); 2532 else if (hdcp->hdcp_encrypted) 2533 ret = _intel_hdcp_disable(connector); 2534 2535 out: 2536 mutex_unlock(&dig_port->hdcp_mutex); 2537 mutex_unlock(&hdcp->mutex); 2538 cancel_delayed_work_sync(&hdcp->check_work); 2539 return ret; 2540 } 2541 2542 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2543 struct intel_encoder *encoder, 2544 const struct intel_crtc_state *crtc_state, 2545 const struct drm_connector_state *conn_state) 2546 { 2547 struct intel_connector *connector = 2548 to_intel_connector(conn_state->connector); 2549 struct intel_hdcp *hdcp = &connector->hdcp; 2550 bool content_protection_type_changed, desired_and_not_enabled = false; 2551 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2552 2553 if (!connector->hdcp.shim) 2554 return; 2555 2556 content_protection_type_changed = 2557 (conn_state->hdcp_content_type != hdcp->content_type && 2558 conn_state->content_protection != 2559 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2560 2561 /* 2562 * During the HDCP encryption session if Type change is requested, 2563 * disable the HDCP and reenable it with new TYPE value. 2564 */ 2565 if (conn_state->content_protection == 2566 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2567 content_protection_type_changed) 2568 intel_hdcp_disable(connector); 2569 2570 /* 2571 * Mark the hdcp state as DESIRED after the hdcp disable of type 2572 * change procedure. 2573 */ 2574 if (content_protection_type_changed) { 2575 mutex_lock(&hdcp->mutex); 2576 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2577 drm_connector_get(&connector->base); 2578 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2579 drm_connector_put(&connector->base); 2580 mutex_unlock(&hdcp->mutex); 2581 } 2582 2583 if (conn_state->content_protection == 2584 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2585 mutex_lock(&hdcp->mutex); 2586 /* Avoid enabling hdcp, if it already ENABLED */ 2587 desired_and_not_enabled = 2588 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2589 mutex_unlock(&hdcp->mutex); 2590 /* 2591 * If HDCP already ENABLED and CP property is DESIRED, schedule 2592 * prop_work to update correct CP property to user space. 2593 */ 2594 if (!desired_and_not_enabled && !content_protection_type_changed) { 2595 drm_connector_get(&connector->base); 2596 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2597 drm_connector_put(&connector->base); 2598 2599 } 2600 } 2601 2602 if (desired_and_not_enabled || content_protection_type_changed) 2603 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2604 } 2605 2606 void intel_hdcp_component_fini(struct intel_display *display) 2607 { 2608 mutex_lock(&display->hdcp.hdcp_mutex); 2609 if (!display->hdcp.comp_added) { 2610 mutex_unlock(&display->hdcp.hdcp_mutex); 2611 return; 2612 } 2613 2614 display->hdcp.comp_added = false; 2615 mutex_unlock(&display->hdcp.hdcp_mutex); 2616 2617 if (intel_hdcp_gsc_cs_required(display)) 2618 intel_hdcp_gsc_fini(display); 2619 else 2620 component_del(display->drm->dev, &i915_hdcp_ops); 2621 } 2622 2623 void intel_hdcp_cleanup(struct intel_connector *connector) 2624 { 2625 struct intel_hdcp *hdcp = &connector->hdcp; 2626 2627 if (!hdcp->shim) 2628 return; 2629 2630 /* 2631 * If the connector is registered, it's possible userspace could kick 2632 * off another HDCP enable, which would re-spawn the workers. 2633 */ 2634 drm_WARN_ON(connector->base.dev, 2635 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2636 2637 /* 2638 * Now that the connector is not registered, check_work won't be run, 2639 * but cancel any outstanding instances of it 2640 */ 2641 cancel_delayed_work_sync(&hdcp->check_work); 2642 2643 /* 2644 * We don't cancel prop_work in the same way as check_work since it 2645 * requires connection_mutex which could be held while calling this 2646 * function. Instead, we rely on the connector references grabbed before 2647 * scheduling prop_work to ensure the connector is alive when prop_work 2648 * is run. So if we're in the destroy path (which is where this 2649 * function should be called), we're "guaranteed" that prop_work is not 2650 * active (tl;dr This Should Never Happen). 2651 */ 2652 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2653 2654 mutex_lock(&hdcp->mutex); 2655 hdcp->shim = NULL; 2656 mutex_unlock(&hdcp->mutex); 2657 } 2658 2659 void intel_hdcp_atomic_check(struct drm_connector *connector, 2660 struct drm_connector_state *old_state, 2661 struct drm_connector_state *new_state) 2662 { 2663 u64 old_cp = old_state->content_protection; 2664 u64 new_cp = new_state->content_protection; 2665 struct drm_crtc_state *crtc_state; 2666 2667 if (!new_state->crtc) { 2668 /* 2669 * If the connector is being disabled with CP enabled, mark it 2670 * desired so it's re-enabled when the connector is brought back 2671 */ 2672 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2673 new_state->content_protection = 2674 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2675 return; 2676 } 2677 2678 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2679 new_state->crtc); 2680 /* 2681 * Fix the HDCP uapi content protection state in case of modeset. 2682 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2683 * need to be sent if there is transition from ENABLED->DESIRED. 2684 */ 2685 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2686 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2687 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2688 new_state->content_protection = 2689 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2690 2691 /* 2692 * Nothing to do if the state didn't change, or HDCP was activated since 2693 * the last commit. And also no change in hdcp content type. 2694 */ 2695 if (old_cp == new_cp || 2696 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2697 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2698 if (old_state->hdcp_content_type == 2699 new_state->hdcp_content_type) 2700 return; 2701 } 2702 2703 crtc_state->mode_changed = true; 2704 } 2705 2706 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2707 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2708 { 2709 struct intel_hdcp *hdcp = &connector->hdcp; 2710 struct intel_display *display = to_intel_display(connector); 2711 struct drm_i915_private *i915 = to_i915(display->drm); 2712 2713 if (!hdcp->shim) 2714 return; 2715 2716 atomic_inc(&connector->hdcp.cp_irq_count); 2717 wake_up_all(&connector->hdcp.cp_irq_queue); 2718 2719 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); 2720 } 2721