1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/random.h> 15 16 #include <drm/display/drm_hdcp_helper.h> 17 #include <drm/intel/i915_component.h> 18 19 #include "i915_drv.h" 20 #include "i915_reg.h" 21 #include "intel_connector.h" 22 #include "intel_de.h" 23 #include "intel_display_power.h" 24 #include "intel_display_power_well.h" 25 #include "intel_display_regs.h" 26 #include "intel_display_rpm.h" 27 #include "intel_display_types.h" 28 #include "intel_dp_mst.h" 29 #include "intel_hdcp.h" 30 #include "intel_hdcp_gsc.h" 31 #include "intel_hdcp_gsc_message.h" 32 #include "intel_hdcp_regs.h" 33 #include "intel_hdcp_shim.h" 34 #include "intel_pcode.h" 35 36 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 37 38 #define KEY_LOAD_TRIES 5 39 #define HDCP2_LC_RETRY_CNT 3 40 41 static void 42 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 43 struct intel_hdcp *hdcp, 44 bool enable) 45 { 46 struct intel_display *display = to_intel_display(encoder); 47 i915_reg_t rekey_reg; 48 u32 rekey_bit = 0; 49 50 /* Here we assume HDMI is in TMDS mode of operation */ 51 if (!intel_encoder_is_hdmi(encoder)) 52 return; 53 54 if (DISPLAY_VER(display) >= 30) { 55 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 56 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 57 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 58 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 59 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 60 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 61 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 62 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 63 rekey_bit = HDCP_LINE_REKEY_DISABLE; 64 } 65 66 if (rekey_bit) 67 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 68 } 69 70 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 71 struct intel_connector *connector) 72 { 73 struct drm_dp_mst_topology_mgr *mgr; 74 struct drm_dp_mst_atomic_payload *payload; 75 struct drm_dp_mst_topology_state *mst_state; 76 int vcpi = 0; 77 78 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 79 if (!connector->mst.port) 80 return 0; 81 mgr = connector->mst.port->mgr; 82 83 drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); 84 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 85 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 86 if (drm_WARN_ON(mgr->dev, !payload)) 87 goto out; 88 89 vcpi = payload->vcpi; 90 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 91 vcpi = 0; 92 goto out; 93 } 94 out: 95 return vcpi; 96 } 97 98 /* 99 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 100 * content_type for all streams in DP MST topology because security f/w doesn't 101 * have any provision to mark content_type for each stream separately, it marks 102 * all available streams with the content_type proivided at the time of port 103 * authentication. This may prohibit the userspace to use type1 content on 104 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 105 * DP MST topology. Though it is not compulsory, security fw should change its 106 * policy to mark different content_types for different streams. 107 */ 108 static int 109 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 110 struct intel_digital_port *dig_port) 111 { 112 struct intel_display *display = to_intel_display(state); 113 struct drm_connector_list_iter conn_iter; 114 struct intel_digital_port *conn_dig_port; 115 struct intel_connector *connector; 116 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 117 bool enforce_type0 = false; 118 int k; 119 120 if (dig_port->hdcp.auth_status) 121 return 0; 122 123 data->k = 0; 124 125 if (!dig_port->hdcp.mst_type1_capable) 126 enforce_type0 = true; 127 128 drm_connector_list_iter_begin(display->drm, &conn_iter); 129 for_each_intel_connector_iter(connector, &conn_iter) { 130 if (connector->base.status == connector_status_disconnected) 131 continue; 132 133 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 134 continue; 135 136 conn_dig_port = intel_attached_dig_port(connector); 137 if (conn_dig_port != dig_port) 138 continue; 139 140 data->streams[data->k].stream_id = 141 intel_conn_to_vcpi(state, connector); 142 data->k++; 143 144 /* if there is only one active stream */ 145 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 146 break; 147 } 148 drm_connector_list_iter_end(&conn_iter); 149 150 if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0)) 151 return -EINVAL; 152 153 /* 154 * Apply common protection level across all streams in DP MST Topology. 155 * Use highest supported content type for all streams in DP MST Topology. 156 */ 157 for (k = 0; k < data->k; k++) 158 data->streams[k].stream_type = 159 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 160 161 return 0; 162 } 163 164 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 165 struct intel_connector *connector) 166 { 167 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 168 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 169 struct intel_hdcp *hdcp = &connector->hdcp; 170 171 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 172 return intel_hdcp_required_content_stream(state, dig_port); 173 174 data->k = 1; 175 data->streams[0].stream_id = 0; 176 data->streams[0].stream_type = hdcp->content_type; 177 178 return 0; 179 } 180 181 static 182 bool intel_hdcp_is_ksv_valid(u8 *ksv) 183 { 184 int i, ones = 0; 185 /* KSV has 20 1's and 20 0's */ 186 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 187 ones += hweight8(ksv[i]); 188 if (ones != 20) 189 return false; 190 191 return true; 192 } 193 194 static 195 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 196 const struct intel_hdcp_shim *shim, u8 *bksv) 197 { 198 struct intel_display *display = to_intel_display(dig_port); 199 int ret, i, tries = 2; 200 201 /* HDCP spec states that we must retry the bksv if it is invalid */ 202 for (i = 0; i < tries; i++) { 203 ret = shim->read_bksv(dig_port, bksv); 204 if (ret) 205 return ret; 206 if (intel_hdcp_is_ksv_valid(bksv)) 207 break; 208 } 209 if (i == tries) { 210 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 211 return -ENODEV; 212 } 213 214 return 0; 215 } 216 217 /* Is HDCP1.4 capable on Platform and Sink */ 218 static bool intel_hdcp_get_capability(struct intel_connector *connector) 219 { 220 struct intel_digital_port *dig_port; 221 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 222 bool capable = false; 223 u8 bksv[5]; 224 225 if (!intel_attached_encoder(connector)) 226 return capable; 227 228 dig_port = intel_attached_dig_port(connector); 229 230 if (!shim) 231 return capable; 232 233 if (shim->hdcp_get_capability) { 234 shim->hdcp_get_capability(dig_port, &capable); 235 } else { 236 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 237 capable = true; 238 } 239 240 return capable; 241 } 242 243 /* 244 * Check if the source has all the building blocks ready to make 245 * HDCP 2.2 work 246 */ 247 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 248 { 249 struct intel_display *display = to_intel_display(connector); 250 struct intel_hdcp *hdcp = &connector->hdcp; 251 252 /* I915 support for HDCP2.2 */ 253 if (!hdcp->hdcp2_supported) 254 return false; 255 256 /* If MTL+ make sure gsc is loaded and proxy is setup */ 257 if (USE_HDCP_GSC(display)) { 258 if (!intel_hdcp_gsc_check_status(display->drm)) 259 return false; 260 } 261 262 /* MEI/GSC interface is solid depending on which is used */ 263 mutex_lock(&display->hdcp.hdcp_mutex); 264 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 265 mutex_unlock(&display->hdcp.hdcp_mutex); 266 return false; 267 } 268 mutex_unlock(&display->hdcp.hdcp_mutex); 269 270 return true; 271 } 272 273 /* Is HDCP2.2 capable on Platform and Sink */ 274 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 275 { 276 struct intel_hdcp *hdcp = &connector->hdcp; 277 bool capable = false; 278 279 if (!intel_hdcp2_prerequisite(connector)) 280 return false; 281 282 /* Sink's capability for HDCP2.2 */ 283 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 284 285 return capable; 286 } 287 288 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 289 bool *hdcp_capable, 290 bool *hdcp2_capable) 291 { 292 struct intel_hdcp *hdcp = &connector->hdcp; 293 294 if (!hdcp->shim->get_remote_hdcp_capability) 295 return; 296 297 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 298 hdcp2_capable); 299 300 if (!intel_hdcp2_prerequisite(connector)) 301 *hdcp2_capable = false; 302 } 303 304 static bool intel_hdcp_in_use(struct intel_display *display, 305 enum transcoder cpu_transcoder, enum port port) 306 { 307 return intel_de_read(display, 308 HDCP_STATUS(display, cpu_transcoder, port)) & 309 HDCP_STATUS_ENC; 310 } 311 312 static bool intel_hdcp2_in_use(struct intel_display *display, 313 enum transcoder cpu_transcoder, enum port port) 314 { 315 return intel_de_read(display, 316 HDCP2_STATUS(display, cpu_transcoder, port)) & 317 LINK_ENCRYPTION_STATUS; 318 } 319 320 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 321 const struct intel_hdcp_shim *shim) 322 { 323 int ret, read_ret; 324 bool ksv_ready; 325 326 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 327 ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, 328 &ksv_ready), 329 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 330 100 * 1000); 331 if (ret) 332 return ret; 333 if (read_ret) 334 return read_ret; 335 if (!ksv_ready) 336 return -ETIMEDOUT; 337 338 return 0; 339 } 340 341 static bool hdcp_key_loadable(struct intel_display *display) 342 { 343 enum i915_power_well_id id; 344 bool enabled = false; 345 346 /* 347 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 348 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 349 */ 350 if (display->platform.haswell || display->platform.broadwell) 351 id = HSW_DISP_PW_GLOBAL; 352 else 353 id = SKL_DISP_PW_1; 354 355 /* PG1 (power well #1) needs to be enabled */ 356 with_intel_display_rpm(display) 357 enabled = intel_display_power_well_is_enabled(display, id); 358 359 /* 360 * Another req for hdcp key loadability is enabled state of pll for 361 * cdclk. Without active crtc we won't land here. So we are assuming that 362 * cdclk is already on. 363 */ 364 365 return enabled; 366 } 367 368 static void intel_hdcp_clear_keys(struct intel_display *display) 369 { 370 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 371 intel_de_write(display, HDCP_KEY_STATUS, 372 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 373 } 374 375 static int intel_hdcp_load_keys(struct intel_display *display) 376 { 377 struct drm_i915_private *i915 = to_i915(display->drm); 378 int ret; 379 u32 val; 380 381 val = intel_de_read(display, HDCP_KEY_STATUS); 382 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 383 return 0; 384 385 /* 386 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 387 * out of reset. So if Key is not already loaded, its an error state. 388 */ 389 if (display->platform.haswell || display->platform.broadwell) 390 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 391 return -ENXIO; 392 393 /* 394 * Initiate loading the HDCP key from fuses. 395 * 396 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 397 * version 9 platforms (minus BXT) differ in the key load trigger 398 * process from other platforms. These platforms use the GT Driver 399 * Mailbox interface. 400 */ 401 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 402 ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); 403 if (ret) { 404 drm_err(display->drm, 405 "Failed to initiate HDCP key load (%d)\n", 406 ret); 407 return ret; 408 } 409 } else { 410 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 411 } 412 413 /* Wait for the keys to load (500us) */ 414 ret = intel_de_wait_custom(display, HDCP_KEY_STATUS, 415 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 416 10, 1, &val); 417 if (ret) 418 return ret; 419 else if (!(val & HDCP_KEY_LOAD_STATUS)) 420 return -ENXIO; 421 422 /* Send Aksv over to PCH display for use in authentication */ 423 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 424 425 return 0; 426 } 427 428 /* Returns updated SHA-1 index */ 429 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 430 { 431 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 432 if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 433 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 434 return -ETIMEDOUT; 435 } 436 return 0; 437 } 438 439 static 440 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 441 enum transcoder cpu_transcoder, enum port port) 442 { 443 if (DISPLAY_VER(display) >= 12) { 444 switch (cpu_transcoder) { 445 case TRANSCODER_A: 446 return HDCP_TRANSA_REP_PRESENT | 447 HDCP_TRANSA_SHA1_M0; 448 case TRANSCODER_B: 449 return HDCP_TRANSB_REP_PRESENT | 450 HDCP_TRANSB_SHA1_M0; 451 case TRANSCODER_C: 452 return HDCP_TRANSC_REP_PRESENT | 453 HDCP_TRANSC_SHA1_M0; 454 case TRANSCODER_D: 455 return HDCP_TRANSD_REP_PRESENT | 456 HDCP_TRANSD_SHA1_M0; 457 default: 458 drm_err(display->drm, "Unknown transcoder %d\n", 459 cpu_transcoder); 460 return 0; 461 } 462 } 463 464 switch (port) { 465 case PORT_A: 466 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 467 case PORT_B: 468 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 469 case PORT_C: 470 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 471 case PORT_D: 472 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 473 case PORT_E: 474 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 475 default: 476 drm_err(display->drm, "Unknown port %d\n", port); 477 return 0; 478 } 479 } 480 481 static 482 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 483 const struct intel_hdcp_shim *shim, 484 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 485 { 486 struct intel_display *display = to_intel_display(connector); 487 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 488 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 489 enum port port = dig_port->base.port; 490 u32 vprime, sha_text, sha_leftovers, rep_ctl; 491 int ret, i, j, sha_idx; 492 493 /* Process V' values from the receiver */ 494 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 495 ret = shim->read_v_prime_part(dig_port, i, &vprime); 496 if (ret) 497 return ret; 498 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 499 } 500 501 /* 502 * We need to write the concatenation of all device KSVs, BINFO (DP) || 503 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 504 * stream is written via the HDCP_SHA_TEXT register in 32-bit 505 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 506 * index will keep track of our progress through the 64 bytes as well as 507 * helping us work the 40-bit KSVs through our 32-bit register. 508 * 509 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 510 */ 511 sha_idx = 0; 512 sha_text = 0; 513 sha_leftovers = 0; 514 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 515 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 516 for (i = 0; i < num_downstream; i++) { 517 unsigned int sha_empty; 518 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 519 520 /* Fill up the empty slots in sha_text and write it out */ 521 sha_empty = sizeof(sha_text) - sha_leftovers; 522 for (j = 0; j < sha_empty; j++) { 523 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 524 sha_text |= ksv[j] << off; 525 } 526 527 ret = intel_write_sha_text(display, sha_text); 528 if (ret < 0) 529 return ret; 530 531 /* Programming guide writes this every 64 bytes */ 532 sha_idx += sizeof(sha_text); 533 if (!(sha_idx % 64)) 534 intel_de_write(display, HDCP_REP_CTL, 535 rep_ctl | HDCP_SHA1_TEXT_32); 536 537 /* Store the leftover bytes from the ksv in sha_text */ 538 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 539 sha_text = 0; 540 for (j = 0; j < sha_leftovers; j++) 541 sha_text |= ksv[sha_empty + j] << 542 ((sizeof(sha_text) - j - 1) * 8); 543 544 /* 545 * If we still have room in sha_text for more data, continue. 546 * Otherwise, write it out immediately. 547 */ 548 if (sizeof(sha_text) > sha_leftovers) 549 continue; 550 551 ret = intel_write_sha_text(display, sha_text); 552 if (ret < 0) 553 return ret; 554 sha_leftovers = 0; 555 sha_text = 0; 556 sha_idx += sizeof(sha_text); 557 } 558 559 /* 560 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 561 * bytes are leftover from the last ksv, we might be able to fit them 562 * all in sha_text (first 2 cases), or we might need to split them up 563 * into 2 writes (last 2 cases). 564 */ 565 if (sha_leftovers == 0) { 566 /* Write 16 bits of text, 16 bits of M0 */ 567 intel_de_write(display, HDCP_REP_CTL, 568 rep_ctl | HDCP_SHA1_TEXT_16); 569 ret = intel_write_sha_text(display, 570 bstatus[0] << 8 | bstatus[1]); 571 if (ret < 0) 572 return ret; 573 sha_idx += sizeof(sha_text); 574 575 /* Write 32 bits of M0 */ 576 intel_de_write(display, HDCP_REP_CTL, 577 rep_ctl | HDCP_SHA1_TEXT_0); 578 ret = intel_write_sha_text(display, 0); 579 if (ret < 0) 580 return ret; 581 sha_idx += sizeof(sha_text); 582 583 /* Write 16 bits of M0 */ 584 intel_de_write(display, HDCP_REP_CTL, 585 rep_ctl | HDCP_SHA1_TEXT_16); 586 ret = intel_write_sha_text(display, 0); 587 if (ret < 0) 588 return ret; 589 sha_idx += sizeof(sha_text); 590 591 } else if (sha_leftovers == 1) { 592 /* Write 24 bits of text, 8 bits of M0 */ 593 intel_de_write(display, HDCP_REP_CTL, 594 rep_ctl | HDCP_SHA1_TEXT_24); 595 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 596 /* Only 24-bits of data, must be in the LSB */ 597 sha_text = (sha_text & 0xffffff00) >> 8; 598 ret = intel_write_sha_text(display, sha_text); 599 if (ret < 0) 600 return ret; 601 sha_idx += sizeof(sha_text); 602 603 /* Write 32 bits of M0 */ 604 intel_de_write(display, HDCP_REP_CTL, 605 rep_ctl | HDCP_SHA1_TEXT_0); 606 ret = intel_write_sha_text(display, 0); 607 if (ret < 0) 608 return ret; 609 sha_idx += sizeof(sha_text); 610 611 /* Write 24 bits of M0 */ 612 intel_de_write(display, HDCP_REP_CTL, 613 rep_ctl | HDCP_SHA1_TEXT_8); 614 ret = intel_write_sha_text(display, 0); 615 if (ret < 0) 616 return ret; 617 sha_idx += sizeof(sha_text); 618 619 } else if (sha_leftovers == 2) { 620 /* Write 32 bits of text */ 621 intel_de_write(display, HDCP_REP_CTL, 622 rep_ctl | HDCP_SHA1_TEXT_32); 623 sha_text |= bstatus[0] << 8 | bstatus[1]; 624 ret = intel_write_sha_text(display, sha_text); 625 if (ret < 0) 626 return ret; 627 sha_idx += sizeof(sha_text); 628 629 /* Write 64 bits of M0 */ 630 intel_de_write(display, HDCP_REP_CTL, 631 rep_ctl | HDCP_SHA1_TEXT_0); 632 for (i = 0; i < 2; i++) { 633 ret = intel_write_sha_text(display, 0); 634 if (ret < 0) 635 return ret; 636 sha_idx += sizeof(sha_text); 637 } 638 639 /* 640 * Terminate the SHA-1 stream by hand. For the other leftover 641 * cases this is appended by the hardware. 642 */ 643 intel_de_write(display, HDCP_REP_CTL, 644 rep_ctl | HDCP_SHA1_TEXT_32); 645 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 646 ret = intel_write_sha_text(display, sha_text); 647 if (ret < 0) 648 return ret; 649 sha_idx += sizeof(sha_text); 650 } else if (sha_leftovers == 3) { 651 /* Write 32 bits of text (filled from LSB) */ 652 intel_de_write(display, HDCP_REP_CTL, 653 rep_ctl | HDCP_SHA1_TEXT_32); 654 sha_text |= bstatus[0]; 655 ret = intel_write_sha_text(display, sha_text); 656 if (ret < 0) 657 return ret; 658 sha_idx += sizeof(sha_text); 659 660 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 661 intel_de_write(display, HDCP_REP_CTL, 662 rep_ctl | HDCP_SHA1_TEXT_8); 663 ret = intel_write_sha_text(display, bstatus[1]); 664 if (ret < 0) 665 return ret; 666 sha_idx += sizeof(sha_text); 667 668 /* Write 32 bits of M0 */ 669 intel_de_write(display, HDCP_REP_CTL, 670 rep_ctl | HDCP_SHA1_TEXT_0); 671 ret = intel_write_sha_text(display, 0); 672 if (ret < 0) 673 return ret; 674 sha_idx += sizeof(sha_text); 675 676 /* Write 8 bits of M0 */ 677 intel_de_write(display, HDCP_REP_CTL, 678 rep_ctl | HDCP_SHA1_TEXT_24); 679 ret = intel_write_sha_text(display, 0); 680 if (ret < 0) 681 return ret; 682 sha_idx += sizeof(sha_text); 683 } else { 684 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 685 sha_leftovers); 686 return -EINVAL; 687 } 688 689 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 690 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 691 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 692 ret = intel_write_sha_text(display, 0); 693 if (ret < 0) 694 return ret; 695 sha_idx += sizeof(sha_text); 696 } 697 698 /* 699 * Last write gets the length of the concatenation in bits. That is: 700 * - 5 bytes per device 701 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 702 */ 703 sha_text = (num_downstream * 5 + 10) * 8; 704 ret = intel_write_sha_text(display, sha_text); 705 if (ret < 0) 706 return ret; 707 708 /* Tell the HW we're done with the hash and wait for it to ACK */ 709 intel_de_write(display, HDCP_REP_CTL, 710 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 711 if (intel_de_wait_for_set(display, HDCP_REP_CTL, 712 HDCP_SHA1_COMPLETE, 1)) { 713 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 714 return -ETIMEDOUT; 715 } 716 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 717 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 718 return -ENXIO; 719 } 720 721 return 0; 722 } 723 724 /* Implements Part 2 of the HDCP authorization procedure */ 725 static 726 int intel_hdcp_auth_downstream(struct intel_connector *connector) 727 { 728 struct intel_display *display = to_intel_display(connector); 729 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 730 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 731 u8 bstatus[2], num_downstream, *ksv_fifo; 732 int ret, i, tries = 3; 733 734 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 735 if (ret) { 736 drm_dbg_kms(display->drm, 737 "KSV list failed to become ready (%d)\n", ret); 738 return ret; 739 } 740 741 ret = shim->read_bstatus(dig_port, bstatus); 742 if (ret) 743 return ret; 744 745 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 746 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 747 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 748 return -EPERM; 749 } 750 751 /* 752 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 753 * the HDCP encryption. That implies that repeater can't have its own 754 * display. As there is no consumption of encrypted content in the 755 * repeater with 0 downstream devices, we are failing the 756 * authentication. 757 */ 758 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 759 if (num_downstream == 0) { 760 drm_dbg_kms(display->drm, 761 "Repeater with zero downstream devices\n"); 762 return -EINVAL; 763 } 764 765 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 766 if (!ksv_fifo) { 767 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 768 return -ENOMEM; 769 } 770 771 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 772 if (ret) 773 goto err; 774 775 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 776 num_downstream) > 0) { 777 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 778 ret = -EPERM; 779 goto err; 780 } 781 782 /* 783 * When V prime mismatches, DP Spec mandates re-read of 784 * V prime atleast twice. 785 */ 786 for (i = 0; i < tries; i++) { 787 ret = intel_hdcp_validate_v_prime(connector, shim, 788 ksv_fifo, num_downstream, 789 bstatus); 790 if (!ret) 791 break; 792 } 793 794 if (i == tries) { 795 drm_dbg_kms(display->drm, 796 "V Prime validation failed.(%d)\n", ret); 797 goto err; 798 } 799 800 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 801 num_downstream); 802 ret = 0; 803 err: 804 kfree(ksv_fifo); 805 return ret; 806 } 807 808 /* Implements Part 1 of the HDCP authorization procedure */ 809 static int intel_hdcp_auth(struct intel_connector *connector) 810 { 811 struct intel_display *display = to_intel_display(connector); 812 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 813 struct intel_hdcp *hdcp = &connector->hdcp; 814 const struct intel_hdcp_shim *shim = hdcp->shim; 815 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 816 enum port port = dig_port->base.port; 817 unsigned long r0_prime_gen_start; 818 int ret, i, tries = 2; 819 union { 820 u32 reg[2]; 821 u8 shim[DRM_HDCP_AN_LEN]; 822 } an; 823 union { 824 u32 reg[2]; 825 u8 shim[DRM_HDCP_KSV_LEN]; 826 } bksv; 827 union { 828 u32 reg; 829 u8 shim[DRM_HDCP_RI_LEN]; 830 } ri; 831 bool repeater_present, hdcp_capable; 832 833 /* 834 * Detects whether the display is HDCP capable. Although we check for 835 * valid Bksv below, the HDCP over DP spec requires that we check 836 * whether the display supports HDCP before we write An. For HDMI 837 * displays, this is not necessary. 838 */ 839 if (shim->hdcp_get_capability) { 840 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 841 if (ret) 842 return ret; 843 if (!hdcp_capable) { 844 drm_dbg_kms(display->drm, 845 "Panel is not HDCP capable\n"); 846 return -EINVAL; 847 } 848 } 849 850 /* Initialize An with 2 random values and acquire it */ 851 for (i = 0; i < 2; i++) 852 intel_de_write(display, 853 HDCP_ANINIT(display, cpu_transcoder, port), 854 get_random_u32()); 855 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 856 HDCP_CONF_CAPTURE_AN); 857 858 /* Wait for An to be acquired */ 859 if (intel_de_wait_for_set(display, 860 HDCP_STATUS(display, cpu_transcoder, port), 861 HDCP_STATUS_AN_READY, 1)) { 862 drm_err(display->drm, "Timed out waiting for An\n"); 863 return -ETIMEDOUT; 864 } 865 866 an.reg[0] = intel_de_read(display, 867 HDCP_ANLO(display, cpu_transcoder, port)); 868 an.reg[1] = intel_de_read(display, 869 HDCP_ANHI(display, cpu_transcoder, port)); 870 ret = shim->write_an_aksv(dig_port, an.shim); 871 if (ret) 872 return ret; 873 874 r0_prime_gen_start = jiffies; 875 876 memset(&bksv, 0, sizeof(bksv)); 877 878 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 879 if (ret < 0) 880 return ret; 881 882 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 883 drm_err(display->drm, "BKSV is revoked\n"); 884 return -EPERM; 885 } 886 887 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 888 bksv.reg[0]); 889 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 890 bksv.reg[1]); 891 892 ret = shim->repeater_present(dig_port, &repeater_present); 893 if (ret) 894 return ret; 895 if (repeater_present) 896 intel_de_write(display, HDCP_REP_CTL, 897 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 898 899 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 900 if (ret) 901 return ret; 902 903 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 904 HDCP_CONF_AUTH_AND_ENC); 905 906 /* Wait for R0 ready */ 907 if (wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 908 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 909 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 910 return -ETIMEDOUT; 911 } 912 913 /* 914 * Wait for R0' to become available. The spec says 100ms from Aksv, but 915 * some monitors can take longer than this. We'll set the timeout at 916 * 300ms just to be sure. 917 * 918 * On DP, there's an R0_READY bit available but no such bit 919 * exists on HDMI. Since the upper-bound is the same, we'll just do 920 * the stupid thing instead of polling on one and not the other. 921 */ 922 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 923 924 tries = 3; 925 926 /* 927 * DP HDCP Spec mandates the two more reattempt to read R0, incase 928 * of R0 mismatch. 929 */ 930 for (i = 0; i < tries; i++) { 931 ri.reg = 0; 932 ret = shim->read_ri_prime(dig_port, ri.shim); 933 if (ret) 934 return ret; 935 intel_de_write(display, 936 HDCP_RPRIME(display, cpu_transcoder, port), 937 ri.reg); 938 939 /* Wait for Ri prime match */ 940 if (!wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 941 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 942 break; 943 } 944 945 if (i == tries) { 946 drm_dbg_kms(display->drm, 947 "Timed out waiting for Ri prime match (%x)\n", 948 intel_de_read(display, 949 HDCP_STATUS(display, cpu_transcoder, port))); 950 return -ETIMEDOUT; 951 } 952 953 /* Wait for encryption confirmation */ 954 if (intel_de_wait_for_set(display, 955 HDCP_STATUS(display, cpu_transcoder, port), 956 HDCP_STATUS_ENC, 957 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 958 drm_err(display->drm, "Timed out waiting for encryption\n"); 959 return -ETIMEDOUT; 960 } 961 962 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 963 if (shim->stream_encryption) { 964 ret = shim->stream_encryption(connector, true); 965 if (ret) { 966 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 967 connector->base.base.id, connector->base.name); 968 return ret; 969 } 970 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 971 transcoder_name(hdcp->stream_transcoder)); 972 } 973 974 if (repeater_present) 975 return intel_hdcp_auth_downstream(connector); 976 977 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 978 return 0; 979 } 980 981 static int _intel_hdcp_disable(struct intel_connector *connector) 982 { 983 struct intel_display *display = to_intel_display(connector); 984 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 985 struct intel_hdcp *hdcp = &connector->hdcp; 986 enum port port = dig_port->base.port; 987 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 988 u32 repeater_ctl; 989 int ret; 990 991 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 992 connector->base.base.id, connector->base.name); 993 994 if (hdcp->shim->stream_encryption) { 995 ret = hdcp->shim->stream_encryption(connector, false); 996 if (ret) { 997 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 998 connector->base.base.id, connector->base.name); 999 return ret; 1000 } 1001 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1002 transcoder_name(hdcp->stream_transcoder)); 1003 /* 1004 * If there are other connectors on this port using HDCP, 1005 * don't disable it until it disabled HDCP encryption for 1006 * all connectors in MST topology. 1007 */ 1008 if (dig_port->hdcp.num_streams > 0) 1009 return 0; 1010 } 1011 1012 hdcp->hdcp_encrypted = false; 1013 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1014 if (intel_de_wait_for_clear(display, 1015 HDCP_STATUS(display, cpu_transcoder, port), 1016 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1017 drm_err(display->drm, 1018 "Failed to disable HDCP, timeout clearing status\n"); 1019 return -ETIMEDOUT; 1020 } 1021 1022 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1023 port); 1024 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1025 1026 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1027 if (ret) { 1028 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1029 return ret; 1030 } 1031 1032 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1033 return 0; 1034 } 1035 1036 static int intel_hdcp1_enable(struct intel_connector *connector) 1037 { 1038 struct intel_display *display = to_intel_display(connector); 1039 struct intel_hdcp *hdcp = &connector->hdcp; 1040 int i, ret, tries = 3; 1041 1042 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1043 connector->base.base.id, connector->base.name); 1044 1045 if (!hdcp_key_loadable(display)) { 1046 drm_err(display->drm, "HDCP key Load is not possible\n"); 1047 return -ENXIO; 1048 } 1049 1050 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1051 ret = intel_hdcp_load_keys(display); 1052 if (!ret) 1053 break; 1054 intel_hdcp_clear_keys(display); 1055 } 1056 if (ret) { 1057 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1058 ret); 1059 return ret; 1060 } 1061 1062 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1063 1064 /* Incase of authentication failures, HDCP spec expects reauth. */ 1065 for (i = 0; i < tries; i++) { 1066 ret = intel_hdcp_auth(connector); 1067 if (!ret) { 1068 hdcp->hdcp_encrypted = true; 1069 return 0; 1070 } 1071 1072 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1073 1074 /* Ensuring HDCP encryption and signalling are stopped. */ 1075 _intel_hdcp_disable(connector); 1076 } 1077 1078 drm_dbg_kms(display->drm, 1079 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1080 return ret; 1081 } 1082 1083 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1084 { 1085 return container_of(hdcp, struct intel_connector, hdcp); 1086 } 1087 1088 static void intel_hdcp_update_value(struct intel_connector *connector, 1089 u64 value, bool update_property) 1090 { 1091 struct intel_display *display = to_intel_display(connector); 1092 struct drm_i915_private *i915 = to_i915(display->drm); 1093 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1094 struct intel_hdcp *hdcp = &connector->hdcp; 1095 1096 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1097 1098 if (hdcp->value == value) 1099 return; 1100 1101 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1102 1103 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1104 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1105 dig_port->hdcp.num_streams--; 1106 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1107 dig_port->hdcp.num_streams++; 1108 } 1109 1110 hdcp->value = value; 1111 if (update_property) { 1112 drm_connector_get(&connector->base); 1113 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 1114 drm_connector_put(&connector->base); 1115 } 1116 } 1117 1118 /* Implements Part 3 of the HDCP authorization procedure */ 1119 static int intel_hdcp_check_link(struct intel_connector *connector) 1120 { 1121 struct intel_display *display = to_intel_display(connector); 1122 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1123 struct intel_hdcp *hdcp = &connector->hdcp; 1124 enum port port = dig_port->base.port; 1125 enum transcoder cpu_transcoder; 1126 int ret = 0; 1127 1128 mutex_lock(&hdcp->mutex); 1129 mutex_lock(&dig_port->hdcp.mutex); 1130 1131 cpu_transcoder = hdcp->cpu_transcoder; 1132 1133 /* Check_link valid only when HDCP1.4 is enabled */ 1134 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1135 !hdcp->hdcp_encrypted) { 1136 ret = -EINVAL; 1137 goto out; 1138 } 1139 1140 if (drm_WARN_ON(display->drm, 1141 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1142 drm_err(display->drm, 1143 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1144 connector->base.base.id, connector->base.name, 1145 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1146 ret = -ENXIO; 1147 intel_hdcp_update_value(connector, 1148 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1149 true); 1150 goto out; 1151 } 1152 1153 if (hdcp->shim->check_link(dig_port, connector)) { 1154 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1155 intel_hdcp_update_value(connector, 1156 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1157 } 1158 goto out; 1159 } 1160 1161 drm_dbg_kms(display->drm, 1162 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1163 connector->base.base.id, connector->base.name); 1164 1165 ret = _intel_hdcp_disable(connector); 1166 if (ret) { 1167 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1168 intel_hdcp_update_value(connector, 1169 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1170 true); 1171 goto out; 1172 } 1173 1174 ret = intel_hdcp1_enable(connector); 1175 if (ret) { 1176 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1177 intel_hdcp_update_value(connector, 1178 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1179 true); 1180 goto out; 1181 } 1182 1183 out: 1184 mutex_unlock(&dig_port->hdcp.mutex); 1185 mutex_unlock(&hdcp->mutex); 1186 return ret; 1187 } 1188 1189 static void intel_hdcp_prop_work(struct work_struct *work) 1190 { 1191 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1192 prop_work); 1193 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1194 struct intel_display *display = to_intel_display(connector); 1195 1196 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1197 mutex_lock(&hdcp->mutex); 1198 1199 /* 1200 * This worker is only used to flip between ENABLED/DESIRED. Either of 1201 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1202 * we're running just after hdcp has been disabled, so just exit 1203 */ 1204 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1205 drm_hdcp_update_content_protection(&connector->base, 1206 hdcp->value); 1207 1208 mutex_unlock(&hdcp->mutex); 1209 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1210 1211 drm_connector_put(&connector->base); 1212 } 1213 1214 bool is_hdcp_supported(struct intel_display *display, enum port port) 1215 { 1216 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1217 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1218 } 1219 1220 static int 1221 hdcp2_prepare_ake_init(struct intel_connector *connector, 1222 struct hdcp2_ake_init *ake_data) 1223 { 1224 struct intel_display *display = to_intel_display(connector); 1225 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1226 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1227 struct i915_hdcp_arbiter *arbiter; 1228 int ret; 1229 1230 mutex_lock(&display->hdcp.hdcp_mutex); 1231 arbiter = display->hdcp.arbiter; 1232 1233 if (!arbiter || !arbiter->ops) { 1234 mutex_unlock(&display->hdcp.hdcp_mutex); 1235 return -EINVAL; 1236 } 1237 1238 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1239 if (ret) 1240 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1241 ret); 1242 mutex_unlock(&display->hdcp.hdcp_mutex); 1243 1244 return ret; 1245 } 1246 1247 static int 1248 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1249 struct hdcp2_ake_send_cert *rx_cert, 1250 bool *paired, 1251 struct hdcp2_ake_no_stored_km *ek_pub_km, 1252 size_t *msg_sz) 1253 { 1254 struct intel_display *display = to_intel_display(connector); 1255 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1256 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1257 struct i915_hdcp_arbiter *arbiter; 1258 int ret; 1259 1260 mutex_lock(&display->hdcp.hdcp_mutex); 1261 arbiter = display->hdcp.arbiter; 1262 1263 if (!arbiter || !arbiter->ops) { 1264 mutex_unlock(&display->hdcp.hdcp_mutex); 1265 return -EINVAL; 1266 } 1267 1268 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1269 rx_cert, paired, 1270 ek_pub_km, msg_sz); 1271 if (ret < 0) 1272 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1273 ret); 1274 mutex_unlock(&display->hdcp.hdcp_mutex); 1275 1276 return ret; 1277 } 1278 1279 static int hdcp2_verify_hprime(struct intel_connector *connector, 1280 struct hdcp2_ake_send_hprime *rx_hprime) 1281 { 1282 struct intel_display *display = to_intel_display(connector); 1283 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1284 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1285 struct i915_hdcp_arbiter *arbiter; 1286 int ret; 1287 1288 mutex_lock(&display->hdcp.hdcp_mutex); 1289 arbiter = display->hdcp.arbiter; 1290 1291 if (!arbiter || !arbiter->ops) { 1292 mutex_unlock(&display->hdcp.hdcp_mutex); 1293 return -EINVAL; 1294 } 1295 1296 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1297 if (ret < 0) 1298 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1299 mutex_unlock(&display->hdcp.hdcp_mutex); 1300 1301 return ret; 1302 } 1303 1304 static int 1305 hdcp2_store_pairing_info(struct intel_connector *connector, 1306 struct hdcp2_ake_send_pairing_info *pairing_info) 1307 { 1308 struct intel_display *display = to_intel_display(connector); 1309 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1310 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1311 struct i915_hdcp_arbiter *arbiter; 1312 int ret; 1313 1314 mutex_lock(&display->hdcp.hdcp_mutex); 1315 arbiter = display->hdcp.arbiter; 1316 1317 if (!arbiter || !arbiter->ops) { 1318 mutex_unlock(&display->hdcp.hdcp_mutex); 1319 return -EINVAL; 1320 } 1321 1322 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1323 if (ret < 0) 1324 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1325 ret); 1326 mutex_unlock(&display->hdcp.hdcp_mutex); 1327 1328 return ret; 1329 } 1330 1331 static int 1332 hdcp2_prepare_lc_init(struct intel_connector *connector, 1333 struct hdcp2_lc_init *lc_init) 1334 { 1335 struct intel_display *display = to_intel_display(connector); 1336 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1337 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1338 struct i915_hdcp_arbiter *arbiter; 1339 int ret; 1340 1341 mutex_lock(&display->hdcp.hdcp_mutex); 1342 arbiter = display->hdcp.arbiter; 1343 1344 if (!arbiter || !arbiter->ops) { 1345 mutex_unlock(&display->hdcp.hdcp_mutex); 1346 return -EINVAL; 1347 } 1348 1349 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1350 if (ret < 0) 1351 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1352 ret); 1353 mutex_unlock(&display->hdcp.hdcp_mutex); 1354 1355 return ret; 1356 } 1357 1358 static int 1359 hdcp2_verify_lprime(struct intel_connector *connector, 1360 struct hdcp2_lc_send_lprime *rx_lprime) 1361 { 1362 struct intel_display *display = to_intel_display(connector); 1363 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1364 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1365 struct i915_hdcp_arbiter *arbiter; 1366 int ret; 1367 1368 mutex_lock(&display->hdcp.hdcp_mutex); 1369 arbiter = display->hdcp.arbiter; 1370 1371 if (!arbiter || !arbiter->ops) { 1372 mutex_unlock(&display->hdcp.hdcp_mutex); 1373 return -EINVAL; 1374 } 1375 1376 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1377 if (ret < 0) 1378 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1379 ret); 1380 mutex_unlock(&display->hdcp.hdcp_mutex); 1381 1382 return ret; 1383 } 1384 1385 static int hdcp2_prepare_skey(struct intel_connector *connector, 1386 struct hdcp2_ske_send_eks *ske_data) 1387 { 1388 struct intel_display *display = to_intel_display(connector); 1389 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1390 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1391 struct i915_hdcp_arbiter *arbiter; 1392 int ret; 1393 1394 mutex_lock(&display->hdcp.hdcp_mutex); 1395 arbiter = display->hdcp.arbiter; 1396 1397 if (!arbiter || !arbiter->ops) { 1398 mutex_unlock(&display->hdcp.hdcp_mutex); 1399 return -EINVAL; 1400 } 1401 1402 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1403 if (ret < 0) 1404 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1405 ret); 1406 mutex_unlock(&display->hdcp.hdcp_mutex); 1407 1408 return ret; 1409 } 1410 1411 static int 1412 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1413 struct hdcp2_rep_send_receiverid_list 1414 *rep_topology, 1415 struct hdcp2_rep_send_ack *rep_send_ack) 1416 { 1417 struct intel_display *display = to_intel_display(connector); 1418 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1419 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1420 struct i915_hdcp_arbiter *arbiter; 1421 int ret; 1422 1423 mutex_lock(&display->hdcp.hdcp_mutex); 1424 arbiter = display->hdcp.arbiter; 1425 1426 if (!arbiter || !arbiter->ops) { 1427 mutex_unlock(&display->hdcp.hdcp_mutex); 1428 return -EINVAL; 1429 } 1430 1431 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1432 data, 1433 rep_topology, 1434 rep_send_ack); 1435 if (ret < 0) 1436 drm_dbg_kms(display->drm, 1437 "Verify rep topology failed. %d\n", ret); 1438 mutex_unlock(&display->hdcp.hdcp_mutex); 1439 1440 return ret; 1441 } 1442 1443 static int 1444 hdcp2_verify_mprime(struct intel_connector *connector, 1445 struct hdcp2_rep_stream_ready *stream_ready) 1446 { 1447 struct intel_display *display = to_intel_display(connector); 1448 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1449 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1450 struct i915_hdcp_arbiter *arbiter; 1451 int ret; 1452 1453 mutex_lock(&display->hdcp.hdcp_mutex); 1454 arbiter = display->hdcp.arbiter; 1455 1456 if (!arbiter || !arbiter->ops) { 1457 mutex_unlock(&display->hdcp.hdcp_mutex); 1458 return -EINVAL; 1459 } 1460 1461 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1462 if (ret < 0) 1463 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1464 mutex_unlock(&display->hdcp.hdcp_mutex); 1465 1466 return ret; 1467 } 1468 1469 static int hdcp2_authenticate_port(struct intel_connector *connector) 1470 { 1471 struct intel_display *display = to_intel_display(connector); 1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1473 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1474 struct i915_hdcp_arbiter *arbiter; 1475 int ret; 1476 1477 mutex_lock(&display->hdcp.hdcp_mutex); 1478 arbiter = display->hdcp.arbiter; 1479 1480 if (!arbiter || !arbiter->ops) { 1481 mutex_unlock(&display->hdcp.hdcp_mutex); 1482 return -EINVAL; 1483 } 1484 1485 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1486 if (ret < 0) 1487 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1488 ret); 1489 mutex_unlock(&display->hdcp.hdcp_mutex); 1490 1491 return ret; 1492 } 1493 1494 static int hdcp2_close_session(struct intel_connector *connector) 1495 { 1496 struct intel_display *display = to_intel_display(connector); 1497 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1498 struct i915_hdcp_arbiter *arbiter; 1499 int ret; 1500 1501 mutex_lock(&display->hdcp.hdcp_mutex); 1502 arbiter = display->hdcp.arbiter; 1503 1504 if (!arbiter || !arbiter->ops) { 1505 mutex_unlock(&display->hdcp.hdcp_mutex); 1506 return -EINVAL; 1507 } 1508 1509 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1510 &dig_port->hdcp.port_data); 1511 mutex_unlock(&display->hdcp.hdcp_mutex); 1512 1513 return ret; 1514 } 1515 1516 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1517 { 1518 return hdcp2_close_session(connector); 1519 } 1520 1521 /* Authentication flow starts from here */ 1522 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1523 { 1524 struct intel_display *display = to_intel_display(connector); 1525 struct intel_digital_port *dig_port = 1526 intel_attached_dig_port(connector); 1527 struct intel_hdcp *hdcp = &connector->hdcp; 1528 union { 1529 struct hdcp2_ake_init ake_init; 1530 struct hdcp2_ake_send_cert send_cert; 1531 struct hdcp2_ake_no_stored_km no_stored_km; 1532 struct hdcp2_ake_send_hprime send_hprime; 1533 struct hdcp2_ake_send_pairing_info pairing_info; 1534 } msgs; 1535 const struct intel_hdcp_shim *shim = hdcp->shim; 1536 size_t size; 1537 int ret, i, max_retries; 1538 1539 /* Init for seq_num */ 1540 hdcp->seq_num_v = 0; 1541 hdcp->seq_num_m = 0; 1542 1543 if (intel_encoder_is_dp(&dig_port->base) || 1544 intel_encoder_is_mst(&dig_port->base)) 1545 max_retries = 10; 1546 else 1547 max_retries = 1; 1548 1549 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1550 if (ret < 0) 1551 return ret; 1552 1553 /* 1554 * Retry the first read and write to downstream at least 10 times 1555 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1556 * (dock decides to stop advertising hdcp2 capability for some reason). 1557 * The reason being that during suspend resume dock usually keeps the 1558 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1559 * big problem if the userspace just kept retrying with some delay while 1560 * it continues to play low value content but most userspace applications 1561 * end up throwing an error when it receives one from KMD. This makes 1562 * sure we give the dock and the sink devices to complete its power cycle 1563 * and then try HDCP authentication. The values of 10 and delay of 50ms 1564 * was decided based on multiple trial and errors. 1565 */ 1566 for (i = 0; i < max_retries; i++) { 1567 if (!intel_hdcp2_get_capability(connector)) { 1568 msleep(50); 1569 continue; 1570 } 1571 1572 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1573 sizeof(msgs.ake_init)); 1574 if (ret < 0) 1575 continue; 1576 1577 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1578 &msgs.send_cert, sizeof(msgs.send_cert)); 1579 if (ret > 0) 1580 break; 1581 } 1582 1583 if (ret < 0) 1584 return ret; 1585 1586 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1587 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1588 return -EINVAL; 1589 } 1590 1591 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1592 1593 if (drm_hdcp_check_ksvs_revoked(display->drm, 1594 msgs.send_cert.cert_rx.receiver_id, 1595 1) > 0) { 1596 drm_err(display->drm, "Receiver ID is revoked\n"); 1597 return -EPERM; 1598 } 1599 1600 /* 1601 * Here msgs.no_stored_km will hold msgs corresponding to the km 1602 * stored also. 1603 */ 1604 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1605 &hdcp->is_paired, 1606 &msgs.no_stored_km, &size); 1607 if (ret < 0) 1608 return ret; 1609 1610 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1611 if (ret < 0) 1612 return ret; 1613 1614 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1615 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1616 if (ret < 0) 1617 return ret; 1618 1619 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1620 if (ret < 0) 1621 return ret; 1622 1623 if (!hdcp->is_paired) { 1624 /* Pairing is required */ 1625 ret = shim->read_2_2_msg(connector, 1626 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1627 &msgs.pairing_info, 1628 sizeof(msgs.pairing_info)); 1629 if (ret < 0) 1630 return ret; 1631 1632 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1633 if (ret < 0) 1634 return ret; 1635 hdcp->is_paired = true; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int hdcp2_locality_check(struct intel_connector *connector) 1642 { 1643 struct intel_hdcp *hdcp = &connector->hdcp; 1644 union { 1645 struct hdcp2_lc_init lc_init; 1646 struct hdcp2_lc_send_lprime send_lprime; 1647 } msgs; 1648 const struct intel_hdcp_shim *shim = hdcp->shim; 1649 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1650 1651 for (i = 0; i < tries; i++) { 1652 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1653 if (ret < 0) 1654 continue; 1655 1656 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1657 sizeof(msgs.lc_init)); 1658 if (ret < 0) 1659 continue; 1660 1661 ret = shim->read_2_2_msg(connector, 1662 HDCP_2_2_LC_SEND_LPRIME, 1663 &msgs.send_lprime, 1664 sizeof(msgs.send_lprime)); 1665 if (ret < 0) 1666 continue; 1667 1668 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1669 if (!ret) 1670 break; 1671 } 1672 1673 return ret; 1674 } 1675 1676 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1677 { 1678 struct intel_hdcp *hdcp = &connector->hdcp; 1679 struct hdcp2_ske_send_eks send_eks; 1680 int ret; 1681 1682 ret = hdcp2_prepare_skey(connector, &send_eks); 1683 if (ret < 0) 1684 return ret; 1685 1686 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1687 sizeof(send_eks)); 1688 if (ret < 0) 1689 return ret; 1690 1691 return 0; 1692 } 1693 1694 static 1695 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1696 { 1697 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1698 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1699 struct intel_hdcp *hdcp = &connector->hdcp; 1700 union { 1701 struct hdcp2_rep_stream_manage stream_manage; 1702 struct hdcp2_rep_stream_ready stream_ready; 1703 } msgs; 1704 const struct intel_hdcp_shim *shim = hdcp->shim; 1705 int ret, streams_size_delta, i; 1706 1707 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1708 return -ERANGE; 1709 1710 /* Prepare RepeaterAuth_Stream_Manage msg */ 1711 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1712 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1713 1714 msgs.stream_manage.k = cpu_to_be16(data->k); 1715 1716 for (i = 0; i < data->k; i++) { 1717 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1718 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1719 } 1720 1721 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1722 sizeof(struct hdcp2_streamid_type); 1723 /* Send it to Repeater */ 1724 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1725 sizeof(msgs.stream_manage) - streams_size_delta); 1726 if (ret < 0) 1727 goto out; 1728 1729 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1730 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1731 if (ret < 0) 1732 goto out; 1733 1734 data->seq_num_m = hdcp->seq_num_m; 1735 1736 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1737 1738 out: 1739 hdcp->seq_num_m++; 1740 1741 return ret; 1742 } 1743 1744 static 1745 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1746 { 1747 struct intel_display *display = to_intel_display(connector); 1748 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1749 struct intel_hdcp *hdcp = &connector->hdcp; 1750 union { 1751 struct hdcp2_rep_send_receiverid_list recvid_list; 1752 struct hdcp2_rep_send_ack rep_ack; 1753 } msgs; 1754 const struct intel_hdcp_shim *shim = hdcp->shim; 1755 u32 seq_num_v, device_cnt; 1756 u8 *rx_info; 1757 int ret; 1758 1759 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1760 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1761 if (ret < 0) 1762 return ret; 1763 1764 rx_info = msgs.recvid_list.rx_info; 1765 1766 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1767 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1768 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1769 return -EINVAL; 1770 } 1771 1772 /* 1773 * MST topology is not Type 1 capable if it contains a downstream 1774 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1775 */ 1776 dig_port->hdcp.mst_type1_capable = 1777 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1778 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1779 1780 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1781 drm_dbg_kms(display->drm, 1782 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1783 return -EINVAL; 1784 } 1785 1786 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1787 seq_num_v = 1788 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1789 1790 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1791 drm_dbg_kms(display->drm, 1792 "Non zero Seq_num_v at first RecvId_List msg\n"); 1793 return -EINVAL; 1794 } 1795 1796 if (seq_num_v < hdcp->seq_num_v) { 1797 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1798 drm_dbg_kms(display->drm, "Seq_num_v roll over.\n"); 1799 return -EINVAL; 1800 } 1801 1802 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1803 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1804 if (drm_hdcp_check_ksvs_revoked(display->drm, 1805 msgs.recvid_list.receiver_ids, 1806 device_cnt) > 0) { 1807 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1808 return -EPERM; 1809 } 1810 1811 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1812 &msgs.recvid_list, 1813 &msgs.rep_ack); 1814 if (ret < 0) 1815 return ret; 1816 1817 hdcp->seq_num_v = seq_num_v; 1818 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1819 sizeof(msgs.rep_ack)); 1820 if (ret < 0) 1821 return ret; 1822 1823 return 0; 1824 } 1825 1826 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1827 { 1828 struct intel_display *display = to_intel_display(connector); 1829 struct intel_hdcp *hdcp = &connector->hdcp; 1830 const struct intel_hdcp_shim *shim = hdcp->shim; 1831 int ret; 1832 1833 ret = hdcp2_authentication_key_exchange(connector); 1834 if (ret < 0) { 1835 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1836 return ret; 1837 } 1838 1839 ret = hdcp2_locality_check(connector); 1840 if (ret < 0) { 1841 drm_dbg_kms(display->drm, 1842 "Locality Check failed. Err : %d\n", ret); 1843 return ret; 1844 } 1845 1846 ret = hdcp2_session_key_exchange(connector); 1847 if (ret < 0) { 1848 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1849 return ret; 1850 } 1851 1852 if (shim->config_stream_type) { 1853 ret = shim->config_stream_type(connector, 1854 hdcp->is_repeater, 1855 hdcp->content_type); 1856 if (ret < 0) 1857 return ret; 1858 } 1859 1860 if (hdcp->is_repeater) { 1861 ret = hdcp2_authenticate_repeater_topology(connector); 1862 if (ret < 0) { 1863 drm_dbg_kms(display->drm, 1864 "Repeater Auth Failed. Err: %d\n", ret); 1865 return ret; 1866 } 1867 } 1868 1869 return ret; 1870 } 1871 1872 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1873 { 1874 struct intel_display *display = to_intel_display(connector); 1875 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1876 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1877 struct intel_hdcp *hdcp = &connector->hdcp; 1878 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1879 enum port port = dig_port->base.port; 1880 int ret = 0; 1881 1882 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1883 LINK_ENCRYPTION_STATUS)) { 1884 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1885 connector->base.base.id, connector->base.name); 1886 ret = -EPERM; 1887 goto link_recover; 1888 } 1889 1890 if (hdcp->shim->stream_2_2_encryption) { 1891 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1892 if (ret) { 1893 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1894 connector->base.base.id, connector->base.name); 1895 return ret; 1896 } 1897 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1898 transcoder_name(hdcp->stream_transcoder)); 1899 } 1900 1901 return 0; 1902 1903 link_recover: 1904 if (hdcp2_deauthenticate_port(connector) < 0) 1905 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1906 1907 dig_port->hdcp.auth_status = false; 1908 data->k = 0; 1909 1910 return ret; 1911 } 1912 1913 static int hdcp2_enable_encryption(struct intel_connector *connector) 1914 { 1915 struct intel_display *display = to_intel_display(connector); 1916 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1917 struct intel_hdcp *hdcp = &connector->hdcp; 1918 enum port port = dig_port->base.port; 1919 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1920 int ret; 1921 1922 drm_WARN_ON(display->drm, 1923 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1924 LINK_ENCRYPTION_STATUS); 1925 if (hdcp->shim->toggle_signalling) { 1926 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1927 true); 1928 if (ret) { 1929 drm_err(display->drm, 1930 "Failed to enable HDCP signalling. %d\n", 1931 ret); 1932 return ret; 1933 } 1934 } 1935 1936 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1937 LINK_AUTH_STATUS) 1938 /* Link is Authenticated. Now set for Encryption */ 1939 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1940 0, CTL_LINK_ENCRYPTION_REQ); 1941 1942 ret = intel_de_wait_for_set(display, 1943 HDCP2_STATUS(display, cpu_transcoder, 1944 port), 1945 LINK_ENCRYPTION_STATUS, 1946 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1947 dig_port->hdcp.auth_status = true; 1948 1949 return ret; 1950 } 1951 1952 static int hdcp2_disable_encryption(struct intel_connector *connector) 1953 { 1954 struct intel_display *display = to_intel_display(connector); 1955 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1956 struct intel_hdcp *hdcp = &connector->hdcp; 1957 enum port port = dig_port->base.port; 1958 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1959 int ret; 1960 1961 drm_WARN_ON(display->drm, 1962 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1963 LINK_ENCRYPTION_STATUS)); 1964 1965 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1966 CTL_LINK_ENCRYPTION_REQ, 0); 1967 1968 ret = intel_de_wait_for_clear(display, 1969 HDCP2_STATUS(display, cpu_transcoder, 1970 port), 1971 LINK_ENCRYPTION_STATUS, 1972 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1973 if (ret == -ETIMEDOUT) 1974 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1975 1976 if (hdcp->shim->toggle_signalling) { 1977 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1978 false); 1979 if (ret) { 1980 drm_err(display->drm, 1981 "Failed to disable HDCP signalling. %d\n", 1982 ret); 1983 return ret; 1984 } 1985 } 1986 1987 return ret; 1988 } 1989 1990 static int 1991 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1992 { 1993 struct intel_display *display = to_intel_display(connector); 1994 int i, tries = 3, ret; 1995 1996 if (!connector->hdcp.is_repeater) 1997 return 0; 1998 1999 for (i = 0; i < tries; i++) { 2000 ret = _hdcp2_propagate_stream_management_info(connector); 2001 if (!ret) 2002 break; 2003 2004 /* Lets restart the auth incase of seq_num_m roll over */ 2005 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2006 drm_dbg_kms(display->drm, 2007 "seq_num_m roll over.(%d)\n", ret); 2008 break; 2009 } 2010 2011 drm_dbg_kms(display->drm, 2012 "HDCP2 stream management %d of %d Failed.(%d)\n", 2013 i + 1, tries, ret); 2014 } 2015 2016 return ret; 2017 } 2018 2019 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2020 struct intel_connector *connector) 2021 { 2022 struct intel_display *display = to_intel_display(connector); 2023 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2024 int ret = 0, i, tries = 3; 2025 2026 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2027 ret = hdcp2_authenticate_sink(connector); 2028 if (!ret) { 2029 ret = intel_hdcp_prepare_streams(state, connector); 2030 if (ret) { 2031 drm_dbg_kms(display->drm, 2032 "Prepare stream failed.(%d)\n", 2033 ret); 2034 break; 2035 } 2036 2037 ret = hdcp2_propagate_stream_management_info(connector); 2038 if (ret) { 2039 drm_dbg_kms(display->drm, 2040 "Stream management failed.(%d)\n", 2041 ret); 2042 break; 2043 } 2044 2045 ret = hdcp2_authenticate_port(connector); 2046 if (!ret) 2047 break; 2048 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2049 ret); 2050 } 2051 2052 /* Clearing the mei hdcp session */ 2053 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2054 i + 1, tries, ret); 2055 if (hdcp2_deauthenticate_port(connector) < 0) 2056 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2057 } 2058 2059 if (!ret && !dig_port->hdcp.auth_status) { 2060 /* 2061 * Ensuring the required 200mSec min time interval between 2062 * Session Key Exchange and encryption. 2063 */ 2064 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2065 ret = hdcp2_enable_encryption(connector); 2066 if (ret < 0) { 2067 drm_dbg_kms(display->drm, 2068 "Encryption Enable Failed.(%d)\n", ret); 2069 if (hdcp2_deauthenticate_port(connector) < 0) 2070 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2071 } 2072 } 2073 2074 if (!ret) 2075 ret = hdcp2_enable_stream_encryption(connector); 2076 2077 return ret; 2078 } 2079 2080 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2081 struct intel_connector *connector) 2082 { 2083 struct intel_display *display = to_intel_display(connector); 2084 struct intel_hdcp *hdcp = &connector->hdcp; 2085 int ret; 2086 2087 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2088 connector->base.base.id, connector->base.name, 2089 hdcp->content_type); 2090 2091 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2092 2093 ret = hdcp2_authenticate_and_encrypt(state, connector); 2094 if (ret) { 2095 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2096 hdcp->content_type, ret); 2097 return ret; 2098 } 2099 2100 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2101 connector->base.base.id, connector->base.name, 2102 hdcp->content_type); 2103 2104 hdcp->hdcp2_encrypted = true; 2105 return 0; 2106 } 2107 2108 static int 2109 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2110 { 2111 struct intel_display *display = to_intel_display(connector); 2112 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2113 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2114 struct intel_hdcp *hdcp = &connector->hdcp; 2115 int ret; 2116 2117 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2118 connector->base.base.id, connector->base.name); 2119 2120 if (hdcp->shim->stream_2_2_encryption) { 2121 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2122 if (ret) { 2123 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2124 connector->base.base.id, connector->base.name); 2125 return ret; 2126 } 2127 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2128 transcoder_name(hdcp->stream_transcoder)); 2129 2130 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2131 return 0; 2132 } 2133 2134 ret = hdcp2_disable_encryption(connector); 2135 2136 if (hdcp2_deauthenticate_port(connector) < 0) 2137 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2138 2139 connector->hdcp.hdcp2_encrypted = false; 2140 dig_port->hdcp.auth_status = false; 2141 data->k = 0; 2142 2143 return ret; 2144 } 2145 2146 /* Implements the Link Integrity Check for HDCP2.2 */ 2147 static int intel_hdcp2_check_link(struct intel_connector *connector) 2148 { 2149 struct intel_display *display = to_intel_display(connector); 2150 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2151 struct intel_hdcp *hdcp = &connector->hdcp; 2152 enum port port = dig_port->base.port; 2153 enum transcoder cpu_transcoder; 2154 int ret = 0; 2155 2156 mutex_lock(&hdcp->mutex); 2157 mutex_lock(&dig_port->hdcp.mutex); 2158 cpu_transcoder = hdcp->cpu_transcoder; 2159 2160 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2161 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2162 !hdcp->hdcp2_encrypted) { 2163 ret = -EINVAL; 2164 goto out; 2165 } 2166 2167 if (drm_WARN_ON(display->drm, 2168 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2169 drm_err(display->drm, 2170 "HDCP2.2 link stopped the encryption, %x\n", 2171 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2172 ret = -ENXIO; 2173 _intel_hdcp2_disable(connector, true); 2174 intel_hdcp_update_value(connector, 2175 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2176 true); 2177 goto out; 2178 } 2179 2180 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2181 if (ret == HDCP_LINK_PROTECTED) { 2182 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2183 intel_hdcp_update_value(connector, 2184 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2185 true); 2186 } 2187 goto out; 2188 } 2189 2190 if (ret == HDCP_TOPOLOGY_CHANGE) { 2191 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2192 goto out; 2193 2194 drm_dbg_kms(display->drm, 2195 "HDCP2.2 Downstream topology change\n"); 2196 2197 ret = hdcp2_authenticate_repeater_topology(connector); 2198 if (!ret) { 2199 intel_hdcp_update_value(connector, 2200 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2201 true); 2202 goto out; 2203 } 2204 2205 drm_dbg_kms(display->drm, 2206 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2207 connector->base.base.id, connector->base.name, 2208 ret); 2209 } else { 2210 drm_dbg_kms(display->drm, 2211 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2212 connector->base.base.id, connector->base.name); 2213 } 2214 2215 ret = _intel_hdcp2_disable(connector, true); 2216 if (ret) { 2217 drm_err(display->drm, 2218 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2219 connector->base.base.id, connector->base.name, ret); 2220 intel_hdcp_update_value(connector, 2221 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2222 goto out; 2223 } 2224 2225 intel_hdcp_update_value(connector, 2226 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2227 out: 2228 mutex_unlock(&dig_port->hdcp.mutex); 2229 mutex_unlock(&hdcp->mutex); 2230 return ret; 2231 } 2232 2233 static void intel_hdcp_check_work(struct work_struct *work) 2234 { 2235 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2236 struct intel_hdcp, 2237 check_work); 2238 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2239 struct intel_display *display = to_intel_display(connector); 2240 struct drm_i915_private *i915 = to_i915(display->drm); 2241 2242 if (drm_connector_is_unregistered(&connector->base)) 2243 return; 2244 2245 if (!intel_hdcp2_check_link(connector)) 2246 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2247 DRM_HDCP2_CHECK_PERIOD_MS); 2248 else if (!intel_hdcp_check_link(connector)) 2249 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2250 DRM_HDCP_CHECK_PERIOD_MS); 2251 } 2252 2253 static int i915_hdcp_component_bind(struct device *drv_kdev, 2254 struct device *mei_kdev, void *data) 2255 { 2256 struct intel_display *display = to_intel_display(drv_kdev); 2257 2258 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2259 mutex_lock(&display->hdcp.hdcp_mutex); 2260 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2261 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2262 mutex_unlock(&display->hdcp.hdcp_mutex); 2263 2264 return 0; 2265 } 2266 2267 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2268 struct device *mei_kdev, void *data) 2269 { 2270 struct intel_display *display = to_intel_display(drv_kdev); 2271 2272 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2273 mutex_lock(&display->hdcp.hdcp_mutex); 2274 display->hdcp.arbiter = NULL; 2275 mutex_unlock(&display->hdcp.hdcp_mutex); 2276 } 2277 2278 static const struct component_ops i915_hdcp_ops = { 2279 .bind = i915_hdcp_component_bind, 2280 .unbind = i915_hdcp_component_unbind, 2281 }; 2282 2283 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2284 { 2285 switch (port) { 2286 case PORT_A: 2287 return HDCP_DDI_A; 2288 case PORT_B ... PORT_F: 2289 return (enum hdcp_ddi)port; 2290 default: 2291 return HDCP_DDI_INVALID_PORT; 2292 } 2293 } 2294 2295 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2296 { 2297 switch (cpu_transcoder) { 2298 case TRANSCODER_A ... TRANSCODER_D: 2299 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2300 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2301 return HDCP_INVALID_TRANSCODER; 2302 } 2303 } 2304 2305 static int initialize_hdcp_port_data(struct intel_connector *connector, 2306 struct intel_digital_port *dig_port, 2307 const struct intel_hdcp_shim *shim) 2308 { 2309 struct intel_display *display = to_intel_display(connector); 2310 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2311 enum port port = dig_port->base.port; 2312 2313 if (DISPLAY_VER(display) < 12) 2314 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2315 else 2316 /* 2317 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2318 * with zero(INVALID PORT index). 2319 */ 2320 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2321 2322 /* 2323 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2324 * is initialized to zero (invalid transcoder index). This will be 2325 * retained for <Gen12 forever. 2326 */ 2327 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2328 2329 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2330 data->protocol = (u8)shim->protocol; 2331 2332 if (!data->streams) 2333 data->streams = kcalloc(INTEL_NUM_PIPES(display), 2334 sizeof(struct hdcp2_streamid_type), 2335 GFP_KERNEL); 2336 if (!data->streams) { 2337 drm_err(display->drm, "Out of Memory\n"); 2338 return -ENOMEM; 2339 } 2340 2341 return 0; 2342 } 2343 2344 static bool is_hdcp2_supported(struct intel_display *display) 2345 { 2346 if (USE_HDCP_GSC(display)) 2347 return true; 2348 2349 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2350 return false; 2351 2352 return DISPLAY_VER(display) >= 10 || 2353 display->platform.kabylake || 2354 display->platform.coffeelake || 2355 display->platform.cometlake; 2356 } 2357 2358 void intel_hdcp_component_init(struct intel_display *display) 2359 { 2360 int ret; 2361 2362 if (!is_hdcp2_supported(display)) 2363 return; 2364 2365 mutex_lock(&display->hdcp.hdcp_mutex); 2366 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2367 2368 display->hdcp.comp_added = true; 2369 mutex_unlock(&display->hdcp.hdcp_mutex); 2370 if (USE_HDCP_GSC(display)) 2371 ret = intel_hdcp_gsc_init(display); 2372 else 2373 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2374 I915_COMPONENT_HDCP); 2375 2376 if (ret < 0) { 2377 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2378 ret); 2379 mutex_lock(&display->hdcp.hdcp_mutex); 2380 display->hdcp.comp_added = false; 2381 mutex_unlock(&display->hdcp.hdcp_mutex); 2382 return; 2383 } 2384 } 2385 2386 static void intel_hdcp2_init(struct intel_connector *connector, 2387 struct intel_digital_port *dig_port, 2388 const struct intel_hdcp_shim *shim) 2389 { 2390 struct intel_display *display = to_intel_display(connector); 2391 struct intel_hdcp *hdcp = &connector->hdcp; 2392 int ret; 2393 2394 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2395 if (ret) { 2396 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2397 return; 2398 } 2399 2400 hdcp->hdcp2_supported = true; 2401 } 2402 2403 int intel_hdcp_init(struct intel_connector *connector, 2404 struct intel_digital_port *dig_port, 2405 const struct intel_hdcp_shim *shim) 2406 { 2407 struct intel_display *display = to_intel_display(connector); 2408 struct intel_hdcp *hdcp = &connector->hdcp; 2409 int ret; 2410 2411 if (!shim) 2412 return -EINVAL; 2413 2414 if (is_hdcp2_supported(display)) 2415 intel_hdcp2_init(connector, dig_port, shim); 2416 2417 ret = drm_connector_attach_content_protection_property(&connector->base, 2418 hdcp->hdcp2_supported); 2419 if (ret) { 2420 hdcp->hdcp2_supported = false; 2421 kfree(dig_port->hdcp.port_data.streams); 2422 return ret; 2423 } 2424 2425 hdcp->shim = shim; 2426 mutex_init(&hdcp->mutex); 2427 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2428 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2429 init_waitqueue_head(&hdcp->cp_irq_queue); 2430 2431 return 0; 2432 } 2433 2434 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2435 struct intel_encoder *encoder, 2436 const struct intel_crtc_state *pipe_config, 2437 const struct drm_connector_state *conn_state) 2438 { 2439 struct intel_display *display = to_intel_display(encoder); 2440 struct drm_i915_private *i915 = to_i915(display->drm); 2441 struct intel_connector *connector = 2442 to_intel_connector(conn_state->connector); 2443 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2444 struct intel_hdcp *hdcp = &connector->hdcp; 2445 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2446 int ret = -EINVAL; 2447 2448 if (!hdcp->shim) 2449 return -ENOENT; 2450 2451 if (!connector->encoder) { 2452 drm_err(display->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n", 2453 connector->base.base.id, connector->base.name); 2454 return -ENODEV; 2455 } 2456 2457 mutex_lock(&hdcp->mutex); 2458 mutex_lock(&dig_port->hdcp.mutex); 2459 drm_WARN_ON(display->drm, 2460 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2461 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2462 2463 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2464 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2465 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2466 } else { 2467 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2468 hdcp->stream_transcoder = INVALID_TRANSCODER; 2469 } 2470 2471 if (DISPLAY_VER(display) >= 12) 2472 dig_port->hdcp.port_data.hdcp_transcoder = 2473 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2474 2475 /* 2476 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2477 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2478 */ 2479 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2480 ret = _intel_hdcp2_enable(state, connector); 2481 if (!ret) 2482 check_link_interval = 2483 DRM_HDCP2_CHECK_PERIOD_MS; 2484 } 2485 2486 if (hdcp->force_hdcp14) 2487 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2488 2489 /* 2490 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2491 * be attempted. 2492 */ 2493 if (ret && intel_hdcp_get_capability(connector) && 2494 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2495 ret = intel_hdcp1_enable(connector); 2496 } 2497 2498 if (!ret) { 2499 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 2500 check_link_interval); 2501 intel_hdcp_update_value(connector, 2502 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2503 true); 2504 } 2505 2506 mutex_unlock(&dig_port->hdcp.mutex); 2507 mutex_unlock(&hdcp->mutex); 2508 return ret; 2509 } 2510 2511 void intel_hdcp_enable(struct intel_atomic_state *state, 2512 struct intel_encoder *encoder, 2513 const struct intel_crtc_state *crtc_state, 2514 const struct drm_connector_state *conn_state) 2515 { 2516 struct intel_connector *connector = 2517 to_intel_connector(conn_state->connector); 2518 struct intel_hdcp *hdcp = &connector->hdcp; 2519 2520 /* 2521 * Enable hdcp if it's desired or if userspace is enabled and 2522 * driver set its state to undesired 2523 */ 2524 if (conn_state->content_protection == 2525 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2526 (conn_state->content_protection == 2527 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2528 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2529 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2530 } 2531 2532 int intel_hdcp_disable(struct intel_connector *connector) 2533 { 2534 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2535 struct intel_hdcp *hdcp = &connector->hdcp; 2536 int ret = 0; 2537 2538 if (!hdcp->shim) 2539 return -ENOENT; 2540 2541 mutex_lock(&hdcp->mutex); 2542 mutex_lock(&dig_port->hdcp.mutex); 2543 2544 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2545 goto out; 2546 2547 intel_hdcp_update_value(connector, 2548 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2549 if (hdcp->hdcp2_encrypted) 2550 ret = _intel_hdcp2_disable(connector, false); 2551 else if (hdcp->hdcp_encrypted) 2552 ret = _intel_hdcp_disable(connector); 2553 2554 out: 2555 mutex_unlock(&dig_port->hdcp.mutex); 2556 mutex_unlock(&hdcp->mutex); 2557 cancel_delayed_work_sync(&hdcp->check_work); 2558 return ret; 2559 } 2560 2561 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2562 struct intel_encoder *encoder, 2563 const struct intel_crtc_state *crtc_state, 2564 const struct drm_connector_state *conn_state) 2565 { 2566 struct intel_connector *connector = 2567 to_intel_connector(conn_state->connector); 2568 struct intel_hdcp *hdcp = &connector->hdcp; 2569 bool content_protection_type_changed, desired_and_not_enabled = false; 2570 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2571 2572 if (!connector->hdcp.shim) 2573 return; 2574 2575 content_protection_type_changed = 2576 (conn_state->hdcp_content_type != hdcp->content_type && 2577 conn_state->content_protection != 2578 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2579 2580 /* 2581 * During the HDCP encryption session if Type change is requested, 2582 * disable the HDCP and re-enable it with new TYPE value. 2583 */ 2584 if (conn_state->content_protection == 2585 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2586 content_protection_type_changed) 2587 intel_hdcp_disable(connector); 2588 2589 /* 2590 * Mark the hdcp state as DESIRED after the hdcp disable of type 2591 * change procedure. 2592 */ 2593 if (content_protection_type_changed) { 2594 mutex_lock(&hdcp->mutex); 2595 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2596 drm_connector_get(&connector->base); 2597 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2598 drm_connector_put(&connector->base); 2599 mutex_unlock(&hdcp->mutex); 2600 } 2601 2602 if (conn_state->content_protection == 2603 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2604 mutex_lock(&hdcp->mutex); 2605 /* Avoid enabling hdcp, if it already ENABLED */ 2606 desired_and_not_enabled = 2607 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2608 mutex_unlock(&hdcp->mutex); 2609 /* 2610 * If HDCP already ENABLED and CP property is DESIRED, schedule 2611 * prop_work to update correct CP property to user space. 2612 */ 2613 if (!desired_and_not_enabled && !content_protection_type_changed) { 2614 drm_connector_get(&connector->base); 2615 if (!queue_work(i915->unordered_wq, &hdcp->prop_work)) 2616 drm_connector_put(&connector->base); 2617 2618 } 2619 } 2620 2621 if (desired_and_not_enabled || content_protection_type_changed) 2622 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2623 } 2624 2625 void intel_hdcp_cancel_works(struct intel_connector *connector) 2626 { 2627 if (!connector->hdcp.shim) 2628 return; 2629 2630 cancel_delayed_work_sync(&connector->hdcp.check_work); 2631 cancel_work_sync(&connector->hdcp.prop_work); 2632 } 2633 2634 void intel_hdcp_component_fini(struct intel_display *display) 2635 { 2636 mutex_lock(&display->hdcp.hdcp_mutex); 2637 if (!display->hdcp.comp_added) { 2638 mutex_unlock(&display->hdcp.hdcp_mutex); 2639 return; 2640 } 2641 2642 display->hdcp.comp_added = false; 2643 mutex_unlock(&display->hdcp.hdcp_mutex); 2644 2645 if (USE_HDCP_GSC(display)) 2646 intel_hdcp_gsc_fini(display); 2647 else 2648 component_del(display->drm->dev, &i915_hdcp_ops); 2649 } 2650 2651 void intel_hdcp_cleanup(struct intel_connector *connector) 2652 { 2653 struct intel_hdcp *hdcp = &connector->hdcp; 2654 2655 if (!hdcp->shim) 2656 return; 2657 2658 /* 2659 * If the connector is registered, it's possible userspace could kick 2660 * off another HDCP enable, which would re-spawn the workers. 2661 */ 2662 drm_WARN_ON(connector->base.dev, 2663 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2664 2665 /* 2666 * Now that the connector is not registered, check_work won't be run, 2667 * but cancel any outstanding instances of it 2668 */ 2669 cancel_delayed_work_sync(&hdcp->check_work); 2670 2671 /* 2672 * We don't cancel prop_work in the same way as check_work since it 2673 * requires connection_mutex which could be held while calling this 2674 * function. Instead, we rely on the connector references grabbed before 2675 * scheduling prop_work to ensure the connector is alive when prop_work 2676 * is run. So if we're in the destroy path (which is where this 2677 * function should be called), we're "guaranteed" that prop_work is not 2678 * active (tl;dr This Should Never Happen). 2679 */ 2680 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2681 2682 mutex_lock(&hdcp->mutex); 2683 hdcp->shim = NULL; 2684 mutex_unlock(&hdcp->mutex); 2685 } 2686 2687 void intel_hdcp_atomic_check(struct drm_connector *connector, 2688 struct drm_connector_state *old_state, 2689 struct drm_connector_state *new_state) 2690 { 2691 u64 old_cp = old_state->content_protection; 2692 u64 new_cp = new_state->content_protection; 2693 struct drm_crtc_state *crtc_state; 2694 2695 if (!new_state->crtc) { 2696 /* 2697 * If the connector is being disabled with CP enabled, mark it 2698 * desired so it's re-enabled when the connector is brought back 2699 */ 2700 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2701 new_state->content_protection = 2702 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2703 return; 2704 } 2705 2706 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2707 new_state->crtc); 2708 /* 2709 * Fix the HDCP uapi content protection state in case of modeset. 2710 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2711 * need to be sent if there is transition from ENABLED->DESIRED. 2712 */ 2713 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2714 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2715 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2716 new_state->content_protection = 2717 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2718 2719 /* 2720 * Nothing to do if the state didn't change, or HDCP was activated since 2721 * the last commit. And also no change in hdcp content type. 2722 */ 2723 if (old_cp == new_cp || 2724 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2725 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2726 if (old_state->hdcp_content_type == 2727 new_state->hdcp_content_type) 2728 return; 2729 } 2730 2731 crtc_state->mode_changed = true; 2732 } 2733 2734 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2735 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2736 { 2737 struct intel_hdcp *hdcp = &connector->hdcp; 2738 struct intel_display *display = to_intel_display(connector); 2739 struct drm_i915_private *i915 = to_i915(display->drm); 2740 2741 if (!hdcp->shim) 2742 return; 2743 2744 atomic_inc(&connector->hdcp.cp_irq_count); 2745 wake_up_all(&connector->hdcp.cp_irq_queue); 2746 2747 queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); 2748 } 2749 2750 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2751 bool remote_req) 2752 { 2753 bool hdcp_cap = false, hdcp2_cap = false; 2754 2755 if (!connector->hdcp.shim) { 2756 seq_puts(m, "No Connector Support"); 2757 goto out; 2758 } 2759 2760 if (remote_req) { 2761 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2762 } else { 2763 hdcp_cap = intel_hdcp_get_capability(connector); 2764 hdcp2_cap = intel_hdcp2_get_capability(connector); 2765 } 2766 2767 if (hdcp_cap) 2768 seq_puts(m, "HDCP1.4 "); 2769 if (hdcp2_cap) 2770 seq_puts(m, "HDCP2.2 "); 2771 2772 if (!hdcp_cap && !hdcp2_cap) 2773 seq_puts(m, "None"); 2774 2775 out: 2776 seq_puts(m, "\n"); 2777 } 2778 2779 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2780 { 2781 seq_puts(m, "\tHDCP version: "); 2782 if (connector->mst.dp) { 2783 __intel_hdcp_info(m, connector, true); 2784 seq_puts(m, "\tMST Hub HDCP version: "); 2785 } 2786 __intel_hdcp_info(m, connector, false); 2787 } 2788 2789 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2790 { 2791 struct intel_connector *connector = m->private; 2792 struct intel_display *display = to_intel_display(connector); 2793 int ret; 2794 2795 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2796 if (ret) 2797 return ret; 2798 2799 if (!connector->base.encoder || 2800 connector->base.status != connector_status_connected) { 2801 ret = -ENODEV; 2802 goto out; 2803 } 2804 2805 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2806 connector->base.base.id); 2807 __intel_hdcp_info(m, connector, false); 2808 2809 out: 2810 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2811 2812 return ret; 2813 } 2814 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2815 2816 static ssize_t intel_hdcp_force_14_write(struct file *file, 2817 const char __user *ubuf, 2818 size_t len, loff_t *offp) 2819 { 2820 struct seq_file *m = file->private_data; 2821 struct intel_connector *connector = m->private; 2822 struct intel_hdcp *hdcp = &connector->hdcp; 2823 bool force_hdcp14 = false; 2824 int ret; 2825 2826 if (len == 0) 2827 return 0; 2828 2829 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2830 if (ret < 0) 2831 return ret; 2832 2833 hdcp->force_hdcp14 = force_hdcp14; 2834 *offp += len; 2835 2836 return len; 2837 } 2838 2839 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2840 { 2841 struct intel_connector *connector = m->private; 2842 struct intel_display *display = to_intel_display(connector); 2843 struct intel_encoder *encoder = intel_attached_encoder(connector); 2844 struct intel_hdcp *hdcp = &connector->hdcp; 2845 struct drm_crtc *crtc; 2846 int ret; 2847 2848 if (!encoder) 2849 return -ENODEV; 2850 2851 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2852 if (ret) 2853 return ret; 2854 2855 crtc = connector->base.state->crtc; 2856 if (connector->base.status != connector_status_connected || !crtc) { 2857 ret = -ENODEV; 2858 goto out; 2859 } 2860 2861 seq_printf(m, "%s\n", 2862 str_yes_no(hdcp->force_hdcp14)); 2863 out: 2864 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2865 2866 return ret; 2867 } 2868 2869 static int intel_hdcp_force_14_open(struct inode *inode, 2870 struct file *file) 2871 { 2872 return single_open(file, intel_hdcp_force_14_show, 2873 inode->i_private); 2874 } 2875 2876 static const struct file_operations intel_hdcp_force_14_fops = { 2877 .owner = THIS_MODULE, 2878 .open = intel_hdcp_force_14_open, 2879 .read = seq_read, 2880 .llseek = seq_lseek, 2881 .release = single_release, 2882 .write = intel_hdcp_force_14_write 2883 }; 2884 2885 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2886 { 2887 struct dentry *root = connector->base.debugfs_entry; 2888 int connector_type = connector->base.connector_type; 2889 2890 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2891 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2892 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2893 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2894 connector, &intel_hdcp_sink_capability_fops); 2895 debugfs_create_file("i915_force_hdcp14", 0644, root, 2896 connector, &intel_hdcp_force_14_fops); 2897 } 2898 } 2899