1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/iopoll.h> 15 #include <linux/random.h> 16 17 #include <drm/display/drm_hdcp_helper.h> 18 #include <drm/drm_print.h> 19 #include <drm/intel/i915_component.h> 20 #include <drm/intel/intel_pcode_regs.h> 21 #include <drm/intel/step.h> 22 23 #include "intel_connector.h" 24 #include "intel_de.h" 25 #include "intel_display_jiffies.h" 26 #include "intel_display_power.h" 27 #include "intel_display_power_well.h" 28 #include "intel_display_regs.h" 29 #include "intel_display_rpm.h" 30 #include "intel_display_types.h" 31 #include "intel_dp_mst.h" 32 #include "intel_hdcp.h" 33 #include "intel_hdcp_gsc_message.h" 34 #include "intel_hdcp_regs.h" 35 #include "intel_hdcp_shim.h" 36 #include "intel_parent.h" 37 38 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 39 40 #define KEY_LOAD_TRIES 5 41 #define HDCP2_LC_RETRY_CNT 3 42 43 static void 44 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 45 struct intel_hdcp *hdcp, 46 bool enable) 47 { 48 struct intel_display *display = to_intel_display(encoder); 49 intel_reg_t rekey_reg; 50 u32 rekey_bit = 0; 51 52 /* Here we assume HDMI is in TMDS mode of operation */ 53 if (!intel_encoder_is_hdmi(encoder)) 54 return; 55 56 if (DISPLAY_VER(display) >= 30) { 57 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 58 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 59 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 60 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 61 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 62 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 63 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 64 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 65 rekey_bit = HDCP_LINE_REKEY_DISABLE; 66 } 67 68 if (rekey_bit) 69 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 70 } 71 72 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 73 struct intel_connector *connector) 74 { 75 struct intel_display *display = to_intel_display(state); 76 struct drm_dp_mst_topology_mgr *mgr; 77 struct drm_dp_mst_atomic_payload *payload; 78 struct drm_dp_mst_topology_state *mst_state; 79 80 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 81 if (!connector->mst.port) 82 return 0; 83 84 mgr = connector->mst.port->mgr; 85 mst_state = drm_atomic_get_new_mst_topology_state(&state->base, mgr); 86 if (!mst_state) { 87 drm_dbg_kms(display->drm, "MST topology still not created\n"); 88 return 0; 89 } 90 91 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 92 if (!payload) { 93 drm_dbg_kms(display->drm, "MST Payload not present\n"); 94 return 0; 95 } 96 97 return payload->vcpi; 98 } 99 100 /* 101 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 102 * content_type for all streams in DP MST topology because security f/w doesn't 103 * have any provision to mark content_type for each stream separately, it marks 104 * all available streams with the content_type proivided at the time of port 105 * authentication. This may prohibit the userspace to use type1 content on 106 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 107 * DP MST topology. Though it is not compulsory, security fw should change its 108 * policy to mark different content_types for different streams. 109 */ 110 static int 111 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 112 struct intel_digital_port *dig_port) 113 { 114 struct intel_display *display = to_intel_display(state); 115 struct drm_connector_list_iter conn_iter; 116 struct drm_connector_state *new_conn_state; 117 struct intel_digital_port *conn_dig_port; 118 struct intel_connector *connector; 119 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 120 bool enforce_type0 = false; 121 int k; 122 123 if (dig_port->hdcp.auth_status) 124 return 0; 125 126 data->k = 0; 127 128 if (!dig_port->hdcp.mst_type1_capable) 129 enforce_type0 = true; 130 131 drm_connector_list_iter_begin(display->drm, &conn_iter); 132 for_each_intel_connector_iter(connector, &conn_iter) { 133 if (connector->base.status == connector_status_disconnected) 134 continue; 135 136 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 137 continue; 138 139 conn_dig_port = intel_attached_dig_port(connector); 140 if (conn_dig_port != dig_port) 141 continue; 142 143 new_conn_state = drm_atomic_get_new_connector_state(&state->base, 144 &connector->base); 145 if (!new_conn_state || !new_conn_state->crtc) 146 continue; 147 148 if (drm_WARN_ON(display->drm, data->k >= INTEL_NUM_PIPES(display))) 149 return -EINVAL; 150 151 data->streams[data->k].stream_id = 152 intel_conn_to_vcpi(state, connector); 153 data->k++; 154 155 /* if there is only one active stream */ 156 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 157 break; 158 } 159 drm_connector_list_iter_end(&conn_iter); 160 161 if (drm_WARN_ON(display->drm, !data->k)) 162 return -EINVAL; 163 164 /* 165 * Apply common protection level across all streams in DP MST Topology. 166 * Use highest supported content type for all streams in DP MST Topology. 167 */ 168 for (k = 0; k < data->k; k++) 169 data->streams[k].stream_type = 170 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 171 172 return 0; 173 } 174 175 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 176 struct intel_connector *connector) 177 { 178 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 179 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 180 struct intel_hdcp *hdcp = &connector->hdcp; 181 182 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 183 return intel_hdcp_required_content_stream(state, dig_port); 184 185 data->k = 1; 186 data->streams[0].stream_id = 0; 187 data->streams[0].stream_type = hdcp->content_type; 188 189 return 0; 190 } 191 192 static 193 bool intel_hdcp_is_ksv_valid(u8 *ksv) 194 { 195 int i, ones = 0; 196 /* KSV has 20 1's and 20 0's */ 197 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 198 ones += hweight8(ksv[i]); 199 if (ones != 20) 200 return false; 201 202 return true; 203 } 204 205 static 206 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 207 const struct intel_hdcp_shim *shim, u8 *bksv) 208 { 209 struct intel_display *display = to_intel_display(dig_port); 210 int ret, i, tries = 2; 211 212 /* HDCP spec states that we must retry the bksv if it is invalid */ 213 for (i = 0; i < tries; i++) { 214 ret = shim->read_bksv(dig_port, bksv); 215 if (ret) 216 return ret; 217 if (intel_hdcp_is_ksv_valid(bksv)) 218 break; 219 } 220 if (i == tries) { 221 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 222 return -ENODEV; 223 } 224 225 return 0; 226 } 227 228 /* Is HDCP1.4 capable on Platform and Sink */ 229 static bool intel_hdcp_get_capability(struct intel_connector *connector) 230 { 231 struct intel_digital_port *dig_port; 232 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 233 bool capable = false; 234 u8 bksv[5]; 235 236 if (!intel_attached_encoder(connector)) 237 return capable; 238 239 dig_port = intel_attached_dig_port(connector); 240 241 if (!shim) 242 return capable; 243 244 if (shim->hdcp_get_capability) { 245 shim->hdcp_get_capability(dig_port, &capable); 246 } else { 247 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 248 capable = true; 249 } 250 251 return capable; 252 } 253 254 /* 255 * Check if the source has all the building blocks ready to make 256 * HDCP 2.2 work 257 */ 258 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 259 { 260 struct intel_display *display = to_intel_display(connector); 261 struct intel_hdcp *hdcp = &connector->hdcp; 262 263 /* I915 support for HDCP2.2 */ 264 if (!hdcp->hdcp2_supported) 265 return false; 266 267 /* If MTL+ make sure gsc is loaded and proxy is setup */ 268 if (USE_HDCP_GSC(display)) { 269 if (!intel_parent_hdcp_gsc_check_status(display)) 270 return false; 271 } 272 273 /* MEI/GSC interface is solid depending on which is used */ 274 mutex_lock(&display->hdcp.hdcp_mutex); 275 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 276 mutex_unlock(&display->hdcp.hdcp_mutex); 277 return false; 278 } 279 mutex_unlock(&display->hdcp.hdcp_mutex); 280 281 return true; 282 } 283 284 /* Is HDCP2.2 capable on Platform and Sink */ 285 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 286 { 287 struct intel_hdcp *hdcp = &connector->hdcp; 288 bool capable = false; 289 290 if (!intel_hdcp2_prerequisite(connector)) 291 return false; 292 293 /* Sink's capability for HDCP2.2 */ 294 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 295 296 return capable; 297 } 298 299 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 300 bool *hdcp_capable, 301 bool *hdcp2_capable) 302 { 303 struct intel_hdcp *hdcp = &connector->hdcp; 304 305 if (!hdcp->shim->get_remote_hdcp_capability) 306 return; 307 308 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 309 hdcp2_capable); 310 311 if (!intel_hdcp2_prerequisite(connector)) 312 *hdcp2_capable = false; 313 } 314 315 static bool intel_hdcp_in_use(struct intel_display *display, 316 enum transcoder cpu_transcoder, enum port port) 317 { 318 return intel_de_read(display, 319 HDCP_STATUS(display, cpu_transcoder, port)) & 320 HDCP_STATUS_ENC; 321 } 322 323 static bool intel_hdcp2_in_use(struct intel_display *display, 324 enum transcoder cpu_transcoder, enum port port) 325 { 326 return intel_de_read(display, 327 HDCP2_STATUS(display, cpu_transcoder, port)) & 328 LINK_ENCRYPTION_STATUS; 329 } 330 331 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 332 const struct intel_hdcp_shim *shim) 333 { 334 int ret, read_ret; 335 bool ksv_ready; 336 337 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 338 ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), 339 read_ret || ksv_ready, 340 100 * 1000, 5 * 1000 * 1000, false); 341 if (ret) 342 return ret; 343 if (read_ret) 344 return read_ret; 345 346 return 0; 347 } 348 349 static bool hdcp_key_loadable(struct intel_display *display) 350 { 351 enum i915_power_well_id id; 352 bool enabled = false; 353 354 /* 355 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 356 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 357 */ 358 if (display->platform.haswell || display->platform.broadwell) 359 id = HSW_DISP_PW_GLOBAL; 360 else 361 id = SKL_DISP_PW_1; 362 363 /* PG1 (power well #1) needs to be enabled */ 364 with_intel_display_rpm(display) 365 enabled = intel_display_power_well_is_enabled(display, id); 366 367 /* 368 * Another req for hdcp key loadability is enabled state of pll for 369 * cdclk. Without active crtc we won't land here. So we are assuming that 370 * cdclk is already on. 371 */ 372 373 return enabled; 374 } 375 376 static void intel_hdcp_clear_keys(struct intel_display *display) 377 { 378 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 379 intel_de_write(display, HDCP_KEY_STATUS, 380 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 381 } 382 383 static int intel_hdcp_load_keys(struct intel_display *display) 384 { 385 int ret; 386 u32 val; 387 388 val = intel_de_read(display, HDCP_KEY_STATUS); 389 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 390 return 0; 391 392 /* 393 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 394 * out of reset. So if Key is not already loaded, its an error state. 395 */ 396 if (display->platform.haswell || display->platform.broadwell) 397 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 398 return -ENXIO; 399 400 /* 401 * Initiate loading the HDCP key from fuses. 402 * 403 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 404 * version 9 platforms (minus BXT) differ in the key load trigger 405 * process from other platforms. These platforms use the GT Driver 406 * Mailbox interface. 407 */ 408 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 409 ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1); 410 if (ret) { 411 drm_err(display->drm, 412 "Failed to initiate HDCP key load (%d)\n", 413 ret); 414 return ret; 415 } 416 } else { 417 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 418 } 419 420 /* Wait for the keys to load (500us) */ 421 ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE, 422 HDCP_KEY_LOAD_DONE, 1, &val); 423 if (ret) 424 return ret; 425 else if (!(val & HDCP_KEY_LOAD_STATUS)) 426 return -ENXIO; 427 428 /* Send Aksv over to PCH display for use in authentication */ 429 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 430 431 return 0; 432 } 433 434 /* Returns updated SHA-1 index */ 435 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 436 { 437 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 438 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 439 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 440 return -ETIMEDOUT; 441 } 442 return 0; 443 } 444 445 static 446 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 447 enum transcoder cpu_transcoder, enum port port) 448 { 449 if (DISPLAY_VER(display) >= 12) { 450 switch (cpu_transcoder) { 451 case TRANSCODER_A: 452 return HDCP_TRANSA_REP_PRESENT | 453 HDCP_TRANSA_SHA1_M0; 454 case TRANSCODER_B: 455 return HDCP_TRANSB_REP_PRESENT | 456 HDCP_TRANSB_SHA1_M0; 457 case TRANSCODER_C: 458 return HDCP_TRANSC_REP_PRESENT | 459 HDCP_TRANSC_SHA1_M0; 460 case TRANSCODER_D: 461 return HDCP_TRANSD_REP_PRESENT | 462 HDCP_TRANSD_SHA1_M0; 463 default: 464 drm_err(display->drm, "Unknown transcoder %d\n", 465 cpu_transcoder); 466 return 0; 467 } 468 } 469 470 switch (port) { 471 case PORT_A: 472 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 473 case PORT_B: 474 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 475 case PORT_C: 476 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 477 case PORT_D: 478 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 479 case PORT_E: 480 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 481 default: 482 drm_err(display->drm, "Unknown port %d\n", port); 483 return 0; 484 } 485 } 486 487 static 488 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 489 const struct intel_hdcp_shim *shim, 490 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 491 { 492 struct intel_display *display = to_intel_display(connector); 493 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 494 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 495 enum port port = dig_port->base.port; 496 u32 vprime, sha_text, sha_leftovers, rep_ctl; 497 int ret, i, j, sha_idx; 498 499 /* Process V' values from the receiver */ 500 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 501 ret = shim->read_v_prime_part(dig_port, i, &vprime); 502 if (ret) 503 return ret; 504 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 505 } 506 507 /* 508 * We need to write the concatenation of all device KSVs, BINFO (DP) || 509 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 510 * stream is written via the HDCP_SHA_TEXT register in 32-bit 511 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 512 * index will keep track of our progress through the 64 bytes as well as 513 * helping us work the 40-bit KSVs through our 32-bit register. 514 * 515 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 516 */ 517 sha_idx = 0; 518 sha_text = 0; 519 sha_leftovers = 0; 520 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 521 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 522 for (i = 0; i < num_downstream; i++) { 523 unsigned int sha_empty; 524 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 525 526 /* Fill up the empty slots in sha_text and write it out */ 527 sha_empty = sizeof(sha_text) - sha_leftovers; 528 for (j = 0; j < sha_empty; j++) { 529 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 530 sha_text |= ksv[j] << off; 531 } 532 533 ret = intel_write_sha_text(display, sha_text); 534 if (ret < 0) 535 return ret; 536 537 /* Programming guide writes this every 64 bytes */ 538 sha_idx += sizeof(sha_text); 539 if (!(sha_idx % 64)) 540 intel_de_write(display, HDCP_REP_CTL, 541 rep_ctl | HDCP_SHA1_TEXT_32); 542 543 /* Store the leftover bytes from the ksv in sha_text */ 544 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 545 sha_text = 0; 546 for (j = 0; j < sha_leftovers; j++) 547 sha_text |= ksv[sha_empty + j] << 548 ((sizeof(sha_text) - j - 1) * 8); 549 550 /* 551 * If we still have room in sha_text for more data, continue. 552 * Otherwise, write it out immediately. 553 */ 554 if (sizeof(sha_text) > sha_leftovers) 555 continue; 556 557 ret = intel_write_sha_text(display, sha_text); 558 if (ret < 0) 559 return ret; 560 sha_leftovers = 0; 561 sha_text = 0; 562 sha_idx += sizeof(sha_text); 563 } 564 565 /* 566 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 567 * bytes are leftover from the last ksv, we might be able to fit them 568 * all in sha_text (first 2 cases), or we might need to split them up 569 * into 2 writes (last 2 cases). 570 */ 571 if (sha_leftovers == 0) { 572 /* Write 16 bits of text, 16 bits of M0 */ 573 intel_de_write(display, HDCP_REP_CTL, 574 rep_ctl | HDCP_SHA1_TEXT_16); 575 ret = intel_write_sha_text(display, 576 bstatus[0] << 8 | bstatus[1]); 577 if (ret < 0) 578 return ret; 579 sha_idx += sizeof(sha_text); 580 581 /* Write 32 bits of M0 */ 582 intel_de_write(display, HDCP_REP_CTL, 583 rep_ctl | HDCP_SHA1_TEXT_0); 584 ret = intel_write_sha_text(display, 0); 585 if (ret < 0) 586 return ret; 587 sha_idx += sizeof(sha_text); 588 589 /* Write 16 bits of M0 */ 590 intel_de_write(display, HDCP_REP_CTL, 591 rep_ctl | HDCP_SHA1_TEXT_16); 592 ret = intel_write_sha_text(display, 0); 593 if (ret < 0) 594 return ret; 595 sha_idx += sizeof(sha_text); 596 597 } else if (sha_leftovers == 1) { 598 /* Write 24 bits of text, 8 bits of M0 */ 599 intel_de_write(display, HDCP_REP_CTL, 600 rep_ctl | HDCP_SHA1_TEXT_24); 601 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 602 /* Only 24-bits of data, must be in the LSB */ 603 sha_text = (sha_text & 0xffffff00) >> 8; 604 ret = intel_write_sha_text(display, sha_text); 605 if (ret < 0) 606 return ret; 607 sha_idx += sizeof(sha_text); 608 609 /* Write 32 bits of M0 */ 610 intel_de_write(display, HDCP_REP_CTL, 611 rep_ctl | HDCP_SHA1_TEXT_0); 612 ret = intel_write_sha_text(display, 0); 613 if (ret < 0) 614 return ret; 615 sha_idx += sizeof(sha_text); 616 617 /* Write 24 bits of M0 */ 618 intel_de_write(display, HDCP_REP_CTL, 619 rep_ctl | HDCP_SHA1_TEXT_8); 620 ret = intel_write_sha_text(display, 0); 621 if (ret < 0) 622 return ret; 623 sha_idx += sizeof(sha_text); 624 625 } else if (sha_leftovers == 2) { 626 /* Write 32 bits of text */ 627 intel_de_write(display, HDCP_REP_CTL, 628 rep_ctl | HDCP_SHA1_TEXT_32); 629 sha_text |= bstatus[0] << 8 | bstatus[1]; 630 ret = intel_write_sha_text(display, sha_text); 631 if (ret < 0) 632 return ret; 633 sha_idx += sizeof(sha_text); 634 635 /* Write 64 bits of M0 */ 636 intel_de_write(display, HDCP_REP_CTL, 637 rep_ctl | HDCP_SHA1_TEXT_0); 638 for (i = 0; i < 2; i++) { 639 ret = intel_write_sha_text(display, 0); 640 if (ret < 0) 641 return ret; 642 sha_idx += sizeof(sha_text); 643 } 644 645 /* 646 * Terminate the SHA-1 stream by hand. For the other leftover 647 * cases this is appended by the hardware. 648 */ 649 intel_de_write(display, HDCP_REP_CTL, 650 rep_ctl | HDCP_SHA1_TEXT_32); 651 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 652 ret = intel_write_sha_text(display, sha_text); 653 if (ret < 0) 654 return ret; 655 sha_idx += sizeof(sha_text); 656 } else if (sha_leftovers == 3) { 657 /* Write 32 bits of text (filled from LSB) */ 658 intel_de_write(display, HDCP_REP_CTL, 659 rep_ctl | HDCP_SHA1_TEXT_32); 660 sha_text |= bstatus[0]; 661 ret = intel_write_sha_text(display, sha_text); 662 if (ret < 0) 663 return ret; 664 sha_idx += sizeof(sha_text); 665 666 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 667 intel_de_write(display, HDCP_REP_CTL, 668 rep_ctl | HDCP_SHA1_TEXT_8); 669 ret = intel_write_sha_text(display, bstatus[1]); 670 if (ret < 0) 671 return ret; 672 sha_idx += sizeof(sha_text); 673 674 /* Write 32 bits of M0 */ 675 intel_de_write(display, HDCP_REP_CTL, 676 rep_ctl | HDCP_SHA1_TEXT_0); 677 ret = intel_write_sha_text(display, 0); 678 if (ret < 0) 679 return ret; 680 sha_idx += sizeof(sha_text); 681 682 /* Write 8 bits of M0 */ 683 intel_de_write(display, HDCP_REP_CTL, 684 rep_ctl | HDCP_SHA1_TEXT_24); 685 ret = intel_write_sha_text(display, 0); 686 if (ret < 0) 687 return ret; 688 sha_idx += sizeof(sha_text); 689 } else { 690 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 691 sha_leftovers); 692 return -EINVAL; 693 } 694 695 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 696 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 697 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 698 ret = intel_write_sha_text(display, 0); 699 if (ret < 0) 700 return ret; 701 sha_idx += sizeof(sha_text); 702 } 703 704 /* 705 * Last write gets the length of the concatenation in bits. That is: 706 * - 5 bytes per device 707 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 708 */ 709 sha_text = (num_downstream * 5 + 10) * 8; 710 ret = intel_write_sha_text(display, sha_text); 711 if (ret < 0) 712 return ret; 713 714 /* Tell the HW we're done with the hash and wait for it to ACK */ 715 intel_de_write(display, HDCP_REP_CTL, 716 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 717 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, 718 HDCP_SHA1_COMPLETE, 1)) { 719 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 720 return -ETIMEDOUT; 721 } 722 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 723 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 724 return -ENXIO; 725 } 726 727 return 0; 728 } 729 730 /* Implements Part 2 of the HDCP authorization procedure */ 731 static 732 int intel_hdcp_auth_downstream(struct intel_connector *connector) 733 { 734 struct intel_display *display = to_intel_display(connector); 735 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 736 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 737 u8 bstatus[2], num_downstream, *ksv_fifo; 738 int ret, i, tries = 3; 739 740 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 741 if (ret) { 742 drm_dbg_kms(display->drm, 743 "KSV list failed to become ready (%d)\n", ret); 744 return ret; 745 } 746 747 ret = shim->read_bstatus(dig_port, bstatus); 748 if (ret) 749 return ret; 750 751 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 752 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 753 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 754 return -EPERM; 755 } 756 757 /* 758 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 759 * the HDCP encryption. That implies that repeater can't have its own 760 * display. As there is no consumption of encrypted content in the 761 * repeater with 0 downstream devices, we are failing the 762 * authentication. 763 */ 764 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 765 if (num_downstream == 0) { 766 drm_dbg_kms(display->drm, 767 "Repeater with zero downstream devices\n"); 768 return -EINVAL; 769 } 770 771 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 772 if (!ksv_fifo) { 773 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 774 return -ENOMEM; 775 } 776 777 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 778 if (ret) 779 goto err; 780 781 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 782 num_downstream) > 0) { 783 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 784 ret = -EPERM; 785 goto err; 786 } 787 788 /* 789 * When V prime mismatches, DP Spec mandates re-read of 790 * V prime atleast twice. 791 */ 792 for (i = 0; i < tries; i++) { 793 ret = intel_hdcp_validate_v_prime(connector, shim, 794 ksv_fifo, num_downstream, 795 bstatus); 796 if (!ret) 797 break; 798 } 799 800 if (i == tries) { 801 drm_dbg_kms(display->drm, 802 "V Prime validation failed.(%d)\n", ret); 803 goto err; 804 } 805 806 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 807 num_downstream); 808 ret = 0; 809 err: 810 kfree(ksv_fifo); 811 return ret; 812 } 813 814 /* Implements Part 1 of the HDCP authorization procedure */ 815 static int intel_hdcp_auth(struct intel_connector *connector) 816 { 817 struct intel_display *display = to_intel_display(connector); 818 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 819 struct intel_hdcp *hdcp = &connector->hdcp; 820 const struct intel_hdcp_shim *shim = hdcp->shim; 821 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 822 enum port port = dig_port->base.port; 823 unsigned long r0_prime_gen_start; 824 int ret, i, tries = 2; 825 u32 val; 826 union { 827 u32 reg[2]; 828 u8 shim[DRM_HDCP_AN_LEN]; 829 } an; 830 union { 831 u32 reg[2]; 832 u8 shim[DRM_HDCP_KSV_LEN]; 833 } bksv; 834 union { 835 u32 reg; 836 u8 shim[DRM_HDCP_RI_LEN]; 837 } ri; 838 bool repeater_present, hdcp_capable; 839 840 /* 841 * Detects whether the display is HDCP capable. Although we check for 842 * valid Bksv below, the HDCP over DP spec requires that we check 843 * whether the display supports HDCP before we write An. For HDMI 844 * displays, this is not necessary. 845 */ 846 if (shim->hdcp_get_capability) { 847 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 848 if (ret) 849 return ret; 850 if (!hdcp_capable) { 851 drm_dbg_kms(display->drm, 852 "Panel is not HDCP capable\n"); 853 return -EINVAL; 854 } 855 } 856 857 /* Initialize An with 2 random values and acquire it */ 858 for (i = 0; i < 2; i++) 859 intel_de_write(display, 860 HDCP_ANINIT(display, cpu_transcoder, port), 861 get_random_u32()); 862 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 863 HDCP_CONF_CAPTURE_AN); 864 865 /* Wait for An to be acquired */ 866 if (intel_de_wait_for_set_ms(display, 867 HDCP_STATUS(display, cpu_transcoder, port), 868 HDCP_STATUS_AN_READY, 1)) { 869 drm_err(display->drm, "Timed out waiting for An\n"); 870 return -ETIMEDOUT; 871 } 872 873 an.reg[0] = intel_de_read(display, 874 HDCP_ANLO(display, cpu_transcoder, port)); 875 an.reg[1] = intel_de_read(display, 876 HDCP_ANHI(display, cpu_transcoder, port)); 877 ret = shim->write_an_aksv(dig_port, an.shim); 878 if (ret) 879 return ret; 880 881 r0_prime_gen_start = jiffies; 882 883 memset(&bksv, 0, sizeof(bksv)); 884 885 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 886 if (ret < 0) 887 return ret; 888 889 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 890 drm_err(display->drm, "BKSV is revoked\n"); 891 return -EPERM; 892 } 893 894 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 895 bksv.reg[0]); 896 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 897 bksv.reg[1]); 898 899 ret = shim->repeater_present(dig_port, &repeater_present); 900 if (ret) 901 return ret; 902 if (repeater_present) 903 intel_de_write(display, HDCP_REP_CTL, 904 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 905 906 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 907 if (ret) 908 return ret; 909 910 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 911 HDCP_CONF_AUTH_AND_ENC); 912 913 /* Wait for R0 ready */ 914 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 915 val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 916 100, 1000, false); 917 if (ret) { 918 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 919 return -ETIMEDOUT; 920 } 921 922 /* 923 * Wait for R0' to become available. The spec says 100ms from Aksv, but 924 * some monitors can take longer than this. We'll set the timeout at 925 * 300ms just to be sure. 926 * 927 * On DP, there's an R0_READY bit available but no such bit 928 * exists on HDMI. Since the upper-bound is the same, we'll just do 929 * the stupid thing instead of polling on one and not the other. 930 */ 931 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 932 933 tries = 3; 934 935 /* 936 * DP HDCP Spec mandates the two more reattempt to read R0, incase 937 * of R0 mismatch. 938 */ 939 for (i = 0; i < tries; i++) { 940 ri.reg = 0; 941 ret = shim->read_ri_prime(dig_port, ri.shim); 942 if (ret) 943 return ret; 944 intel_de_write(display, 945 HDCP_RPRIME(display, cpu_transcoder, port), 946 ri.reg); 947 948 /* Wait for Ri prime match */ 949 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 950 val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 951 100, 1000, false); 952 if (!ret) 953 break; 954 } 955 956 if (i == tries) { 957 drm_dbg_kms(display->drm, 958 "Timed out waiting for Ri prime match (%x)\n", val); 959 return -ETIMEDOUT; 960 } 961 962 /* Wait for encryption confirmation */ 963 if (intel_de_wait_for_set_ms(display, 964 HDCP_STATUS(display, cpu_transcoder, port), 965 HDCP_STATUS_ENC, 966 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 967 drm_err(display->drm, "Timed out waiting for encryption\n"); 968 return -ETIMEDOUT; 969 } 970 971 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 972 if (shim->stream_encryption) { 973 ret = shim->stream_encryption(connector, true); 974 if (ret) { 975 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 976 connector->base.base.id, connector->base.name); 977 return ret; 978 } 979 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 980 transcoder_name(hdcp->stream_transcoder)); 981 } 982 983 if (repeater_present) 984 return intel_hdcp_auth_downstream(connector); 985 986 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 987 return 0; 988 } 989 990 static int _intel_hdcp_disable(struct intel_connector *connector) 991 { 992 struct intel_display *display = to_intel_display(connector); 993 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 994 struct intel_hdcp *hdcp = &connector->hdcp; 995 enum port port = dig_port->base.port; 996 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 997 u32 repeater_ctl; 998 int ret; 999 1000 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 1001 connector->base.base.id, connector->base.name); 1002 1003 if (hdcp->shim->stream_encryption) { 1004 ret = hdcp->shim->stream_encryption(connector, false); 1005 if (ret) { 1006 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 1007 connector->base.base.id, connector->base.name); 1008 return ret; 1009 } 1010 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1011 transcoder_name(hdcp->stream_transcoder)); 1012 /* 1013 * If there are other connectors on this port using HDCP, 1014 * don't disable it until it disabled HDCP encryption for 1015 * all connectors in MST topology. 1016 */ 1017 if (dig_port->hdcp.num_streams > 0) 1018 return 0; 1019 } 1020 1021 hdcp->hdcp_encrypted = false; 1022 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1023 if (intel_de_wait_for_clear_ms(display, 1024 HDCP_STATUS(display, cpu_transcoder, port), 1025 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1026 drm_err(display->drm, 1027 "Failed to disable HDCP, timeout clearing status\n"); 1028 return -ETIMEDOUT; 1029 } 1030 1031 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1032 port); 1033 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1034 1035 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1036 if (ret) { 1037 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1038 return ret; 1039 } 1040 1041 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1042 return 0; 1043 } 1044 1045 static int intel_hdcp1_enable(struct intel_connector *connector) 1046 { 1047 struct intel_display *display = to_intel_display(connector); 1048 struct intel_hdcp *hdcp = &connector->hdcp; 1049 int i, ret, tries = 3; 1050 1051 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1052 connector->base.base.id, connector->base.name); 1053 1054 if (!hdcp_key_loadable(display)) { 1055 drm_err(display->drm, "HDCP key Load is not possible\n"); 1056 return -ENXIO; 1057 } 1058 1059 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1060 ret = intel_hdcp_load_keys(display); 1061 if (!ret) 1062 break; 1063 intel_hdcp_clear_keys(display); 1064 } 1065 if (ret) { 1066 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1067 ret); 1068 return ret; 1069 } 1070 1071 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1072 1073 /* Incase of authentication failures, HDCP spec expects reauth. */ 1074 for (i = 0; i < tries; i++) { 1075 ret = intel_hdcp_auth(connector); 1076 if (!ret) { 1077 hdcp->hdcp_encrypted = true; 1078 return 0; 1079 } 1080 1081 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1082 1083 /* Ensuring HDCP encryption and signalling are stopped. */ 1084 _intel_hdcp_disable(connector); 1085 } 1086 1087 drm_dbg_kms(display->drm, 1088 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1089 return ret; 1090 } 1091 1092 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1093 { 1094 return container_of(hdcp, struct intel_connector, hdcp); 1095 } 1096 1097 static void intel_hdcp_update_value(struct intel_connector *connector, 1098 u64 value, bool update_property) 1099 { 1100 struct intel_display *display = to_intel_display(connector); 1101 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1102 struct intel_hdcp *hdcp = &connector->hdcp; 1103 1104 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1105 1106 if (hdcp->value == value) 1107 return; 1108 1109 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1110 1111 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1112 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1113 dig_port->hdcp.num_streams--; 1114 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1115 dig_port->hdcp.num_streams++; 1116 } 1117 1118 hdcp->value = value; 1119 if (update_property) { 1120 drm_connector_get(&connector->base); 1121 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 1122 drm_connector_put(&connector->base); 1123 } 1124 } 1125 1126 /* Implements Part 3 of the HDCP authorization procedure */ 1127 static int intel_hdcp_check_link(struct intel_connector *connector) 1128 { 1129 struct intel_display *display = to_intel_display(connector); 1130 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1131 struct intel_hdcp *hdcp = &connector->hdcp; 1132 enum port port = dig_port->base.port; 1133 enum transcoder cpu_transcoder; 1134 int ret = 0; 1135 1136 mutex_lock(&hdcp->mutex); 1137 mutex_lock(&dig_port->hdcp.mutex); 1138 1139 cpu_transcoder = hdcp->cpu_transcoder; 1140 1141 /* Check_link valid only when HDCP1.4 is enabled */ 1142 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1143 !hdcp->hdcp_encrypted) { 1144 ret = -EINVAL; 1145 goto out; 1146 } 1147 1148 if (drm_WARN_ON(display->drm, 1149 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1150 drm_err(display->drm, 1151 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1152 connector->base.base.id, connector->base.name, 1153 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1154 ret = -ENXIO; 1155 intel_hdcp_update_value(connector, 1156 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1157 true); 1158 goto out; 1159 } 1160 1161 if (hdcp->shim->check_link(dig_port, connector)) { 1162 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1163 intel_hdcp_update_value(connector, 1164 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1165 } 1166 goto out; 1167 } 1168 1169 drm_dbg_kms(display->drm, 1170 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1171 connector->base.base.id, connector->base.name); 1172 1173 ret = _intel_hdcp_disable(connector); 1174 if (ret) { 1175 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1176 intel_hdcp_update_value(connector, 1177 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1178 true); 1179 goto out; 1180 } 1181 1182 ret = intel_hdcp1_enable(connector); 1183 if (ret) { 1184 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1185 intel_hdcp_update_value(connector, 1186 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1187 true); 1188 goto out; 1189 } 1190 1191 out: 1192 mutex_unlock(&dig_port->hdcp.mutex); 1193 mutex_unlock(&hdcp->mutex); 1194 return ret; 1195 } 1196 1197 static void intel_hdcp_prop_work(struct work_struct *work) 1198 { 1199 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1200 prop_work); 1201 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1202 struct intel_display *display = to_intel_display(connector); 1203 1204 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1205 mutex_lock(&hdcp->mutex); 1206 1207 /* 1208 * This worker is only used to flip between ENABLED/DESIRED. Either of 1209 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1210 * we're running just after hdcp has been disabled, so just exit 1211 */ 1212 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1213 drm_hdcp_update_content_protection(&connector->base, 1214 hdcp->value); 1215 1216 mutex_unlock(&hdcp->mutex); 1217 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1218 1219 drm_connector_put(&connector->base); 1220 } 1221 1222 bool is_hdcp_supported(struct intel_display *display, enum port port) 1223 { 1224 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1225 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1226 } 1227 1228 static int 1229 hdcp2_prepare_ake_init(struct intel_connector *connector, 1230 struct hdcp2_ake_init *ake_data) 1231 { 1232 struct intel_display *display = to_intel_display(connector); 1233 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1234 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1235 struct i915_hdcp_arbiter *arbiter; 1236 int ret; 1237 1238 mutex_lock(&display->hdcp.hdcp_mutex); 1239 arbiter = display->hdcp.arbiter; 1240 1241 if (!arbiter || !arbiter->ops) { 1242 mutex_unlock(&display->hdcp.hdcp_mutex); 1243 return -EINVAL; 1244 } 1245 1246 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1247 if (ret) 1248 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1249 ret); 1250 mutex_unlock(&display->hdcp.hdcp_mutex); 1251 1252 return ret; 1253 } 1254 1255 static int 1256 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1257 struct hdcp2_ake_send_cert *rx_cert, 1258 bool *paired, 1259 struct hdcp2_ake_no_stored_km *ek_pub_km, 1260 size_t *msg_sz) 1261 { 1262 struct intel_display *display = to_intel_display(connector); 1263 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1264 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1265 struct i915_hdcp_arbiter *arbiter; 1266 int ret; 1267 1268 mutex_lock(&display->hdcp.hdcp_mutex); 1269 arbiter = display->hdcp.arbiter; 1270 1271 if (!arbiter || !arbiter->ops) { 1272 mutex_unlock(&display->hdcp.hdcp_mutex); 1273 return -EINVAL; 1274 } 1275 1276 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1277 rx_cert, paired, 1278 ek_pub_km, msg_sz); 1279 if (ret < 0) 1280 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1281 ret); 1282 mutex_unlock(&display->hdcp.hdcp_mutex); 1283 1284 return ret; 1285 } 1286 1287 static int hdcp2_verify_hprime(struct intel_connector *connector, 1288 struct hdcp2_ake_send_hprime *rx_hprime) 1289 { 1290 struct intel_display *display = to_intel_display(connector); 1291 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1292 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1293 struct i915_hdcp_arbiter *arbiter; 1294 int ret; 1295 1296 mutex_lock(&display->hdcp.hdcp_mutex); 1297 arbiter = display->hdcp.arbiter; 1298 1299 if (!arbiter || !arbiter->ops) { 1300 mutex_unlock(&display->hdcp.hdcp_mutex); 1301 return -EINVAL; 1302 } 1303 1304 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1305 if (ret < 0) 1306 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1307 mutex_unlock(&display->hdcp.hdcp_mutex); 1308 1309 return ret; 1310 } 1311 1312 static int 1313 hdcp2_store_pairing_info(struct intel_connector *connector, 1314 struct hdcp2_ake_send_pairing_info *pairing_info) 1315 { 1316 struct intel_display *display = to_intel_display(connector); 1317 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1318 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1319 struct i915_hdcp_arbiter *arbiter; 1320 int ret; 1321 1322 mutex_lock(&display->hdcp.hdcp_mutex); 1323 arbiter = display->hdcp.arbiter; 1324 1325 if (!arbiter || !arbiter->ops) { 1326 mutex_unlock(&display->hdcp.hdcp_mutex); 1327 return -EINVAL; 1328 } 1329 1330 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1331 if (ret < 0) 1332 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1333 ret); 1334 mutex_unlock(&display->hdcp.hdcp_mutex); 1335 1336 return ret; 1337 } 1338 1339 static int 1340 hdcp2_prepare_lc_init(struct intel_connector *connector, 1341 struct hdcp2_lc_init *lc_init) 1342 { 1343 struct intel_display *display = to_intel_display(connector); 1344 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1345 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1346 struct i915_hdcp_arbiter *arbiter; 1347 int ret; 1348 1349 mutex_lock(&display->hdcp.hdcp_mutex); 1350 arbiter = display->hdcp.arbiter; 1351 1352 if (!arbiter || !arbiter->ops) { 1353 mutex_unlock(&display->hdcp.hdcp_mutex); 1354 return -EINVAL; 1355 } 1356 1357 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1358 if (ret < 0) 1359 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1360 ret); 1361 mutex_unlock(&display->hdcp.hdcp_mutex); 1362 1363 return ret; 1364 } 1365 1366 static int 1367 hdcp2_verify_lprime(struct intel_connector *connector, 1368 struct hdcp2_lc_send_lprime *rx_lprime) 1369 { 1370 struct intel_display *display = to_intel_display(connector); 1371 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1372 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1373 struct i915_hdcp_arbiter *arbiter; 1374 int ret; 1375 1376 mutex_lock(&display->hdcp.hdcp_mutex); 1377 arbiter = display->hdcp.arbiter; 1378 1379 if (!arbiter || !arbiter->ops) { 1380 mutex_unlock(&display->hdcp.hdcp_mutex); 1381 return -EINVAL; 1382 } 1383 1384 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1385 if (ret < 0) 1386 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1387 ret); 1388 mutex_unlock(&display->hdcp.hdcp_mutex); 1389 1390 return ret; 1391 } 1392 1393 static int hdcp2_prepare_skey(struct intel_connector *connector, 1394 struct hdcp2_ske_send_eks *ske_data) 1395 { 1396 struct intel_display *display = to_intel_display(connector); 1397 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1398 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1399 struct i915_hdcp_arbiter *arbiter; 1400 int ret; 1401 1402 mutex_lock(&display->hdcp.hdcp_mutex); 1403 arbiter = display->hdcp.arbiter; 1404 1405 if (!arbiter || !arbiter->ops) { 1406 mutex_unlock(&display->hdcp.hdcp_mutex); 1407 return -EINVAL; 1408 } 1409 1410 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1411 if (ret < 0) 1412 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1413 ret); 1414 mutex_unlock(&display->hdcp.hdcp_mutex); 1415 1416 return ret; 1417 } 1418 1419 static int 1420 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1421 struct hdcp2_rep_send_receiverid_list 1422 *rep_topology, 1423 struct hdcp2_rep_send_ack *rep_send_ack) 1424 { 1425 struct intel_display *display = to_intel_display(connector); 1426 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1427 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1428 struct i915_hdcp_arbiter *arbiter; 1429 int ret; 1430 1431 mutex_lock(&display->hdcp.hdcp_mutex); 1432 arbiter = display->hdcp.arbiter; 1433 1434 if (!arbiter || !arbiter->ops) { 1435 mutex_unlock(&display->hdcp.hdcp_mutex); 1436 return -EINVAL; 1437 } 1438 1439 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1440 data, 1441 rep_topology, 1442 rep_send_ack); 1443 if (ret < 0) 1444 drm_dbg_kms(display->drm, 1445 "Verify rep topology failed. %d\n", ret); 1446 mutex_unlock(&display->hdcp.hdcp_mutex); 1447 1448 return ret; 1449 } 1450 1451 static int 1452 hdcp2_verify_mprime(struct intel_connector *connector, 1453 struct hdcp2_rep_stream_ready *stream_ready) 1454 { 1455 struct intel_display *display = to_intel_display(connector); 1456 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1457 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1458 struct i915_hdcp_arbiter *arbiter; 1459 int ret; 1460 1461 mutex_lock(&display->hdcp.hdcp_mutex); 1462 arbiter = display->hdcp.arbiter; 1463 1464 if (!arbiter || !arbiter->ops) { 1465 mutex_unlock(&display->hdcp.hdcp_mutex); 1466 return -EINVAL; 1467 } 1468 1469 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1470 if (ret < 0) 1471 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1472 mutex_unlock(&display->hdcp.hdcp_mutex); 1473 1474 return ret; 1475 } 1476 1477 static int hdcp2_authenticate_port(struct intel_connector *connector) 1478 { 1479 struct intel_display *display = to_intel_display(connector); 1480 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1481 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1482 struct i915_hdcp_arbiter *arbiter; 1483 int ret; 1484 1485 mutex_lock(&display->hdcp.hdcp_mutex); 1486 arbiter = display->hdcp.arbiter; 1487 1488 if (!arbiter || !arbiter->ops) { 1489 mutex_unlock(&display->hdcp.hdcp_mutex); 1490 return -EINVAL; 1491 } 1492 1493 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1494 if (ret < 0) 1495 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1496 ret); 1497 mutex_unlock(&display->hdcp.hdcp_mutex); 1498 1499 return ret; 1500 } 1501 1502 static int hdcp2_close_session(struct intel_connector *connector) 1503 { 1504 struct intel_display *display = to_intel_display(connector); 1505 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1506 struct i915_hdcp_arbiter *arbiter; 1507 int ret; 1508 1509 mutex_lock(&display->hdcp.hdcp_mutex); 1510 arbiter = display->hdcp.arbiter; 1511 1512 if (!arbiter || !arbiter->ops) { 1513 mutex_unlock(&display->hdcp.hdcp_mutex); 1514 return -EINVAL; 1515 } 1516 1517 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1518 &dig_port->hdcp.port_data); 1519 mutex_unlock(&display->hdcp.hdcp_mutex); 1520 1521 return ret; 1522 } 1523 1524 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1525 { 1526 return hdcp2_close_session(connector); 1527 } 1528 1529 /* Authentication flow starts from here */ 1530 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1531 { 1532 struct intel_display *display = to_intel_display(connector); 1533 struct intel_digital_port *dig_port = 1534 intel_attached_dig_port(connector); 1535 struct intel_hdcp *hdcp = &connector->hdcp; 1536 union { 1537 struct hdcp2_ake_init ake_init; 1538 struct hdcp2_ake_send_cert send_cert; 1539 struct hdcp2_ake_no_stored_km no_stored_km; 1540 struct hdcp2_ake_send_hprime send_hprime; 1541 struct hdcp2_ake_send_pairing_info pairing_info; 1542 } msgs; 1543 const struct intel_hdcp_shim *shim = hdcp->shim; 1544 size_t size; 1545 int ret, i, max_retries; 1546 1547 /* Init for seq_num */ 1548 hdcp->seq_num_v = 0; 1549 hdcp->seq_num_m = 0; 1550 1551 if (intel_encoder_is_dp(&dig_port->base) || 1552 intel_encoder_is_mst(&dig_port->base)) 1553 max_retries = 10; 1554 else 1555 max_retries = 1; 1556 1557 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1558 if (ret < 0) 1559 return ret; 1560 1561 /* 1562 * Retry the first read and write to downstream at least 10 times 1563 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1564 * (dock decides to stop advertising hdcp2 capability for some reason). 1565 * The reason being that during suspend resume dock usually keeps the 1566 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1567 * big problem if the userspace just kept retrying with some delay while 1568 * it continues to play low value content but most userspace applications 1569 * end up throwing an error when it receives one from KMD. This makes 1570 * sure we give the dock and the sink devices to complete its power cycle 1571 * and then try HDCP authentication. The values of 10 and delay of 50ms 1572 * was decided based on multiple trial and errors. 1573 */ 1574 for (i = 0; i < max_retries; i++) { 1575 if (!intel_hdcp2_get_capability(connector)) { 1576 msleep(50); 1577 continue; 1578 } 1579 1580 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1581 sizeof(msgs.ake_init)); 1582 if (ret < 0) 1583 continue; 1584 1585 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1586 &msgs.send_cert, sizeof(msgs.send_cert)); 1587 if (ret > 0) 1588 break; 1589 } 1590 1591 if (ret < 0) 1592 return ret; 1593 1594 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1595 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1596 return -EINVAL; 1597 } 1598 1599 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1600 1601 if (drm_hdcp_check_ksvs_revoked(display->drm, 1602 msgs.send_cert.cert_rx.receiver_id, 1603 1) > 0) { 1604 drm_err(display->drm, "Receiver ID is revoked\n"); 1605 return -EPERM; 1606 } 1607 1608 /* 1609 * Here msgs.no_stored_km will hold msgs corresponding to the km 1610 * stored also. 1611 */ 1612 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1613 &hdcp->is_paired, 1614 &msgs.no_stored_km, &size); 1615 if (ret < 0) 1616 return ret; 1617 1618 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1619 if (ret < 0) 1620 return ret; 1621 1622 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1623 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1624 if (ret < 0) 1625 return ret; 1626 1627 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1628 if (ret < 0) 1629 return ret; 1630 1631 if (!hdcp->is_paired) { 1632 /* Pairing is required */ 1633 ret = shim->read_2_2_msg(connector, 1634 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1635 &msgs.pairing_info, 1636 sizeof(msgs.pairing_info)); 1637 if (ret < 0) 1638 return ret; 1639 1640 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1641 if (ret < 0) 1642 return ret; 1643 hdcp->is_paired = true; 1644 } 1645 1646 return 0; 1647 } 1648 1649 static int hdcp2_locality_check(struct intel_connector *connector) 1650 { 1651 struct intel_hdcp *hdcp = &connector->hdcp; 1652 union { 1653 struct hdcp2_lc_init lc_init; 1654 struct hdcp2_lc_send_lprime send_lprime; 1655 } msgs; 1656 const struct intel_hdcp_shim *shim = hdcp->shim; 1657 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1658 1659 for (i = 0; i < tries; i++) { 1660 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1661 if (ret < 0) 1662 continue; 1663 1664 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1665 sizeof(msgs.lc_init)); 1666 if (ret < 0) 1667 continue; 1668 1669 ret = shim->read_2_2_msg(connector, 1670 HDCP_2_2_LC_SEND_LPRIME, 1671 &msgs.send_lprime, 1672 sizeof(msgs.send_lprime)); 1673 if (ret < 0) 1674 continue; 1675 1676 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1677 if (!ret) 1678 break; 1679 } 1680 1681 return ret; 1682 } 1683 1684 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1685 { 1686 struct intel_hdcp *hdcp = &connector->hdcp; 1687 struct hdcp2_ske_send_eks send_eks; 1688 int ret; 1689 1690 ret = hdcp2_prepare_skey(connector, &send_eks); 1691 if (ret < 0) 1692 return ret; 1693 1694 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1695 sizeof(send_eks)); 1696 if (ret < 0) 1697 return ret; 1698 1699 return 0; 1700 } 1701 1702 static 1703 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1704 { 1705 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1706 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1707 struct intel_hdcp *hdcp = &connector->hdcp; 1708 union { 1709 struct hdcp2_rep_stream_manage stream_manage; 1710 struct hdcp2_rep_stream_ready stream_ready; 1711 } msgs; 1712 const struct intel_hdcp_shim *shim = hdcp->shim; 1713 int ret, streams_size_delta, i; 1714 1715 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1716 return -ERANGE; 1717 1718 /* Prepare RepeaterAuth_Stream_Manage msg */ 1719 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1720 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1721 1722 msgs.stream_manage.k = cpu_to_be16(data->k); 1723 1724 for (i = 0; i < data->k; i++) { 1725 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1726 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1727 } 1728 1729 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1730 sizeof(struct hdcp2_streamid_type); 1731 /* Send it to Repeater */ 1732 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1733 sizeof(msgs.stream_manage) - streams_size_delta); 1734 if (ret < 0) 1735 goto out; 1736 1737 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1738 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1739 if (ret < 0) 1740 goto out; 1741 1742 data->seq_num_m = hdcp->seq_num_m; 1743 1744 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1745 1746 out: 1747 hdcp->seq_num_m++; 1748 1749 return ret; 1750 } 1751 1752 static 1753 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1754 { 1755 struct intel_display *display = to_intel_display(connector); 1756 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1757 struct intel_hdcp *hdcp = &connector->hdcp; 1758 union { 1759 struct hdcp2_rep_send_receiverid_list recvid_list; 1760 struct hdcp2_rep_send_ack rep_ack; 1761 } msgs; 1762 const struct intel_hdcp_shim *shim = hdcp->shim; 1763 u32 seq_num_v, device_cnt; 1764 u8 *rx_info; 1765 int ret; 1766 1767 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1768 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1769 if (ret < 0) 1770 return ret; 1771 1772 rx_info = msgs.recvid_list.rx_info; 1773 1774 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1775 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1776 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1777 return -EINVAL; 1778 } 1779 1780 /* 1781 * MST topology is not Type 1 capable if it contains a downstream 1782 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1783 */ 1784 dig_port->hdcp.mst_type1_capable = 1785 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1786 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1787 1788 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1789 drm_dbg_kms(display->drm, 1790 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1791 return -EINVAL; 1792 } 1793 1794 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1795 seq_num_v = 1796 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1797 1798 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1799 drm_dbg_kms(display->drm, 1800 "Non zero Seq_num_v at first RecvId_List msg\n"); 1801 return -EINVAL; 1802 } 1803 1804 if (hdcp->hdcp2_encrypted && seq_num_v <= hdcp->seq_num_v) { 1805 /* Reauthenticate on Seq_num_v repeat or rollover */ 1806 drm_dbg_kms(display->drm, "Seq_num_v %s\n", 1807 seq_num_v == hdcp->seq_num_v ? "repeat" : "rollover"); 1808 return -EINVAL; 1809 } 1810 1811 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1812 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1813 if (drm_hdcp_check_ksvs_revoked(display->drm, 1814 msgs.recvid_list.receiver_ids, 1815 device_cnt) > 0) { 1816 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1817 return -EPERM; 1818 } 1819 1820 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1821 &msgs.recvid_list, 1822 &msgs.rep_ack); 1823 if (ret < 0) 1824 return ret; 1825 1826 hdcp->seq_num_v = seq_num_v; 1827 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1828 sizeof(msgs.rep_ack)); 1829 if (ret < 0) 1830 return ret; 1831 1832 return 0; 1833 } 1834 1835 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1836 { 1837 struct intel_display *display = to_intel_display(connector); 1838 struct intel_hdcp *hdcp = &connector->hdcp; 1839 const struct intel_hdcp_shim *shim = hdcp->shim; 1840 int ret; 1841 1842 ret = hdcp2_authentication_key_exchange(connector); 1843 if (ret < 0) { 1844 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1845 return ret; 1846 } 1847 1848 ret = hdcp2_locality_check(connector); 1849 if (ret < 0) { 1850 drm_dbg_kms(display->drm, 1851 "Locality Check failed. Err : %d\n", ret); 1852 return ret; 1853 } 1854 1855 ret = hdcp2_session_key_exchange(connector); 1856 if (ret < 0) { 1857 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1858 return ret; 1859 } 1860 1861 if (shim->config_stream_type) { 1862 ret = shim->config_stream_type(connector, 1863 hdcp->is_repeater, 1864 hdcp->content_type); 1865 if (ret < 0) 1866 return ret; 1867 } 1868 1869 if (hdcp->is_repeater) { 1870 ret = hdcp2_authenticate_repeater_topology(connector); 1871 if (ret < 0) { 1872 drm_dbg_kms(display->drm, 1873 "Repeater Auth Failed. Err: %d\n", ret); 1874 return ret; 1875 } 1876 } 1877 1878 return ret; 1879 } 1880 1881 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1882 { 1883 struct intel_display *display = to_intel_display(connector); 1884 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1885 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1886 struct intel_hdcp *hdcp = &connector->hdcp; 1887 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1888 enum port port = dig_port->base.port; 1889 int ret = 0; 1890 1891 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1892 LINK_ENCRYPTION_STATUS)) { 1893 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1894 connector->base.base.id, connector->base.name); 1895 ret = -EPERM; 1896 goto link_recover; 1897 } 1898 1899 if (hdcp->shim->stream_2_2_encryption) { 1900 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1901 if (ret) { 1902 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1903 connector->base.base.id, connector->base.name); 1904 return ret; 1905 } 1906 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1907 transcoder_name(hdcp->stream_transcoder)); 1908 } 1909 1910 return 0; 1911 1912 link_recover: 1913 if (hdcp2_deauthenticate_port(connector) < 0) 1914 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1915 1916 dig_port->hdcp.auth_status = false; 1917 data->k = 0; 1918 1919 return ret; 1920 } 1921 1922 static int hdcp2_enable_encryption(struct intel_connector *connector) 1923 { 1924 struct intel_display *display = to_intel_display(connector); 1925 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1926 struct intel_hdcp *hdcp = &connector->hdcp; 1927 enum port port = dig_port->base.port; 1928 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1929 int ret; 1930 1931 drm_WARN_ON(display->drm, 1932 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1933 LINK_ENCRYPTION_STATUS); 1934 if (hdcp->shim->toggle_signalling) { 1935 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1936 true); 1937 if (ret) { 1938 drm_err(display->drm, 1939 "Failed to enable HDCP signalling. %d\n", 1940 ret); 1941 return ret; 1942 } 1943 } 1944 1945 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1946 LINK_AUTH_STATUS) 1947 /* Link is Authenticated. Now set for Encryption */ 1948 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1949 0, CTL_LINK_ENCRYPTION_REQ); 1950 1951 ret = intel_de_wait_for_set_ms(display, 1952 HDCP2_STATUS(display, cpu_transcoder, port), 1953 LINK_ENCRYPTION_STATUS, 1954 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1955 dig_port->hdcp.auth_status = true; 1956 1957 return ret; 1958 } 1959 1960 static int hdcp2_disable_encryption(struct intel_connector *connector) 1961 { 1962 struct intel_display *display = to_intel_display(connector); 1963 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1964 struct intel_hdcp *hdcp = &connector->hdcp; 1965 enum port port = dig_port->base.port; 1966 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1967 int ret; 1968 1969 drm_WARN_ON(display->drm, 1970 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1971 LINK_ENCRYPTION_STATUS)); 1972 1973 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1974 CTL_LINK_ENCRYPTION_REQ, 0); 1975 1976 ret = intel_de_wait_for_clear_ms(display, 1977 HDCP2_STATUS(display, cpu_transcoder, port), 1978 LINK_ENCRYPTION_STATUS, 1979 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1980 if (ret == -ETIMEDOUT) 1981 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1982 1983 if (hdcp->shim->toggle_signalling) { 1984 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1985 false); 1986 if (ret) { 1987 drm_err(display->drm, 1988 "Failed to disable HDCP signalling. %d\n", 1989 ret); 1990 return ret; 1991 } 1992 } 1993 1994 return ret; 1995 } 1996 1997 static int 1998 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1999 { 2000 struct intel_display *display = to_intel_display(connector); 2001 int i, tries = 3, ret; 2002 2003 if (!connector->hdcp.is_repeater) 2004 return 0; 2005 2006 for (i = 0; i < tries; i++) { 2007 ret = _hdcp2_propagate_stream_management_info(connector); 2008 if (!ret) 2009 break; 2010 2011 /* Lets restart the auth incase of seq_num_m roll over */ 2012 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2013 drm_dbg_kms(display->drm, 2014 "seq_num_m roll over.(%d)\n", ret); 2015 break; 2016 } 2017 2018 drm_dbg_kms(display->drm, 2019 "HDCP2 stream management %d of %d Failed.(%d)\n", 2020 i + 1, tries, ret); 2021 } 2022 2023 return ret; 2024 } 2025 2026 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2027 struct intel_connector *connector) 2028 { 2029 struct intel_display *display = to_intel_display(connector); 2030 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2031 int ret = 0, i, tries = 3; 2032 2033 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2034 ret = hdcp2_authenticate_sink(connector); 2035 if (!ret) { 2036 ret = intel_hdcp_prepare_streams(state, connector); 2037 if (ret) { 2038 drm_dbg_kms(display->drm, 2039 "Prepare stream failed.(%d)\n", 2040 ret); 2041 break; 2042 } 2043 2044 ret = hdcp2_propagate_stream_management_info(connector); 2045 if (ret) { 2046 drm_dbg_kms(display->drm, 2047 "Stream management failed.(%d)\n", 2048 ret); 2049 break; 2050 } 2051 2052 ret = hdcp2_authenticate_port(connector); 2053 if (!ret) 2054 break; 2055 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2056 ret); 2057 } 2058 2059 /* Clearing the mei hdcp session */ 2060 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2061 i + 1, tries, ret); 2062 if (hdcp2_deauthenticate_port(connector) < 0) 2063 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2064 } 2065 2066 if (!ret && !dig_port->hdcp.auth_status) { 2067 /* 2068 * Ensuring the required 200mSec min time interval between 2069 * Session Key Exchange and encryption. 2070 */ 2071 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2072 ret = hdcp2_enable_encryption(connector); 2073 if (ret < 0) { 2074 drm_dbg_kms(display->drm, 2075 "Encryption Enable Failed.(%d)\n", ret); 2076 if (hdcp2_deauthenticate_port(connector) < 0) 2077 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2078 } 2079 } 2080 2081 if (!ret) 2082 ret = hdcp2_enable_stream_encryption(connector); 2083 2084 return ret; 2085 } 2086 2087 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2088 struct intel_connector *connector) 2089 { 2090 struct intel_display *display = to_intel_display(connector); 2091 struct intel_hdcp *hdcp = &connector->hdcp; 2092 int ret; 2093 2094 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2095 connector->base.base.id, connector->base.name, 2096 hdcp->content_type); 2097 2098 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2099 2100 ret = hdcp2_authenticate_and_encrypt(state, connector); 2101 if (ret) { 2102 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2103 hdcp->content_type, ret); 2104 return ret; 2105 } 2106 2107 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2108 connector->base.base.id, connector->base.name, 2109 hdcp->content_type); 2110 2111 hdcp->hdcp2_encrypted = true; 2112 return 0; 2113 } 2114 2115 static int 2116 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2117 { 2118 struct intel_display *display = to_intel_display(connector); 2119 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2120 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2121 struct intel_hdcp *hdcp = &connector->hdcp; 2122 int ret; 2123 2124 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2125 connector->base.base.id, connector->base.name); 2126 2127 if (hdcp->shim->stream_2_2_encryption) { 2128 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2129 if (ret) { 2130 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2131 connector->base.base.id, connector->base.name); 2132 return ret; 2133 } 2134 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2135 transcoder_name(hdcp->stream_transcoder)); 2136 2137 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2138 return 0; 2139 } 2140 2141 ret = hdcp2_disable_encryption(connector); 2142 2143 if (hdcp2_deauthenticate_port(connector) < 0) 2144 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2145 2146 connector->hdcp.hdcp2_encrypted = false; 2147 dig_port->hdcp.auth_status = false; 2148 data->k = 0; 2149 2150 return ret; 2151 } 2152 2153 /* Implements the Link Integrity Check for HDCP2.2 */ 2154 static int intel_hdcp2_check_link(struct intel_connector *connector) 2155 { 2156 struct intel_display *display = to_intel_display(connector); 2157 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2158 struct intel_hdcp *hdcp = &connector->hdcp; 2159 enum port port = dig_port->base.port; 2160 enum transcoder cpu_transcoder; 2161 int ret = 0; 2162 2163 mutex_lock(&hdcp->mutex); 2164 mutex_lock(&dig_port->hdcp.mutex); 2165 cpu_transcoder = hdcp->cpu_transcoder; 2166 2167 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2168 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2169 !hdcp->hdcp2_encrypted) { 2170 ret = -EINVAL; 2171 goto out; 2172 } 2173 2174 if (drm_WARN_ON(display->drm, 2175 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2176 drm_err(display->drm, 2177 "HDCP2.2 link stopped the encryption, %x\n", 2178 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2179 ret = -ENXIO; 2180 _intel_hdcp2_disable(connector, true); 2181 intel_hdcp_update_value(connector, 2182 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2183 true); 2184 goto out; 2185 } 2186 2187 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2188 if (ret == HDCP_LINK_PROTECTED) { 2189 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2190 intel_hdcp_update_value(connector, 2191 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2192 true); 2193 } 2194 goto out; 2195 } 2196 2197 if (ret == HDCP_TOPOLOGY_CHANGE) { 2198 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2199 goto out; 2200 2201 drm_dbg_kms(display->drm, 2202 "HDCP2.2 Downstream topology change\n"); 2203 2204 ret = hdcp2_authenticate_repeater_topology(connector); 2205 if (!ret) { 2206 intel_hdcp_update_value(connector, 2207 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2208 true); 2209 goto out; 2210 } 2211 2212 drm_dbg_kms(display->drm, 2213 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2214 connector->base.base.id, connector->base.name, 2215 ret); 2216 } else { 2217 drm_dbg_kms(display->drm, 2218 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2219 connector->base.base.id, connector->base.name); 2220 } 2221 2222 ret = _intel_hdcp2_disable(connector, true); 2223 if (ret) { 2224 drm_err(display->drm, 2225 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2226 connector->base.base.id, connector->base.name, ret); 2227 intel_hdcp_update_value(connector, 2228 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2229 goto out; 2230 } 2231 2232 intel_hdcp_update_value(connector, 2233 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2234 out: 2235 mutex_unlock(&dig_port->hdcp.mutex); 2236 mutex_unlock(&hdcp->mutex); 2237 return ret; 2238 } 2239 2240 static void intel_hdcp_check_work(struct work_struct *work) 2241 { 2242 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2243 struct intel_hdcp, 2244 check_work); 2245 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2246 struct intel_display *display = to_intel_display(connector); 2247 2248 if (drm_connector_is_unregistered(&connector->base)) 2249 return; 2250 2251 if (!hdcp->force_hdcp14 && !intel_hdcp2_check_link(connector)) 2252 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2253 DRM_HDCP2_CHECK_PERIOD_MS); 2254 else if (!intel_hdcp_check_link(connector)) 2255 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2256 DRM_HDCP_CHECK_PERIOD_MS); 2257 } 2258 2259 static int i915_hdcp_component_bind(struct device *drv_kdev, 2260 struct device *mei_kdev, void *data) 2261 { 2262 struct intel_display *display = to_intel_display(drv_kdev); 2263 2264 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2265 mutex_lock(&display->hdcp.hdcp_mutex); 2266 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2267 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2268 mutex_unlock(&display->hdcp.hdcp_mutex); 2269 2270 return 0; 2271 } 2272 2273 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2274 struct device *mei_kdev, void *data) 2275 { 2276 struct intel_display *display = to_intel_display(drv_kdev); 2277 2278 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2279 mutex_lock(&display->hdcp.hdcp_mutex); 2280 display->hdcp.arbiter = NULL; 2281 mutex_unlock(&display->hdcp.hdcp_mutex); 2282 } 2283 2284 static const struct component_ops i915_hdcp_ops = { 2285 .bind = i915_hdcp_component_bind, 2286 .unbind = i915_hdcp_component_unbind, 2287 }; 2288 2289 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2290 { 2291 switch (port) { 2292 case PORT_A: 2293 return HDCP_DDI_A; 2294 case PORT_B ... PORT_F: 2295 return (enum hdcp_ddi)port; 2296 default: 2297 return HDCP_DDI_INVALID_PORT; 2298 } 2299 } 2300 2301 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2302 { 2303 switch (cpu_transcoder) { 2304 case TRANSCODER_A ... TRANSCODER_D: 2305 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2306 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2307 return HDCP_INVALID_TRANSCODER; 2308 } 2309 } 2310 2311 static int initialize_hdcp_port_data(struct intel_connector *connector, 2312 struct intel_digital_port *dig_port, 2313 const struct intel_hdcp_shim *shim) 2314 { 2315 struct intel_display *display = to_intel_display(connector); 2316 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2317 enum port port = dig_port->base.port; 2318 2319 if (DISPLAY_VER(display) < 12) 2320 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2321 else 2322 /* 2323 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2324 * with zero(INVALID PORT index). 2325 */ 2326 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2327 2328 /* 2329 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2330 * is initialized to zero (invalid transcoder index). This will be 2331 * retained for <Gen12 forever. 2332 */ 2333 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2334 2335 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2336 data->protocol = (u8)shim->protocol; 2337 2338 if (!data->streams) 2339 data->streams = kzalloc_objs(struct hdcp2_streamid_type, 2340 INTEL_NUM_PIPES(display)); 2341 if (!data->streams) { 2342 drm_err(display->drm, "Out of Memory\n"); 2343 return -ENOMEM; 2344 } 2345 2346 return 0; 2347 } 2348 2349 static bool is_hdcp2_supported(struct intel_display *display) 2350 { 2351 if (USE_HDCP_GSC(display)) 2352 return true; 2353 2354 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2355 return false; 2356 2357 return DISPLAY_VER(display) >= 10 || 2358 display->platform.kabylake || 2359 display->platform.coffeelake || 2360 display->platform.cometlake; 2361 } 2362 2363 void intel_hdcp_component_init(struct intel_display *display) 2364 { 2365 int ret; 2366 2367 if (!is_hdcp2_supported(display)) 2368 return; 2369 2370 mutex_lock(&display->hdcp.hdcp_mutex); 2371 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2372 2373 display->hdcp.comp_added = true; 2374 mutex_unlock(&display->hdcp.hdcp_mutex); 2375 if (USE_HDCP_GSC(display)) 2376 ret = intel_hdcp_gsc_init(display); 2377 else 2378 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2379 I915_COMPONENT_HDCP); 2380 2381 if (ret < 0) { 2382 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2383 ret); 2384 mutex_lock(&display->hdcp.hdcp_mutex); 2385 display->hdcp.comp_added = false; 2386 mutex_unlock(&display->hdcp.hdcp_mutex); 2387 return; 2388 } 2389 } 2390 2391 static void intel_hdcp2_init(struct intel_connector *connector, 2392 struct intel_digital_port *dig_port, 2393 const struct intel_hdcp_shim *shim) 2394 { 2395 struct intel_display *display = to_intel_display(connector); 2396 struct intel_hdcp *hdcp = &connector->hdcp; 2397 int ret; 2398 2399 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2400 if (ret) { 2401 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2402 return; 2403 } 2404 2405 hdcp->hdcp2_supported = true; 2406 } 2407 2408 int intel_hdcp_init(struct intel_connector *connector, 2409 struct intel_digital_port *dig_port, 2410 const struct intel_hdcp_shim *shim) 2411 { 2412 struct intel_display *display = to_intel_display(connector); 2413 struct intel_hdcp *hdcp = &connector->hdcp; 2414 int ret; 2415 2416 if (!shim) 2417 return -EINVAL; 2418 2419 if (is_hdcp2_supported(display)) 2420 intel_hdcp2_init(connector, dig_port, shim); 2421 2422 ret = drm_connector_attach_content_protection_property(&connector->base, 2423 hdcp->hdcp2_supported); 2424 if (ret) { 2425 hdcp->hdcp2_supported = false; 2426 kfree(dig_port->hdcp.port_data.streams); 2427 return ret; 2428 } 2429 2430 hdcp->shim = shim; 2431 mutex_init(&hdcp->mutex); 2432 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2433 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2434 init_waitqueue_head(&hdcp->cp_irq_queue); 2435 2436 return 0; 2437 } 2438 2439 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2440 struct intel_encoder *encoder, 2441 const struct intel_crtc_state *pipe_config, 2442 const struct drm_connector_state *conn_state) 2443 { 2444 struct intel_display *display = to_intel_display(encoder); 2445 struct intel_connector *connector = 2446 to_intel_connector(conn_state->connector); 2447 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2448 struct intel_hdcp *hdcp = &connector->hdcp; 2449 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2450 int ret = -EINVAL; 2451 2452 if (!hdcp->shim) 2453 return -ENOENT; 2454 2455 mutex_lock(&hdcp->mutex); 2456 mutex_lock(&dig_port->hdcp.mutex); 2457 drm_WARN_ON(display->drm, 2458 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2459 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2460 2461 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2462 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2463 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2464 } else { 2465 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2466 hdcp->stream_transcoder = INVALID_TRANSCODER; 2467 } 2468 2469 if (DISPLAY_VER(display) >= 12) 2470 dig_port->hdcp.port_data.hdcp_transcoder = 2471 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2472 2473 /* 2474 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2475 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2476 */ 2477 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2478 ret = _intel_hdcp2_enable(state, connector); 2479 if (!ret) 2480 check_link_interval = 2481 DRM_HDCP2_CHECK_PERIOD_MS; 2482 } 2483 2484 if (hdcp->force_hdcp14) 2485 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2486 2487 /* 2488 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2489 * be attempted. 2490 */ 2491 if (ret && intel_hdcp_get_capability(connector) && 2492 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2493 ret = intel_hdcp1_enable(connector); 2494 } 2495 2496 if (!ret) { 2497 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2498 check_link_interval); 2499 intel_hdcp_update_value(connector, 2500 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2501 true); 2502 } 2503 2504 mutex_unlock(&dig_port->hdcp.mutex); 2505 mutex_unlock(&hdcp->mutex); 2506 return ret; 2507 } 2508 2509 void intel_hdcp_enable(struct intel_atomic_state *state, 2510 struct intel_encoder *encoder, 2511 const struct intel_crtc_state *crtc_state, 2512 const struct drm_connector_state *conn_state) 2513 { 2514 struct intel_connector *connector = 2515 to_intel_connector(conn_state->connector); 2516 struct intel_hdcp *hdcp = &connector->hdcp; 2517 2518 /* 2519 * Enable hdcp if it's desired or if userspace is enabled and 2520 * driver set its state to undesired 2521 */ 2522 if (conn_state->content_protection == 2523 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2524 (conn_state->content_protection == 2525 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2526 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2527 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2528 } 2529 2530 int intel_hdcp_disable(struct intel_connector *connector) 2531 { 2532 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2533 struct intel_hdcp *hdcp = &connector->hdcp; 2534 int ret = 0; 2535 2536 if (!hdcp->shim) 2537 return -ENOENT; 2538 2539 mutex_lock(&hdcp->mutex); 2540 mutex_lock(&dig_port->hdcp.mutex); 2541 2542 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2543 goto out; 2544 2545 intel_hdcp_update_value(connector, 2546 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2547 if (hdcp->hdcp2_encrypted) 2548 ret = _intel_hdcp2_disable(connector, false); 2549 else if (hdcp->hdcp_encrypted) 2550 ret = _intel_hdcp_disable(connector); 2551 2552 out: 2553 mutex_unlock(&dig_port->hdcp.mutex); 2554 mutex_unlock(&hdcp->mutex); 2555 cancel_delayed_work_sync(&hdcp->check_work); 2556 return ret; 2557 } 2558 2559 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2560 struct intel_encoder *encoder, 2561 const struct intel_crtc_state *crtc_state, 2562 const struct drm_connector_state *conn_state) 2563 { 2564 struct intel_connector *connector = 2565 to_intel_connector(conn_state->connector); 2566 struct intel_hdcp *hdcp = &connector->hdcp; 2567 bool content_protection_type_changed, desired_and_not_enabled = false; 2568 struct intel_display *display = to_intel_display(connector); 2569 2570 if (!connector->hdcp.shim) 2571 return; 2572 2573 content_protection_type_changed = 2574 (conn_state->hdcp_content_type != hdcp->content_type && 2575 conn_state->content_protection != 2576 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2577 2578 /* 2579 * During the HDCP encryption session if Type change is requested, 2580 * disable the HDCP and re-enable it with new TYPE value. 2581 */ 2582 if (conn_state->content_protection == 2583 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2584 content_protection_type_changed) 2585 intel_hdcp_disable(connector); 2586 2587 /* 2588 * Mark the hdcp state as DESIRED after the hdcp disable of type 2589 * change procedure. 2590 */ 2591 if (content_protection_type_changed) { 2592 mutex_lock(&hdcp->mutex); 2593 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2594 drm_connector_get(&connector->base); 2595 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2596 drm_connector_put(&connector->base); 2597 mutex_unlock(&hdcp->mutex); 2598 } 2599 2600 if (conn_state->content_protection == 2601 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2602 mutex_lock(&hdcp->mutex); 2603 /* Avoid enabling hdcp, if it already ENABLED */ 2604 desired_and_not_enabled = 2605 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2606 mutex_unlock(&hdcp->mutex); 2607 /* 2608 * If HDCP already ENABLED and CP property is DESIRED, schedule 2609 * prop_work to update correct CP property to user space. 2610 */ 2611 if (!desired_and_not_enabled && !content_protection_type_changed) { 2612 drm_connector_get(&connector->base); 2613 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2614 drm_connector_put(&connector->base); 2615 2616 } 2617 } 2618 2619 if (desired_and_not_enabled || content_protection_type_changed) 2620 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2621 } 2622 2623 void intel_hdcp_cancel_works(struct intel_connector *connector) 2624 { 2625 if (!connector->hdcp.shim) 2626 return; 2627 2628 cancel_delayed_work_sync(&connector->hdcp.check_work); 2629 cancel_work_sync(&connector->hdcp.prop_work); 2630 } 2631 2632 void intel_hdcp_component_fini(struct intel_display *display) 2633 { 2634 mutex_lock(&display->hdcp.hdcp_mutex); 2635 if (!display->hdcp.comp_added) { 2636 mutex_unlock(&display->hdcp.hdcp_mutex); 2637 return; 2638 } 2639 2640 display->hdcp.comp_added = false; 2641 mutex_unlock(&display->hdcp.hdcp_mutex); 2642 2643 if (USE_HDCP_GSC(display)) 2644 intel_hdcp_gsc_fini(display); 2645 else 2646 component_del(display->drm->dev, &i915_hdcp_ops); 2647 } 2648 2649 void intel_hdcp_cleanup(struct intel_connector *connector) 2650 { 2651 struct intel_hdcp *hdcp = &connector->hdcp; 2652 2653 if (!hdcp->shim) 2654 return; 2655 2656 /* 2657 * If the connector is registered, it's possible userspace could kick 2658 * off another HDCP enable, which would re-spawn the workers. 2659 */ 2660 drm_WARN_ON(connector->base.dev, 2661 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2662 2663 /* 2664 * Now that the connector is not registered, check_work won't be run, 2665 * but cancel any outstanding instances of it 2666 */ 2667 cancel_delayed_work_sync(&hdcp->check_work); 2668 2669 /* 2670 * We don't cancel prop_work in the same way as check_work since it 2671 * requires connection_mutex which could be held while calling this 2672 * function. Instead, we rely on the connector references grabbed before 2673 * scheduling prop_work to ensure the connector is alive when prop_work 2674 * is run. So if we're in the destroy path (which is where this 2675 * function should be called), we're "guaranteed" that prop_work is not 2676 * active (tl;dr This Should Never Happen). 2677 */ 2678 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2679 2680 mutex_lock(&hdcp->mutex); 2681 hdcp->shim = NULL; 2682 mutex_unlock(&hdcp->mutex); 2683 } 2684 2685 void intel_hdcp_atomic_check(struct drm_connector *connector, 2686 struct drm_connector_state *old_state, 2687 struct drm_connector_state *new_state) 2688 { 2689 u64 old_cp = old_state->content_protection; 2690 u64 new_cp = new_state->content_protection; 2691 struct drm_crtc_state *crtc_state; 2692 2693 if (!new_state->crtc) { 2694 /* 2695 * If the connector is being disabled with CP enabled, mark it 2696 * desired so it's re-enabled when the connector is brought back 2697 */ 2698 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2699 new_state->content_protection = 2700 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2701 return; 2702 } 2703 2704 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2705 new_state->crtc); 2706 /* 2707 * Fix the HDCP uapi content protection state in case of modeset. 2708 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2709 * need to be sent if there is transition from ENABLED->DESIRED. 2710 */ 2711 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2712 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2713 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2714 new_state->content_protection = 2715 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2716 2717 /* 2718 * Nothing to do if the state didn't change, or HDCP was activated since 2719 * the last commit. And also no change in hdcp content type. 2720 */ 2721 if (old_cp == new_cp || 2722 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2723 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2724 if (old_state->hdcp_content_type == 2725 new_state->hdcp_content_type) 2726 return; 2727 } 2728 2729 crtc_state->mode_changed = true; 2730 } 2731 2732 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2733 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2734 { 2735 struct intel_hdcp *hdcp = &connector->hdcp; 2736 struct intel_display *display = to_intel_display(connector); 2737 2738 if (!hdcp->shim) 2739 return; 2740 2741 atomic_inc(&connector->hdcp.cp_irq_count); 2742 wake_up_all(&connector->hdcp.cp_irq_queue); 2743 2744 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0); 2745 } 2746 2747 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2748 bool remote_req) 2749 { 2750 bool hdcp_cap = false, hdcp2_cap = false; 2751 2752 if (!connector->hdcp.shim) { 2753 seq_puts(m, "No Connector Support"); 2754 goto out; 2755 } 2756 2757 if (remote_req) { 2758 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2759 } else { 2760 hdcp_cap = intel_hdcp_get_capability(connector); 2761 hdcp2_cap = intel_hdcp2_get_capability(connector); 2762 } 2763 2764 if (hdcp_cap) 2765 seq_puts(m, "HDCP1.4 "); 2766 if (hdcp2_cap) 2767 seq_puts(m, "HDCP2.2 "); 2768 2769 if (!hdcp_cap && !hdcp2_cap) 2770 seq_puts(m, "None"); 2771 2772 out: 2773 seq_puts(m, "\n"); 2774 } 2775 2776 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2777 { 2778 seq_puts(m, "\tHDCP version: "); 2779 if (connector->mst.dp) { 2780 __intel_hdcp_info(m, connector, true); 2781 seq_puts(m, "\tMST Hub HDCP version: "); 2782 } 2783 __intel_hdcp_info(m, connector, false); 2784 } 2785 2786 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2787 { 2788 struct intel_connector *connector = m->private; 2789 struct intel_display *display = to_intel_display(connector); 2790 int ret; 2791 2792 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2793 if (ret) 2794 return ret; 2795 2796 if (!connector->base.encoder || 2797 connector->base.status != connector_status_connected) { 2798 ret = -ENODEV; 2799 goto out; 2800 } 2801 2802 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2803 connector->base.base.id); 2804 __intel_hdcp_info(m, connector, false); 2805 2806 out: 2807 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2808 2809 return ret; 2810 } 2811 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2812 2813 static ssize_t intel_hdcp_force_14_write(struct file *file, 2814 const char __user *ubuf, 2815 size_t len, loff_t *offp) 2816 { 2817 struct seq_file *m = file->private_data; 2818 struct intel_connector *connector = m->private; 2819 struct intel_hdcp *hdcp = &connector->hdcp; 2820 bool force_hdcp14 = false; 2821 int ret; 2822 2823 if (len == 0) 2824 return 0; 2825 2826 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2827 if (ret < 0) 2828 return ret; 2829 2830 hdcp->force_hdcp14 = force_hdcp14; 2831 *offp += len; 2832 2833 return len; 2834 } 2835 2836 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2837 { 2838 struct intel_connector *connector = m->private; 2839 struct intel_display *display = to_intel_display(connector); 2840 struct intel_encoder *encoder = intel_attached_encoder(connector); 2841 struct intel_hdcp *hdcp = &connector->hdcp; 2842 struct drm_crtc *crtc; 2843 int ret; 2844 2845 if (!encoder) 2846 return -ENODEV; 2847 2848 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2849 if (ret) 2850 return ret; 2851 2852 crtc = connector->base.state->crtc; 2853 if (connector->base.status != connector_status_connected || !crtc) { 2854 ret = -ENODEV; 2855 goto out; 2856 } 2857 2858 seq_printf(m, "%s\n", 2859 str_yes_no(hdcp->force_hdcp14)); 2860 out: 2861 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2862 2863 return ret; 2864 } 2865 2866 static int intel_hdcp_force_14_open(struct inode *inode, 2867 struct file *file) 2868 { 2869 return single_open(file, intel_hdcp_force_14_show, 2870 inode->i_private); 2871 } 2872 2873 static const struct file_operations intel_hdcp_force_14_fops = { 2874 .owner = THIS_MODULE, 2875 .open = intel_hdcp_force_14_open, 2876 .read = seq_read, 2877 .llseek = seq_lseek, 2878 .release = single_release, 2879 .write = intel_hdcp_force_14_write 2880 }; 2881 2882 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2883 { 2884 struct dentry *root = connector->base.debugfs_entry; 2885 int connector_type = connector->base.connector_type; 2886 2887 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2888 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2889 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2890 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2891 connector, &intel_hdcp_sink_capability_fops); 2892 debugfs_create_file("i915_force_hdcp14", 0644, root, 2893 connector, &intel_hdcp_force_14_fops); 2894 } 2895 } 2896