1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/iopoll.h> 15 #include <linux/random.h> 16 17 #include <drm/display/drm_hdcp_helper.h> 18 #include <drm/drm_print.h> 19 #include <drm/intel/i915_component.h> 20 #include <drm/intel/intel_pcode_regs.h> 21 #include <drm/intel/step.h> 22 23 #include "intel_connector.h" 24 #include "intel_de.h" 25 #include "intel_display_jiffies.h" 26 #include "intel_display_power.h" 27 #include "intel_display_power_well.h" 28 #include "intel_display_regs.h" 29 #include "intel_display_rpm.h" 30 #include "intel_display_types.h" 31 #include "intel_dp_mst.h" 32 #include "intel_hdcp.h" 33 #include "intel_hdcp_gsc_message.h" 34 #include "intel_hdcp_regs.h" 35 #include "intel_hdcp_shim.h" 36 #include "intel_parent.h" 37 38 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 39 40 #define KEY_LOAD_TRIES 5 41 #define HDCP2_LC_RETRY_CNT 3 42 43 static void 44 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 45 struct intel_hdcp *hdcp, 46 bool enable) 47 { 48 struct intel_display *display = to_intel_display(encoder); 49 intel_reg_t rekey_reg; 50 u32 rekey_bit = 0; 51 52 /* Here we assume HDMI is in TMDS mode of operation */ 53 if (!intel_encoder_is_hdmi(encoder)) 54 return; 55 56 if (DISPLAY_VER(display) >= 30) { 57 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 58 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 59 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 60 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 61 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 62 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 63 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 64 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 65 rekey_bit = HDCP_LINE_REKEY_DISABLE; 66 } 67 68 if (rekey_bit) 69 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 70 } 71 72 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 73 struct intel_connector *connector) 74 { 75 struct intel_display *display = to_intel_display(state); 76 struct drm_dp_mst_topology_mgr *mgr; 77 struct drm_dp_mst_atomic_payload *payload; 78 struct drm_dp_mst_topology_state *mst_state; 79 80 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 81 if (!connector->mst.port) 82 return 0; 83 84 mgr = connector->mst.port->mgr; 85 mst_state = drm_atomic_get_new_mst_topology_state(&state->base, mgr); 86 if (!mst_state) { 87 drm_dbg_kms(display->drm, "MST topology still not created\n"); 88 return 0; 89 } 90 91 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 92 if (!payload) { 93 drm_dbg_kms(display->drm, "MST Payload not present\n"); 94 return 0; 95 } 96 97 return payload->vcpi; 98 } 99 100 /* 101 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 102 * content_type for all streams in DP MST topology because security f/w doesn't 103 * have any provision to mark content_type for each stream separately, it marks 104 * all available streams with the content_type proivided at the time of port 105 * authentication. This may prohibit the userspace to use type1 content on 106 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 107 * DP MST topology. Though it is not compulsory, security fw should change its 108 * policy to mark different content_types for different streams. 109 */ 110 static int 111 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 112 struct intel_digital_port *dig_port) 113 { 114 struct intel_display *display = to_intel_display(state); 115 struct drm_connector_list_iter conn_iter; 116 struct drm_connector_state *new_conn_state; 117 struct intel_digital_port *conn_dig_port; 118 struct intel_connector *connector; 119 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 120 bool enforce_type0 = false; 121 int k; 122 123 if (dig_port->hdcp.auth_status) 124 return 0; 125 126 data->k = 0; 127 128 if (!dig_port->hdcp.mst_type1_capable) 129 enforce_type0 = true; 130 131 drm_connector_list_iter_begin(display->drm, &conn_iter); 132 for_each_intel_connector_iter(connector, &conn_iter) { 133 if (connector->base.status == connector_status_disconnected) 134 continue; 135 136 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 137 continue; 138 139 conn_dig_port = intel_attached_dig_port(connector); 140 if (conn_dig_port != dig_port) 141 continue; 142 143 new_conn_state = drm_atomic_get_new_connector_state(&state->base, 144 &connector->base); 145 if (!new_conn_state || !new_conn_state->crtc) 146 continue; 147 148 data->streams[data->k].stream_id = 149 intel_conn_to_vcpi(state, connector); 150 data->k++; 151 152 /* if there is only one active stream */ 153 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 154 break; 155 } 156 drm_connector_list_iter_end(&conn_iter); 157 158 if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0)) 159 return -EINVAL; 160 161 /* 162 * Apply common protection level across all streams in DP MST Topology. 163 * Use highest supported content type for all streams in DP MST Topology. 164 */ 165 for (k = 0; k < data->k; k++) 166 data->streams[k].stream_type = 167 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 168 169 return 0; 170 } 171 172 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 173 struct intel_connector *connector) 174 { 175 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 176 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 177 struct intel_hdcp *hdcp = &connector->hdcp; 178 179 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 180 return intel_hdcp_required_content_stream(state, dig_port); 181 182 data->k = 1; 183 data->streams[0].stream_id = 0; 184 data->streams[0].stream_type = hdcp->content_type; 185 186 return 0; 187 } 188 189 static 190 bool intel_hdcp_is_ksv_valid(u8 *ksv) 191 { 192 int i, ones = 0; 193 /* KSV has 20 1's and 20 0's */ 194 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 195 ones += hweight8(ksv[i]); 196 if (ones != 20) 197 return false; 198 199 return true; 200 } 201 202 static 203 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 204 const struct intel_hdcp_shim *shim, u8 *bksv) 205 { 206 struct intel_display *display = to_intel_display(dig_port); 207 int ret, i, tries = 2; 208 209 /* HDCP spec states that we must retry the bksv if it is invalid */ 210 for (i = 0; i < tries; i++) { 211 ret = shim->read_bksv(dig_port, bksv); 212 if (ret) 213 return ret; 214 if (intel_hdcp_is_ksv_valid(bksv)) 215 break; 216 } 217 if (i == tries) { 218 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 219 return -ENODEV; 220 } 221 222 return 0; 223 } 224 225 /* Is HDCP1.4 capable on Platform and Sink */ 226 static bool intel_hdcp_get_capability(struct intel_connector *connector) 227 { 228 struct intel_digital_port *dig_port; 229 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 230 bool capable = false; 231 u8 bksv[5]; 232 233 if (!intel_attached_encoder(connector)) 234 return capable; 235 236 dig_port = intel_attached_dig_port(connector); 237 238 if (!shim) 239 return capable; 240 241 if (shim->hdcp_get_capability) { 242 shim->hdcp_get_capability(dig_port, &capable); 243 } else { 244 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 245 capable = true; 246 } 247 248 return capable; 249 } 250 251 /* 252 * Check if the source has all the building blocks ready to make 253 * HDCP 2.2 work 254 */ 255 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 256 { 257 struct intel_display *display = to_intel_display(connector); 258 struct intel_hdcp *hdcp = &connector->hdcp; 259 260 /* I915 support for HDCP2.2 */ 261 if (!hdcp->hdcp2_supported) 262 return false; 263 264 /* If MTL+ make sure gsc is loaded and proxy is setup */ 265 if (USE_HDCP_GSC(display)) { 266 if (!intel_parent_hdcp_gsc_check_status(display)) 267 return false; 268 } 269 270 /* MEI/GSC interface is solid depending on which is used */ 271 mutex_lock(&display->hdcp.hdcp_mutex); 272 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 273 mutex_unlock(&display->hdcp.hdcp_mutex); 274 return false; 275 } 276 mutex_unlock(&display->hdcp.hdcp_mutex); 277 278 return true; 279 } 280 281 /* Is HDCP2.2 capable on Platform and Sink */ 282 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 283 { 284 struct intel_hdcp *hdcp = &connector->hdcp; 285 bool capable = false; 286 287 if (!intel_hdcp2_prerequisite(connector)) 288 return false; 289 290 /* Sink's capability for HDCP2.2 */ 291 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 292 293 return capable; 294 } 295 296 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 297 bool *hdcp_capable, 298 bool *hdcp2_capable) 299 { 300 struct intel_hdcp *hdcp = &connector->hdcp; 301 302 if (!hdcp->shim->get_remote_hdcp_capability) 303 return; 304 305 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 306 hdcp2_capable); 307 308 if (!intel_hdcp2_prerequisite(connector)) 309 *hdcp2_capable = false; 310 } 311 312 static bool intel_hdcp_in_use(struct intel_display *display, 313 enum transcoder cpu_transcoder, enum port port) 314 { 315 return intel_de_read(display, 316 HDCP_STATUS(display, cpu_transcoder, port)) & 317 HDCP_STATUS_ENC; 318 } 319 320 static bool intel_hdcp2_in_use(struct intel_display *display, 321 enum transcoder cpu_transcoder, enum port port) 322 { 323 return intel_de_read(display, 324 HDCP2_STATUS(display, cpu_transcoder, port)) & 325 LINK_ENCRYPTION_STATUS; 326 } 327 328 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 329 const struct intel_hdcp_shim *shim) 330 { 331 int ret, read_ret; 332 bool ksv_ready; 333 334 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 335 ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), 336 read_ret || ksv_ready, 337 100 * 1000, 5 * 1000 * 1000, false); 338 if (ret) 339 return ret; 340 if (read_ret) 341 return read_ret; 342 343 return 0; 344 } 345 346 static bool hdcp_key_loadable(struct intel_display *display) 347 { 348 enum i915_power_well_id id; 349 bool enabled = false; 350 351 /* 352 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 353 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 354 */ 355 if (display->platform.haswell || display->platform.broadwell) 356 id = HSW_DISP_PW_GLOBAL; 357 else 358 id = SKL_DISP_PW_1; 359 360 /* PG1 (power well #1) needs to be enabled */ 361 with_intel_display_rpm(display) 362 enabled = intel_display_power_well_is_enabled(display, id); 363 364 /* 365 * Another req for hdcp key loadability is enabled state of pll for 366 * cdclk. Without active crtc we won't land here. So we are assuming that 367 * cdclk is already on. 368 */ 369 370 return enabled; 371 } 372 373 static void intel_hdcp_clear_keys(struct intel_display *display) 374 { 375 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 376 intel_de_write(display, HDCP_KEY_STATUS, 377 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 378 } 379 380 static int intel_hdcp_load_keys(struct intel_display *display) 381 { 382 int ret; 383 u32 val; 384 385 val = intel_de_read(display, HDCP_KEY_STATUS); 386 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 387 return 0; 388 389 /* 390 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 391 * out of reset. So if Key is not already loaded, its an error state. 392 */ 393 if (display->platform.haswell || display->platform.broadwell) 394 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 395 return -ENXIO; 396 397 /* 398 * Initiate loading the HDCP key from fuses. 399 * 400 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 401 * version 9 platforms (minus BXT) differ in the key load trigger 402 * process from other platforms. These platforms use the GT Driver 403 * Mailbox interface. 404 */ 405 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 406 ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1); 407 if (ret) { 408 drm_err(display->drm, 409 "Failed to initiate HDCP key load (%d)\n", 410 ret); 411 return ret; 412 } 413 } else { 414 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 415 } 416 417 /* Wait for the keys to load (500us) */ 418 ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE, 419 HDCP_KEY_LOAD_DONE, 1, &val); 420 if (ret) 421 return ret; 422 else if (!(val & HDCP_KEY_LOAD_STATUS)) 423 return -ENXIO; 424 425 /* Send Aksv over to PCH display for use in authentication */ 426 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 427 428 return 0; 429 } 430 431 /* Returns updated SHA-1 index */ 432 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 433 { 434 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 435 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 436 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 437 return -ETIMEDOUT; 438 } 439 return 0; 440 } 441 442 static 443 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 444 enum transcoder cpu_transcoder, enum port port) 445 { 446 if (DISPLAY_VER(display) >= 12) { 447 switch (cpu_transcoder) { 448 case TRANSCODER_A: 449 return HDCP_TRANSA_REP_PRESENT | 450 HDCP_TRANSA_SHA1_M0; 451 case TRANSCODER_B: 452 return HDCP_TRANSB_REP_PRESENT | 453 HDCP_TRANSB_SHA1_M0; 454 case TRANSCODER_C: 455 return HDCP_TRANSC_REP_PRESENT | 456 HDCP_TRANSC_SHA1_M0; 457 case TRANSCODER_D: 458 return HDCP_TRANSD_REP_PRESENT | 459 HDCP_TRANSD_SHA1_M0; 460 default: 461 drm_err(display->drm, "Unknown transcoder %d\n", 462 cpu_transcoder); 463 return 0; 464 } 465 } 466 467 switch (port) { 468 case PORT_A: 469 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 470 case PORT_B: 471 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 472 case PORT_C: 473 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 474 case PORT_D: 475 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 476 case PORT_E: 477 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 478 default: 479 drm_err(display->drm, "Unknown port %d\n", port); 480 return 0; 481 } 482 } 483 484 static 485 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 486 const struct intel_hdcp_shim *shim, 487 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 488 { 489 struct intel_display *display = to_intel_display(connector); 490 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 491 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 492 enum port port = dig_port->base.port; 493 u32 vprime, sha_text, sha_leftovers, rep_ctl; 494 int ret, i, j, sha_idx; 495 496 /* Process V' values from the receiver */ 497 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 498 ret = shim->read_v_prime_part(dig_port, i, &vprime); 499 if (ret) 500 return ret; 501 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 502 } 503 504 /* 505 * We need to write the concatenation of all device KSVs, BINFO (DP) || 506 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 507 * stream is written via the HDCP_SHA_TEXT register in 32-bit 508 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 509 * index will keep track of our progress through the 64 bytes as well as 510 * helping us work the 40-bit KSVs through our 32-bit register. 511 * 512 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 513 */ 514 sha_idx = 0; 515 sha_text = 0; 516 sha_leftovers = 0; 517 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 518 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 519 for (i = 0; i < num_downstream; i++) { 520 unsigned int sha_empty; 521 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 522 523 /* Fill up the empty slots in sha_text and write it out */ 524 sha_empty = sizeof(sha_text) - sha_leftovers; 525 for (j = 0; j < sha_empty; j++) { 526 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 527 sha_text |= ksv[j] << off; 528 } 529 530 ret = intel_write_sha_text(display, sha_text); 531 if (ret < 0) 532 return ret; 533 534 /* Programming guide writes this every 64 bytes */ 535 sha_idx += sizeof(sha_text); 536 if (!(sha_idx % 64)) 537 intel_de_write(display, HDCP_REP_CTL, 538 rep_ctl | HDCP_SHA1_TEXT_32); 539 540 /* Store the leftover bytes from the ksv in sha_text */ 541 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 542 sha_text = 0; 543 for (j = 0; j < sha_leftovers; j++) 544 sha_text |= ksv[sha_empty + j] << 545 ((sizeof(sha_text) - j - 1) * 8); 546 547 /* 548 * If we still have room in sha_text for more data, continue. 549 * Otherwise, write it out immediately. 550 */ 551 if (sizeof(sha_text) > sha_leftovers) 552 continue; 553 554 ret = intel_write_sha_text(display, sha_text); 555 if (ret < 0) 556 return ret; 557 sha_leftovers = 0; 558 sha_text = 0; 559 sha_idx += sizeof(sha_text); 560 } 561 562 /* 563 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 564 * bytes are leftover from the last ksv, we might be able to fit them 565 * all in sha_text (first 2 cases), or we might need to split them up 566 * into 2 writes (last 2 cases). 567 */ 568 if (sha_leftovers == 0) { 569 /* Write 16 bits of text, 16 bits of M0 */ 570 intel_de_write(display, HDCP_REP_CTL, 571 rep_ctl | HDCP_SHA1_TEXT_16); 572 ret = intel_write_sha_text(display, 573 bstatus[0] << 8 | bstatus[1]); 574 if (ret < 0) 575 return ret; 576 sha_idx += sizeof(sha_text); 577 578 /* Write 32 bits of M0 */ 579 intel_de_write(display, HDCP_REP_CTL, 580 rep_ctl | HDCP_SHA1_TEXT_0); 581 ret = intel_write_sha_text(display, 0); 582 if (ret < 0) 583 return ret; 584 sha_idx += sizeof(sha_text); 585 586 /* Write 16 bits of M0 */ 587 intel_de_write(display, HDCP_REP_CTL, 588 rep_ctl | HDCP_SHA1_TEXT_16); 589 ret = intel_write_sha_text(display, 0); 590 if (ret < 0) 591 return ret; 592 sha_idx += sizeof(sha_text); 593 594 } else if (sha_leftovers == 1) { 595 /* Write 24 bits of text, 8 bits of M0 */ 596 intel_de_write(display, HDCP_REP_CTL, 597 rep_ctl | HDCP_SHA1_TEXT_24); 598 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 599 /* Only 24-bits of data, must be in the LSB */ 600 sha_text = (sha_text & 0xffffff00) >> 8; 601 ret = intel_write_sha_text(display, sha_text); 602 if (ret < 0) 603 return ret; 604 sha_idx += sizeof(sha_text); 605 606 /* Write 32 bits of M0 */ 607 intel_de_write(display, HDCP_REP_CTL, 608 rep_ctl | HDCP_SHA1_TEXT_0); 609 ret = intel_write_sha_text(display, 0); 610 if (ret < 0) 611 return ret; 612 sha_idx += sizeof(sha_text); 613 614 /* Write 24 bits of M0 */ 615 intel_de_write(display, HDCP_REP_CTL, 616 rep_ctl | HDCP_SHA1_TEXT_8); 617 ret = intel_write_sha_text(display, 0); 618 if (ret < 0) 619 return ret; 620 sha_idx += sizeof(sha_text); 621 622 } else if (sha_leftovers == 2) { 623 /* Write 32 bits of text */ 624 intel_de_write(display, HDCP_REP_CTL, 625 rep_ctl | HDCP_SHA1_TEXT_32); 626 sha_text |= bstatus[0] << 8 | bstatus[1]; 627 ret = intel_write_sha_text(display, sha_text); 628 if (ret < 0) 629 return ret; 630 sha_idx += sizeof(sha_text); 631 632 /* Write 64 bits of M0 */ 633 intel_de_write(display, HDCP_REP_CTL, 634 rep_ctl | HDCP_SHA1_TEXT_0); 635 for (i = 0; i < 2; i++) { 636 ret = intel_write_sha_text(display, 0); 637 if (ret < 0) 638 return ret; 639 sha_idx += sizeof(sha_text); 640 } 641 642 /* 643 * Terminate the SHA-1 stream by hand. For the other leftover 644 * cases this is appended by the hardware. 645 */ 646 intel_de_write(display, HDCP_REP_CTL, 647 rep_ctl | HDCP_SHA1_TEXT_32); 648 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 649 ret = intel_write_sha_text(display, sha_text); 650 if (ret < 0) 651 return ret; 652 sha_idx += sizeof(sha_text); 653 } else if (sha_leftovers == 3) { 654 /* Write 32 bits of text (filled from LSB) */ 655 intel_de_write(display, HDCP_REP_CTL, 656 rep_ctl | HDCP_SHA1_TEXT_32); 657 sha_text |= bstatus[0]; 658 ret = intel_write_sha_text(display, sha_text); 659 if (ret < 0) 660 return ret; 661 sha_idx += sizeof(sha_text); 662 663 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 664 intel_de_write(display, HDCP_REP_CTL, 665 rep_ctl | HDCP_SHA1_TEXT_8); 666 ret = intel_write_sha_text(display, bstatus[1]); 667 if (ret < 0) 668 return ret; 669 sha_idx += sizeof(sha_text); 670 671 /* Write 32 bits of M0 */ 672 intel_de_write(display, HDCP_REP_CTL, 673 rep_ctl | HDCP_SHA1_TEXT_0); 674 ret = intel_write_sha_text(display, 0); 675 if (ret < 0) 676 return ret; 677 sha_idx += sizeof(sha_text); 678 679 /* Write 8 bits of M0 */ 680 intel_de_write(display, HDCP_REP_CTL, 681 rep_ctl | HDCP_SHA1_TEXT_24); 682 ret = intel_write_sha_text(display, 0); 683 if (ret < 0) 684 return ret; 685 sha_idx += sizeof(sha_text); 686 } else { 687 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 688 sha_leftovers); 689 return -EINVAL; 690 } 691 692 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 693 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 694 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 695 ret = intel_write_sha_text(display, 0); 696 if (ret < 0) 697 return ret; 698 sha_idx += sizeof(sha_text); 699 } 700 701 /* 702 * Last write gets the length of the concatenation in bits. That is: 703 * - 5 bytes per device 704 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 705 */ 706 sha_text = (num_downstream * 5 + 10) * 8; 707 ret = intel_write_sha_text(display, sha_text); 708 if (ret < 0) 709 return ret; 710 711 /* Tell the HW we're done with the hash and wait for it to ACK */ 712 intel_de_write(display, HDCP_REP_CTL, 713 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 714 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, 715 HDCP_SHA1_COMPLETE, 1)) { 716 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 717 return -ETIMEDOUT; 718 } 719 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 720 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 721 return -ENXIO; 722 } 723 724 return 0; 725 } 726 727 /* Implements Part 2 of the HDCP authorization procedure */ 728 static 729 int intel_hdcp_auth_downstream(struct intel_connector *connector) 730 { 731 struct intel_display *display = to_intel_display(connector); 732 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 733 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 734 u8 bstatus[2], num_downstream, *ksv_fifo; 735 int ret, i, tries = 3; 736 737 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 738 if (ret) { 739 drm_dbg_kms(display->drm, 740 "KSV list failed to become ready (%d)\n", ret); 741 return ret; 742 } 743 744 ret = shim->read_bstatus(dig_port, bstatus); 745 if (ret) 746 return ret; 747 748 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 749 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 750 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 751 return -EPERM; 752 } 753 754 /* 755 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 756 * the HDCP encryption. That implies that repeater can't have its own 757 * display. As there is no consumption of encrypted content in the 758 * repeater with 0 downstream devices, we are failing the 759 * authentication. 760 */ 761 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 762 if (num_downstream == 0) { 763 drm_dbg_kms(display->drm, 764 "Repeater with zero downstream devices\n"); 765 return -EINVAL; 766 } 767 768 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 769 if (!ksv_fifo) { 770 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 771 return -ENOMEM; 772 } 773 774 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 775 if (ret) 776 goto err; 777 778 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 779 num_downstream) > 0) { 780 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 781 ret = -EPERM; 782 goto err; 783 } 784 785 /* 786 * When V prime mismatches, DP Spec mandates re-read of 787 * V prime atleast twice. 788 */ 789 for (i = 0; i < tries; i++) { 790 ret = intel_hdcp_validate_v_prime(connector, shim, 791 ksv_fifo, num_downstream, 792 bstatus); 793 if (!ret) 794 break; 795 } 796 797 if (i == tries) { 798 drm_dbg_kms(display->drm, 799 "V Prime validation failed.(%d)\n", ret); 800 goto err; 801 } 802 803 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 804 num_downstream); 805 ret = 0; 806 err: 807 kfree(ksv_fifo); 808 return ret; 809 } 810 811 /* Implements Part 1 of the HDCP authorization procedure */ 812 static int intel_hdcp_auth(struct intel_connector *connector) 813 { 814 struct intel_display *display = to_intel_display(connector); 815 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 816 struct intel_hdcp *hdcp = &connector->hdcp; 817 const struct intel_hdcp_shim *shim = hdcp->shim; 818 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 819 enum port port = dig_port->base.port; 820 unsigned long r0_prime_gen_start; 821 int ret, i, tries = 2; 822 u32 val; 823 union { 824 u32 reg[2]; 825 u8 shim[DRM_HDCP_AN_LEN]; 826 } an; 827 union { 828 u32 reg[2]; 829 u8 shim[DRM_HDCP_KSV_LEN]; 830 } bksv; 831 union { 832 u32 reg; 833 u8 shim[DRM_HDCP_RI_LEN]; 834 } ri; 835 bool repeater_present, hdcp_capable; 836 837 /* 838 * Detects whether the display is HDCP capable. Although we check for 839 * valid Bksv below, the HDCP over DP spec requires that we check 840 * whether the display supports HDCP before we write An. For HDMI 841 * displays, this is not necessary. 842 */ 843 if (shim->hdcp_get_capability) { 844 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 845 if (ret) 846 return ret; 847 if (!hdcp_capable) { 848 drm_dbg_kms(display->drm, 849 "Panel is not HDCP capable\n"); 850 return -EINVAL; 851 } 852 } 853 854 /* Initialize An with 2 random values and acquire it */ 855 for (i = 0; i < 2; i++) 856 intel_de_write(display, 857 HDCP_ANINIT(display, cpu_transcoder, port), 858 get_random_u32()); 859 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 860 HDCP_CONF_CAPTURE_AN); 861 862 /* Wait for An to be acquired */ 863 if (intel_de_wait_for_set_ms(display, 864 HDCP_STATUS(display, cpu_transcoder, port), 865 HDCP_STATUS_AN_READY, 1)) { 866 drm_err(display->drm, "Timed out waiting for An\n"); 867 return -ETIMEDOUT; 868 } 869 870 an.reg[0] = intel_de_read(display, 871 HDCP_ANLO(display, cpu_transcoder, port)); 872 an.reg[1] = intel_de_read(display, 873 HDCP_ANHI(display, cpu_transcoder, port)); 874 ret = shim->write_an_aksv(dig_port, an.shim); 875 if (ret) 876 return ret; 877 878 r0_prime_gen_start = jiffies; 879 880 memset(&bksv, 0, sizeof(bksv)); 881 882 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 883 if (ret < 0) 884 return ret; 885 886 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 887 drm_err(display->drm, "BKSV is revoked\n"); 888 return -EPERM; 889 } 890 891 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 892 bksv.reg[0]); 893 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 894 bksv.reg[1]); 895 896 ret = shim->repeater_present(dig_port, &repeater_present); 897 if (ret) 898 return ret; 899 if (repeater_present) 900 intel_de_write(display, HDCP_REP_CTL, 901 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 902 903 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 904 if (ret) 905 return ret; 906 907 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 908 HDCP_CONF_AUTH_AND_ENC); 909 910 /* Wait for R0 ready */ 911 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 912 val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 913 100, 1000, false); 914 if (ret) { 915 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 916 return -ETIMEDOUT; 917 } 918 919 /* 920 * Wait for R0' to become available. The spec says 100ms from Aksv, but 921 * some monitors can take longer than this. We'll set the timeout at 922 * 300ms just to be sure. 923 * 924 * On DP, there's an R0_READY bit available but no such bit 925 * exists on HDMI. Since the upper-bound is the same, we'll just do 926 * the stupid thing instead of polling on one and not the other. 927 */ 928 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 929 930 tries = 3; 931 932 /* 933 * DP HDCP Spec mandates the two more reattempt to read R0, incase 934 * of R0 mismatch. 935 */ 936 for (i = 0; i < tries; i++) { 937 ri.reg = 0; 938 ret = shim->read_ri_prime(dig_port, ri.shim); 939 if (ret) 940 return ret; 941 intel_de_write(display, 942 HDCP_RPRIME(display, cpu_transcoder, port), 943 ri.reg); 944 945 /* Wait for Ri prime match */ 946 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 947 val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 948 100, 1000, false); 949 if (!ret) 950 break; 951 } 952 953 if (i == tries) { 954 drm_dbg_kms(display->drm, 955 "Timed out waiting for Ri prime match (%x)\n", val); 956 return -ETIMEDOUT; 957 } 958 959 /* Wait for encryption confirmation */ 960 if (intel_de_wait_for_set_ms(display, 961 HDCP_STATUS(display, cpu_transcoder, port), 962 HDCP_STATUS_ENC, 963 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 964 drm_err(display->drm, "Timed out waiting for encryption\n"); 965 return -ETIMEDOUT; 966 } 967 968 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 969 if (shim->stream_encryption) { 970 ret = shim->stream_encryption(connector, true); 971 if (ret) { 972 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 973 connector->base.base.id, connector->base.name); 974 return ret; 975 } 976 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 977 transcoder_name(hdcp->stream_transcoder)); 978 } 979 980 if (repeater_present) 981 return intel_hdcp_auth_downstream(connector); 982 983 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 984 return 0; 985 } 986 987 static int _intel_hdcp_disable(struct intel_connector *connector) 988 { 989 struct intel_display *display = to_intel_display(connector); 990 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 991 struct intel_hdcp *hdcp = &connector->hdcp; 992 enum port port = dig_port->base.port; 993 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 994 u32 repeater_ctl; 995 int ret; 996 997 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 998 connector->base.base.id, connector->base.name); 999 1000 if (hdcp->shim->stream_encryption) { 1001 ret = hdcp->shim->stream_encryption(connector, false); 1002 if (ret) { 1003 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 1004 connector->base.base.id, connector->base.name); 1005 return ret; 1006 } 1007 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1008 transcoder_name(hdcp->stream_transcoder)); 1009 /* 1010 * If there are other connectors on this port using HDCP, 1011 * don't disable it until it disabled HDCP encryption for 1012 * all connectors in MST topology. 1013 */ 1014 if (dig_port->hdcp.num_streams > 0) 1015 return 0; 1016 } 1017 1018 hdcp->hdcp_encrypted = false; 1019 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1020 if (intel_de_wait_for_clear_ms(display, 1021 HDCP_STATUS(display, cpu_transcoder, port), 1022 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1023 drm_err(display->drm, 1024 "Failed to disable HDCP, timeout clearing status\n"); 1025 return -ETIMEDOUT; 1026 } 1027 1028 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1029 port); 1030 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1031 1032 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1033 if (ret) { 1034 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1035 return ret; 1036 } 1037 1038 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1039 return 0; 1040 } 1041 1042 static int intel_hdcp1_enable(struct intel_connector *connector) 1043 { 1044 struct intel_display *display = to_intel_display(connector); 1045 struct intel_hdcp *hdcp = &connector->hdcp; 1046 int i, ret, tries = 3; 1047 1048 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1049 connector->base.base.id, connector->base.name); 1050 1051 if (!hdcp_key_loadable(display)) { 1052 drm_err(display->drm, "HDCP key Load is not possible\n"); 1053 return -ENXIO; 1054 } 1055 1056 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1057 ret = intel_hdcp_load_keys(display); 1058 if (!ret) 1059 break; 1060 intel_hdcp_clear_keys(display); 1061 } 1062 if (ret) { 1063 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1064 ret); 1065 return ret; 1066 } 1067 1068 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1069 1070 /* Incase of authentication failures, HDCP spec expects reauth. */ 1071 for (i = 0; i < tries; i++) { 1072 ret = intel_hdcp_auth(connector); 1073 if (!ret) { 1074 hdcp->hdcp_encrypted = true; 1075 return 0; 1076 } 1077 1078 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1079 1080 /* Ensuring HDCP encryption and signalling are stopped. */ 1081 _intel_hdcp_disable(connector); 1082 } 1083 1084 drm_dbg_kms(display->drm, 1085 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1086 return ret; 1087 } 1088 1089 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1090 { 1091 return container_of(hdcp, struct intel_connector, hdcp); 1092 } 1093 1094 static void intel_hdcp_update_value(struct intel_connector *connector, 1095 u64 value, bool update_property) 1096 { 1097 struct intel_display *display = to_intel_display(connector); 1098 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1099 struct intel_hdcp *hdcp = &connector->hdcp; 1100 1101 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1102 1103 if (hdcp->value == value) 1104 return; 1105 1106 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1107 1108 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1109 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1110 dig_port->hdcp.num_streams--; 1111 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1112 dig_port->hdcp.num_streams++; 1113 } 1114 1115 hdcp->value = value; 1116 if (update_property) { 1117 drm_connector_get(&connector->base); 1118 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 1119 drm_connector_put(&connector->base); 1120 } 1121 } 1122 1123 /* Implements Part 3 of the HDCP authorization procedure */ 1124 static int intel_hdcp_check_link(struct intel_connector *connector) 1125 { 1126 struct intel_display *display = to_intel_display(connector); 1127 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1128 struct intel_hdcp *hdcp = &connector->hdcp; 1129 enum port port = dig_port->base.port; 1130 enum transcoder cpu_transcoder; 1131 int ret = 0; 1132 1133 mutex_lock(&hdcp->mutex); 1134 mutex_lock(&dig_port->hdcp.mutex); 1135 1136 cpu_transcoder = hdcp->cpu_transcoder; 1137 1138 /* Check_link valid only when HDCP1.4 is enabled */ 1139 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1140 !hdcp->hdcp_encrypted) { 1141 ret = -EINVAL; 1142 goto out; 1143 } 1144 1145 if (drm_WARN_ON(display->drm, 1146 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1147 drm_err(display->drm, 1148 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1149 connector->base.base.id, connector->base.name, 1150 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1151 ret = -ENXIO; 1152 intel_hdcp_update_value(connector, 1153 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1154 true); 1155 goto out; 1156 } 1157 1158 if (hdcp->shim->check_link(dig_port, connector)) { 1159 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1160 intel_hdcp_update_value(connector, 1161 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1162 } 1163 goto out; 1164 } 1165 1166 drm_dbg_kms(display->drm, 1167 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1168 connector->base.base.id, connector->base.name); 1169 1170 ret = _intel_hdcp_disable(connector); 1171 if (ret) { 1172 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1173 intel_hdcp_update_value(connector, 1174 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1175 true); 1176 goto out; 1177 } 1178 1179 ret = intel_hdcp1_enable(connector); 1180 if (ret) { 1181 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1182 intel_hdcp_update_value(connector, 1183 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1184 true); 1185 goto out; 1186 } 1187 1188 out: 1189 mutex_unlock(&dig_port->hdcp.mutex); 1190 mutex_unlock(&hdcp->mutex); 1191 return ret; 1192 } 1193 1194 static void intel_hdcp_prop_work(struct work_struct *work) 1195 { 1196 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1197 prop_work); 1198 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1199 struct intel_display *display = to_intel_display(connector); 1200 1201 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1202 mutex_lock(&hdcp->mutex); 1203 1204 /* 1205 * This worker is only used to flip between ENABLED/DESIRED. Either of 1206 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1207 * we're running just after hdcp has been disabled, so just exit 1208 */ 1209 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1210 drm_hdcp_update_content_protection(&connector->base, 1211 hdcp->value); 1212 1213 mutex_unlock(&hdcp->mutex); 1214 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1215 1216 drm_connector_put(&connector->base); 1217 } 1218 1219 bool is_hdcp_supported(struct intel_display *display, enum port port) 1220 { 1221 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1222 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1223 } 1224 1225 static int 1226 hdcp2_prepare_ake_init(struct intel_connector *connector, 1227 struct hdcp2_ake_init *ake_data) 1228 { 1229 struct intel_display *display = to_intel_display(connector); 1230 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1231 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1232 struct i915_hdcp_arbiter *arbiter; 1233 int ret; 1234 1235 mutex_lock(&display->hdcp.hdcp_mutex); 1236 arbiter = display->hdcp.arbiter; 1237 1238 if (!arbiter || !arbiter->ops) { 1239 mutex_unlock(&display->hdcp.hdcp_mutex); 1240 return -EINVAL; 1241 } 1242 1243 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1244 if (ret) 1245 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1246 ret); 1247 mutex_unlock(&display->hdcp.hdcp_mutex); 1248 1249 return ret; 1250 } 1251 1252 static int 1253 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1254 struct hdcp2_ake_send_cert *rx_cert, 1255 bool *paired, 1256 struct hdcp2_ake_no_stored_km *ek_pub_km, 1257 size_t *msg_sz) 1258 { 1259 struct intel_display *display = to_intel_display(connector); 1260 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1261 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1262 struct i915_hdcp_arbiter *arbiter; 1263 int ret; 1264 1265 mutex_lock(&display->hdcp.hdcp_mutex); 1266 arbiter = display->hdcp.arbiter; 1267 1268 if (!arbiter || !arbiter->ops) { 1269 mutex_unlock(&display->hdcp.hdcp_mutex); 1270 return -EINVAL; 1271 } 1272 1273 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1274 rx_cert, paired, 1275 ek_pub_km, msg_sz); 1276 if (ret < 0) 1277 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1278 ret); 1279 mutex_unlock(&display->hdcp.hdcp_mutex); 1280 1281 return ret; 1282 } 1283 1284 static int hdcp2_verify_hprime(struct intel_connector *connector, 1285 struct hdcp2_ake_send_hprime *rx_hprime) 1286 { 1287 struct intel_display *display = to_intel_display(connector); 1288 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1289 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1290 struct i915_hdcp_arbiter *arbiter; 1291 int ret; 1292 1293 mutex_lock(&display->hdcp.hdcp_mutex); 1294 arbiter = display->hdcp.arbiter; 1295 1296 if (!arbiter || !arbiter->ops) { 1297 mutex_unlock(&display->hdcp.hdcp_mutex); 1298 return -EINVAL; 1299 } 1300 1301 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1302 if (ret < 0) 1303 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1304 mutex_unlock(&display->hdcp.hdcp_mutex); 1305 1306 return ret; 1307 } 1308 1309 static int 1310 hdcp2_store_pairing_info(struct intel_connector *connector, 1311 struct hdcp2_ake_send_pairing_info *pairing_info) 1312 { 1313 struct intel_display *display = to_intel_display(connector); 1314 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1315 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1316 struct i915_hdcp_arbiter *arbiter; 1317 int ret; 1318 1319 mutex_lock(&display->hdcp.hdcp_mutex); 1320 arbiter = display->hdcp.arbiter; 1321 1322 if (!arbiter || !arbiter->ops) { 1323 mutex_unlock(&display->hdcp.hdcp_mutex); 1324 return -EINVAL; 1325 } 1326 1327 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1328 if (ret < 0) 1329 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1330 ret); 1331 mutex_unlock(&display->hdcp.hdcp_mutex); 1332 1333 return ret; 1334 } 1335 1336 static int 1337 hdcp2_prepare_lc_init(struct intel_connector *connector, 1338 struct hdcp2_lc_init *lc_init) 1339 { 1340 struct intel_display *display = to_intel_display(connector); 1341 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1342 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1343 struct i915_hdcp_arbiter *arbiter; 1344 int ret; 1345 1346 mutex_lock(&display->hdcp.hdcp_mutex); 1347 arbiter = display->hdcp.arbiter; 1348 1349 if (!arbiter || !arbiter->ops) { 1350 mutex_unlock(&display->hdcp.hdcp_mutex); 1351 return -EINVAL; 1352 } 1353 1354 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1355 if (ret < 0) 1356 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1357 ret); 1358 mutex_unlock(&display->hdcp.hdcp_mutex); 1359 1360 return ret; 1361 } 1362 1363 static int 1364 hdcp2_verify_lprime(struct intel_connector *connector, 1365 struct hdcp2_lc_send_lprime *rx_lprime) 1366 { 1367 struct intel_display *display = to_intel_display(connector); 1368 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1369 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1370 struct i915_hdcp_arbiter *arbiter; 1371 int ret; 1372 1373 mutex_lock(&display->hdcp.hdcp_mutex); 1374 arbiter = display->hdcp.arbiter; 1375 1376 if (!arbiter || !arbiter->ops) { 1377 mutex_unlock(&display->hdcp.hdcp_mutex); 1378 return -EINVAL; 1379 } 1380 1381 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1382 if (ret < 0) 1383 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1384 ret); 1385 mutex_unlock(&display->hdcp.hdcp_mutex); 1386 1387 return ret; 1388 } 1389 1390 static int hdcp2_prepare_skey(struct intel_connector *connector, 1391 struct hdcp2_ske_send_eks *ske_data) 1392 { 1393 struct intel_display *display = to_intel_display(connector); 1394 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1395 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1396 struct i915_hdcp_arbiter *arbiter; 1397 int ret; 1398 1399 mutex_lock(&display->hdcp.hdcp_mutex); 1400 arbiter = display->hdcp.arbiter; 1401 1402 if (!arbiter || !arbiter->ops) { 1403 mutex_unlock(&display->hdcp.hdcp_mutex); 1404 return -EINVAL; 1405 } 1406 1407 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1408 if (ret < 0) 1409 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1410 ret); 1411 mutex_unlock(&display->hdcp.hdcp_mutex); 1412 1413 return ret; 1414 } 1415 1416 static int 1417 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1418 struct hdcp2_rep_send_receiverid_list 1419 *rep_topology, 1420 struct hdcp2_rep_send_ack *rep_send_ack) 1421 { 1422 struct intel_display *display = to_intel_display(connector); 1423 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1424 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1425 struct i915_hdcp_arbiter *arbiter; 1426 int ret; 1427 1428 mutex_lock(&display->hdcp.hdcp_mutex); 1429 arbiter = display->hdcp.arbiter; 1430 1431 if (!arbiter || !arbiter->ops) { 1432 mutex_unlock(&display->hdcp.hdcp_mutex); 1433 return -EINVAL; 1434 } 1435 1436 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1437 data, 1438 rep_topology, 1439 rep_send_ack); 1440 if (ret < 0) 1441 drm_dbg_kms(display->drm, 1442 "Verify rep topology failed. %d\n", ret); 1443 mutex_unlock(&display->hdcp.hdcp_mutex); 1444 1445 return ret; 1446 } 1447 1448 static int 1449 hdcp2_verify_mprime(struct intel_connector *connector, 1450 struct hdcp2_rep_stream_ready *stream_ready) 1451 { 1452 struct intel_display *display = to_intel_display(connector); 1453 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1454 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1455 struct i915_hdcp_arbiter *arbiter; 1456 int ret; 1457 1458 mutex_lock(&display->hdcp.hdcp_mutex); 1459 arbiter = display->hdcp.arbiter; 1460 1461 if (!arbiter || !arbiter->ops) { 1462 mutex_unlock(&display->hdcp.hdcp_mutex); 1463 return -EINVAL; 1464 } 1465 1466 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1467 if (ret < 0) 1468 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1469 mutex_unlock(&display->hdcp.hdcp_mutex); 1470 1471 return ret; 1472 } 1473 1474 static int hdcp2_authenticate_port(struct intel_connector *connector) 1475 { 1476 struct intel_display *display = to_intel_display(connector); 1477 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1478 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1479 struct i915_hdcp_arbiter *arbiter; 1480 int ret; 1481 1482 mutex_lock(&display->hdcp.hdcp_mutex); 1483 arbiter = display->hdcp.arbiter; 1484 1485 if (!arbiter || !arbiter->ops) { 1486 mutex_unlock(&display->hdcp.hdcp_mutex); 1487 return -EINVAL; 1488 } 1489 1490 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1491 if (ret < 0) 1492 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1493 ret); 1494 mutex_unlock(&display->hdcp.hdcp_mutex); 1495 1496 return ret; 1497 } 1498 1499 static int hdcp2_close_session(struct intel_connector *connector) 1500 { 1501 struct intel_display *display = to_intel_display(connector); 1502 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1503 struct i915_hdcp_arbiter *arbiter; 1504 int ret; 1505 1506 mutex_lock(&display->hdcp.hdcp_mutex); 1507 arbiter = display->hdcp.arbiter; 1508 1509 if (!arbiter || !arbiter->ops) { 1510 mutex_unlock(&display->hdcp.hdcp_mutex); 1511 return -EINVAL; 1512 } 1513 1514 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1515 &dig_port->hdcp.port_data); 1516 mutex_unlock(&display->hdcp.hdcp_mutex); 1517 1518 return ret; 1519 } 1520 1521 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1522 { 1523 return hdcp2_close_session(connector); 1524 } 1525 1526 /* Authentication flow starts from here */ 1527 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1528 { 1529 struct intel_display *display = to_intel_display(connector); 1530 struct intel_digital_port *dig_port = 1531 intel_attached_dig_port(connector); 1532 struct intel_hdcp *hdcp = &connector->hdcp; 1533 union { 1534 struct hdcp2_ake_init ake_init; 1535 struct hdcp2_ake_send_cert send_cert; 1536 struct hdcp2_ake_no_stored_km no_stored_km; 1537 struct hdcp2_ake_send_hprime send_hprime; 1538 struct hdcp2_ake_send_pairing_info pairing_info; 1539 } msgs; 1540 const struct intel_hdcp_shim *shim = hdcp->shim; 1541 size_t size; 1542 int ret, i, max_retries; 1543 1544 /* Init for seq_num */ 1545 hdcp->seq_num_v = 0; 1546 hdcp->seq_num_m = 0; 1547 1548 if (intel_encoder_is_dp(&dig_port->base) || 1549 intel_encoder_is_mst(&dig_port->base)) 1550 max_retries = 10; 1551 else 1552 max_retries = 1; 1553 1554 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1555 if (ret < 0) 1556 return ret; 1557 1558 /* 1559 * Retry the first read and write to downstream at least 10 times 1560 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1561 * (dock decides to stop advertising hdcp2 capability for some reason). 1562 * The reason being that during suspend resume dock usually keeps the 1563 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1564 * big problem if the userspace just kept retrying with some delay while 1565 * it continues to play low value content but most userspace applications 1566 * end up throwing an error when it receives one from KMD. This makes 1567 * sure we give the dock and the sink devices to complete its power cycle 1568 * and then try HDCP authentication. The values of 10 and delay of 50ms 1569 * was decided based on multiple trial and errors. 1570 */ 1571 for (i = 0; i < max_retries; i++) { 1572 if (!intel_hdcp2_get_capability(connector)) { 1573 msleep(50); 1574 continue; 1575 } 1576 1577 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1578 sizeof(msgs.ake_init)); 1579 if (ret < 0) 1580 continue; 1581 1582 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1583 &msgs.send_cert, sizeof(msgs.send_cert)); 1584 if (ret > 0) 1585 break; 1586 } 1587 1588 if (ret < 0) 1589 return ret; 1590 1591 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1592 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1593 return -EINVAL; 1594 } 1595 1596 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1597 1598 if (drm_hdcp_check_ksvs_revoked(display->drm, 1599 msgs.send_cert.cert_rx.receiver_id, 1600 1) > 0) { 1601 drm_err(display->drm, "Receiver ID is revoked\n"); 1602 return -EPERM; 1603 } 1604 1605 /* 1606 * Here msgs.no_stored_km will hold msgs corresponding to the km 1607 * stored also. 1608 */ 1609 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1610 &hdcp->is_paired, 1611 &msgs.no_stored_km, &size); 1612 if (ret < 0) 1613 return ret; 1614 1615 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1616 if (ret < 0) 1617 return ret; 1618 1619 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1620 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1621 if (ret < 0) 1622 return ret; 1623 1624 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1625 if (ret < 0) 1626 return ret; 1627 1628 if (!hdcp->is_paired) { 1629 /* Pairing is required */ 1630 ret = shim->read_2_2_msg(connector, 1631 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1632 &msgs.pairing_info, 1633 sizeof(msgs.pairing_info)); 1634 if (ret < 0) 1635 return ret; 1636 1637 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1638 if (ret < 0) 1639 return ret; 1640 hdcp->is_paired = true; 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int hdcp2_locality_check(struct intel_connector *connector) 1647 { 1648 struct intel_hdcp *hdcp = &connector->hdcp; 1649 union { 1650 struct hdcp2_lc_init lc_init; 1651 struct hdcp2_lc_send_lprime send_lprime; 1652 } msgs; 1653 const struct intel_hdcp_shim *shim = hdcp->shim; 1654 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1655 1656 for (i = 0; i < tries; i++) { 1657 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1658 if (ret < 0) 1659 continue; 1660 1661 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1662 sizeof(msgs.lc_init)); 1663 if (ret < 0) 1664 continue; 1665 1666 ret = shim->read_2_2_msg(connector, 1667 HDCP_2_2_LC_SEND_LPRIME, 1668 &msgs.send_lprime, 1669 sizeof(msgs.send_lprime)); 1670 if (ret < 0) 1671 continue; 1672 1673 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1674 if (!ret) 1675 break; 1676 } 1677 1678 return ret; 1679 } 1680 1681 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1682 { 1683 struct intel_hdcp *hdcp = &connector->hdcp; 1684 struct hdcp2_ske_send_eks send_eks; 1685 int ret; 1686 1687 ret = hdcp2_prepare_skey(connector, &send_eks); 1688 if (ret < 0) 1689 return ret; 1690 1691 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1692 sizeof(send_eks)); 1693 if (ret < 0) 1694 return ret; 1695 1696 return 0; 1697 } 1698 1699 static 1700 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1701 { 1702 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1703 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1704 struct intel_hdcp *hdcp = &connector->hdcp; 1705 union { 1706 struct hdcp2_rep_stream_manage stream_manage; 1707 struct hdcp2_rep_stream_ready stream_ready; 1708 } msgs; 1709 const struct intel_hdcp_shim *shim = hdcp->shim; 1710 int ret, streams_size_delta, i; 1711 1712 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1713 return -ERANGE; 1714 1715 /* Prepare RepeaterAuth_Stream_Manage msg */ 1716 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1717 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1718 1719 msgs.stream_manage.k = cpu_to_be16(data->k); 1720 1721 for (i = 0; i < data->k; i++) { 1722 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1723 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1724 } 1725 1726 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1727 sizeof(struct hdcp2_streamid_type); 1728 /* Send it to Repeater */ 1729 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1730 sizeof(msgs.stream_manage) - streams_size_delta); 1731 if (ret < 0) 1732 goto out; 1733 1734 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1735 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1736 if (ret < 0) 1737 goto out; 1738 1739 data->seq_num_m = hdcp->seq_num_m; 1740 1741 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1742 1743 out: 1744 hdcp->seq_num_m++; 1745 1746 return ret; 1747 } 1748 1749 static 1750 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1751 { 1752 struct intel_display *display = to_intel_display(connector); 1753 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1754 struct intel_hdcp *hdcp = &connector->hdcp; 1755 union { 1756 struct hdcp2_rep_send_receiverid_list recvid_list; 1757 struct hdcp2_rep_send_ack rep_ack; 1758 } msgs; 1759 const struct intel_hdcp_shim *shim = hdcp->shim; 1760 u32 seq_num_v, device_cnt; 1761 u8 *rx_info; 1762 int ret; 1763 1764 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1765 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1766 if (ret < 0) 1767 return ret; 1768 1769 rx_info = msgs.recvid_list.rx_info; 1770 1771 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1772 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1773 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1774 return -EINVAL; 1775 } 1776 1777 /* 1778 * MST topology is not Type 1 capable if it contains a downstream 1779 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1780 */ 1781 dig_port->hdcp.mst_type1_capable = 1782 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1783 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1784 1785 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1786 drm_dbg_kms(display->drm, 1787 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1788 return -EINVAL; 1789 } 1790 1791 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1792 seq_num_v = 1793 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1794 1795 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1796 drm_dbg_kms(display->drm, 1797 "Non zero Seq_num_v at first RecvId_List msg\n"); 1798 return -EINVAL; 1799 } 1800 1801 if (seq_num_v < hdcp->seq_num_v) { 1802 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1803 drm_dbg_kms(display->drm, "Seq_num_v roll over.\n"); 1804 return -EINVAL; 1805 } 1806 1807 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1808 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1809 if (drm_hdcp_check_ksvs_revoked(display->drm, 1810 msgs.recvid_list.receiver_ids, 1811 device_cnt) > 0) { 1812 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1813 return -EPERM; 1814 } 1815 1816 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1817 &msgs.recvid_list, 1818 &msgs.rep_ack); 1819 if (ret < 0) 1820 return ret; 1821 1822 hdcp->seq_num_v = seq_num_v; 1823 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1824 sizeof(msgs.rep_ack)); 1825 if (ret < 0) 1826 return ret; 1827 1828 return 0; 1829 } 1830 1831 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1832 { 1833 struct intel_display *display = to_intel_display(connector); 1834 struct intel_hdcp *hdcp = &connector->hdcp; 1835 const struct intel_hdcp_shim *shim = hdcp->shim; 1836 int ret; 1837 1838 ret = hdcp2_authentication_key_exchange(connector); 1839 if (ret < 0) { 1840 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1841 return ret; 1842 } 1843 1844 ret = hdcp2_locality_check(connector); 1845 if (ret < 0) { 1846 drm_dbg_kms(display->drm, 1847 "Locality Check failed. Err : %d\n", ret); 1848 return ret; 1849 } 1850 1851 ret = hdcp2_session_key_exchange(connector); 1852 if (ret < 0) { 1853 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1854 return ret; 1855 } 1856 1857 if (shim->config_stream_type) { 1858 ret = shim->config_stream_type(connector, 1859 hdcp->is_repeater, 1860 hdcp->content_type); 1861 if (ret < 0) 1862 return ret; 1863 } 1864 1865 if (hdcp->is_repeater) { 1866 ret = hdcp2_authenticate_repeater_topology(connector); 1867 if (ret < 0) { 1868 drm_dbg_kms(display->drm, 1869 "Repeater Auth Failed. Err: %d\n", ret); 1870 return ret; 1871 } 1872 } 1873 1874 return ret; 1875 } 1876 1877 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1878 { 1879 struct intel_display *display = to_intel_display(connector); 1880 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1881 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1882 struct intel_hdcp *hdcp = &connector->hdcp; 1883 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1884 enum port port = dig_port->base.port; 1885 int ret = 0; 1886 1887 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1888 LINK_ENCRYPTION_STATUS)) { 1889 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1890 connector->base.base.id, connector->base.name); 1891 ret = -EPERM; 1892 goto link_recover; 1893 } 1894 1895 if (hdcp->shim->stream_2_2_encryption) { 1896 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1897 if (ret) { 1898 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1899 connector->base.base.id, connector->base.name); 1900 return ret; 1901 } 1902 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1903 transcoder_name(hdcp->stream_transcoder)); 1904 } 1905 1906 return 0; 1907 1908 link_recover: 1909 if (hdcp2_deauthenticate_port(connector) < 0) 1910 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1911 1912 dig_port->hdcp.auth_status = false; 1913 data->k = 0; 1914 1915 return ret; 1916 } 1917 1918 static int hdcp2_enable_encryption(struct intel_connector *connector) 1919 { 1920 struct intel_display *display = to_intel_display(connector); 1921 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1922 struct intel_hdcp *hdcp = &connector->hdcp; 1923 enum port port = dig_port->base.port; 1924 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1925 int ret; 1926 1927 drm_WARN_ON(display->drm, 1928 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1929 LINK_ENCRYPTION_STATUS); 1930 if (hdcp->shim->toggle_signalling) { 1931 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1932 true); 1933 if (ret) { 1934 drm_err(display->drm, 1935 "Failed to enable HDCP signalling. %d\n", 1936 ret); 1937 return ret; 1938 } 1939 } 1940 1941 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1942 LINK_AUTH_STATUS) 1943 /* Link is Authenticated. Now set for Encryption */ 1944 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1945 0, CTL_LINK_ENCRYPTION_REQ); 1946 1947 ret = intel_de_wait_for_set_ms(display, 1948 HDCP2_STATUS(display, cpu_transcoder, port), 1949 LINK_ENCRYPTION_STATUS, 1950 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1951 dig_port->hdcp.auth_status = true; 1952 1953 return ret; 1954 } 1955 1956 static int hdcp2_disable_encryption(struct intel_connector *connector) 1957 { 1958 struct intel_display *display = to_intel_display(connector); 1959 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1960 struct intel_hdcp *hdcp = &connector->hdcp; 1961 enum port port = dig_port->base.port; 1962 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1963 int ret; 1964 1965 drm_WARN_ON(display->drm, 1966 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1967 LINK_ENCRYPTION_STATUS)); 1968 1969 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1970 CTL_LINK_ENCRYPTION_REQ, 0); 1971 1972 ret = intel_de_wait_for_clear_ms(display, 1973 HDCP2_STATUS(display, cpu_transcoder, port), 1974 LINK_ENCRYPTION_STATUS, 1975 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1976 if (ret == -ETIMEDOUT) 1977 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1978 1979 if (hdcp->shim->toggle_signalling) { 1980 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1981 false); 1982 if (ret) { 1983 drm_err(display->drm, 1984 "Failed to disable HDCP signalling. %d\n", 1985 ret); 1986 return ret; 1987 } 1988 } 1989 1990 return ret; 1991 } 1992 1993 static int 1994 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1995 { 1996 struct intel_display *display = to_intel_display(connector); 1997 int i, tries = 3, ret; 1998 1999 if (!connector->hdcp.is_repeater) 2000 return 0; 2001 2002 for (i = 0; i < tries; i++) { 2003 ret = _hdcp2_propagate_stream_management_info(connector); 2004 if (!ret) 2005 break; 2006 2007 /* Lets restart the auth incase of seq_num_m roll over */ 2008 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2009 drm_dbg_kms(display->drm, 2010 "seq_num_m roll over.(%d)\n", ret); 2011 break; 2012 } 2013 2014 drm_dbg_kms(display->drm, 2015 "HDCP2 stream management %d of %d Failed.(%d)\n", 2016 i + 1, tries, ret); 2017 } 2018 2019 return ret; 2020 } 2021 2022 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2023 struct intel_connector *connector) 2024 { 2025 struct intel_display *display = to_intel_display(connector); 2026 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2027 int ret = 0, i, tries = 3; 2028 2029 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2030 ret = hdcp2_authenticate_sink(connector); 2031 if (!ret) { 2032 ret = intel_hdcp_prepare_streams(state, connector); 2033 if (ret) { 2034 drm_dbg_kms(display->drm, 2035 "Prepare stream failed.(%d)\n", 2036 ret); 2037 break; 2038 } 2039 2040 ret = hdcp2_propagate_stream_management_info(connector); 2041 if (ret) { 2042 drm_dbg_kms(display->drm, 2043 "Stream management failed.(%d)\n", 2044 ret); 2045 break; 2046 } 2047 2048 ret = hdcp2_authenticate_port(connector); 2049 if (!ret) 2050 break; 2051 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2052 ret); 2053 } 2054 2055 /* Clearing the mei hdcp session */ 2056 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2057 i + 1, tries, ret); 2058 if (hdcp2_deauthenticate_port(connector) < 0) 2059 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2060 } 2061 2062 if (!ret && !dig_port->hdcp.auth_status) { 2063 /* 2064 * Ensuring the required 200mSec min time interval between 2065 * Session Key Exchange and encryption. 2066 */ 2067 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2068 ret = hdcp2_enable_encryption(connector); 2069 if (ret < 0) { 2070 drm_dbg_kms(display->drm, 2071 "Encryption Enable Failed.(%d)\n", ret); 2072 if (hdcp2_deauthenticate_port(connector) < 0) 2073 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2074 } 2075 } 2076 2077 if (!ret) 2078 ret = hdcp2_enable_stream_encryption(connector); 2079 2080 return ret; 2081 } 2082 2083 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2084 struct intel_connector *connector) 2085 { 2086 struct intel_display *display = to_intel_display(connector); 2087 struct intel_hdcp *hdcp = &connector->hdcp; 2088 int ret; 2089 2090 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2091 connector->base.base.id, connector->base.name, 2092 hdcp->content_type); 2093 2094 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2095 2096 ret = hdcp2_authenticate_and_encrypt(state, connector); 2097 if (ret) { 2098 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2099 hdcp->content_type, ret); 2100 return ret; 2101 } 2102 2103 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2104 connector->base.base.id, connector->base.name, 2105 hdcp->content_type); 2106 2107 hdcp->hdcp2_encrypted = true; 2108 return 0; 2109 } 2110 2111 static int 2112 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2113 { 2114 struct intel_display *display = to_intel_display(connector); 2115 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2116 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2117 struct intel_hdcp *hdcp = &connector->hdcp; 2118 int ret; 2119 2120 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2121 connector->base.base.id, connector->base.name); 2122 2123 if (hdcp->shim->stream_2_2_encryption) { 2124 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2125 if (ret) { 2126 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2127 connector->base.base.id, connector->base.name); 2128 return ret; 2129 } 2130 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2131 transcoder_name(hdcp->stream_transcoder)); 2132 2133 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2134 return 0; 2135 } 2136 2137 ret = hdcp2_disable_encryption(connector); 2138 2139 if (hdcp2_deauthenticate_port(connector) < 0) 2140 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2141 2142 connector->hdcp.hdcp2_encrypted = false; 2143 dig_port->hdcp.auth_status = false; 2144 data->k = 0; 2145 2146 return ret; 2147 } 2148 2149 /* Implements the Link Integrity Check for HDCP2.2 */ 2150 static int intel_hdcp2_check_link(struct intel_connector *connector) 2151 { 2152 struct intel_display *display = to_intel_display(connector); 2153 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2154 struct intel_hdcp *hdcp = &connector->hdcp; 2155 enum port port = dig_port->base.port; 2156 enum transcoder cpu_transcoder; 2157 int ret = 0; 2158 2159 mutex_lock(&hdcp->mutex); 2160 mutex_lock(&dig_port->hdcp.mutex); 2161 cpu_transcoder = hdcp->cpu_transcoder; 2162 2163 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2164 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2165 !hdcp->hdcp2_encrypted) { 2166 ret = -EINVAL; 2167 goto out; 2168 } 2169 2170 if (drm_WARN_ON(display->drm, 2171 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2172 drm_err(display->drm, 2173 "HDCP2.2 link stopped the encryption, %x\n", 2174 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2175 ret = -ENXIO; 2176 _intel_hdcp2_disable(connector, true); 2177 intel_hdcp_update_value(connector, 2178 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2179 true); 2180 goto out; 2181 } 2182 2183 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2184 if (ret == HDCP_LINK_PROTECTED) { 2185 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2186 intel_hdcp_update_value(connector, 2187 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2188 true); 2189 } 2190 goto out; 2191 } 2192 2193 if (ret == HDCP_TOPOLOGY_CHANGE) { 2194 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2195 goto out; 2196 2197 drm_dbg_kms(display->drm, 2198 "HDCP2.2 Downstream topology change\n"); 2199 2200 ret = hdcp2_authenticate_repeater_topology(connector); 2201 if (!ret) { 2202 intel_hdcp_update_value(connector, 2203 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2204 true); 2205 goto out; 2206 } 2207 2208 drm_dbg_kms(display->drm, 2209 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2210 connector->base.base.id, connector->base.name, 2211 ret); 2212 } else { 2213 drm_dbg_kms(display->drm, 2214 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2215 connector->base.base.id, connector->base.name); 2216 } 2217 2218 ret = _intel_hdcp2_disable(connector, true); 2219 if (ret) { 2220 drm_err(display->drm, 2221 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2222 connector->base.base.id, connector->base.name, ret); 2223 intel_hdcp_update_value(connector, 2224 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2225 goto out; 2226 } 2227 2228 intel_hdcp_update_value(connector, 2229 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2230 out: 2231 mutex_unlock(&dig_port->hdcp.mutex); 2232 mutex_unlock(&hdcp->mutex); 2233 return ret; 2234 } 2235 2236 static void intel_hdcp_check_work(struct work_struct *work) 2237 { 2238 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2239 struct intel_hdcp, 2240 check_work); 2241 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2242 struct intel_display *display = to_intel_display(connector); 2243 2244 if (drm_connector_is_unregistered(&connector->base)) 2245 return; 2246 2247 if (!hdcp->force_hdcp14 && !intel_hdcp2_check_link(connector)) 2248 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2249 DRM_HDCP2_CHECK_PERIOD_MS); 2250 else if (!intel_hdcp_check_link(connector)) 2251 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2252 DRM_HDCP_CHECK_PERIOD_MS); 2253 } 2254 2255 static int i915_hdcp_component_bind(struct device *drv_kdev, 2256 struct device *mei_kdev, void *data) 2257 { 2258 struct intel_display *display = to_intel_display(drv_kdev); 2259 2260 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2261 mutex_lock(&display->hdcp.hdcp_mutex); 2262 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2263 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2264 mutex_unlock(&display->hdcp.hdcp_mutex); 2265 2266 return 0; 2267 } 2268 2269 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2270 struct device *mei_kdev, void *data) 2271 { 2272 struct intel_display *display = to_intel_display(drv_kdev); 2273 2274 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2275 mutex_lock(&display->hdcp.hdcp_mutex); 2276 display->hdcp.arbiter = NULL; 2277 mutex_unlock(&display->hdcp.hdcp_mutex); 2278 } 2279 2280 static const struct component_ops i915_hdcp_ops = { 2281 .bind = i915_hdcp_component_bind, 2282 .unbind = i915_hdcp_component_unbind, 2283 }; 2284 2285 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2286 { 2287 switch (port) { 2288 case PORT_A: 2289 return HDCP_DDI_A; 2290 case PORT_B ... PORT_F: 2291 return (enum hdcp_ddi)port; 2292 default: 2293 return HDCP_DDI_INVALID_PORT; 2294 } 2295 } 2296 2297 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2298 { 2299 switch (cpu_transcoder) { 2300 case TRANSCODER_A ... TRANSCODER_D: 2301 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2302 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2303 return HDCP_INVALID_TRANSCODER; 2304 } 2305 } 2306 2307 static int initialize_hdcp_port_data(struct intel_connector *connector, 2308 struct intel_digital_port *dig_port, 2309 const struct intel_hdcp_shim *shim) 2310 { 2311 struct intel_display *display = to_intel_display(connector); 2312 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2313 enum port port = dig_port->base.port; 2314 2315 if (DISPLAY_VER(display) < 12) 2316 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2317 else 2318 /* 2319 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2320 * with zero(INVALID PORT index). 2321 */ 2322 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2323 2324 /* 2325 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2326 * is initialized to zero (invalid transcoder index). This will be 2327 * retained for <Gen12 forever. 2328 */ 2329 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2330 2331 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2332 data->protocol = (u8)shim->protocol; 2333 2334 if (!data->streams) 2335 data->streams = kzalloc_objs(struct hdcp2_streamid_type, 2336 INTEL_NUM_PIPES(display)); 2337 if (!data->streams) { 2338 drm_err(display->drm, "Out of Memory\n"); 2339 return -ENOMEM; 2340 } 2341 2342 return 0; 2343 } 2344 2345 static bool is_hdcp2_supported(struct intel_display *display) 2346 { 2347 if (USE_HDCP_GSC(display)) 2348 return true; 2349 2350 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2351 return false; 2352 2353 return DISPLAY_VER(display) >= 10 || 2354 display->platform.kabylake || 2355 display->platform.coffeelake || 2356 display->platform.cometlake; 2357 } 2358 2359 void intel_hdcp_component_init(struct intel_display *display) 2360 { 2361 int ret; 2362 2363 if (!is_hdcp2_supported(display)) 2364 return; 2365 2366 mutex_lock(&display->hdcp.hdcp_mutex); 2367 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2368 2369 display->hdcp.comp_added = true; 2370 mutex_unlock(&display->hdcp.hdcp_mutex); 2371 if (USE_HDCP_GSC(display)) 2372 ret = intel_hdcp_gsc_init(display); 2373 else 2374 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2375 I915_COMPONENT_HDCP); 2376 2377 if (ret < 0) { 2378 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2379 ret); 2380 mutex_lock(&display->hdcp.hdcp_mutex); 2381 display->hdcp.comp_added = false; 2382 mutex_unlock(&display->hdcp.hdcp_mutex); 2383 return; 2384 } 2385 } 2386 2387 static void intel_hdcp2_init(struct intel_connector *connector, 2388 struct intel_digital_port *dig_port, 2389 const struct intel_hdcp_shim *shim) 2390 { 2391 struct intel_display *display = to_intel_display(connector); 2392 struct intel_hdcp *hdcp = &connector->hdcp; 2393 int ret; 2394 2395 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2396 if (ret) { 2397 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2398 return; 2399 } 2400 2401 hdcp->hdcp2_supported = true; 2402 } 2403 2404 int intel_hdcp_init(struct intel_connector *connector, 2405 struct intel_digital_port *dig_port, 2406 const struct intel_hdcp_shim *shim) 2407 { 2408 struct intel_display *display = to_intel_display(connector); 2409 struct intel_hdcp *hdcp = &connector->hdcp; 2410 int ret; 2411 2412 if (!shim) 2413 return -EINVAL; 2414 2415 if (is_hdcp2_supported(display)) 2416 intel_hdcp2_init(connector, dig_port, shim); 2417 2418 ret = drm_connector_attach_content_protection_property(&connector->base, 2419 hdcp->hdcp2_supported); 2420 if (ret) { 2421 hdcp->hdcp2_supported = false; 2422 kfree(dig_port->hdcp.port_data.streams); 2423 return ret; 2424 } 2425 2426 hdcp->shim = shim; 2427 mutex_init(&hdcp->mutex); 2428 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2429 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2430 init_waitqueue_head(&hdcp->cp_irq_queue); 2431 2432 return 0; 2433 } 2434 2435 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2436 struct intel_encoder *encoder, 2437 const struct intel_crtc_state *pipe_config, 2438 const struct drm_connector_state *conn_state) 2439 { 2440 struct intel_display *display = to_intel_display(encoder); 2441 struct intel_connector *connector = 2442 to_intel_connector(conn_state->connector); 2443 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2444 struct intel_hdcp *hdcp = &connector->hdcp; 2445 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2446 int ret = -EINVAL; 2447 2448 if (!hdcp->shim) 2449 return -ENOENT; 2450 2451 mutex_lock(&hdcp->mutex); 2452 mutex_lock(&dig_port->hdcp.mutex); 2453 drm_WARN_ON(display->drm, 2454 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2455 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2456 2457 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2458 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2459 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2460 } else { 2461 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2462 hdcp->stream_transcoder = INVALID_TRANSCODER; 2463 } 2464 2465 if (DISPLAY_VER(display) >= 12) 2466 dig_port->hdcp.port_data.hdcp_transcoder = 2467 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2468 2469 /* 2470 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2471 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2472 */ 2473 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2474 ret = _intel_hdcp2_enable(state, connector); 2475 if (!ret) 2476 check_link_interval = 2477 DRM_HDCP2_CHECK_PERIOD_MS; 2478 } 2479 2480 if (hdcp->force_hdcp14) 2481 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2482 2483 /* 2484 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2485 * be attempted. 2486 */ 2487 if (ret && intel_hdcp_get_capability(connector) && 2488 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2489 ret = intel_hdcp1_enable(connector); 2490 } 2491 2492 if (!ret) { 2493 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2494 check_link_interval); 2495 intel_hdcp_update_value(connector, 2496 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2497 true); 2498 } 2499 2500 mutex_unlock(&dig_port->hdcp.mutex); 2501 mutex_unlock(&hdcp->mutex); 2502 return ret; 2503 } 2504 2505 void intel_hdcp_enable(struct intel_atomic_state *state, 2506 struct intel_encoder *encoder, 2507 const struct intel_crtc_state *crtc_state, 2508 const struct drm_connector_state *conn_state) 2509 { 2510 struct intel_connector *connector = 2511 to_intel_connector(conn_state->connector); 2512 struct intel_hdcp *hdcp = &connector->hdcp; 2513 2514 /* 2515 * Enable hdcp if it's desired or if userspace is enabled and 2516 * driver set its state to undesired 2517 */ 2518 if (conn_state->content_protection == 2519 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2520 (conn_state->content_protection == 2521 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2522 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2523 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2524 } 2525 2526 int intel_hdcp_disable(struct intel_connector *connector) 2527 { 2528 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2529 struct intel_hdcp *hdcp = &connector->hdcp; 2530 int ret = 0; 2531 2532 if (!hdcp->shim) 2533 return -ENOENT; 2534 2535 mutex_lock(&hdcp->mutex); 2536 mutex_lock(&dig_port->hdcp.mutex); 2537 2538 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2539 goto out; 2540 2541 intel_hdcp_update_value(connector, 2542 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2543 if (hdcp->hdcp2_encrypted) 2544 ret = _intel_hdcp2_disable(connector, false); 2545 else if (hdcp->hdcp_encrypted) 2546 ret = _intel_hdcp_disable(connector); 2547 2548 out: 2549 mutex_unlock(&dig_port->hdcp.mutex); 2550 mutex_unlock(&hdcp->mutex); 2551 cancel_delayed_work_sync(&hdcp->check_work); 2552 return ret; 2553 } 2554 2555 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2556 struct intel_encoder *encoder, 2557 const struct intel_crtc_state *crtc_state, 2558 const struct drm_connector_state *conn_state) 2559 { 2560 struct intel_connector *connector = 2561 to_intel_connector(conn_state->connector); 2562 struct intel_hdcp *hdcp = &connector->hdcp; 2563 bool content_protection_type_changed, desired_and_not_enabled = false; 2564 struct intel_display *display = to_intel_display(connector); 2565 2566 if (!connector->hdcp.shim) 2567 return; 2568 2569 content_protection_type_changed = 2570 (conn_state->hdcp_content_type != hdcp->content_type && 2571 conn_state->content_protection != 2572 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2573 2574 /* 2575 * During the HDCP encryption session if Type change is requested, 2576 * disable the HDCP and re-enable it with new TYPE value. 2577 */ 2578 if (conn_state->content_protection == 2579 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2580 content_protection_type_changed) 2581 intel_hdcp_disable(connector); 2582 2583 /* 2584 * Mark the hdcp state as DESIRED after the hdcp disable of type 2585 * change procedure. 2586 */ 2587 if (content_protection_type_changed) { 2588 mutex_lock(&hdcp->mutex); 2589 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2590 drm_connector_get(&connector->base); 2591 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2592 drm_connector_put(&connector->base); 2593 mutex_unlock(&hdcp->mutex); 2594 } 2595 2596 if (conn_state->content_protection == 2597 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2598 mutex_lock(&hdcp->mutex); 2599 /* Avoid enabling hdcp, if it already ENABLED */ 2600 desired_and_not_enabled = 2601 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2602 mutex_unlock(&hdcp->mutex); 2603 /* 2604 * If HDCP already ENABLED and CP property is DESIRED, schedule 2605 * prop_work to update correct CP property to user space. 2606 */ 2607 if (!desired_and_not_enabled && !content_protection_type_changed) { 2608 drm_connector_get(&connector->base); 2609 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2610 drm_connector_put(&connector->base); 2611 2612 } 2613 } 2614 2615 if (desired_and_not_enabled || content_protection_type_changed) 2616 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2617 } 2618 2619 void intel_hdcp_cancel_works(struct intel_connector *connector) 2620 { 2621 if (!connector->hdcp.shim) 2622 return; 2623 2624 cancel_delayed_work_sync(&connector->hdcp.check_work); 2625 cancel_work_sync(&connector->hdcp.prop_work); 2626 } 2627 2628 void intel_hdcp_component_fini(struct intel_display *display) 2629 { 2630 mutex_lock(&display->hdcp.hdcp_mutex); 2631 if (!display->hdcp.comp_added) { 2632 mutex_unlock(&display->hdcp.hdcp_mutex); 2633 return; 2634 } 2635 2636 display->hdcp.comp_added = false; 2637 mutex_unlock(&display->hdcp.hdcp_mutex); 2638 2639 if (USE_HDCP_GSC(display)) 2640 intel_hdcp_gsc_fini(display); 2641 else 2642 component_del(display->drm->dev, &i915_hdcp_ops); 2643 } 2644 2645 void intel_hdcp_cleanup(struct intel_connector *connector) 2646 { 2647 struct intel_hdcp *hdcp = &connector->hdcp; 2648 2649 if (!hdcp->shim) 2650 return; 2651 2652 /* 2653 * If the connector is registered, it's possible userspace could kick 2654 * off another HDCP enable, which would re-spawn the workers. 2655 */ 2656 drm_WARN_ON(connector->base.dev, 2657 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2658 2659 /* 2660 * Now that the connector is not registered, check_work won't be run, 2661 * but cancel any outstanding instances of it 2662 */ 2663 cancel_delayed_work_sync(&hdcp->check_work); 2664 2665 /* 2666 * We don't cancel prop_work in the same way as check_work since it 2667 * requires connection_mutex which could be held while calling this 2668 * function. Instead, we rely on the connector references grabbed before 2669 * scheduling prop_work to ensure the connector is alive when prop_work 2670 * is run. So if we're in the destroy path (which is where this 2671 * function should be called), we're "guaranteed" that prop_work is not 2672 * active (tl;dr This Should Never Happen). 2673 */ 2674 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2675 2676 mutex_lock(&hdcp->mutex); 2677 hdcp->shim = NULL; 2678 mutex_unlock(&hdcp->mutex); 2679 } 2680 2681 void intel_hdcp_atomic_check(struct drm_connector *connector, 2682 struct drm_connector_state *old_state, 2683 struct drm_connector_state *new_state) 2684 { 2685 u64 old_cp = old_state->content_protection; 2686 u64 new_cp = new_state->content_protection; 2687 struct drm_crtc_state *crtc_state; 2688 2689 if (!new_state->crtc) { 2690 /* 2691 * If the connector is being disabled with CP enabled, mark it 2692 * desired so it's re-enabled when the connector is brought back 2693 */ 2694 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2695 new_state->content_protection = 2696 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2697 return; 2698 } 2699 2700 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2701 new_state->crtc); 2702 /* 2703 * Fix the HDCP uapi content protection state in case of modeset. 2704 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2705 * need to be sent if there is transition from ENABLED->DESIRED. 2706 */ 2707 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2708 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2709 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2710 new_state->content_protection = 2711 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2712 2713 /* 2714 * Nothing to do if the state didn't change, or HDCP was activated since 2715 * the last commit. And also no change in hdcp content type. 2716 */ 2717 if (old_cp == new_cp || 2718 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2719 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2720 if (old_state->hdcp_content_type == 2721 new_state->hdcp_content_type) 2722 return; 2723 } 2724 2725 crtc_state->mode_changed = true; 2726 } 2727 2728 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2729 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2730 { 2731 struct intel_hdcp *hdcp = &connector->hdcp; 2732 struct intel_display *display = to_intel_display(connector); 2733 2734 if (!hdcp->shim) 2735 return; 2736 2737 atomic_inc(&connector->hdcp.cp_irq_count); 2738 wake_up_all(&connector->hdcp.cp_irq_queue); 2739 2740 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0); 2741 } 2742 2743 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2744 bool remote_req) 2745 { 2746 bool hdcp_cap = false, hdcp2_cap = false; 2747 2748 if (!connector->hdcp.shim) { 2749 seq_puts(m, "No Connector Support"); 2750 goto out; 2751 } 2752 2753 if (remote_req) { 2754 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2755 } else { 2756 hdcp_cap = intel_hdcp_get_capability(connector); 2757 hdcp2_cap = intel_hdcp2_get_capability(connector); 2758 } 2759 2760 if (hdcp_cap) 2761 seq_puts(m, "HDCP1.4 "); 2762 if (hdcp2_cap) 2763 seq_puts(m, "HDCP2.2 "); 2764 2765 if (!hdcp_cap && !hdcp2_cap) 2766 seq_puts(m, "None"); 2767 2768 out: 2769 seq_puts(m, "\n"); 2770 } 2771 2772 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2773 { 2774 seq_puts(m, "\tHDCP version: "); 2775 if (connector->mst.dp) { 2776 __intel_hdcp_info(m, connector, true); 2777 seq_puts(m, "\tMST Hub HDCP version: "); 2778 } 2779 __intel_hdcp_info(m, connector, false); 2780 } 2781 2782 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2783 { 2784 struct intel_connector *connector = m->private; 2785 struct intel_display *display = to_intel_display(connector); 2786 int ret; 2787 2788 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2789 if (ret) 2790 return ret; 2791 2792 if (!connector->base.encoder || 2793 connector->base.status != connector_status_connected) { 2794 ret = -ENODEV; 2795 goto out; 2796 } 2797 2798 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2799 connector->base.base.id); 2800 __intel_hdcp_info(m, connector, false); 2801 2802 out: 2803 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2804 2805 return ret; 2806 } 2807 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2808 2809 static ssize_t intel_hdcp_force_14_write(struct file *file, 2810 const char __user *ubuf, 2811 size_t len, loff_t *offp) 2812 { 2813 struct seq_file *m = file->private_data; 2814 struct intel_connector *connector = m->private; 2815 struct intel_hdcp *hdcp = &connector->hdcp; 2816 bool force_hdcp14 = false; 2817 int ret; 2818 2819 if (len == 0) 2820 return 0; 2821 2822 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2823 if (ret < 0) 2824 return ret; 2825 2826 hdcp->force_hdcp14 = force_hdcp14; 2827 *offp += len; 2828 2829 return len; 2830 } 2831 2832 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2833 { 2834 struct intel_connector *connector = m->private; 2835 struct intel_display *display = to_intel_display(connector); 2836 struct intel_encoder *encoder = intel_attached_encoder(connector); 2837 struct intel_hdcp *hdcp = &connector->hdcp; 2838 struct drm_crtc *crtc; 2839 int ret; 2840 2841 if (!encoder) 2842 return -ENODEV; 2843 2844 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2845 if (ret) 2846 return ret; 2847 2848 crtc = connector->base.state->crtc; 2849 if (connector->base.status != connector_status_connected || !crtc) { 2850 ret = -ENODEV; 2851 goto out; 2852 } 2853 2854 seq_printf(m, "%s\n", 2855 str_yes_no(hdcp->force_hdcp14)); 2856 out: 2857 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2858 2859 return ret; 2860 } 2861 2862 static int intel_hdcp_force_14_open(struct inode *inode, 2863 struct file *file) 2864 { 2865 return single_open(file, intel_hdcp_force_14_show, 2866 inode->i_private); 2867 } 2868 2869 static const struct file_operations intel_hdcp_force_14_fops = { 2870 .owner = THIS_MODULE, 2871 .open = intel_hdcp_force_14_open, 2872 .read = seq_read, 2873 .llseek = seq_lseek, 2874 .release = single_release, 2875 .write = intel_hdcp_force_14_write 2876 }; 2877 2878 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2879 { 2880 struct dentry *root = connector->base.debugfs_entry; 2881 int connector_type = connector->base.connector_type; 2882 2883 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2884 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2885 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2886 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2887 connector, &intel_hdcp_sink_capability_fops); 2888 debugfs_create_file("i915_force_hdcp14", 0644, root, 2889 connector, &intel_hdcp_force_14_fops); 2890 } 2891 } 2892