1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/iopoll.h> 15 #include <linux/random.h> 16 17 #include <drm/display/drm_hdcp_helper.h> 18 #include <drm/drm_print.h> 19 #include <drm/intel/i915_component.h> 20 #include <drm/intel/intel_pcode_regs.h> 21 #include <drm/intel/step.h> 22 23 #include "intel_connector.h" 24 #include "intel_de.h" 25 #include "intel_display_jiffies.h" 26 #include "intel_display_power.h" 27 #include "intel_display_power_well.h" 28 #include "intel_display_regs.h" 29 #include "intel_display_rpm.h" 30 #include "intel_display_types.h" 31 #include "intel_dp_mst.h" 32 #include "intel_hdcp.h" 33 #include "intel_hdcp_gsc_message.h" 34 #include "intel_hdcp_regs.h" 35 #include "intel_hdcp_shim.h" 36 #include "intel_parent.h" 37 38 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 39 40 #define KEY_LOAD_TRIES 5 41 #define HDCP2_LC_RETRY_CNT 3 42 43 static void 44 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 45 struct intel_hdcp *hdcp, 46 bool enable) 47 { 48 struct intel_display *display = to_intel_display(encoder); 49 intel_reg_t rekey_reg; 50 u32 rekey_bit = 0; 51 52 /* Here we assume HDMI is in TMDS mode of operation */ 53 if (!intel_encoder_is_hdmi(encoder)) 54 return; 55 56 if (DISPLAY_VER(display) >= 30) { 57 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 58 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 59 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 60 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 61 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 62 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 63 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 64 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 65 rekey_bit = HDCP_LINE_REKEY_DISABLE; 66 } 67 68 if (rekey_bit) 69 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 70 } 71 72 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 73 struct intel_connector *connector) 74 { 75 struct intel_display *display = to_intel_display(state); 76 struct drm_dp_mst_topology_mgr *mgr; 77 struct drm_dp_mst_atomic_payload *payload; 78 struct drm_dp_mst_topology_state *mst_state; 79 80 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 81 if (!connector->mst.port) 82 return 0; 83 84 mgr = connector->mst.port->mgr; 85 mst_state = drm_atomic_get_new_mst_topology_state(&state->base, mgr); 86 if (!mst_state) { 87 drm_dbg_kms(display->drm, "MST topology still not created\n"); 88 return 0; 89 } 90 91 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 92 if (!payload) { 93 drm_dbg_kms(display->drm, "MST Payload not present\n"); 94 return 0; 95 } 96 97 return payload->vcpi; 98 } 99 100 /* 101 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 102 * content_type for all streams in DP MST topology because security f/w doesn't 103 * have any provision to mark content_type for each stream separately, it marks 104 * all available streams with the content_type proivided at the time of port 105 * authentication. This may prohibit the userspace to use type1 content on 106 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 107 * DP MST topology. Though it is not compulsory, security fw should change its 108 * policy to mark different content_types for different streams. 109 */ 110 static int 111 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 112 struct intel_digital_port *dig_port) 113 { 114 struct intel_display *display = to_intel_display(state); 115 struct drm_connector_list_iter conn_iter; 116 struct drm_connector_state *new_conn_state; 117 struct intel_digital_port *conn_dig_port; 118 struct intel_connector *connector; 119 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 120 bool enforce_type0 = false; 121 int k; 122 123 if (dig_port->hdcp.auth_status) 124 return 0; 125 126 data->k = 0; 127 128 if (!dig_port->hdcp.mst_type1_capable) 129 enforce_type0 = true; 130 131 drm_connector_list_iter_begin(display->drm, &conn_iter); 132 for_each_intel_connector_iter(connector, &conn_iter) { 133 if (connector->base.status == connector_status_disconnected) 134 continue; 135 136 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 137 continue; 138 139 conn_dig_port = intel_attached_dig_port(connector); 140 if (conn_dig_port != dig_port) 141 continue; 142 143 new_conn_state = drm_atomic_get_new_connector_state(&state->base, 144 &connector->base); 145 if (!new_conn_state || !new_conn_state->crtc) 146 continue; 147 148 if (drm_WARN_ON(display->drm, data->k >= INTEL_NUM_PIPES(display))) 149 return -EINVAL; 150 151 data->streams[data->k].stream_id = 152 intel_conn_to_vcpi(state, connector); 153 data->k++; 154 155 /* if there is only one active stream */ 156 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 157 break; 158 } 159 drm_connector_list_iter_end(&conn_iter); 160 161 if (drm_WARN_ON(display->drm, !data->k)) 162 return -EINVAL; 163 164 /* 165 * Apply common protection level across all streams in DP MST Topology. 166 * Use highest supported content type for all streams in DP MST Topology. 167 */ 168 for (k = 0; k < data->k; k++) 169 data->streams[k].stream_type = 170 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 171 172 return 0; 173 } 174 175 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 176 struct intel_connector *connector) 177 { 178 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 179 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 180 struct intel_hdcp *hdcp = &connector->hdcp; 181 182 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 183 return intel_hdcp_required_content_stream(state, dig_port); 184 185 data->k = 1; 186 data->streams[0].stream_id = 0; 187 data->streams[0].stream_type = hdcp->content_type; 188 189 return 0; 190 } 191 192 static 193 bool intel_hdcp_is_ksv_valid(u8 *ksv) 194 { 195 int i, ones = 0; 196 /* KSV has 20 1's and 20 0's */ 197 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 198 ones += hweight8(ksv[i]); 199 if (ones != 20) 200 return false; 201 202 return true; 203 } 204 205 static 206 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 207 const struct intel_hdcp_shim *shim, u8 *bksv) 208 { 209 struct intel_display *display = to_intel_display(dig_port); 210 int ret, i, tries = 2; 211 212 /* HDCP spec states that we must retry the bksv if it is invalid */ 213 for (i = 0; i < tries; i++) { 214 ret = shim->read_bksv(dig_port, bksv); 215 if (ret) 216 return ret; 217 if (intel_hdcp_is_ksv_valid(bksv)) 218 break; 219 } 220 if (i == tries) { 221 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 222 return -ENODEV; 223 } 224 225 return 0; 226 } 227 228 /* Is HDCP1.4 capable on Platform and Sink */ 229 static bool intel_hdcp_get_capability(struct intel_connector *connector) 230 { 231 struct intel_digital_port *dig_port; 232 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 233 bool capable = false; 234 u8 bksv[5]; 235 236 if (!intel_attached_encoder(connector)) 237 return capable; 238 239 dig_port = intel_attached_dig_port(connector); 240 241 if (!shim) 242 return capable; 243 244 if (shim->hdcp_get_capability) { 245 shim->hdcp_get_capability(dig_port, &capable); 246 } else { 247 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 248 capable = true; 249 } 250 251 return capable; 252 } 253 254 /* 255 * Check if the source has all the building blocks ready to make 256 * HDCP 2.2 work 257 */ 258 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 259 { 260 struct intel_display *display = to_intel_display(connector); 261 struct intel_hdcp *hdcp = &connector->hdcp; 262 263 /* I915 support for HDCP2.2 */ 264 if (!hdcp->hdcp2_supported) 265 return false; 266 267 /* If MTL+ make sure gsc is loaded and proxy is setup */ 268 if (USE_HDCP_GSC(display)) { 269 if (!intel_parent_hdcp_gsc_check_status(display)) 270 return false; 271 } 272 273 /* MEI/GSC interface is solid depending on which is used */ 274 mutex_lock(&display->hdcp.hdcp_mutex); 275 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 276 mutex_unlock(&display->hdcp.hdcp_mutex); 277 return false; 278 } 279 mutex_unlock(&display->hdcp.hdcp_mutex); 280 281 return true; 282 } 283 284 /* Is HDCP2.2 capable on Platform and Sink */ 285 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 286 { 287 struct intel_hdcp *hdcp = &connector->hdcp; 288 bool capable = false; 289 290 if (!intel_hdcp2_prerequisite(connector)) 291 return false; 292 293 /* Sink's capability for HDCP2.2 */ 294 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 295 296 return capable; 297 } 298 299 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 300 bool *hdcp_capable, 301 bool *hdcp2_capable) 302 { 303 struct intel_hdcp *hdcp = &connector->hdcp; 304 305 if (!hdcp->shim->get_remote_hdcp_capability) 306 return; 307 308 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 309 hdcp2_capable); 310 311 if (!intel_hdcp2_prerequisite(connector)) 312 *hdcp2_capable = false; 313 } 314 315 static bool intel_hdcp_in_use(struct intel_display *display, 316 enum transcoder cpu_transcoder, enum port port) 317 { 318 return intel_de_read(display, 319 HDCP_STATUS(display, cpu_transcoder, port)) & 320 HDCP_STATUS_ENC; 321 } 322 323 static bool intel_hdcp2_in_use(struct intel_display *display, 324 enum transcoder cpu_transcoder, enum port port) 325 { 326 return intel_de_read(display, 327 HDCP2_STATUS(display, cpu_transcoder, port)) & 328 LINK_ENCRYPTION_STATUS; 329 } 330 331 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 332 const struct intel_hdcp_shim *shim) 333 { 334 int ret, read_ret; 335 bool ksv_ready; 336 337 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 338 ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), 339 read_ret || ksv_ready, 340 100 * 1000, 5 * 1000 * 1000, false); 341 if (ret) 342 return ret; 343 if (read_ret) 344 return read_ret; 345 346 return 0; 347 } 348 349 static bool hdcp_key_loadable(struct intel_display *display) 350 { 351 enum i915_power_well_id id; 352 bool enabled = false; 353 354 /* 355 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 356 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 357 */ 358 if (display->platform.haswell || display->platform.broadwell) 359 id = HSW_DISP_PW_GLOBAL; 360 else 361 id = SKL_DISP_PW_1; 362 363 /* PG1 (power well #1) needs to be enabled */ 364 with_intel_display_rpm(display) 365 enabled = intel_display_power_well_is_enabled(display, id); 366 367 /* 368 * Another req for hdcp key loadability is enabled state of pll for 369 * cdclk. Without active crtc we won't land here. So we are assuming that 370 * cdclk is already on. 371 */ 372 373 return enabled; 374 } 375 376 static void intel_hdcp_clear_keys(struct intel_display *display) 377 { 378 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 379 intel_de_write(display, HDCP_KEY_STATUS, 380 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 381 } 382 383 static int intel_hdcp_load_keys(struct intel_display *display) 384 { 385 int ret; 386 u32 val; 387 388 val = intel_de_read(display, HDCP_KEY_STATUS); 389 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 390 return 0; 391 392 /* 393 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 394 * out of reset. So if Key is not already loaded, its an error state. 395 */ 396 if (display->platform.haswell || display->platform.broadwell) 397 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 398 return -ENXIO; 399 400 /* 401 * Initiate loading the HDCP key from fuses. 402 * 403 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 404 * version 9 platforms (minus BXT) differ in the key load trigger 405 * process from other platforms. These platforms use the GT Driver 406 * Mailbox interface. 407 */ 408 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 409 ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1); 410 if (ret) { 411 drm_err(display->drm, 412 "Failed to initiate HDCP key load (%d)\n", 413 ret); 414 return ret; 415 } 416 } else { 417 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 418 } 419 420 /* Wait for the keys to load (500us) */ 421 ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE, 422 HDCP_KEY_LOAD_DONE, 1, &val); 423 if (ret) 424 return ret; 425 else if (!(val & HDCP_KEY_LOAD_STATUS)) 426 return -ENXIO; 427 428 /* Send Aksv over to PCH display for use in authentication */ 429 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 430 431 return 0; 432 } 433 434 /* Returns updated SHA-1 index */ 435 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 436 { 437 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 438 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 439 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 440 return -ETIMEDOUT; 441 } 442 return 0; 443 } 444 445 static 446 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 447 enum transcoder cpu_transcoder, enum port port) 448 { 449 if (DISPLAY_VER(display) >= 12) { 450 switch (cpu_transcoder) { 451 case TRANSCODER_A: 452 return HDCP_TRANSA_REP_PRESENT | 453 HDCP_TRANSA_SHA1_M0; 454 case TRANSCODER_B: 455 return HDCP_TRANSB_REP_PRESENT | 456 HDCP_TRANSB_SHA1_M0; 457 case TRANSCODER_C: 458 return HDCP_TRANSC_REP_PRESENT | 459 HDCP_TRANSC_SHA1_M0; 460 case TRANSCODER_D: 461 return HDCP_TRANSD_REP_PRESENT | 462 HDCP_TRANSD_SHA1_M0; 463 default: 464 drm_err(display->drm, "Unknown transcoder %d\n", 465 cpu_transcoder); 466 return 0; 467 } 468 } 469 470 switch (port) { 471 case PORT_A: 472 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 473 case PORT_B: 474 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 475 case PORT_C: 476 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 477 case PORT_D: 478 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 479 case PORT_E: 480 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 481 default: 482 drm_err(display->drm, "Unknown port %d\n", port); 483 return 0; 484 } 485 } 486 487 static 488 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 489 const struct intel_hdcp_shim *shim, 490 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 491 { 492 struct intel_display *display = to_intel_display(connector); 493 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 494 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 495 enum port port = dig_port->base.port; 496 u32 vprime, sha_text, sha_leftovers, rep_ctl; 497 int ret, i, j, sha_idx; 498 499 /* Process V' values from the receiver */ 500 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 501 ret = shim->read_v_prime_part(dig_port, i, &vprime); 502 if (ret) 503 return ret; 504 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 505 } 506 507 /* 508 * We need to write the concatenation of all device KSVs, BINFO (DP) || 509 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 510 * stream is written via the HDCP_SHA_TEXT register in 32-bit 511 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 512 * index will keep track of our progress through the 64 bytes as well as 513 * helping us work the 40-bit KSVs through our 32-bit register. 514 * 515 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 516 */ 517 sha_idx = 0; 518 sha_text = 0; 519 sha_leftovers = 0; 520 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 521 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 522 for (i = 0; i < num_downstream; i++) { 523 unsigned int sha_empty; 524 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 525 526 /* Fill up the empty slots in sha_text and write it out */ 527 sha_empty = sizeof(sha_text) - sha_leftovers; 528 for (j = 0; j < sha_empty; j++) { 529 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 530 sha_text |= ksv[j] << off; 531 } 532 533 ret = intel_write_sha_text(display, sha_text); 534 if (ret < 0) 535 return ret; 536 537 /* Programming guide writes this every 64 bytes */ 538 sha_idx += sizeof(sha_text); 539 if (!(sha_idx % 64)) 540 intel_de_write(display, HDCP_REP_CTL, 541 rep_ctl | HDCP_SHA1_TEXT_32); 542 543 /* Store the leftover bytes from the ksv in sha_text */ 544 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 545 sha_text = 0; 546 for (j = 0; j < sha_leftovers; j++) 547 sha_text |= ksv[sha_empty + j] << 548 ((sizeof(sha_text) - j - 1) * 8); 549 550 /* 551 * If we still have room in sha_text for more data, continue. 552 * Otherwise, write it out immediately. 553 */ 554 if (sizeof(sha_text) > sha_leftovers) 555 continue; 556 557 ret = intel_write_sha_text(display, sha_text); 558 if (ret < 0) 559 return ret; 560 sha_leftovers = 0; 561 sha_text = 0; 562 sha_idx += sizeof(sha_text); 563 } 564 565 /* 566 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 567 * bytes are leftover from the last ksv, we might be able to fit them 568 * all in sha_text (first 2 cases), or we might need to split them up 569 * into 2 writes (last 2 cases). 570 */ 571 if (sha_leftovers == 0) { 572 /* Write 16 bits of text, 16 bits of M0 */ 573 intel_de_write(display, HDCP_REP_CTL, 574 rep_ctl | HDCP_SHA1_TEXT_16); 575 ret = intel_write_sha_text(display, 576 bstatus[0] << 8 | bstatus[1]); 577 if (ret < 0) 578 return ret; 579 sha_idx += sizeof(sha_text); 580 581 /* Write 32 bits of M0 */ 582 intel_de_write(display, HDCP_REP_CTL, 583 rep_ctl | HDCP_SHA1_TEXT_0); 584 ret = intel_write_sha_text(display, 0); 585 if (ret < 0) 586 return ret; 587 sha_idx += sizeof(sha_text); 588 589 /* Write 16 bits of M0 */ 590 intel_de_write(display, HDCP_REP_CTL, 591 rep_ctl | HDCP_SHA1_TEXT_16); 592 ret = intel_write_sha_text(display, 0); 593 if (ret < 0) 594 return ret; 595 sha_idx += sizeof(sha_text); 596 597 } else if (sha_leftovers == 1) { 598 /* Write 24 bits of text, 8 bits of M0 */ 599 intel_de_write(display, HDCP_REP_CTL, 600 rep_ctl | HDCP_SHA1_TEXT_24); 601 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 602 /* Only 24-bits of data, must be in the LSB */ 603 sha_text = (sha_text & 0xffffff00) >> 8; 604 ret = intel_write_sha_text(display, sha_text); 605 if (ret < 0) 606 return ret; 607 sha_idx += sizeof(sha_text); 608 609 /* Write 32 bits of M0 */ 610 intel_de_write(display, HDCP_REP_CTL, 611 rep_ctl | HDCP_SHA1_TEXT_0); 612 ret = intel_write_sha_text(display, 0); 613 if (ret < 0) 614 return ret; 615 sha_idx += sizeof(sha_text); 616 617 /* Write 24 bits of M0 */ 618 intel_de_write(display, HDCP_REP_CTL, 619 rep_ctl | HDCP_SHA1_TEXT_8); 620 ret = intel_write_sha_text(display, 0); 621 if (ret < 0) 622 return ret; 623 sha_idx += sizeof(sha_text); 624 625 } else if (sha_leftovers == 2) { 626 /* Write 32 bits of text */ 627 intel_de_write(display, HDCP_REP_CTL, 628 rep_ctl | HDCP_SHA1_TEXT_32); 629 sha_text |= bstatus[0] << 8 | bstatus[1]; 630 ret = intel_write_sha_text(display, sha_text); 631 if (ret < 0) 632 return ret; 633 sha_idx += sizeof(sha_text); 634 635 /* Write 64 bits of M0 */ 636 intel_de_write(display, HDCP_REP_CTL, 637 rep_ctl | HDCP_SHA1_TEXT_0); 638 for (i = 0; i < 2; i++) { 639 ret = intel_write_sha_text(display, 0); 640 if (ret < 0) 641 return ret; 642 sha_idx += sizeof(sha_text); 643 } 644 645 /* 646 * Terminate the SHA-1 stream by hand. For the other leftover 647 * cases this is appended by the hardware. 648 */ 649 intel_de_write(display, HDCP_REP_CTL, 650 rep_ctl | HDCP_SHA1_TEXT_32); 651 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 652 ret = intel_write_sha_text(display, sha_text); 653 if (ret < 0) 654 return ret; 655 sha_idx += sizeof(sha_text); 656 } else if (sha_leftovers == 3) { 657 /* Write 32 bits of text (filled from LSB) */ 658 intel_de_write(display, HDCP_REP_CTL, 659 rep_ctl | HDCP_SHA1_TEXT_32); 660 sha_text |= bstatus[0]; 661 ret = intel_write_sha_text(display, sha_text); 662 if (ret < 0) 663 return ret; 664 sha_idx += sizeof(sha_text); 665 666 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 667 intel_de_write(display, HDCP_REP_CTL, 668 rep_ctl | HDCP_SHA1_TEXT_8); 669 ret = intel_write_sha_text(display, bstatus[1]); 670 if (ret < 0) 671 return ret; 672 sha_idx += sizeof(sha_text); 673 674 /* Write 32 bits of M0 */ 675 intel_de_write(display, HDCP_REP_CTL, 676 rep_ctl | HDCP_SHA1_TEXT_0); 677 ret = intel_write_sha_text(display, 0); 678 if (ret < 0) 679 return ret; 680 sha_idx += sizeof(sha_text); 681 682 /* Write 8 bits of M0 */ 683 intel_de_write(display, HDCP_REP_CTL, 684 rep_ctl | HDCP_SHA1_TEXT_24); 685 ret = intel_write_sha_text(display, 0); 686 if (ret < 0) 687 return ret; 688 sha_idx += sizeof(sha_text); 689 } else { 690 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 691 sha_leftovers); 692 return -EINVAL; 693 } 694 695 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 696 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 697 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 698 ret = intel_write_sha_text(display, 0); 699 if (ret < 0) 700 return ret; 701 sha_idx += sizeof(sha_text); 702 } 703 704 /* 705 * Last write gets the length of the concatenation in bits. That is: 706 * - 5 bytes per device 707 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 708 */ 709 sha_text = (num_downstream * 5 + 10) * 8; 710 ret = intel_write_sha_text(display, sha_text); 711 if (ret < 0) 712 return ret; 713 714 /* Tell the HW we're done with the hash and wait for it to ACK */ 715 intel_de_write(display, HDCP_REP_CTL, 716 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 717 if (intel_de_wait_for_set_ms(display, HDCP_REP_CTL, 718 HDCP_SHA1_COMPLETE, 1)) { 719 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 720 return -ETIMEDOUT; 721 } 722 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 723 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 724 return -ENXIO; 725 } 726 727 return 0; 728 } 729 730 /* Implements Part 2 of the HDCP authorization procedure */ 731 static 732 int intel_hdcp_auth_downstream(struct intel_connector *connector) 733 { 734 struct intel_display *display = to_intel_display(connector); 735 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 736 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 737 u8 bstatus[2], num_downstream, *ksv_fifo; 738 int ret, i, tries = 3; 739 740 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 741 if (ret) { 742 drm_dbg_kms(display->drm, 743 "KSV list failed to become ready (%d)\n", ret); 744 return ret; 745 } 746 747 ret = shim->read_bstatus(dig_port, bstatus); 748 if (ret) 749 return ret; 750 751 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 752 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 753 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 754 return -EPERM; 755 } 756 757 /* 758 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 759 * the HDCP encryption. That implies that repeater can't have its own 760 * display. As there is no consumption of encrypted content in the 761 * repeater with 0 downstream devices, we are failing the 762 * authentication. 763 */ 764 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 765 if (num_downstream == 0) { 766 drm_dbg_kms(display->drm, 767 "Repeater with zero downstream devices\n"); 768 return -EINVAL; 769 } 770 771 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 772 if (!ksv_fifo) { 773 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 774 return -ENOMEM; 775 } 776 777 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 778 if (ret) 779 goto err; 780 781 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 782 num_downstream) > 0) { 783 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 784 ret = -EPERM; 785 goto err; 786 } 787 788 /* 789 * When V prime mismatches, DP Spec mandates re-read of 790 * V prime atleast twice. 791 */ 792 for (i = 0; i < tries; i++) { 793 ret = intel_hdcp_validate_v_prime(connector, shim, 794 ksv_fifo, num_downstream, 795 bstatus); 796 if (!ret) 797 break; 798 } 799 800 if (i == tries) { 801 drm_dbg_kms(display->drm, 802 "V Prime validation failed.(%d)\n", ret); 803 goto err; 804 } 805 806 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 807 num_downstream); 808 ret = 0; 809 err: 810 kfree(ksv_fifo); 811 return ret; 812 } 813 814 /* Implements Part 1 of the HDCP authorization procedure */ 815 static int intel_hdcp_auth(struct intel_connector *connector) 816 { 817 struct intel_display *display = to_intel_display(connector); 818 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 819 struct intel_hdcp *hdcp = &connector->hdcp; 820 const struct intel_hdcp_shim *shim = hdcp->shim; 821 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 822 enum port port = dig_port->base.port; 823 unsigned long r0_prime_gen_start; 824 int ret, i, tries = 2; 825 u32 val; 826 union { 827 u32 reg[2]; 828 u8 shim[DRM_HDCP_AN_LEN]; 829 } an; 830 union { 831 u32 reg[2]; 832 u8 shim[DRM_HDCP_KSV_LEN]; 833 } bksv; 834 union { 835 u32 reg; 836 u8 shim[DRM_HDCP_RI_LEN]; 837 } ri; 838 bool repeater_present, hdcp_capable; 839 840 /* 841 * Detects whether the display is HDCP capable. Although we check for 842 * valid Bksv below, the HDCP over DP spec requires that we check 843 * whether the display supports HDCP before we write An. For HDMI 844 * displays, this is not necessary. 845 */ 846 if (shim->hdcp_get_capability) { 847 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 848 if (ret) 849 return ret; 850 if (!hdcp_capable) { 851 drm_dbg_kms(display->drm, 852 "Panel is not HDCP capable\n"); 853 return -EINVAL; 854 } 855 } 856 857 /* Initialize An with 2 random values and acquire it */ 858 for (i = 0; i < 2; i++) 859 intel_de_write(display, 860 HDCP_ANINIT(display, cpu_transcoder, port), 861 get_random_u32()); 862 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 863 HDCP_CONF_CAPTURE_AN); 864 865 /* Wait for An to be acquired */ 866 if (intel_de_wait_for_set_ms(display, 867 HDCP_STATUS(display, cpu_transcoder, port), 868 HDCP_STATUS_AN_READY, 1)) { 869 drm_err(display->drm, "Timed out waiting for An\n"); 870 return -ETIMEDOUT; 871 } 872 873 an.reg[0] = intel_de_read(display, 874 HDCP_ANLO(display, cpu_transcoder, port)); 875 an.reg[1] = intel_de_read(display, 876 HDCP_ANHI(display, cpu_transcoder, port)); 877 ret = shim->write_an_aksv(dig_port, an.shim); 878 if (ret) 879 return ret; 880 881 r0_prime_gen_start = jiffies; 882 883 memset(&bksv, 0, sizeof(bksv)); 884 885 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 886 if (ret < 0) 887 return ret; 888 889 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 890 drm_err(display->drm, "BKSV is revoked\n"); 891 return -EPERM; 892 } 893 894 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 895 bksv.reg[0]); 896 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 897 bksv.reg[1]); 898 899 ret = shim->repeater_present(dig_port, &repeater_present); 900 if (ret) 901 return ret; 902 if (repeater_present) 903 intel_de_write(display, HDCP_REP_CTL, 904 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 905 906 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 907 if (ret) 908 return ret; 909 910 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 911 HDCP_CONF_AUTH_AND_ENC); 912 913 /* Wait for R0 ready */ 914 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 915 val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 916 100, 1000, false); 917 if (ret) { 918 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 919 return -ETIMEDOUT; 920 } 921 922 /* 923 * Wait for R0' to become available. The spec says 100ms from Aksv, but 924 * some monitors can take longer than this. We'll set the timeout at 925 * 300ms just to be sure. 926 * 927 * On DP, there's an R0_READY bit available but no such bit 928 * exists on HDMI. Since the upper-bound is the same, we'll just do 929 * the stupid thing instead of polling on one and not the other. 930 */ 931 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 932 933 tries = 3; 934 935 /* 936 * DP HDCP Spec mandates the two more reattempt to read R0, incase 937 * of R0 mismatch. 938 */ 939 for (i = 0; i < tries; i++) { 940 ri.reg = 0; 941 ret = shim->read_ri_prime(dig_port, ri.shim); 942 if (ret) 943 return ret; 944 intel_de_write(display, 945 HDCP_RPRIME(display, cpu_transcoder, port), 946 ri.reg); 947 948 /* Wait for Ri prime match */ 949 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 950 val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 951 100, 1000, false); 952 if (!ret) 953 break; 954 } 955 956 if (i == tries) { 957 drm_dbg_kms(display->drm, 958 "Timed out waiting for Ri prime match (%x)\n", val); 959 return -ETIMEDOUT; 960 } 961 962 /* Wait for encryption confirmation */ 963 if (intel_de_wait_for_set_ms(display, 964 HDCP_STATUS(display, cpu_transcoder, port), 965 HDCP_STATUS_ENC, 966 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 967 drm_err(display->drm, "Timed out waiting for encryption\n"); 968 return -ETIMEDOUT; 969 } 970 971 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 972 if (shim->stream_encryption) { 973 ret = shim->stream_encryption(connector, true); 974 if (ret) { 975 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 976 connector->base.base.id, connector->base.name); 977 return ret; 978 } 979 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 980 transcoder_name(hdcp->stream_transcoder)); 981 } 982 983 if (repeater_present) 984 return intel_hdcp_auth_downstream(connector); 985 986 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 987 return 0; 988 } 989 990 static int _intel_hdcp_disable(struct intel_connector *connector) 991 { 992 struct intel_display *display = to_intel_display(connector); 993 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 994 struct intel_hdcp *hdcp = &connector->hdcp; 995 enum port port = dig_port->base.port; 996 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 997 u32 repeater_ctl; 998 int ret; 999 1000 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 1001 connector->base.base.id, connector->base.name); 1002 1003 if (hdcp->shim->stream_encryption) { 1004 ret = hdcp->shim->stream_encryption(connector, false); 1005 if (ret) { 1006 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 1007 connector->base.base.id, connector->base.name); 1008 return ret; 1009 } 1010 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1011 transcoder_name(hdcp->stream_transcoder)); 1012 /* 1013 * If there are other connectors on this port using HDCP, 1014 * don't disable it until it disabled HDCP encryption for 1015 * all connectors in MST topology. 1016 */ 1017 if (dig_port->hdcp.num_streams > 0) 1018 return 0; 1019 } 1020 1021 hdcp->hdcp_encrypted = false; 1022 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1023 if (intel_de_wait_for_clear_ms(display, 1024 HDCP_STATUS(display, cpu_transcoder, port), 1025 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1026 drm_err(display->drm, 1027 "Failed to disable HDCP, timeout clearing status\n"); 1028 return -ETIMEDOUT; 1029 } 1030 1031 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1032 port); 1033 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1034 1035 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1036 if (ret) { 1037 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1038 return ret; 1039 } 1040 1041 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1042 return 0; 1043 } 1044 1045 static int intel_hdcp1_enable(struct intel_connector *connector) 1046 { 1047 struct intel_display *display = to_intel_display(connector); 1048 struct intel_hdcp *hdcp = &connector->hdcp; 1049 int i, ret, tries = 3; 1050 1051 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1052 connector->base.base.id, connector->base.name); 1053 1054 if (!hdcp_key_loadable(display)) { 1055 drm_err(display->drm, "HDCP key Load is not possible\n"); 1056 return -ENXIO; 1057 } 1058 1059 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1060 ret = intel_hdcp_load_keys(display); 1061 if (!ret) 1062 break; 1063 intel_hdcp_clear_keys(display); 1064 } 1065 if (ret) { 1066 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1067 ret); 1068 return ret; 1069 } 1070 1071 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1072 1073 /* Incase of authentication failures, HDCP spec expects reauth. */ 1074 for (i = 0; i < tries; i++) { 1075 ret = intel_hdcp_auth(connector); 1076 if (!ret) { 1077 hdcp->hdcp_encrypted = true; 1078 hdcp->hdcp2_encrypted = false; 1079 return 0; 1080 } 1081 1082 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1083 1084 /* Ensuring HDCP encryption and signalling are stopped. */ 1085 _intel_hdcp_disable(connector); 1086 } 1087 1088 drm_dbg_kms(display->drm, 1089 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1090 return ret; 1091 } 1092 1093 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1094 { 1095 return container_of(hdcp, struct intel_connector, hdcp); 1096 } 1097 1098 static void intel_hdcp_update_value(struct intel_connector *connector, 1099 u64 value, bool update_property) 1100 { 1101 struct intel_display *display = to_intel_display(connector); 1102 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1103 struct intel_hdcp *hdcp = &connector->hdcp; 1104 1105 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1106 1107 if (hdcp->value == value) 1108 return; 1109 1110 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1111 1112 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1113 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1114 dig_port->hdcp.num_streams--; 1115 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1116 dig_port->hdcp.num_streams++; 1117 } 1118 1119 hdcp->value = value; 1120 if (update_property) { 1121 drm_connector_get(&connector->base); 1122 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 1123 drm_connector_put(&connector->base); 1124 } 1125 } 1126 1127 /* Implements Part 3 of the HDCP authorization procedure */ 1128 static int intel_hdcp_check_link(struct intel_connector *connector) 1129 { 1130 struct intel_display *display = to_intel_display(connector); 1131 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1132 struct intel_hdcp *hdcp = &connector->hdcp; 1133 enum port port = dig_port->base.port; 1134 enum transcoder cpu_transcoder; 1135 int ret = 0; 1136 1137 mutex_lock(&hdcp->mutex); 1138 mutex_lock(&dig_port->hdcp.mutex); 1139 1140 cpu_transcoder = hdcp->cpu_transcoder; 1141 1142 /* Check_link valid only when HDCP1.4 is enabled */ 1143 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1144 !hdcp->hdcp_encrypted) { 1145 ret = -EINVAL; 1146 goto out; 1147 } 1148 1149 if (drm_WARN_ON(display->drm, 1150 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1151 drm_err(display->drm, 1152 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1153 connector->base.base.id, connector->base.name, 1154 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1155 ret = -ENXIO; 1156 intel_hdcp_update_value(connector, 1157 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1158 true); 1159 goto out; 1160 } 1161 1162 if (hdcp->shim->check_link(dig_port, connector)) { 1163 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1164 intel_hdcp_update_value(connector, 1165 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1166 } 1167 goto out; 1168 } 1169 1170 drm_dbg_kms(display->drm, 1171 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1172 connector->base.base.id, connector->base.name); 1173 1174 ret = _intel_hdcp_disable(connector); 1175 if (ret) { 1176 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1177 intel_hdcp_update_value(connector, 1178 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1179 true); 1180 goto out; 1181 } 1182 1183 ret = intel_hdcp1_enable(connector); 1184 if (ret) { 1185 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1186 intel_hdcp_update_value(connector, 1187 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1188 true); 1189 goto out; 1190 } 1191 1192 out: 1193 mutex_unlock(&dig_port->hdcp.mutex); 1194 mutex_unlock(&hdcp->mutex); 1195 return ret; 1196 } 1197 1198 static void intel_hdcp_prop_work(struct work_struct *work) 1199 { 1200 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1201 prop_work); 1202 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1203 struct intel_display *display = to_intel_display(connector); 1204 1205 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1206 mutex_lock(&hdcp->mutex); 1207 1208 /* 1209 * This worker is only used to flip between ENABLED/DESIRED. Either of 1210 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1211 * we're running just after hdcp has been disabled, so just exit 1212 */ 1213 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1214 drm_hdcp_update_content_protection(&connector->base, 1215 hdcp->value); 1216 1217 mutex_unlock(&hdcp->mutex); 1218 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1219 1220 drm_connector_put(&connector->base); 1221 } 1222 1223 bool is_hdcp_supported(struct intel_display *display, enum port port) 1224 { 1225 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1226 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1227 } 1228 1229 static int 1230 hdcp2_prepare_ake_init(struct intel_connector *connector, 1231 struct hdcp2_ake_init *ake_data) 1232 { 1233 struct intel_display *display = to_intel_display(connector); 1234 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1235 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1236 struct i915_hdcp_arbiter *arbiter; 1237 int ret; 1238 1239 mutex_lock(&display->hdcp.hdcp_mutex); 1240 arbiter = display->hdcp.arbiter; 1241 1242 if (!arbiter || !arbiter->ops) { 1243 mutex_unlock(&display->hdcp.hdcp_mutex); 1244 return -EINVAL; 1245 } 1246 1247 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1248 if (ret) 1249 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1250 ret); 1251 mutex_unlock(&display->hdcp.hdcp_mutex); 1252 1253 return ret; 1254 } 1255 1256 static int 1257 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1258 struct hdcp2_ake_send_cert *rx_cert, 1259 bool *paired, 1260 struct hdcp2_ake_no_stored_km *ek_pub_km, 1261 size_t *msg_sz) 1262 { 1263 struct intel_display *display = to_intel_display(connector); 1264 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1265 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1266 struct i915_hdcp_arbiter *arbiter; 1267 int ret; 1268 1269 mutex_lock(&display->hdcp.hdcp_mutex); 1270 arbiter = display->hdcp.arbiter; 1271 1272 if (!arbiter || !arbiter->ops) { 1273 mutex_unlock(&display->hdcp.hdcp_mutex); 1274 return -EINVAL; 1275 } 1276 1277 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1278 rx_cert, paired, 1279 ek_pub_km, msg_sz); 1280 if (ret < 0) 1281 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1282 ret); 1283 mutex_unlock(&display->hdcp.hdcp_mutex); 1284 1285 return ret; 1286 } 1287 1288 static int hdcp2_verify_hprime(struct intel_connector *connector, 1289 struct hdcp2_ake_send_hprime *rx_hprime) 1290 { 1291 struct intel_display *display = to_intel_display(connector); 1292 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1293 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1294 struct i915_hdcp_arbiter *arbiter; 1295 int ret; 1296 1297 mutex_lock(&display->hdcp.hdcp_mutex); 1298 arbiter = display->hdcp.arbiter; 1299 1300 if (!arbiter || !arbiter->ops) { 1301 mutex_unlock(&display->hdcp.hdcp_mutex); 1302 return -EINVAL; 1303 } 1304 1305 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1306 if (ret < 0) 1307 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1308 mutex_unlock(&display->hdcp.hdcp_mutex); 1309 1310 return ret; 1311 } 1312 1313 static int 1314 hdcp2_store_pairing_info(struct intel_connector *connector, 1315 struct hdcp2_ake_send_pairing_info *pairing_info) 1316 { 1317 struct intel_display *display = to_intel_display(connector); 1318 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1319 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1320 struct i915_hdcp_arbiter *arbiter; 1321 int ret; 1322 1323 mutex_lock(&display->hdcp.hdcp_mutex); 1324 arbiter = display->hdcp.arbiter; 1325 1326 if (!arbiter || !arbiter->ops) { 1327 mutex_unlock(&display->hdcp.hdcp_mutex); 1328 return -EINVAL; 1329 } 1330 1331 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1332 if (ret < 0) 1333 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1334 ret); 1335 mutex_unlock(&display->hdcp.hdcp_mutex); 1336 1337 return ret; 1338 } 1339 1340 static int 1341 hdcp2_prepare_lc_init(struct intel_connector *connector, 1342 struct hdcp2_lc_init *lc_init) 1343 { 1344 struct intel_display *display = to_intel_display(connector); 1345 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1346 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1347 struct i915_hdcp_arbiter *arbiter; 1348 int ret; 1349 1350 mutex_lock(&display->hdcp.hdcp_mutex); 1351 arbiter = display->hdcp.arbiter; 1352 1353 if (!arbiter || !arbiter->ops) { 1354 mutex_unlock(&display->hdcp.hdcp_mutex); 1355 return -EINVAL; 1356 } 1357 1358 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1359 if (ret < 0) 1360 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1361 ret); 1362 mutex_unlock(&display->hdcp.hdcp_mutex); 1363 1364 return ret; 1365 } 1366 1367 static int 1368 hdcp2_verify_lprime(struct intel_connector *connector, 1369 struct hdcp2_lc_send_lprime *rx_lprime) 1370 { 1371 struct intel_display *display = to_intel_display(connector); 1372 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1373 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1374 struct i915_hdcp_arbiter *arbiter; 1375 int ret; 1376 1377 mutex_lock(&display->hdcp.hdcp_mutex); 1378 arbiter = display->hdcp.arbiter; 1379 1380 if (!arbiter || !arbiter->ops) { 1381 mutex_unlock(&display->hdcp.hdcp_mutex); 1382 return -EINVAL; 1383 } 1384 1385 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1386 if (ret < 0) 1387 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1388 ret); 1389 mutex_unlock(&display->hdcp.hdcp_mutex); 1390 1391 return ret; 1392 } 1393 1394 static int hdcp2_prepare_skey(struct intel_connector *connector, 1395 struct hdcp2_ske_send_eks *ske_data) 1396 { 1397 struct intel_display *display = to_intel_display(connector); 1398 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1399 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1400 struct i915_hdcp_arbiter *arbiter; 1401 int ret; 1402 1403 mutex_lock(&display->hdcp.hdcp_mutex); 1404 arbiter = display->hdcp.arbiter; 1405 1406 if (!arbiter || !arbiter->ops) { 1407 mutex_unlock(&display->hdcp.hdcp_mutex); 1408 return -EINVAL; 1409 } 1410 1411 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1412 if (ret < 0) 1413 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1414 ret); 1415 mutex_unlock(&display->hdcp.hdcp_mutex); 1416 1417 return ret; 1418 } 1419 1420 static int 1421 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1422 struct hdcp2_rep_send_receiverid_list 1423 *rep_topology, 1424 struct hdcp2_rep_send_ack *rep_send_ack) 1425 { 1426 struct intel_display *display = to_intel_display(connector); 1427 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1428 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1429 struct i915_hdcp_arbiter *arbiter; 1430 int ret; 1431 1432 mutex_lock(&display->hdcp.hdcp_mutex); 1433 arbiter = display->hdcp.arbiter; 1434 1435 if (!arbiter || !arbiter->ops) { 1436 mutex_unlock(&display->hdcp.hdcp_mutex); 1437 return -EINVAL; 1438 } 1439 1440 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1441 data, 1442 rep_topology, 1443 rep_send_ack); 1444 if (ret < 0) 1445 drm_dbg_kms(display->drm, 1446 "Verify rep topology failed. %d\n", ret); 1447 mutex_unlock(&display->hdcp.hdcp_mutex); 1448 1449 return ret; 1450 } 1451 1452 static int 1453 hdcp2_verify_mprime(struct intel_connector *connector, 1454 struct hdcp2_rep_stream_ready *stream_ready) 1455 { 1456 struct intel_display *display = to_intel_display(connector); 1457 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1458 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1459 struct i915_hdcp_arbiter *arbiter; 1460 int ret; 1461 1462 mutex_lock(&display->hdcp.hdcp_mutex); 1463 arbiter = display->hdcp.arbiter; 1464 1465 if (!arbiter || !arbiter->ops) { 1466 mutex_unlock(&display->hdcp.hdcp_mutex); 1467 return -EINVAL; 1468 } 1469 1470 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1471 if (ret < 0) 1472 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1473 mutex_unlock(&display->hdcp.hdcp_mutex); 1474 1475 return ret; 1476 } 1477 1478 static int hdcp2_authenticate_port(struct intel_connector *connector) 1479 { 1480 struct intel_display *display = to_intel_display(connector); 1481 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1482 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1483 struct i915_hdcp_arbiter *arbiter; 1484 int ret; 1485 1486 mutex_lock(&display->hdcp.hdcp_mutex); 1487 arbiter = display->hdcp.arbiter; 1488 1489 if (!arbiter || !arbiter->ops) { 1490 mutex_unlock(&display->hdcp.hdcp_mutex); 1491 return -EINVAL; 1492 } 1493 1494 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1495 if (ret < 0) 1496 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1497 ret); 1498 mutex_unlock(&display->hdcp.hdcp_mutex); 1499 1500 return ret; 1501 } 1502 1503 static int hdcp2_close_session(struct intel_connector *connector) 1504 { 1505 struct intel_display *display = to_intel_display(connector); 1506 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1507 struct i915_hdcp_arbiter *arbiter; 1508 int ret; 1509 1510 mutex_lock(&display->hdcp.hdcp_mutex); 1511 arbiter = display->hdcp.arbiter; 1512 1513 if (!arbiter || !arbiter->ops) { 1514 mutex_unlock(&display->hdcp.hdcp_mutex); 1515 return -EINVAL; 1516 } 1517 1518 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1519 &dig_port->hdcp.port_data); 1520 mutex_unlock(&display->hdcp.hdcp_mutex); 1521 1522 return ret; 1523 } 1524 1525 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1526 { 1527 return hdcp2_close_session(connector); 1528 } 1529 1530 /* Authentication flow starts from here */ 1531 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1532 { 1533 struct intel_display *display = to_intel_display(connector); 1534 struct intel_digital_port *dig_port = 1535 intel_attached_dig_port(connector); 1536 struct intel_hdcp *hdcp = &connector->hdcp; 1537 union { 1538 struct hdcp2_ake_init ake_init; 1539 struct hdcp2_ake_send_cert send_cert; 1540 struct hdcp2_ake_no_stored_km no_stored_km; 1541 struct hdcp2_ake_send_hprime send_hprime; 1542 struct hdcp2_ake_send_pairing_info pairing_info; 1543 } msgs; 1544 const struct intel_hdcp_shim *shim = hdcp->shim; 1545 size_t size; 1546 int ret, i, max_retries; 1547 1548 /* Init for seq_num */ 1549 hdcp->seq_num_v = 0; 1550 hdcp->seq_num_m = 0; 1551 1552 if (intel_encoder_is_dp(&dig_port->base) || 1553 intel_encoder_is_mst(&dig_port->base)) 1554 max_retries = 10; 1555 else 1556 max_retries = 1; 1557 1558 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1559 if (ret < 0) 1560 return ret; 1561 1562 /* 1563 * Retry the first read and write to downstream at least 10 times 1564 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1565 * (dock decides to stop advertising hdcp2 capability for some reason). 1566 * The reason being that during suspend resume dock usually keeps the 1567 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1568 * big problem if the userspace just kept retrying with some delay while 1569 * it continues to play low value content but most userspace applications 1570 * end up throwing an error when it receives one from KMD. This makes 1571 * sure we give the dock and the sink devices to complete its power cycle 1572 * and then try HDCP authentication. The values of 10 and delay of 50ms 1573 * was decided based on multiple trial and errors. 1574 */ 1575 for (i = 0; i < max_retries; i++) { 1576 if (!intel_hdcp2_get_capability(connector)) { 1577 msleep(50); 1578 continue; 1579 } 1580 1581 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1582 sizeof(msgs.ake_init)); 1583 if (ret < 0) 1584 continue; 1585 1586 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1587 &msgs.send_cert, sizeof(msgs.send_cert)); 1588 if (ret > 0) 1589 break; 1590 } 1591 1592 if (ret < 0) 1593 return ret; 1594 1595 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1596 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1597 return -EINVAL; 1598 } 1599 1600 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1601 1602 if (drm_hdcp_check_ksvs_revoked(display->drm, 1603 msgs.send_cert.cert_rx.receiver_id, 1604 1) > 0) { 1605 drm_err(display->drm, "Receiver ID is revoked\n"); 1606 return -EPERM; 1607 } 1608 1609 /* 1610 * Here msgs.no_stored_km will hold msgs corresponding to the km 1611 * stored also. 1612 */ 1613 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1614 &hdcp->is_paired, 1615 &msgs.no_stored_km, &size); 1616 if (ret < 0) 1617 return ret; 1618 1619 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1620 if (ret < 0) 1621 return ret; 1622 1623 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1624 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1625 if (ret < 0) 1626 return ret; 1627 1628 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1629 if (ret < 0) 1630 return ret; 1631 1632 if (!hdcp->is_paired) { 1633 /* Pairing is required */ 1634 ret = shim->read_2_2_msg(connector, 1635 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1636 &msgs.pairing_info, 1637 sizeof(msgs.pairing_info)); 1638 if (ret < 0) 1639 return ret; 1640 1641 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1642 if (ret < 0) 1643 return ret; 1644 hdcp->is_paired = true; 1645 } 1646 1647 return 0; 1648 } 1649 1650 static int hdcp2_locality_check(struct intel_connector *connector) 1651 { 1652 struct intel_hdcp *hdcp = &connector->hdcp; 1653 union { 1654 struct hdcp2_lc_init lc_init; 1655 struct hdcp2_lc_send_lprime send_lprime; 1656 } msgs; 1657 const struct intel_hdcp_shim *shim = hdcp->shim; 1658 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1659 1660 for (i = 0; i < tries; i++) { 1661 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1662 if (ret < 0) 1663 continue; 1664 1665 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1666 sizeof(msgs.lc_init)); 1667 if (ret < 0) 1668 continue; 1669 1670 ret = shim->read_2_2_msg(connector, 1671 HDCP_2_2_LC_SEND_LPRIME, 1672 &msgs.send_lprime, 1673 sizeof(msgs.send_lprime)); 1674 if (ret < 0) 1675 continue; 1676 1677 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1678 if (!ret) 1679 break; 1680 } 1681 1682 return ret; 1683 } 1684 1685 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1686 { 1687 struct intel_hdcp *hdcp = &connector->hdcp; 1688 struct hdcp2_ske_send_eks send_eks; 1689 int ret; 1690 1691 ret = hdcp2_prepare_skey(connector, &send_eks); 1692 if (ret < 0) 1693 return ret; 1694 1695 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1696 sizeof(send_eks)); 1697 if (ret < 0) 1698 return ret; 1699 1700 return 0; 1701 } 1702 1703 static 1704 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1705 { 1706 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1707 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1708 struct intel_hdcp *hdcp = &connector->hdcp; 1709 union { 1710 struct hdcp2_rep_stream_manage stream_manage; 1711 struct hdcp2_rep_stream_ready stream_ready; 1712 } msgs; 1713 const struct intel_hdcp_shim *shim = hdcp->shim; 1714 int ret, streams_size_delta, i; 1715 1716 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1717 return -ERANGE; 1718 1719 /* Prepare RepeaterAuth_Stream_Manage msg */ 1720 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1721 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1722 1723 msgs.stream_manage.k = cpu_to_be16(data->k); 1724 1725 for (i = 0; i < data->k; i++) { 1726 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1727 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1728 } 1729 1730 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1731 sizeof(struct hdcp2_streamid_type); 1732 /* Send it to Repeater */ 1733 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1734 sizeof(msgs.stream_manage) - streams_size_delta); 1735 if (ret < 0) 1736 goto out; 1737 1738 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1739 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1740 if (ret < 0) 1741 goto out; 1742 1743 data->seq_num_m = hdcp->seq_num_m; 1744 1745 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1746 1747 out: 1748 hdcp->seq_num_m++; 1749 1750 return ret; 1751 } 1752 1753 static 1754 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1755 { 1756 struct intel_display *display = to_intel_display(connector); 1757 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1758 struct intel_hdcp *hdcp = &connector->hdcp; 1759 union { 1760 struct hdcp2_rep_send_receiverid_list recvid_list; 1761 struct hdcp2_rep_send_ack rep_ack; 1762 } msgs; 1763 const struct intel_hdcp_shim *shim = hdcp->shim; 1764 u32 seq_num_v, device_cnt; 1765 u8 *rx_info; 1766 int ret; 1767 1768 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1769 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1770 if (ret < 0) 1771 return ret; 1772 1773 rx_info = msgs.recvid_list.rx_info; 1774 1775 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1776 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1777 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1778 return -EINVAL; 1779 } 1780 1781 /* 1782 * MST topology is not Type 1 capable if it contains a downstream 1783 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1784 */ 1785 dig_port->hdcp.mst_type1_capable = 1786 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1787 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1788 1789 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1790 drm_dbg_kms(display->drm, 1791 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1792 return -EINVAL; 1793 } 1794 1795 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1796 seq_num_v = 1797 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1798 1799 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1800 drm_dbg_kms(display->drm, 1801 "Non zero Seq_num_v at first RecvId_List msg\n"); 1802 return -EINVAL; 1803 } 1804 1805 if (hdcp->hdcp2_encrypted && seq_num_v <= hdcp->seq_num_v) { 1806 /* Reauthenticate on Seq_num_v repeat or rollover */ 1807 drm_dbg_kms(display->drm, "Seq_num_v %s\n", 1808 seq_num_v == hdcp->seq_num_v ? "repeat" : "rollover"); 1809 return -EINVAL; 1810 } 1811 1812 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1813 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1814 if (drm_hdcp_check_ksvs_revoked(display->drm, 1815 msgs.recvid_list.receiver_ids, 1816 device_cnt) > 0) { 1817 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1818 return -EPERM; 1819 } 1820 1821 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1822 &msgs.recvid_list, 1823 &msgs.rep_ack); 1824 if (ret < 0) 1825 return ret; 1826 1827 hdcp->seq_num_v = seq_num_v; 1828 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1829 sizeof(msgs.rep_ack)); 1830 if (ret < 0) 1831 return ret; 1832 1833 return 0; 1834 } 1835 1836 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1837 { 1838 struct intel_display *display = to_intel_display(connector); 1839 struct intel_hdcp *hdcp = &connector->hdcp; 1840 const struct intel_hdcp_shim *shim = hdcp->shim; 1841 int ret; 1842 1843 ret = hdcp2_authentication_key_exchange(connector); 1844 if (ret < 0) { 1845 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1846 return ret; 1847 } 1848 1849 ret = hdcp2_locality_check(connector); 1850 if (ret < 0) { 1851 drm_dbg_kms(display->drm, 1852 "Locality Check failed. Err : %d\n", ret); 1853 return ret; 1854 } 1855 1856 ret = hdcp2_session_key_exchange(connector); 1857 if (ret < 0) { 1858 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1859 return ret; 1860 } 1861 1862 if (shim->config_stream_type) { 1863 ret = shim->config_stream_type(connector, 1864 hdcp->is_repeater, 1865 hdcp->content_type); 1866 if (ret < 0) 1867 return ret; 1868 } 1869 1870 if (hdcp->is_repeater) { 1871 ret = hdcp2_authenticate_repeater_topology(connector); 1872 if (ret < 0) { 1873 drm_dbg_kms(display->drm, 1874 "Repeater Auth Failed. Err: %d\n", ret); 1875 return ret; 1876 } 1877 } 1878 1879 return ret; 1880 } 1881 1882 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1883 { 1884 struct intel_display *display = to_intel_display(connector); 1885 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1886 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1887 struct intel_hdcp *hdcp = &connector->hdcp; 1888 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1889 enum port port = dig_port->base.port; 1890 int ret = 0; 1891 1892 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1893 LINK_ENCRYPTION_STATUS)) { 1894 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1895 connector->base.base.id, connector->base.name); 1896 ret = -EPERM; 1897 goto link_recover; 1898 } 1899 1900 if (hdcp->shim->stream_2_2_encryption) { 1901 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1902 if (ret) { 1903 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1904 connector->base.base.id, connector->base.name); 1905 return ret; 1906 } 1907 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1908 transcoder_name(hdcp->stream_transcoder)); 1909 } 1910 1911 return 0; 1912 1913 link_recover: 1914 if (hdcp2_deauthenticate_port(connector) < 0) 1915 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1916 1917 dig_port->hdcp.auth_status = false; 1918 data->k = 0; 1919 1920 return ret; 1921 } 1922 1923 static int hdcp2_enable_encryption(struct intel_connector *connector) 1924 { 1925 struct intel_display *display = to_intel_display(connector); 1926 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1927 struct intel_hdcp *hdcp = &connector->hdcp; 1928 enum port port = dig_port->base.port; 1929 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1930 int ret; 1931 1932 drm_WARN_ON(display->drm, 1933 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1934 LINK_ENCRYPTION_STATUS); 1935 if (hdcp->shim->toggle_signalling) { 1936 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1937 true); 1938 if (ret) { 1939 drm_err(display->drm, 1940 "Failed to enable HDCP signalling. %d\n", 1941 ret); 1942 return ret; 1943 } 1944 } 1945 1946 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1947 LINK_AUTH_STATUS) 1948 /* Link is Authenticated. Now set for Encryption */ 1949 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1950 0, CTL_LINK_ENCRYPTION_REQ); 1951 1952 ret = intel_de_wait_for_set_ms(display, 1953 HDCP2_STATUS(display, cpu_transcoder, port), 1954 LINK_ENCRYPTION_STATUS, 1955 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1956 dig_port->hdcp.auth_status = true; 1957 1958 return ret; 1959 } 1960 1961 static int hdcp2_disable_encryption(struct intel_connector *connector) 1962 { 1963 struct intel_display *display = to_intel_display(connector); 1964 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1965 struct intel_hdcp *hdcp = &connector->hdcp; 1966 enum port port = dig_port->base.port; 1967 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1968 int ret; 1969 1970 drm_WARN_ON(display->drm, 1971 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1972 LINK_ENCRYPTION_STATUS)); 1973 1974 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1975 CTL_LINK_ENCRYPTION_REQ, 0); 1976 1977 ret = intel_de_wait_for_clear_ms(display, 1978 HDCP2_STATUS(display, cpu_transcoder, port), 1979 LINK_ENCRYPTION_STATUS, 1980 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1981 if (ret == -ETIMEDOUT) 1982 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1983 1984 if (hdcp->shim->toggle_signalling) { 1985 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1986 false); 1987 if (ret) { 1988 drm_err(display->drm, 1989 "Failed to disable HDCP signalling. %d\n", 1990 ret); 1991 return ret; 1992 } 1993 } 1994 1995 return ret; 1996 } 1997 1998 static int 1999 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 2000 { 2001 struct intel_display *display = to_intel_display(connector); 2002 int i, tries = 3, ret; 2003 2004 if (!connector->hdcp.is_repeater) 2005 return 0; 2006 2007 for (i = 0; i < tries; i++) { 2008 ret = _hdcp2_propagate_stream_management_info(connector); 2009 if (!ret) 2010 break; 2011 2012 /* Lets restart the auth incase of seq_num_m roll over */ 2013 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2014 drm_dbg_kms(display->drm, 2015 "seq_num_m roll over.(%d)\n", ret); 2016 break; 2017 } 2018 2019 drm_dbg_kms(display->drm, 2020 "HDCP2 stream management %d of %d Failed.(%d)\n", 2021 i + 1, tries, ret); 2022 } 2023 2024 return ret; 2025 } 2026 2027 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2028 struct intel_connector *connector) 2029 { 2030 struct intel_display *display = to_intel_display(connector); 2031 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2032 int ret = 0, i, tries = 3; 2033 2034 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2035 ret = hdcp2_authenticate_sink(connector); 2036 if (!ret) { 2037 ret = intel_hdcp_prepare_streams(state, connector); 2038 if (ret) { 2039 drm_dbg_kms(display->drm, 2040 "Prepare stream failed.(%d)\n", 2041 ret); 2042 break; 2043 } 2044 2045 ret = hdcp2_propagate_stream_management_info(connector); 2046 if (ret) { 2047 drm_dbg_kms(display->drm, 2048 "Stream management failed.(%d)\n", 2049 ret); 2050 break; 2051 } 2052 2053 ret = hdcp2_authenticate_port(connector); 2054 if (!ret) 2055 break; 2056 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2057 ret); 2058 } 2059 2060 /* Clearing the mei hdcp session */ 2061 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2062 i + 1, tries, ret); 2063 if (hdcp2_deauthenticate_port(connector) < 0) 2064 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2065 } 2066 2067 if (!ret && !dig_port->hdcp.auth_status) { 2068 /* 2069 * Ensuring the required 200mSec min time interval between 2070 * Session Key Exchange and encryption. 2071 */ 2072 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2073 ret = hdcp2_enable_encryption(connector); 2074 if (ret < 0) { 2075 drm_dbg_kms(display->drm, 2076 "Encryption Enable Failed.(%d)\n", ret); 2077 if (hdcp2_deauthenticate_port(connector) < 0) 2078 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2079 } 2080 } 2081 2082 if (!ret) 2083 ret = hdcp2_enable_stream_encryption(connector); 2084 2085 return ret; 2086 } 2087 2088 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2089 struct intel_connector *connector) 2090 { 2091 struct intel_display *display = to_intel_display(connector); 2092 struct intel_hdcp *hdcp = &connector->hdcp; 2093 int ret; 2094 2095 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2096 connector->base.base.id, connector->base.name, 2097 hdcp->content_type); 2098 2099 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2100 2101 ret = hdcp2_authenticate_and_encrypt(state, connector); 2102 if (ret) { 2103 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2104 hdcp->content_type, ret); 2105 return ret; 2106 } 2107 2108 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2109 connector->base.base.id, connector->base.name, 2110 hdcp->content_type); 2111 2112 hdcp->hdcp2_encrypted = true; 2113 hdcp->hdcp_encrypted = false; 2114 return 0; 2115 } 2116 2117 static int 2118 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2119 { 2120 struct intel_display *display = to_intel_display(connector); 2121 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2122 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2123 struct intel_hdcp *hdcp = &connector->hdcp; 2124 int ret; 2125 2126 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2127 connector->base.base.id, connector->base.name); 2128 2129 if (hdcp->shim->stream_2_2_encryption) { 2130 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2131 if (ret) { 2132 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2133 connector->base.base.id, connector->base.name); 2134 return ret; 2135 } 2136 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2137 transcoder_name(hdcp->stream_transcoder)); 2138 2139 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2140 return 0; 2141 } 2142 2143 ret = hdcp2_disable_encryption(connector); 2144 2145 if (hdcp2_deauthenticate_port(connector) < 0) 2146 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2147 2148 connector->hdcp.hdcp2_encrypted = false; 2149 dig_port->hdcp.auth_status = false; 2150 data->k = 0; 2151 2152 return ret; 2153 } 2154 2155 /* Implements the Link Integrity Check for HDCP2.2 */ 2156 static int intel_hdcp2_check_link(struct intel_connector *connector) 2157 { 2158 struct intel_display *display = to_intel_display(connector); 2159 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2160 struct intel_hdcp *hdcp = &connector->hdcp; 2161 enum port port = dig_port->base.port; 2162 enum transcoder cpu_transcoder; 2163 int ret = 0; 2164 2165 mutex_lock(&hdcp->mutex); 2166 mutex_lock(&dig_port->hdcp.mutex); 2167 cpu_transcoder = hdcp->cpu_transcoder; 2168 2169 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2170 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2171 !hdcp->hdcp2_encrypted) { 2172 ret = -EINVAL; 2173 goto out; 2174 } 2175 2176 if (drm_WARN_ON(display->drm, 2177 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2178 drm_err(display->drm, 2179 "HDCP2.2 link stopped the encryption, %x\n", 2180 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2181 ret = -ENXIO; 2182 _intel_hdcp2_disable(connector, true); 2183 intel_hdcp_update_value(connector, 2184 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2185 true); 2186 goto out; 2187 } 2188 2189 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2190 if (ret == HDCP_LINK_PROTECTED) { 2191 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2192 intel_hdcp_update_value(connector, 2193 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2194 true); 2195 } 2196 goto out; 2197 } 2198 2199 if (ret == HDCP_TOPOLOGY_CHANGE) { 2200 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2201 goto out; 2202 2203 drm_dbg_kms(display->drm, 2204 "HDCP2.2 Downstream topology change\n"); 2205 2206 ret = hdcp2_authenticate_repeater_topology(connector); 2207 if (!ret) { 2208 intel_hdcp_update_value(connector, 2209 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2210 true); 2211 goto out; 2212 } 2213 2214 drm_dbg_kms(display->drm, 2215 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2216 connector->base.base.id, connector->base.name, 2217 ret); 2218 } else { 2219 drm_dbg_kms(display->drm, 2220 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2221 connector->base.base.id, connector->base.name); 2222 } 2223 2224 ret = _intel_hdcp2_disable(connector, true); 2225 if (ret) { 2226 drm_err(display->drm, 2227 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2228 connector->base.base.id, connector->base.name, ret); 2229 intel_hdcp_update_value(connector, 2230 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2231 goto out; 2232 } 2233 2234 intel_hdcp_update_value(connector, 2235 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2236 out: 2237 mutex_unlock(&dig_port->hdcp.mutex); 2238 mutex_unlock(&hdcp->mutex); 2239 return ret; 2240 } 2241 2242 static void intel_hdcp_check_work(struct work_struct *work) 2243 { 2244 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2245 struct intel_hdcp, 2246 check_work); 2247 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2248 struct intel_display *display = to_intel_display(connector); 2249 2250 if (drm_connector_is_unregistered(&connector->base)) 2251 return; 2252 2253 if (!hdcp->force_hdcp14 && !intel_hdcp2_check_link(connector)) 2254 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2255 DRM_HDCP2_CHECK_PERIOD_MS); 2256 else if (!intel_hdcp_check_link(connector)) 2257 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2258 DRM_HDCP_CHECK_PERIOD_MS); 2259 } 2260 2261 static int i915_hdcp_component_bind(struct device *drv_kdev, 2262 struct device *mei_kdev, void *data) 2263 { 2264 struct intel_display *display = to_intel_display(drv_kdev); 2265 2266 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2267 mutex_lock(&display->hdcp.hdcp_mutex); 2268 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2269 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2270 mutex_unlock(&display->hdcp.hdcp_mutex); 2271 2272 return 0; 2273 } 2274 2275 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2276 struct device *mei_kdev, void *data) 2277 { 2278 struct intel_display *display = to_intel_display(drv_kdev); 2279 2280 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2281 mutex_lock(&display->hdcp.hdcp_mutex); 2282 display->hdcp.arbiter = NULL; 2283 mutex_unlock(&display->hdcp.hdcp_mutex); 2284 } 2285 2286 static const struct component_ops i915_hdcp_ops = { 2287 .bind = i915_hdcp_component_bind, 2288 .unbind = i915_hdcp_component_unbind, 2289 }; 2290 2291 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2292 { 2293 switch (port) { 2294 case PORT_A: 2295 return HDCP_DDI_A; 2296 case PORT_B ... PORT_F: 2297 return (enum hdcp_ddi)port; 2298 default: 2299 return HDCP_DDI_INVALID_PORT; 2300 } 2301 } 2302 2303 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2304 { 2305 switch (cpu_transcoder) { 2306 case TRANSCODER_A ... TRANSCODER_D: 2307 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2308 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2309 return HDCP_INVALID_TRANSCODER; 2310 } 2311 } 2312 2313 static int initialize_hdcp_port_data(struct intel_connector *connector, 2314 struct intel_digital_port *dig_port, 2315 const struct intel_hdcp_shim *shim) 2316 { 2317 struct intel_display *display = to_intel_display(connector); 2318 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2319 enum port port = dig_port->base.port; 2320 2321 if (DISPLAY_VER(display) < 12) 2322 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2323 else 2324 /* 2325 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2326 * with zero(INVALID PORT index). 2327 */ 2328 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2329 2330 /* 2331 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2332 * is initialized to zero (invalid transcoder index). This will be 2333 * retained for <Gen12 forever. 2334 */ 2335 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2336 2337 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2338 data->protocol = (u8)shim->protocol; 2339 2340 if (!data->streams) 2341 data->streams = kzalloc_objs(struct hdcp2_streamid_type, 2342 INTEL_NUM_PIPES(display)); 2343 if (!data->streams) { 2344 drm_err(display->drm, "Out of Memory\n"); 2345 return -ENOMEM; 2346 } 2347 2348 return 0; 2349 } 2350 2351 static bool is_hdcp2_supported(struct intel_display *display) 2352 { 2353 if (USE_HDCP_GSC(display)) 2354 return true; 2355 2356 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2357 return false; 2358 2359 return DISPLAY_VER(display) >= 10 || 2360 display->platform.kabylake || 2361 display->platform.coffeelake || 2362 display->platform.cometlake; 2363 } 2364 2365 void intel_hdcp_component_init(struct intel_display *display) 2366 { 2367 int ret; 2368 2369 if (!is_hdcp2_supported(display)) 2370 return; 2371 2372 mutex_lock(&display->hdcp.hdcp_mutex); 2373 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2374 2375 display->hdcp.comp_added = true; 2376 mutex_unlock(&display->hdcp.hdcp_mutex); 2377 if (USE_HDCP_GSC(display)) 2378 ret = intel_hdcp_gsc_init(display); 2379 else 2380 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2381 I915_COMPONENT_HDCP); 2382 2383 if (ret < 0) { 2384 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2385 ret); 2386 mutex_lock(&display->hdcp.hdcp_mutex); 2387 display->hdcp.comp_added = false; 2388 mutex_unlock(&display->hdcp.hdcp_mutex); 2389 return; 2390 } 2391 } 2392 2393 static void intel_hdcp2_init(struct intel_connector *connector, 2394 struct intel_digital_port *dig_port, 2395 const struct intel_hdcp_shim *shim) 2396 { 2397 struct intel_display *display = to_intel_display(connector); 2398 struct intel_hdcp *hdcp = &connector->hdcp; 2399 int ret; 2400 2401 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2402 if (ret) { 2403 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2404 return; 2405 } 2406 2407 hdcp->hdcp2_supported = true; 2408 } 2409 2410 int intel_hdcp_init(struct intel_connector *connector, 2411 struct intel_digital_port *dig_port, 2412 const struct intel_hdcp_shim *shim) 2413 { 2414 struct intel_display *display = to_intel_display(connector); 2415 struct intel_hdcp *hdcp = &connector->hdcp; 2416 int ret; 2417 2418 if (!shim) 2419 return -EINVAL; 2420 2421 if (is_hdcp2_supported(display)) 2422 intel_hdcp2_init(connector, dig_port, shim); 2423 2424 ret = drm_connector_attach_content_protection_property(&connector->base, 2425 hdcp->hdcp2_supported); 2426 if (ret) { 2427 hdcp->hdcp2_supported = false; 2428 kfree(dig_port->hdcp.port_data.streams); 2429 return ret; 2430 } 2431 2432 hdcp->shim = shim; 2433 mutex_init(&hdcp->mutex); 2434 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2435 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2436 init_waitqueue_head(&hdcp->cp_irq_queue); 2437 2438 return 0; 2439 } 2440 2441 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2442 struct intel_encoder *encoder, 2443 const struct intel_crtc_state *pipe_config, 2444 const struct drm_connector_state *conn_state) 2445 { 2446 struct intel_display *display = to_intel_display(encoder); 2447 struct intel_connector *connector = 2448 to_intel_connector(conn_state->connector); 2449 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2450 struct intel_hdcp *hdcp = &connector->hdcp; 2451 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2452 int ret = -EINVAL; 2453 2454 if (!hdcp->shim) 2455 return -ENOENT; 2456 2457 mutex_lock(&hdcp->mutex); 2458 mutex_lock(&dig_port->hdcp.mutex); 2459 drm_WARN_ON(display->drm, 2460 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2461 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2462 2463 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2464 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2465 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2466 } else { 2467 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2468 hdcp->stream_transcoder = INVALID_TRANSCODER; 2469 } 2470 2471 if (DISPLAY_VER(display) >= 12) 2472 dig_port->hdcp.port_data.hdcp_transcoder = 2473 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2474 2475 /* 2476 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2477 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2478 */ 2479 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2480 ret = _intel_hdcp2_enable(state, connector); 2481 if (!ret) 2482 check_link_interval = 2483 DRM_HDCP2_CHECK_PERIOD_MS; 2484 } 2485 2486 if (hdcp->force_hdcp14) 2487 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2488 2489 /* 2490 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2491 * be attempted. 2492 */ 2493 if (ret && intel_hdcp_get_capability(connector) && 2494 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2495 ret = intel_hdcp1_enable(connector); 2496 } 2497 2498 if (!ret) { 2499 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2500 check_link_interval); 2501 intel_hdcp_update_value(connector, 2502 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2503 true); 2504 } 2505 2506 mutex_unlock(&dig_port->hdcp.mutex); 2507 mutex_unlock(&hdcp->mutex); 2508 return ret; 2509 } 2510 2511 void intel_hdcp_enable(struct intel_atomic_state *state, 2512 struct intel_encoder *encoder, 2513 const struct intel_crtc_state *crtc_state, 2514 const struct drm_connector_state *conn_state) 2515 { 2516 struct intel_connector *connector = 2517 to_intel_connector(conn_state->connector); 2518 struct intel_hdcp *hdcp = &connector->hdcp; 2519 2520 /* 2521 * Enable hdcp if it's desired or if userspace is enabled and 2522 * driver set its state to undesired 2523 */ 2524 if (conn_state->content_protection == 2525 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2526 (conn_state->content_protection == 2527 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2528 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2529 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2530 } 2531 2532 int intel_hdcp_disable(struct intel_connector *connector) 2533 { 2534 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2535 struct intel_hdcp *hdcp = &connector->hdcp; 2536 int ret = 0; 2537 2538 if (!hdcp->shim) 2539 return -ENOENT; 2540 2541 mutex_lock(&hdcp->mutex); 2542 mutex_lock(&dig_port->hdcp.mutex); 2543 2544 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2545 goto out; 2546 2547 intel_hdcp_update_value(connector, 2548 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2549 if (hdcp->hdcp2_encrypted) 2550 ret = _intel_hdcp2_disable(connector, false); 2551 else if (hdcp->hdcp_encrypted) 2552 ret = _intel_hdcp_disable(connector); 2553 2554 out: 2555 mutex_unlock(&dig_port->hdcp.mutex); 2556 mutex_unlock(&hdcp->mutex); 2557 cancel_delayed_work_sync(&hdcp->check_work); 2558 return ret; 2559 } 2560 2561 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2562 struct intel_encoder *encoder, 2563 const struct intel_crtc_state *crtc_state, 2564 const struct drm_connector_state *conn_state) 2565 { 2566 struct intel_connector *connector = 2567 to_intel_connector(conn_state->connector); 2568 struct intel_hdcp *hdcp = &connector->hdcp; 2569 bool content_protection_type_changed, desired_and_not_enabled = false; 2570 struct intel_display *display = to_intel_display(connector); 2571 2572 if (!connector->hdcp.shim) 2573 return; 2574 2575 content_protection_type_changed = 2576 (conn_state->hdcp_content_type != hdcp->content_type && 2577 conn_state->content_protection != 2578 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2579 2580 /* 2581 * During the HDCP encryption session if Type change is requested, 2582 * disable the HDCP and re-enable it with new TYPE value. 2583 */ 2584 if (conn_state->content_protection == 2585 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2586 content_protection_type_changed) 2587 intel_hdcp_disable(connector); 2588 2589 /* 2590 * Mark the hdcp state as DESIRED after the hdcp disable of type 2591 * change procedure. 2592 */ 2593 if (content_protection_type_changed) { 2594 mutex_lock(&hdcp->mutex); 2595 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2596 drm_connector_get(&connector->base); 2597 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2598 drm_connector_put(&connector->base); 2599 mutex_unlock(&hdcp->mutex); 2600 } 2601 2602 if (conn_state->content_protection == 2603 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2604 mutex_lock(&hdcp->mutex); 2605 /* Avoid enabling hdcp, if it already ENABLED */ 2606 desired_and_not_enabled = 2607 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2608 mutex_unlock(&hdcp->mutex); 2609 /* 2610 * If HDCP already ENABLED and CP property is DESIRED, schedule 2611 * prop_work to update correct CP property to user space. 2612 */ 2613 if (!desired_and_not_enabled && !content_protection_type_changed) { 2614 drm_connector_get(&connector->base); 2615 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2616 drm_connector_put(&connector->base); 2617 2618 } 2619 } 2620 2621 if (desired_and_not_enabled || content_protection_type_changed) 2622 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2623 } 2624 2625 void intel_hdcp_cancel_works(struct intel_connector *connector) 2626 { 2627 if (!connector->hdcp.shim) 2628 return; 2629 2630 cancel_delayed_work_sync(&connector->hdcp.check_work); 2631 cancel_work_sync(&connector->hdcp.prop_work); 2632 } 2633 2634 void intel_hdcp_component_fini(struct intel_display *display) 2635 { 2636 mutex_lock(&display->hdcp.hdcp_mutex); 2637 if (!display->hdcp.comp_added) { 2638 mutex_unlock(&display->hdcp.hdcp_mutex); 2639 return; 2640 } 2641 2642 display->hdcp.comp_added = false; 2643 mutex_unlock(&display->hdcp.hdcp_mutex); 2644 2645 if (USE_HDCP_GSC(display)) 2646 intel_hdcp_gsc_fini(display); 2647 else 2648 component_del(display->drm->dev, &i915_hdcp_ops); 2649 } 2650 2651 void intel_hdcp_cleanup(struct intel_connector *connector) 2652 { 2653 struct intel_hdcp *hdcp = &connector->hdcp; 2654 2655 if (!hdcp->shim) 2656 return; 2657 2658 /* 2659 * If the connector is registered, it's possible userspace could kick 2660 * off another HDCP enable, which would re-spawn the workers. 2661 */ 2662 drm_WARN_ON(connector->base.dev, 2663 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2664 2665 /* 2666 * Now that the connector is not registered, check_work won't be run, 2667 * but cancel any outstanding instances of it 2668 */ 2669 cancel_delayed_work_sync(&hdcp->check_work); 2670 2671 /* 2672 * We don't cancel prop_work in the same way as check_work since it 2673 * requires connection_mutex which could be held while calling this 2674 * function. Instead, we rely on the connector references grabbed before 2675 * scheduling prop_work to ensure the connector is alive when prop_work 2676 * is run. So if we're in the destroy path (which is where this 2677 * function should be called), we're "guaranteed" that prop_work is not 2678 * active (tl;dr This Should Never Happen). 2679 */ 2680 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2681 2682 mutex_lock(&hdcp->mutex); 2683 hdcp->shim = NULL; 2684 mutex_unlock(&hdcp->mutex); 2685 } 2686 2687 void intel_hdcp_atomic_check(struct drm_connector *connector, 2688 struct drm_connector_state *old_state, 2689 struct drm_connector_state *new_state) 2690 { 2691 u64 old_cp = old_state->content_protection; 2692 u64 new_cp = new_state->content_protection; 2693 struct drm_crtc_state *crtc_state; 2694 2695 if (!new_state->crtc) { 2696 /* 2697 * If the connector is being disabled with CP enabled, mark it 2698 * desired so it's re-enabled when the connector is brought back 2699 */ 2700 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2701 new_state->content_protection = 2702 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2703 return; 2704 } 2705 2706 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2707 new_state->crtc); 2708 /* 2709 * Fix the HDCP uapi content protection state in case of modeset. 2710 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2711 * need to be sent if there is transition from ENABLED->DESIRED. 2712 */ 2713 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2714 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2715 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2716 new_state->content_protection = 2717 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2718 2719 /* 2720 * Nothing to do if the state didn't change, or HDCP was activated since 2721 * the last commit. And also no change in hdcp content type. 2722 */ 2723 if (old_cp == new_cp || 2724 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2725 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2726 if (old_state->hdcp_content_type == 2727 new_state->hdcp_content_type) 2728 return; 2729 } 2730 2731 crtc_state->mode_changed = true; 2732 } 2733 2734 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2735 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2736 { 2737 struct intel_hdcp *hdcp = &connector->hdcp; 2738 struct intel_display *display = to_intel_display(connector); 2739 2740 if (!hdcp->shim) 2741 return; 2742 2743 atomic_inc(&connector->hdcp.cp_irq_count); 2744 wake_up_all(&connector->hdcp.cp_irq_queue); 2745 2746 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0); 2747 } 2748 2749 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2750 bool remote_req) 2751 { 2752 bool hdcp_cap = false, hdcp2_cap = false; 2753 2754 if (!connector->hdcp.shim) { 2755 seq_puts(m, "No Connector Support"); 2756 goto out; 2757 } 2758 2759 if (remote_req) { 2760 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2761 } else { 2762 hdcp_cap = intel_hdcp_get_capability(connector); 2763 hdcp2_cap = intel_hdcp2_get_capability(connector); 2764 } 2765 2766 if (hdcp_cap) 2767 seq_puts(m, "HDCP1.4 "); 2768 if (hdcp2_cap) 2769 seq_puts(m, "HDCP2.2 "); 2770 2771 if (!hdcp_cap && !hdcp2_cap) 2772 seq_puts(m, "None"); 2773 2774 out: 2775 seq_puts(m, "\n"); 2776 } 2777 2778 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2779 { 2780 seq_puts(m, "\tHDCP version: "); 2781 if (connector->mst.dp) { 2782 __intel_hdcp_info(m, connector, true); 2783 seq_puts(m, "\tMST Hub HDCP version: "); 2784 } 2785 __intel_hdcp_info(m, connector, false); 2786 } 2787 2788 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2789 { 2790 struct intel_connector *connector = m->private; 2791 struct intel_display *display = to_intel_display(connector); 2792 int ret; 2793 2794 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2795 if (ret) 2796 return ret; 2797 2798 if (!connector->base.encoder || 2799 connector->base.status != connector_status_connected) { 2800 ret = -ENODEV; 2801 goto out; 2802 } 2803 2804 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2805 connector->base.base.id); 2806 __intel_hdcp_info(m, connector, false); 2807 2808 out: 2809 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2810 2811 return ret; 2812 } 2813 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2814 2815 static ssize_t intel_hdcp_force_14_write(struct file *file, 2816 const char __user *ubuf, 2817 size_t len, loff_t *offp) 2818 { 2819 struct seq_file *m = file->private_data; 2820 struct intel_connector *connector = m->private; 2821 struct intel_hdcp *hdcp = &connector->hdcp; 2822 bool force_hdcp14 = false; 2823 int ret; 2824 2825 if (len == 0) 2826 return 0; 2827 2828 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2829 if (ret < 0) 2830 return ret; 2831 2832 hdcp->force_hdcp14 = force_hdcp14; 2833 *offp += len; 2834 2835 return len; 2836 } 2837 2838 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2839 { 2840 struct intel_connector *connector = m->private; 2841 struct intel_display *display = to_intel_display(connector); 2842 struct intel_encoder *encoder = intel_attached_encoder(connector); 2843 struct intel_hdcp *hdcp = &connector->hdcp; 2844 struct drm_crtc *crtc; 2845 int ret; 2846 2847 if (!encoder) 2848 return -ENODEV; 2849 2850 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2851 if (ret) 2852 return ret; 2853 2854 crtc = connector->base.state->crtc; 2855 if (connector->base.status != connector_status_connected || !crtc) { 2856 ret = -ENODEV; 2857 goto out; 2858 } 2859 2860 seq_printf(m, "%s\n", 2861 str_yes_no(hdcp->force_hdcp14)); 2862 out: 2863 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2864 2865 return ret; 2866 } 2867 2868 static int intel_hdcp_force_14_open(struct inode *inode, 2869 struct file *file) 2870 { 2871 return single_open(file, intel_hdcp_force_14_show, 2872 inode->i_private); 2873 } 2874 2875 static const struct file_operations intel_hdcp_force_14_fops = { 2876 .owner = THIS_MODULE, 2877 .open = intel_hdcp_force_14_open, 2878 .read = seq_read, 2879 .llseek = seq_lseek, 2880 .release = single_release, 2881 .write = intel_hdcp_force_14_write 2882 }; 2883 2884 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2885 { 2886 struct dentry *root = connector->base.debugfs_entry; 2887 int connector_type = connector->base.connector_type; 2888 2889 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2890 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2891 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2892 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2893 connector, &intel_hdcp_sink_capability_fops); 2894 debugfs_create_file("i915_force_hdcp14", 0644, root, 2895 connector, &intel_hdcp_force_14_fops); 2896 } 2897 } 2898