1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/random.h> 15 16 #include <drm/display/drm_hdcp_helper.h> 17 #include <drm/drm_print.h> 18 #include <drm/intel/i915_component.h> 19 20 #include "i915_reg.h" 21 #include "i915_utils.h" 22 #include "intel_connector.h" 23 #include "intel_de.h" 24 #include "intel_display_power.h" 25 #include "intel_display_power_well.h" 26 #include "intel_display_regs.h" 27 #include "intel_display_rpm.h" 28 #include "intel_display_types.h" 29 #include "intel_dp_mst.h" 30 #include "intel_hdcp.h" 31 #include "intel_hdcp_gsc.h" 32 #include "intel_hdcp_gsc_message.h" 33 #include "intel_hdcp_regs.h" 34 #include "intel_hdcp_shim.h" 35 #include "intel_pcode.h" 36 #include "intel_step.h" 37 38 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 39 40 #define KEY_LOAD_TRIES 5 41 #define HDCP2_LC_RETRY_CNT 3 42 43 static void 44 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 45 struct intel_hdcp *hdcp, 46 bool enable) 47 { 48 struct intel_display *display = to_intel_display(encoder); 49 i915_reg_t rekey_reg; 50 u32 rekey_bit = 0; 51 52 /* Here we assume HDMI is in TMDS mode of operation */ 53 if (!intel_encoder_is_hdmi(encoder)) 54 return; 55 56 if (DISPLAY_VER(display) >= 30) { 57 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 58 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 59 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 60 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 61 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 62 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 63 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 64 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 65 rekey_bit = HDCP_LINE_REKEY_DISABLE; 66 } 67 68 if (rekey_bit) 69 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 70 } 71 72 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 73 struct intel_connector *connector) 74 { 75 struct drm_dp_mst_topology_mgr *mgr; 76 struct drm_dp_mst_atomic_payload *payload; 77 struct drm_dp_mst_topology_state *mst_state; 78 int vcpi = 0; 79 80 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 81 if (!connector->mst.port) 82 return 0; 83 mgr = connector->mst.port->mgr; 84 85 drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); 86 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 87 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 88 if (drm_WARN_ON(mgr->dev, !payload)) 89 goto out; 90 91 vcpi = payload->vcpi; 92 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 93 vcpi = 0; 94 goto out; 95 } 96 out: 97 return vcpi; 98 } 99 100 /* 101 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 102 * content_type for all streams in DP MST topology because security f/w doesn't 103 * have any provision to mark content_type for each stream separately, it marks 104 * all available streams with the content_type proivided at the time of port 105 * authentication. This may prohibit the userspace to use type1 content on 106 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 107 * DP MST topology. Though it is not compulsory, security fw should change its 108 * policy to mark different content_types for different streams. 109 */ 110 static int 111 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 112 struct intel_digital_port *dig_port) 113 { 114 struct intel_display *display = to_intel_display(state); 115 struct drm_connector_list_iter conn_iter; 116 struct intel_digital_port *conn_dig_port; 117 struct intel_connector *connector; 118 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 119 bool enforce_type0 = false; 120 int k; 121 122 if (dig_port->hdcp.auth_status) 123 return 0; 124 125 data->k = 0; 126 127 if (!dig_port->hdcp.mst_type1_capable) 128 enforce_type0 = true; 129 130 drm_connector_list_iter_begin(display->drm, &conn_iter); 131 for_each_intel_connector_iter(connector, &conn_iter) { 132 if (connector->base.status == connector_status_disconnected) 133 continue; 134 135 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 136 continue; 137 138 conn_dig_port = intel_attached_dig_port(connector); 139 if (conn_dig_port != dig_port) 140 continue; 141 142 data->streams[data->k].stream_id = 143 intel_conn_to_vcpi(state, connector); 144 data->k++; 145 146 /* if there is only one active stream */ 147 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 148 break; 149 } 150 drm_connector_list_iter_end(&conn_iter); 151 152 if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0)) 153 return -EINVAL; 154 155 /* 156 * Apply common protection level across all streams in DP MST Topology. 157 * Use highest supported content type for all streams in DP MST Topology. 158 */ 159 for (k = 0; k < data->k; k++) 160 data->streams[k].stream_type = 161 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 162 163 return 0; 164 } 165 166 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 167 struct intel_connector *connector) 168 { 169 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 170 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 171 struct intel_hdcp *hdcp = &connector->hdcp; 172 173 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 174 return intel_hdcp_required_content_stream(state, dig_port); 175 176 data->k = 1; 177 data->streams[0].stream_id = 0; 178 data->streams[0].stream_type = hdcp->content_type; 179 180 return 0; 181 } 182 183 static 184 bool intel_hdcp_is_ksv_valid(u8 *ksv) 185 { 186 int i, ones = 0; 187 /* KSV has 20 1's and 20 0's */ 188 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 189 ones += hweight8(ksv[i]); 190 if (ones != 20) 191 return false; 192 193 return true; 194 } 195 196 static 197 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 198 const struct intel_hdcp_shim *shim, u8 *bksv) 199 { 200 struct intel_display *display = to_intel_display(dig_port); 201 int ret, i, tries = 2; 202 203 /* HDCP spec states that we must retry the bksv if it is invalid */ 204 for (i = 0; i < tries; i++) { 205 ret = shim->read_bksv(dig_port, bksv); 206 if (ret) 207 return ret; 208 if (intel_hdcp_is_ksv_valid(bksv)) 209 break; 210 } 211 if (i == tries) { 212 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 213 return -ENODEV; 214 } 215 216 return 0; 217 } 218 219 /* Is HDCP1.4 capable on Platform and Sink */ 220 static bool intel_hdcp_get_capability(struct intel_connector *connector) 221 { 222 struct intel_digital_port *dig_port; 223 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 224 bool capable = false; 225 u8 bksv[5]; 226 227 if (!intel_attached_encoder(connector)) 228 return capable; 229 230 dig_port = intel_attached_dig_port(connector); 231 232 if (!shim) 233 return capable; 234 235 if (shim->hdcp_get_capability) { 236 shim->hdcp_get_capability(dig_port, &capable); 237 } else { 238 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 239 capable = true; 240 } 241 242 return capable; 243 } 244 245 /* 246 * Check if the source has all the building blocks ready to make 247 * HDCP 2.2 work 248 */ 249 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 250 { 251 struct intel_display *display = to_intel_display(connector); 252 struct intel_hdcp *hdcp = &connector->hdcp; 253 254 /* I915 support for HDCP2.2 */ 255 if (!hdcp->hdcp2_supported) 256 return false; 257 258 /* If MTL+ make sure gsc is loaded and proxy is setup */ 259 if (USE_HDCP_GSC(display)) { 260 if (!intel_hdcp_gsc_check_status(display->drm)) 261 return false; 262 } 263 264 /* MEI/GSC interface is solid depending on which is used */ 265 mutex_lock(&display->hdcp.hdcp_mutex); 266 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 267 mutex_unlock(&display->hdcp.hdcp_mutex); 268 return false; 269 } 270 mutex_unlock(&display->hdcp.hdcp_mutex); 271 272 return true; 273 } 274 275 /* Is HDCP2.2 capable on Platform and Sink */ 276 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 277 { 278 struct intel_hdcp *hdcp = &connector->hdcp; 279 bool capable = false; 280 281 if (!intel_hdcp2_prerequisite(connector)) 282 return false; 283 284 /* Sink's capability for HDCP2.2 */ 285 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 286 287 return capable; 288 } 289 290 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 291 bool *hdcp_capable, 292 bool *hdcp2_capable) 293 { 294 struct intel_hdcp *hdcp = &connector->hdcp; 295 296 if (!hdcp->shim->get_remote_hdcp_capability) 297 return; 298 299 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 300 hdcp2_capable); 301 302 if (!intel_hdcp2_prerequisite(connector)) 303 *hdcp2_capable = false; 304 } 305 306 static bool intel_hdcp_in_use(struct intel_display *display, 307 enum transcoder cpu_transcoder, enum port port) 308 { 309 return intel_de_read(display, 310 HDCP_STATUS(display, cpu_transcoder, port)) & 311 HDCP_STATUS_ENC; 312 } 313 314 static bool intel_hdcp2_in_use(struct intel_display *display, 315 enum transcoder cpu_transcoder, enum port port) 316 { 317 return intel_de_read(display, 318 HDCP2_STATUS(display, cpu_transcoder, port)) & 319 LINK_ENCRYPTION_STATUS; 320 } 321 322 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 323 const struct intel_hdcp_shim *shim) 324 { 325 int ret, read_ret; 326 bool ksv_ready; 327 328 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 329 ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, 330 &ksv_ready), 331 read_ret || ksv_ready, 5 * 1000 * 1000, 1000, 332 100 * 1000); 333 if (ret) 334 return ret; 335 if (read_ret) 336 return read_ret; 337 if (!ksv_ready) 338 return -ETIMEDOUT; 339 340 return 0; 341 } 342 343 static bool hdcp_key_loadable(struct intel_display *display) 344 { 345 enum i915_power_well_id id; 346 bool enabled = false; 347 348 /* 349 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 350 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 351 */ 352 if (display->platform.haswell || display->platform.broadwell) 353 id = HSW_DISP_PW_GLOBAL; 354 else 355 id = SKL_DISP_PW_1; 356 357 /* PG1 (power well #1) needs to be enabled */ 358 with_intel_display_rpm(display) 359 enabled = intel_display_power_well_is_enabled(display, id); 360 361 /* 362 * Another req for hdcp key loadability is enabled state of pll for 363 * cdclk. Without active crtc we won't land here. So we are assuming that 364 * cdclk is already on. 365 */ 366 367 return enabled; 368 } 369 370 static void intel_hdcp_clear_keys(struct intel_display *display) 371 { 372 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 373 intel_de_write(display, HDCP_KEY_STATUS, 374 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 375 } 376 377 static int intel_hdcp_load_keys(struct intel_display *display) 378 { 379 int ret; 380 u32 val; 381 382 val = intel_de_read(display, HDCP_KEY_STATUS); 383 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 384 return 0; 385 386 /* 387 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 388 * out of reset. So if Key is not already loaded, its an error state. 389 */ 390 if (display->platform.haswell || display->platform.broadwell) 391 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 392 return -ENXIO; 393 394 /* 395 * Initiate loading the HDCP key from fuses. 396 * 397 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 398 * version 9 platforms (minus BXT) differ in the key load trigger 399 * process from other platforms. These platforms use the GT Driver 400 * Mailbox interface. 401 */ 402 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 403 ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1); 404 if (ret) { 405 drm_err(display->drm, 406 "Failed to initiate HDCP key load (%d)\n", 407 ret); 408 return ret; 409 } 410 } else { 411 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 412 } 413 414 /* Wait for the keys to load (500us) */ 415 ret = intel_de_wait_custom(display, HDCP_KEY_STATUS, 416 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 417 10, 1, &val); 418 if (ret) 419 return ret; 420 else if (!(val & HDCP_KEY_LOAD_STATUS)) 421 return -ENXIO; 422 423 /* Send Aksv over to PCH display for use in authentication */ 424 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 425 426 return 0; 427 } 428 429 /* Returns updated SHA-1 index */ 430 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 431 { 432 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 433 if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 434 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 435 return -ETIMEDOUT; 436 } 437 return 0; 438 } 439 440 static 441 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 442 enum transcoder cpu_transcoder, enum port port) 443 { 444 if (DISPLAY_VER(display) >= 12) { 445 switch (cpu_transcoder) { 446 case TRANSCODER_A: 447 return HDCP_TRANSA_REP_PRESENT | 448 HDCP_TRANSA_SHA1_M0; 449 case TRANSCODER_B: 450 return HDCP_TRANSB_REP_PRESENT | 451 HDCP_TRANSB_SHA1_M0; 452 case TRANSCODER_C: 453 return HDCP_TRANSC_REP_PRESENT | 454 HDCP_TRANSC_SHA1_M0; 455 case TRANSCODER_D: 456 return HDCP_TRANSD_REP_PRESENT | 457 HDCP_TRANSD_SHA1_M0; 458 default: 459 drm_err(display->drm, "Unknown transcoder %d\n", 460 cpu_transcoder); 461 return 0; 462 } 463 } 464 465 switch (port) { 466 case PORT_A: 467 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 468 case PORT_B: 469 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 470 case PORT_C: 471 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 472 case PORT_D: 473 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 474 case PORT_E: 475 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 476 default: 477 drm_err(display->drm, "Unknown port %d\n", port); 478 return 0; 479 } 480 } 481 482 static 483 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 484 const struct intel_hdcp_shim *shim, 485 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 486 { 487 struct intel_display *display = to_intel_display(connector); 488 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 489 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 490 enum port port = dig_port->base.port; 491 u32 vprime, sha_text, sha_leftovers, rep_ctl; 492 int ret, i, j, sha_idx; 493 494 /* Process V' values from the receiver */ 495 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 496 ret = shim->read_v_prime_part(dig_port, i, &vprime); 497 if (ret) 498 return ret; 499 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 500 } 501 502 /* 503 * We need to write the concatenation of all device KSVs, BINFO (DP) || 504 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 505 * stream is written via the HDCP_SHA_TEXT register in 32-bit 506 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 507 * index will keep track of our progress through the 64 bytes as well as 508 * helping us work the 40-bit KSVs through our 32-bit register. 509 * 510 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 511 */ 512 sha_idx = 0; 513 sha_text = 0; 514 sha_leftovers = 0; 515 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 516 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 517 for (i = 0; i < num_downstream; i++) { 518 unsigned int sha_empty; 519 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 520 521 /* Fill up the empty slots in sha_text and write it out */ 522 sha_empty = sizeof(sha_text) - sha_leftovers; 523 for (j = 0; j < sha_empty; j++) { 524 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 525 sha_text |= ksv[j] << off; 526 } 527 528 ret = intel_write_sha_text(display, sha_text); 529 if (ret < 0) 530 return ret; 531 532 /* Programming guide writes this every 64 bytes */ 533 sha_idx += sizeof(sha_text); 534 if (!(sha_idx % 64)) 535 intel_de_write(display, HDCP_REP_CTL, 536 rep_ctl | HDCP_SHA1_TEXT_32); 537 538 /* Store the leftover bytes from the ksv in sha_text */ 539 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 540 sha_text = 0; 541 for (j = 0; j < sha_leftovers; j++) 542 sha_text |= ksv[sha_empty + j] << 543 ((sizeof(sha_text) - j - 1) * 8); 544 545 /* 546 * If we still have room in sha_text for more data, continue. 547 * Otherwise, write it out immediately. 548 */ 549 if (sizeof(sha_text) > sha_leftovers) 550 continue; 551 552 ret = intel_write_sha_text(display, sha_text); 553 if (ret < 0) 554 return ret; 555 sha_leftovers = 0; 556 sha_text = 0; 557 sha_idx += sizeof(sha_text); 558 } 559 560 /* 561 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 562 * bytes are leftover from the last ksv, we might be able to fit them 563 * all in sha_text (first 2 cases), or we might need to split them up 564 * into 2 writes (last 2 cases). 565 */ 566 if (sha_leftovers == 0) { 567 /* Write 16 bits of text, 16 bits of M0 */ 568 intel_de_write(display, HDCP_REP_CTL, 569 rep_ctl | HDCP_SHA1_TEXT_16); 570 ret = intel_write_sha_text(display, 571 bstatus[0] << 8 | bstatus[1]); 572 if (ret < 0) 573 return ret; 574 sha_idx += sizeof(sha_text); 575 576 /* Write 32 bits of M0 */ 577 intel_de_write(display, HDCP_REP_CTL, 578 rep_ctl | HDCP_SHA1_TEXT_0); 579 ret = intel_write_sha_text(display, 0); 580 if (ret < 0) 581 return ret; 582 sha_idx += sizeof(sha_text); 583 584 /* Write 16 bits of M0 */ 585 intel_de_write(display, HDCP_REP_CTL, 586 rep_ctl | HDCP_SHA1_TEXT_16); 587 ret = intel_write_sha_text(display, 0); 588 if (ret < 0) 589 return ret; 590 sha_idx += sizeof(sha_text); 591 592 } else if (sha_leftovers == 1) { 593 /* Write 24 bits of text, 8 bits of M0 */ 594 intel_de_write(display, HDCP_REP_CTL, 595 rep_ctl | HDCP_SHA1_TEXT_24); 596 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 597 /* Only 24-bits of data, must be in the LSB */ 598 sha_text = (sha_text & 0xffffff00) >> 8; 599 ret = intel_write_sha_text(display, sha_text); 600 if (ret < 0) 601 return ret; 602 sha_idx += sizeof(sha_text); 603 604 /* Write 32 bits of M0 */ 605 intel_de_write(display, HDCP_REP_CTL, 606 rep_ctl | HDCP_SHA1_TEXT_0); 607 ret = intel_write_sha_text(display, 0); 608 if (ret < 0) 609 return ret; 610 sha_idx += sizeof(sha_text); 611 612 /* Write 24 bits of M0 */ 613 intel_de_write(display, HDCP_REP_CTL, 614 rep_ctl | HDCP_SHA1_TEXT_8); 615 ret = intel_write_sha_text(display, 0); 616 if (ret < 0) 617 return ret; 618 sha_idx += sizeof(sha_text); 619 620 } else if (sha_leftovers == 2) { 621 /* Write 32 bits of text */ 622 intel_de_write(display, HDCP_REP_CTL, 623 rep_ctl | HDCP_SHA1_TEXT_32); 624 sha_text |= bstatus[0] << 8 | bstatus[1]; 625 ret = intel_write_sha_text(display, sha_text); 626 if (ret < 0) 627 return ret; 628 sha_idx += sizeof(sha_text); 629 630 /* Write 64 bits of M0 */ 631 intel_de_write(display, HDCP_REP_CTL, 632 rep_ctl | HDCP_SHA1_TEXT_0); 633 for (i = 0; i < 2; i++) { 634 ret = intel_write_sha_text(display, 0); 635 if (ret < 0) 636 return ret; 637 sha_idx += sizeof(sha_text); 638 } 639 640 /* 641 * Terminate the SHA-1 stream by hand. For the other leftover 642 * cases this is appended by the hardware. 643 */ 644 intel_de_write(display, HDCP_REP_CTL, 645 rep_ctl | HDCP_SHA1_TEXT_32); 646 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 647 ret = intel_write_sha_text(display, sha_text); 648 if (ret < 0) 649 return ret; 650 sha_idx += sizeof(sha_text); 651 } else if (sha_leftovers == 3) { 652 /* Write 32 bits of text (filled from LSB) */ 653 intel_de_write(display, HDCP_REP_CTL, 654 rep_ctl | HDCP_SHA1_TEXT_32); 655 sha_text |= bstatus[0]; 656 ret = intel_write_sha_text(display, sha_text); 657 if (ret < 0) 658 return ret; 659 sha_idx += sizeof(sha_text); 660 661 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 662 intel_de_write(display, HDCP_REP_CTL, 663 rep_ctl | HDCP_SHA1_TEXT_8); 664 ret = intel_write_sha_text(display, bstatus[1]); 665 if (ret < 0) 666 return ret; 667 sha_idx += sizeof(sha_text); 668 669 /* Write 32 bits of M0 */ 670 intel_de_write(display, HDCP_REP_CTL, 671 rep_ctl | HDCP_SHA1_TEXT_0); 672 ret = intel_write_sha_text(display, 0); 673 if (ret < 0) 674 return ret; 675 sha_idx += sizeof(sha_text); 676 677 /* Write 8 bits of M0 */ 678 intel_de_write(display, HDCP_REP_CTL, 679 rep_ctl | HDCP_SHA1_TEXT_24); 680 ret = intel_write_sha_text(display, 0); 681 if (ret < 0) 682 return ret; 683 sha_idx += sizeof(sha_text); 684 } else { 685 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 686 sha_leftovers); 687 return -EINVAL; 688 } 689 690 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 691 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 692 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 693 ret = intel_write_sha_text(display, 0); 694 if (ret < 0) 695 return ret; 696 sha_idx += sizeof(sha_text); 697 } 698 699 /* 700 * Last write gets the length of the concatenation in bits. That is: 701 * - 5 bytes per device 702 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 703 */ 704 sha_text = (num_downstream * 5 + 10) * 8; 705 ret = intel_write_sha_text(display, sha_text); 706 if (ret < 0) 707 return ret; 708 709 /* Tell the HW we're done with the hash and wait for it to ACK */ 710 intel_de_write(display, HDCP_REP_CTL, 711 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 712 if (intel_de_wait_for_set(display, HDCP_REP_CTL, 713 HDCP_SHA1_COMPLETE, 1)) { 714 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 715 return -ETIMEDOUT; 716 } 717 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 718 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 719 return -ENXIO; 720 } 721 722 return 0; 723 } 724 725 /* Implements Part 2 of the HDCP authorization procedure */ 726 static 727 int intel_hdcp_auth_downstream(struct intel_connector *connector) 728 { 729 struct intel_display *display = to_intel_display(connector); 730 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 731 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 732 u8 bstatus[2], num_downstream, *ksv_fifo; 733 int ret, i, tries = 3; 734 735 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 736 if (ret) { 737 drm_dbg_kms(display->drm, 738 "KSV list failed to become ready (%d)\n", ret); 739 return ret; 740 } 741 742 ret = shim->read_bstatus(dig_port, bstatus); 743 if (ret) 744 return ret; 745 746 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 747 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 748 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 749 return -EPERM; 750 } 751 752 /* 753 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 754 * the HDCP encryption. That implies that repeater can't have its own 755 * display. As there is no consumption of encrypted content in the 756 * repeater with 0 downstream devices, we are failing the 757 * authentication. 758 */ 759 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 760 if (num_downstream == 0) { 761 drm_dbg_kms(display->drm, 762 "Repeater with zero downstream devices\n"); 763 return -EINVAL; 764 } 765 766 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 767 if (!ksv_fifo) { 768 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 769 return -ENOMEM; 770 } 771 772 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 773 if (ret) 774 goto err; 775 776 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 777 num_downstream) > 0) { 778 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 779 ret = -EPERM; 780 goto err; 781 } 782 783 /* 784 * When V prime mismatches, DP Spec mandates re-read of 785 * V prime atleast twice. 786 */ 787 for (i = 0; i < tries; i++) { 788 ret = intel_hdcp_validate_v_prime(connector, shim, 789 ksv_fifo, num_downstream, 790 bstatus); 791 if (!ret) 792 break; 793 } 794 795 if (i == tries) { 796 drm_dbg_kms(display->drm, 797 "V Prime validation failed.(%d)\n", ret); 798 goto err; 799 } 800 801 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 802 num_downstream); 803 ret = 0; 804 err: 805 kfree(ksv_fifo); 806 return ret; 807 } 808 809 /* Implements Part 1 of the HDCP authorization procedure */ 810 static int intel_hdcp_auth(struct intel_connector *connector) 811 { 812 struct intel_display *display = to_intel_display(connector); 813 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 814 struct intel_hdcp *hdcp = &connector->hdcp; 815 const struct intel_hdcp_shim *shim = hdcp->shim; 816 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 817 enum port port = dig_port->base.port; 818 unsigned long r0_prime_gen_start; 819 int ret, i, tries = 2; 820 union { 821 u32 reg[2]; 822 u8 shim[DRM_HDCP_AN_LEN]; 823 } an; 824 union { 825 u32 reg[2]; 826 u8 shim[DRM_HDCP_KSV_LEN]; 827 } bksv; 828 union { 829 u32 reg; 830 u8 shim[DRM_HDCP_RI_LEN]; 831 } ri; 832 bool repeater_present, hdcp_capable; 833 834 /* 835 * Detects whether the display is HDCP capable. Although we check for 836 * valid Bksv below, the HDCP over DP spec requires that we check 837 * whether the display supports HDCP before we write An. For HDMI 838 * displays, this is not necessary. 839 */ 840 if (shim->hdcp_get_capability) { 841 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 842 if (ret) 843 return ret; 844 if (!hdcp_capable) { 845 drm_dbg_kms(display->drm, 846 "Panel is not HDCP capable\n"); 847 return -EINVAL; 848 } 849 } 850 851 /* Initialize An with 2 random values and acquire it */ 852 for (i = 0; i < 2; i++) 853 intel_de_write(display, 854 HDCP_ANINIT(display, cpu_transcoder, port), 855 get_random_u32()); 856 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 857 HDCP_CONF_CAPTURE_AN); 858 859 /* Wait for An to be acquired */ 860 if (intel_de_wait_for_set(display, 861 HDCP_STATUS(display, cpu_transcoder, port), 862 HDCP_STATUS_AN_READY, 1)) { 863 drm_err(display->drm, "Timed out waiting for An\n"); 864 return -ETIMEDOUT; 865 } 866 867 an.reg[0] = intel_de_read(display, 868 HDCP_ANLO(display, cpu_transcoder, port)); 869 an.reg[1] = intel_de_read(display, 870 HDCP_ANHI(display, cpu_transcoder, port)); 871 ret = shim->write_an_aksv(dig_port, an.shim); 872 if (ret) 873 return ret; 874 875 r0_prime_gen_start = jiffies; 876 877 memset(&bksv, 0, sizeof(bksv)); 878 879 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 880 if (ret < 0) 881 return ret; 882 883 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 884 drm_err(display->drm, "BKSV is revoked\n"); 885 return -EPERM; 886 } 887 888 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 889 bksv.reg[0]); 890 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 891 bksv.reg[1]); 892 893 ret = shim->repeater_present(dig_port, &repeater_present); 894 if (ret) 895 return ret; 896 if (repeater_present) 897 intel_de_write(display, HDCP_REP_CTL, 898 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 899 900 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 901 if (ret) 902 return ret; 903 904 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 905 HDCP_CONF_AUTH_AND_ENC); 906 907 /* Wait for R0 ready */ 908 if (wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 909 (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { 910 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 911 return -ETIMEDOUT; 912 } 913 914 /* 915 * Wait for R0' to become available. The spec says 100ms from Aksv, but 916 * some monitors can take longer than this. We'll set the timeout at 917 * 300ms just to be sure. 918 * 919 * On DP, there's an R0_READY bit available but no such bit 920 * exists on HDMI. Since the upper-bound is the same, we'll just do 921 * the stupid thing instead of polling on one and not the other. 922 */ 923 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 924 925 tries = 3; 926 927 /* 928 * DP HDCP Spec mandates the two more reattempt to read R0, incase 929 * of R0 mismatch. 930 */ 931 for (i = 0; i < tries; i++) { 932 ri.reg = 0; 933 ret = shim->read_ri_prime(dig_port, ri.shim); 934 if (ret) 935 return ret; 936 intel_de_write(display, 937 HDCP_RPRIME(display, cpu_transcoder, port), 938 ri.reg); 939 940 /* Wait for Ri prime match */ 941 if (!wait_for(intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) & 942 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) 943 break; 944 } 945 946 if (i == tries) { 947 drm_dbg_kms(display->drm, 948 "Timed out waiting for Ri prime match (%x)\n", 949 intel_de_read(display, 950 HDCP_STATUS(display, cpu_transcoder, port))); 951 return -ETIMEDOUT; 952 } 953 954 /* Wait for encryption confirmation */ 955 if (intel_de_wait_for_set(display, 956 HDCP_STATUS(display, cpu_transcoder, port), 957 HDCP_STATUS_ENC, 958 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 959 drm_err(display->drm, "Timed out waiting for encryption\n"); 960 return -ETIMEDOUT; 961 } 962 963 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 964 if (shim->stream_encryption) { 965 ret = shim->stream_encryption(connector, true); 966 if (ret) { 967 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 968 connector->base.base.id, connector->base.name); 969 return ret; 970 } 971 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 972 transcoder_name(hdcp->stream_transcoder)); 973 } 974 975 if (repeater_present) 976 return intel_hdcp_auth_downstream(connector); 977 978 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 979 return 0; 980 } 981 982 static int _intel_hdcp_disable(struct intel_connector *connector) 983 { 984 struct intel_display *display = to_intel_display(connector); 985 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 986 struct intel_hdcp *hdcp = &connector->hdcp; 987 enum port port = dig_port->base.port; 988 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 989 u32 repeater_ctl; 990 int ret; 991 992 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 993 connector->base.base.id, connector->base.name); 994 995 if (hdcp->shim->stream_encryption) { 996 ret = hdcp->shim->stream_encryption(connector, false); 997 if (ret) { 998 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 999 connector->base.base.id, connector->base.name); 1000 return ret; 1001 } 1002 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1003 transcoder_name(hdcp->stream_transcoder)); 1004 /* 1005 * If there are other connectors on this port using HDCP, 1006 * don't disable it until it disabled HDCP encryption for 1007 * all connectors in MST topology. 1008 */ 1009 if (dig_port->hdcp.num_streams > 0) 1010 return 0; 1011 } 1012 1013 hdcp->hdcp_encrypted = false; 1014 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1015 if (intel_de_wait_for_clear(display, 1016 HDCP_STATUS(display, cpu_transcoder, port), 1017 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1018 drm_err(display->drm, 1019 "Failed to disable HDCP, timeout clearing status\n"); 1020 return -ETIMEDOUT; 1021 } 1022 1023 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1024 port); 1025 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1026 1027 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1028 if (ret) { 1029 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1030 return ret; 1031 } 1032 1033 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1034 return 0; 1035 } 1036 1037 static int intel_hdcp1_enable(struct intel_connector *connector) 1038 { 1039 struct intel_display *display = to_intel_display(connector); 1040 struct intel_hdcp *hdcp = &connector->hdcp; 1041 int i, ret, tries = 3; 1042 1043 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1044 connector->base.base.id, connector->base.name); 1045 1046 if (!hdcp_key_loadable(display)) { 1047 drm_err(display->drm, "HDCP key Load is not possible\n"); 1048 return -ENXIO; 1049 } 1050 1051 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1052 ret = intel_hdcp_load_keys(display); 1053 if (!ret) 1054 break; 1055 intel_hdcp_clear_keys(display); 1056 } 1057 if (ret) { 1058 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1059 ret); 1060 return ret; 1061 } 1062 1063 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1064 1065 /* Incase of authentication failures, HDCP spec expects reauth. */ 1066 for (i = 0; i < tries; i++) { 1067 ret = intel_hdcp_auth(connector); 1068 if (!ret) { 1069 hdcp->hdcp_encrypted = true; 1070 return 0; 1071 } 1072 1073 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1074 1075 /* Ensuring HDCP encryption and signalling are stopped. */ 1076 _intel_hdcp_disable(connector); 1077 } 1078 1079 drm_dbg_kms(display->drm, 1080 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1081 return ret; 1082 } 1083 1084 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1085 { 1086 return container_of(hdcp, struct intel_connector, hdcp); 1087 } 1088 1089 static void intel_hdcp_update_value(struct intel_connector *connector, 1090 u64 value, bool update_property) 1091 { 1092 struct intel_display *display = to_intel_display(connector); 1093 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1094 struct intel_hdcp *hdcp = &connector->hdcp; 1095 1096 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1097 1098 if (hdcp->value == value) 1099 return; 1100 1101 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1102 1103 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1104 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1105 dig_port->hdcp.num_streams--; 1106 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1107 dig_port->hdcp.num_streams++; 1108 } 1109 1110 hdcp->value = value; 1111 if (update_property) { 1112 drm_connector_get(&connector->base); 1113 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 1114 drm_connector_put(&connector->base); 1115 } 1116 } 1117 1118 /* Implements Part 3 of the HDCP authorization procedure */ 1119 static int intel_hdcp_check_link(struct intel_connector *connector) 1120 { 1121 struct intel_display *display = to_intel_display(connector); 1122 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1123 struct intel_hdcp *hdcp = &connector->hdcp; 1124 enum port port = dig_port->base.port; 1125 enum transcoder cpu_transcoder; 1126 int ret = 0; 1127 1128 mutex_lock(&hdcp->mutex); 1129 mutex_lock(&dig_port->hdcp.mutex); 1130 1131 cpu_transcoder = hdcp->cpu_transcoder; 1132 1133 /* Check_link valid only when HDCP1.4 is enabled */ 1134 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1135 !hdcp->hdcp_encrypted) { 1136 ret = -EINVAL; 1137 goto out; 1138 } 1139 1140 if (drm_WARN_ON(display->drm, 1141 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1142 drm_err(display->drm, 1143 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1144 connector->base.base.id, connector->base.name, 1145 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1146 ret = -ENXIO; 1147 intel_hdcp_update_value(connector, 1148 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1149 true); 1150 goto out; 1151 } 1152 1153 if (hdcp->shim->check_link(dig_port, connector)) { 1154 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1155 intel_hdcp_update_value(connector, 1156 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1157 } 1158 goto out; 1159 } 1160 1161 drm_dbg_kms(display->drm, 1162 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1163 connector->base.base.id, connector->base.name); 1164 1165 ret = _intel_hdcp_disable(connector); 1166 if (ret) { 1167 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1168 intel_hdcp_update_value(connector, 1169 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1170 true); 1171 goto out; 1172 } 1173 1174 ret = intel_hdcp1_enable(connector); 1175 if (ret) { 1176 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1177 intel_hdcp_update_value(connector, 1178 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1179 true); 1180 goto out; 1181 } 1182 1183 out: 1184 mutex_unlock(&dig_port->hdcp.mutex); 1185 mutex_unlock(&hdcp->mutex); 1186 return ret; 1187 } 1188 1189 static void intel_hdcp_prop_work(struct work_struct *work) 1190 { 1191 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1192 prop_work); 1193 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1194 struct intel_display *display = to_intel_display(connector); 1195 1196 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1197 mutex_lock(&hdcp->mutex); 1198 1199 /* 1200 * This worker is only used to flip between ENABLED/DESIRED. Either of 1201 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1202 * we're running just after hdcp has been disabled, so just exit 1203 */ 1204 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1205 drm_hdcp_update_content_protection(&connector->base, 1206 hdcp->value); 1207 1208 mutex_unlock(&hdcp->mutex); 1209 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1210 1211 drm_connector_put(&connector->base); 1212 } 1213 1214 bool is_hdcp_supported(struct intel_display *display, enum port port) 1215 { 1216 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1217 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1218 } 1219 1220 static int 1221 hdcp2_prepare_ake_init(struct intel_connector *connector, 1222 struct hdcp2_ake_init *ake_data) 1223 { 1224 struct intel_display *display = to_intel_display(connector); 1225 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1226 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1227 struct i915_hdcp_arbiter *arbiter; 1228 int ret; 1229 1230 mutex_lock(&display->hdcp.hdcp_mutex); 1231 arbiter = display->hdcp.arbiter; 1232 1233 if (!arbiter || !arbiter->ops) { 1234 mutex_unlock(&display->hdcp.hdcp_mutex); 1235 return -EINVAL; 1236 } 1237 1238 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1239 if (ret) 1240 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1241 ret); 1242 mutex_unlock(&display->hdcp.hdcp_mutex); 1243 1244 return ret; 1245 } 1246 1247 static int 1248 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1249 struct hdcp2_ake_send_cert *rx_cert, 1250 bool *paired, 1251 struct hdcp2_ake_no_stored_km *ek_pub_km, 1252 size_t *msg_sz) 1253 { 1254 struct intel_display *display = to_intel_display(connector); 1255 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1256 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1257 struct i915_hdcp_arbiter *arbiter; 1258 int ret; 1259 1260 mutex_lock(&display->hdcp.hdcp_mutex); 1261 arbiter = display->hdcp.arbiter; 1262 1263 if (!arbiter || !arbiter->ops) { 1264 mutex_unlock(&display->hdcp.hdcp_mutex); 1265 return -EINVAL; 1266 } 1267 1268 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1269 rx_cert, paired, 1270 ek_pub_km, msg_sz); 1271 if (ret < 0) 1272 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1273 ret); 1274 mutex_unlock(&display->hdcp.hdcp_mutex); 1275 1276 return ret; 1277 } 1278 1279 static int hdcp2_verify_hprime(struct intel_connector *connector, 1280 struct hdcp2_ake_send_hprime *rx_hprime) 1281 { 1282 struct intel_display *display = to_intel_display(connector); 1283 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1284 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1285 struct i915_hdcp_arbiter *arbiter; 1286 int ret; 1287 1288 mutex_lock(&display->hdcp.hdcp_mutex); 1289 arbiter = display->hdcp.arbiter; 1290 1291 if (!arbiter || !arbiter->ops) { 1292 mutex_unlock(&display->hdcp.hdcp_mutex); 1293 return -EINVAL; 1294 } 1295 1296 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1297 if (ret < 0) 1298 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1299 mutex_unlock(&display->hdcp.hdcp_mutex); 1300 1301 return ret; 1302 } 1303 1304 static int 1305 hdcp2_store_pairing_info(struct intel_connector *connector, 1306 struct hdcp2_ake_send_pairing_info *pairing_info) 1307 { 1308 struct intel_display *display = to_intel_display(connector); 1309 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1310 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1311 struct i915_hdcp_arbiter *arbiter; 1312 int ret; 1313 1314 mutex_lock(&display->hdcp.hdcp_mutex); 1315 arbiter = display->hdcp.arbiter; 1316 1317 if (!arbiter || !arbiter->ops) { 1318 mutex_unlock(&display->hdcp.hdcp_mutex); 1319 return -EINVAL; 1320 } 1321 1322 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1323 if (ret < 0) 1324 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1325 ret); 1326 mutex_unlock(&display->hdcp.hdcp_mutex); 1327 1328 return ret; 1329 } 1330 1331 static int 1332 hdcp2_prepare_lc_init(struct intel_connector *connector, 1333 struct hdcp2_lc_init *lc_init) 1334 { 1335 struct intel_display *display = to_intel_display(connector); 1336 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1337 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1338 struct i915_hdcp_arbiter *arbiter; 1339 int ret; 1340 1341 mutex_lock(&display->hdcp.hdcp_mutex); 1342 arbiter = display->hdcp.arbiter; 1343 1344 if (!arbiter || !arbiter->ops) { 1345 mutex_unlock(&display->hdcp.hdcp_mutex); 1346 return -EINVAL; 1347 } 1348 1349 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1350 if (ret < 0) 1351 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1352 ret); 1353 mutex_unlock(&display->hdcp.hdcp_mutex); 1354 1355 return ret; 1356 } 1357 1358 static int 1359 hdcp2_verify_lprime(struct intel_connector *connector, 1360 struct hdcp2_lc_send_lprime *rx_lprime) 1361 { 1362 struct intel_display *display = to_intel_display(connector); 1363 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1364 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1365 struct i915_hdcp_arbiter *arbiter; 1366 int ret; 1367 1368 mutex_lock(&display->hdcp.hdcp_mutex); 1369 arbiter = display->hdcp.arbiter; 1370 1371 if (!arbiter || !arbiter->ops) { 1372 mutex_unlock(&display->hdcp.hdcp_mutex); 1373 return -EINVAL; 1374 } 1375 1376 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1377 if (ret < 0) 1378 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1379 ret); 1380 mutex_unlock(&display->hdcp.hdcp_mutex); 1381 1382 return ret; 1383 } 1384 1385 static int hdcp2_prepare_skey(struct intel_connector *connector, 1386 struct hdcp2_ske_send_eks *ske_data) 1387 { 1388 struct intel_display *display = to_intel_display(connector); 1389 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1390 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1391 struct i915_hdcp_arbiter *arbiter; 1392 int ret; 1393 1394 mutex_lock(&display->hdcp.hdcp_mutex); 1395 arbiter = display->hdcp.arbiter; 1396 1397 if (!arbiter || !arbiter->ops) { 1398 mutex_unlock(&display->hdcp.hdcp_mutex); 1399 return -EINVAL; 1400 } 1401 1402 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1403 if (ret < 0) 1404 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1405 ret); 1406 mutex_unlock(&display->hdcp.hdcp_mutex); 1407 1408 return ret; 1409 } 1410 1411 static int 1412 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1413 struct hdcp2_rep_send_receiverid_list 1414 *rep_topology, 1415 struct hdcp2_rep_send_ack *rep_send_ack) 1416 { 1417 struct intel_display *display = to_intel_display(connector); 1418 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1419 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1420 struct i915_hdcp_arbiter *arbiter; 1421 int ret; 1422 1423 mutex_lock(&display->hdcp.hdcp_mutex); 1424 arbiter = display->hdcp.arbiter; 1425 1426 if (!arbiter || !arbiter->ops) { 1427 mutex_unlock(&display->hdcp.hdcp_mutex); 1428 return -EINVAL; 1429 } 1430 1431 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1432 data, 1433 rep_topology, 1434 rep_send_ack); 1435 if (ret < 0) 1436 drm_dbg_kms(display->drm, 1437 "Verify rep topology failed. %d\n", ret); 1438 mutex_unlock(&display->hdcp.hdcp_mutex); 1439 1440 return ret; 1441 } 1442 1443 static int 1444 hdcp2_verify_mprime(struct intel_connector *connector, 1445 struct hdcp2_rep_stream_ready *stream_ready) 1446 { 1447 struct intel_display *display = to_intel_display(connector); 1448 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1449 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1450 struct i915_hdcp_arbiter *arbiter; 1451 int ret; 1452 1453 mutex_lock(&display->hdcp.hdcp_mutex); 1454 arbiter = display->hdcp.arbiter; 1455 1456 if (!arbiter || !arbiter->ops) { 1457 mutex_unlock(&display->hdcp.hdcp_mutex); 1458 return -EINVAL; 1459 } 1460 1461 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1462 if (ret < 0) 1463 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1464 mutex_unlock(&display->hdcp.hdcp_mutex); 1465 1466 return ret; 1467 } 1468 1469 static int hdcp2_authenticate_port(struct intel_connector *connector) 1470 { 1471 struct intel_display *display = to_intel_display(connector); 1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1473 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1474 struct i915_hdcp_arbiter *arbiter; 1475 int ret; 1476 1477 mutex_lock(&display->hdcp.hdcp_mutex); 1478 arbiter = display->hdcp.arbiter; 1479 1480 if (!arbiter || !arbiter->ops) { 1481 mutex_unlock(&display->hdcp.hdcp_mutex); 1482 return -EINVAL; 1483 } 1484 1485 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1486 if (ret < 0) 1487 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1488 ret); 1489 mutex_unlock(&display->hdcp.hdcp_mutex); 1490 1491 return ret; 1492 } 1493 1494 static int hdcp2_close_session(struct intel_connector *connector) 1495 { 1496 struct intel_display *display = to_intel_display(connector); 1497 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1498 struct i915_hdcp_arbiter *arbiter; 1499 int ret; 1500 1501 mutex_lock(&display->hdcp.hdcp_mutex); 1502 arbiter = display->hdcp.arbiter; 1503 1504 if (!arbiter || !arbiter->ops) { 1505 mutex_unlock(&display->hdcp.hdcp_mutex); 1506 return -EINVAL; 1507 } 1508 1509 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1510 &dig_port->hdcp.port_data); 1511 mutex_unlock(&display->hdcp.hdcp_mutex); 1512 1513 return ret; 1514 } 1515 1516 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1517 { 1518 return hdcp2_close_session(connector); 1519 } 1520 1521 /* Authentication flow starts from here */ 1522 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1523 { 1524 struct intel_display *display = to_intel_display(connector); 1525 struct intel_digital_port *dig_port = 1526 intel_attached_dig_port(connector); 1527 struct intel_hdcp *hdcp = &connector->hdcp; 1528 union { 1529 struct hdcp2_ake_init ake_init; 1530 struct hdcp2_ake_send_cert send_cert; 1531 struct hdcp2_ake_no_stored_km no_stored_km; 1532 struct hdcp2_ake_send_hprime send_hprime; 1533 struct hdcp2_ake_send_pairing_info pairing_info; 1534 } msgs; 1535 const struct intel_hdcp_shim *shim = hdcp->shim; 1536 size_t size; 1537 int ret, i, max_retries; 1538 1539 /* Init for seq_num */ 1540 hdcp->seq_num_v = 0; 1541 hdcp->seq_num_m = 0; 1542 1543 if (intel_encoder_is_dp(&dig_port->base) || 1544 intel_encoder_is_mst(&dig_port->base)) 1545 max_retries = 10; 1546 else 1547 max_retries = 1; 1548 1549 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1550 if (ret < 0) 1551 return ret; 1552 1553 /* 1554 * Retry the first read and write to downstream at least 10 times 1555 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1556 * (dock decides to stop advertising hdcp2 capability for some reason). 1557 * The reason being that during suspend resume dock usually keeps the 1558 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1559 * big problem if the userspace just kept retrying with some delay while 1560 * it continues to play low value content but most userspace applications 1561 * end up throwing an error when it receives one from KMD. This makes 1562 * sure we give the dock and the sink devices to complete its power cycle 1563 * and then try HDCP authentication. The values of 10 and delay of 50ms 1564 * was decided based on multiple trial and errors. 1565 */ 1566 for (i = 0; i < max_retries; i++) { 1567 if (!intel_hdcp2_get_capability(connector)) { 1568 msleep(50); 1569 continue; 1570 } 1571 1572 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1573 sizeof(msgs.ake_init)); 1574 if (ret < 0) 1575 continue; 1576 1577 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1578 &msgs.send_cert, sizeof(msgs.send_cert)); 1579 if (ret > 0) 1580 break; 1581 } 1582 1583 if (ret < 0) 1584 return ret; 1585 1586 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1587 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1588 return -EINVAL; 1589 } 1590 1591 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1592 1593 if (drm_hdcp_check_ksvs_revoked(display->drm, 1594 msgs.send_cert.cert_rx.receiver_id, 1595 1) > 0) { 1596 drm_err(display->drm, "Receiver ID is revoked\n"); 1597 return -EPERM; 1598 } 1599 1600 /* 1601 * Here msgs.no_stored_km will hold msgs corresponding to the km 1602 * stored also. 1603 */ 1604 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1605 &hdcp->is_paired, 1606 &msgs.no_stored_km, &size); 1607 if (ret < 0) 1608 return ret; 1609 1610 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1611 if (ret < 0) 1612 return ret; 1613 1614 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1615 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1616 if (ret < 0) 1617 return ret; 1618 1619 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1620 if (ret < 0) 1621 return ret; 1622 1623 if (!hdcp->is_paired) { 1624 /* Pairing is required */ 1625 ret = shim->read_2_2_msg(connector, 1626 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1627 &msgs.pairing_info, 1628 sizeof(msgs.pairing_info)); 1629 if (ret < 0) 1630 return ret; 1631 1632 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1633 if (ret < 0) 1634 return ret; 1635 hdcp->is_paired = true; 1636 } 1637 1638 return 0; 1639 } 1640 1641 static int hdcp2_locality_check(struct intel_connector *connector) 1642 { 1643 struct intel_hdcp *hdcp = &connector->hdcp; 1644 union { 1645 struct hdcp2_lc_init lc_init; 1646 struct hdcp2_lc_send_lprime send_lprime; 1647 } msgs; 1648 const struct intel_hdcp_shim *shim = hdcp->shim; 1649 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1650 1651 for (i = 0; i < tries; i++) { 1652 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1653 if (ret < 0) 1654 continue; 1655 1656 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1657 sizeof(msgs.lc_init)); 1658 if (ret < 0) 1659 continue; 1660 1661 ret = shim->read_2_2_msg(connector, 1662 HDCP_2_2_LC_SEND_LPRIME, 1663 &msgs.send_lprime, 1664 sizeof(msgs.send_lprime)); 1665 if (ret < 0) 1666 continue; 1667 1668 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1669 if (!ret) 1670 break; 1671 } 1672 1673 return ret; 1674 } 1675 1676 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1677 { 1678 struct intel_hdcp *hdcp = &connector->hdcp; 1679 struct hdcp2_ske_send_eks send_eks; 1680 int ret; 1681 1682 ret = hdcp2_prepare_skey(connector, &send_eks); 1683 if (ret < 0) 1684 return ret; 1685 1686 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1687 sizeof(send_eks)); 1688 if (ret < 0) 1689 return ret; 1690 1691 return 0; 1692 } 1693 1694 static 1695 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1696 { 1697 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1698 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1699 struct intel_hdcp *hdcp = &connector->hdcp; 1700 union { 1701 struct hdcp2_rep_stream_manage stream_manage; 1702 struct hdcp2_rep_stream_ready stream_ready; 1703 } msgs; 1704 const struct intel_hdcp_shim *shim = hdcp->shim; 1705 int ret, streams_size_delta, i; 1706 1707 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1708 return -ERANGE; 1709 1710 /* Prepare RepeaterAuth_Stream_Manage msg */ 1711 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1712 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1713 1714 msgs.stream_manage.k = cpu_to_be16(data->k); 1715 1716 for (i = 0; i < data->k; i++) { 1717 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1718 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1719 } 1720 1721 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1722 sizeof(struct hdcp2_streamid_type); 1723 /* Send it to Repeater */ 1724 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1725 sizeof(msgs.stream_manage) - streams_size_delta); 1726 if (ret < 0) 1727 goto out; 1728 1729 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1730 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1731 if (ret < 0) 1732 goto out; 1733 1734 data->seq_num_m = hdcp->seq_num_m; 1735 1736 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1737 1738 out: 1739 hdcp->seq_num_m++; 1740 1741 return ret; 1742 } 1743 1744 static 1745 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1746 { 1747 struct intel_display *display = to_intel_display(connector); 1748 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1749 struct intel_hdcp *hdcp = &connector->hdcp; 1750 union { 1751 struct hdcp2_rep_send_receiverid_list recvid_list; 1752 struct hdcp2_rep_send_ack rep_ack; 1753 } msgs; 1754 const struct intel_hdcp_shim *shim = hdcp->shim; 1755 u32 seq_num_v, device_cnt; 1756 u8 *rx_info; 1757 int ret; 1758 1759 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1760 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1761 if (ret < 0) 1762 return ret; 1763 1764 rx_info = msgs.recvid_list.rx_info; 1765 1766 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1767 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1768 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1769 return -EINVAL; 1770 } 1771 1772 /* 1773 * MST topology is not Type 1 capable if it contains a downstream 1774 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1775 */ 1776 dig_port->hdcp.mst_type1_capable = 1777 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1778 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1779 1780 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1781 drm_dbg_kms(display->drm, 1782 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1783 return -EINVAL; 1784 } 1785 1786 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1787 seq_num_v = 1788 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1789 1790 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1791 drm_dbg_kms(display->drm, 1792 "Non zero Seq_num_v at first RecvId_List msg\n"); 1793 return -EINVAL; 1794 } 1795 1796 if (seq_num_v < hdcp->seq_num_v) { 1797 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1798 drm_dbg_kms(display->drm, "Seq_num_v roll over.\n"); 1799 return -EINVAL; 1800 } 1801 1802 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1803 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1804 if (drm_hdcp_check_ksvs_revoked(display->drm, 1805 msgs.recvid_list.receiver_ids, 1806 device_cnt) > 0) { 1807 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1808 return -EPERM; 1809 } 1810 1811 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1812 &msgs.recvid_list, 1813 &msgs.rep_ack); 1814 if (ret < 0) 1815 return ret; 1816 1817 hdcp->seq_num_v = seq_num_v; 1818 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1819 sizeof(msgs.rep_ack)); 1820 if (ret < 0) 1821 return ret; 1822 1823 return 0; 1824 } 1825 1826 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1827 { 1828 struct intel_display *display = to_intel_display(connector); 1829 struct intel_hdcp *hdcp = &connector->hdcp; 1830 const struct intel_hdcp_shim *shim = hdcp->shim; 1831 int ret; 1832 1833 ret = hdcp2_authentication_key_exchange(connector); 1834 if (ret < 0) { 1835 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1836 return ret; 1837 } 1838 1839 ret = hdcp2_locality_check(connector); 1840 if (ret < 0) { 1841 drm_dbg_kms(display->drm, 1842 "Locality Check failed. Err : %d\n", ret); 1843 return ret; 1844 } 1845 1846 ret = hdcp2_session_key_exchange(connector); 1847 if (ret < 0) { 1848 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1849 return ret; 1850 } 1851 1852 if (shim->config_stream_type) { 1853 ret = shim->config_stream_type(connector, 1854 hdcp->is_repeater, 1855 hdcp->content_type); 1856 if (ret < 0) 1857 return ret; 1858 } 1859 1860 if (hdcp->is_repeater) { 1861 ret = hdcp2_authenticate_repeater_topology(connector); 1862 if (ret < 0) { 1863 drm_dbg_kms(display->drm, 1864 "Repeater Auth Failed. Err: %d\n", ret); 1865 return ret; 1866 } 1867 } 1868 1869 return ret; 1870 } 1871 1872 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1873 { 1874 struct intel_display *display = to_intel_display(connector); 1875 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1876 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1877 struct intel_hdcp *hdcp = &connector->hdcp; 1878 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1879 enum port port = dig_port->base.port; 1880 int ret = 0; 1881 1882 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1883 LINK_ENCRYPTION_STATUS)) { 1884 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1885 connector->base.base.id, connector->base.name); 1886 ret = -EPERM; 1887 goto link_recover; 1888 } 1889 1890 if (hdcp->shim->stream_2_2_encryption) { 1891 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1892 if (ret) { 1893 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1894 connector->base.base.id, connector->base.name); 1895 return ret; 1896 } 1897 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1898 transcoder_name(hdcp->stream_transcoder)); 1899 } 1900 1901 return 0; 1902 1903 link_recover: 1904 if (hdcp2_deauthenticate_port(connector) < 0) 1905 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1906 1907 dig_port->hdcp.auth_status = false; 1908 data->k = 0; 1909 1910 return ret; 1911 } 1912 1913 static int hdcp2_enable_encryption(struct intel_connector *connector) 1914 { 1915 struct intel_display *display = to_intel_display(connector); 1916 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1917 struct intel_hdcp *hdcp = &connector->hdcp; 1918 enum port port = dig_port->base.port; 1919 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1920 int ret; 1921 1922 drm_WARN_ON(display->drm, 1923 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1924 LINK_ENCRYPTION_STATUS); 1925 if (hdcp->shim->toggle_signalling) { 1926 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1927 true); 1928 if (ret) { 1929 drm_err(display->drm, 1930 "Failed to enable HDCP signalling. %d\n", 1931 ret); 1932 return ret; 1933 } 1934 } 1935 1936 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1937 LINK_AUTH_STATUS) 1938 /* Link is Authenticated. Now set for Encryption */ 1939 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1940 0, CTL_LINK_ENCRYPTION_REQ); 1941 1942 ret = intel_de_wait_for_set(display, 1943 HDCP2_STATUS(display, cpu_transcoder, 1944 port), 1945 LINK_ENCRYPTION_STATUS, 1946 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1947 dig_port->hdcp.auth_status = true; 1948 1949 return ret; 1950 } 1951 1952 static int hdcp2_disable_encryption(struct intel_connector *connector) 1953 { 1954 struct intel_display *display = to_intel_display(connector); 1955 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1956 struct intel_hdcp *hdcp = &connector->hdcp; 1957 enum port port = dig_port->base.port; 1958 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1959 int ret; 1960 1961 drm_WARN_ON(display->drm, 1962 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1963 LINK_ENCRYPTION_STATUS)); 1964 1965 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1966 CTL_LINK_ENCRYPTION_REQ, 0); 1967 1968 ret = intel_de_wait_for_clear(display, 1969 HDCP2_STATUS(display, cpu_transcoder, 1970 port), 1971 LINK_ENCRYPTION_STATUS, 1972 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1973 if (ret == -ETIMEDOUT) 1974 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1975 1976 if (hdcp->shim->toggle_signalling) { 1977 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1978 false); 1979 if (ret) { 1980 drm_err(display->drm, 1981 "Failed to disable HDCP signalling. %d\n", 1982 ret); 1983 return ret; 1984 } 1985 } 1986 1987 return ret; 1988 } 1989 1990 static int 1991 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1992 { 1993 struct intel_display *display = to_intel_display(connector); 1994 int i, tries = 3, ret; 1995 1996 if (!connector->hdcp.is_repeater) 1997 return 0; 1998 1999 for (i = 0; i < tries; i++) { 2000 ret = _hdcp2_propagate_stream_management_info(connector); 2001 if (!ret) 2002 break; 2003 2004 /* Lets restart the auth incase of seq_num_m roll over */ 2005 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2006 drm_dbg_kms(display->drm, 2007 "seq_num_m roll over.(%d)\n", ret); 2008 break; 2009 } 2010 2011 drm_dbg_kms(display->drm, 2012 "HDCP2 stream management %d of %d Failed.(%d)\n", 2013 i + 1, tries, ret); 2014 } 2015 2016 return ret; 2017 } 2018 2019 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2020 struct intel_connector *connector) 2021 { 2022 struct intel_display *display = to_intel_display(connector); 2023 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2024 int ret = 0, i, tries = 3; 2025 2026 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2027 ret = hdcp2_authenticate_sink(connector); 2028 if (!ret) { 2029 ret = intel_hdcp_prepare_streams(state, connector); 2030 if (ret) { 2031 drm_dbg_kms(display->drm, 2032 "Prepare stream failed.(%d)\n", 2033 ret); 2034 break; 2035 } 2036 2037 ret = hdcp2_propagate_stream_management_info(connector); 2038 if (ret) { 2039 drm_dbg_kms(display->drm, 2040 "Stream management failed.(%d)\n", 2041 ret); 2042 break; 2043 } 2044 2045 ret = hdcp2_authenticate_port(connector); 2046 if (!ret) 2047 break; 2048 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2049 ret); 2050 } 2051 2052 /* Clearing the mei hdcp session */ 2053 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2054 i + 1, tries, ret); 2055 if (hdcp2_deauthenticate_port(connector) < 0) 2056 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2057 } 2058 2059 if (!ret && !dig_port->hdcp.auth_status) { 2060 /* 2061 * Ensuring the required 200mSec min time interval between 2062 * Session Key Exchange and encryption. 2063 */ 2064 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2065 ret = hdcp2_enable_encryption(connector); 2066 if (ret < 0) { 2067 drm_dbg_kms(display->drm, 2068 "Encryption Enable Failed.(%d)\n", ret); 2069 if (hdcp2_deauthenticate_port(connector) < 0) 2070 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2071 } 2072 } 2073 2074 if (!ret) 2075 ret = hdcp2_enable_stream_encryption(connector); 2076 2077 return ret; 2078 } 2079 2080 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2081 struct intel_connector *connector) 2082 { 2083 struct intel_display *display = to_intel_display(connector); 2084 struct intel_hdcp *hdcp = &connector->hdcp; 2085 int ret; 2086 2087 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2088 connector->base.base.id, connector->base.name, 2089 hdcp->content_type); 2090 2091 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2092 2093 ret = hdcp2_authenticate_and_encrypt(state, connector); 2094 if (ret) { 2095 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2096 hdcp->content_type, ret); 2097 return ret; 2098 } 2099 2100 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2101 connector->base.base.id, connector->base.name, 2102 hdcp->content_type); 2103 2104 hdcp->hdcp2_encrypted = true; 2105 return 0; 2106 } 2107 2108 static int 2109 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2110 { 2111 struct intel_display *display = to_intel_display(connector); 2112 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2113 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2114 struct intel_hdcp *hdcp = &connector->hdcp; 2115 int ret; 2116 2117 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2118 connector->base.base.id, connector->base.name); 2119 2120 if (hdcp->shim->stream_2_2_encryption) { 2121 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2122 if (ret) { 2123 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2124 connector->base.base.id, connector->base.name); 2125 return ret; 2126 } 2127 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2128 transcoder_name(hdcp->stream_transcoder)); 2129 2130 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2131 return 0; 2132 } 2133 2134 ret = hdcp2_disable_encryption(connector); 2135 2136 if (hdcp2_deauthenticate_port(connector) < 0) 2137 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2138 2139 connector->hdcp.hdcp2_encrypted = false; 2140 dig_port->hdcp.auth_status = false; 2141 data->k = 0; 2142 2143 return ret; 2144 } 2145 2146 /* Implements the Link Integrity Check for HDCP2.2 */ 2147 static int intel_hdcp2_check_link(struct intel_connector *connector) 2148 { 2149 struct intel_display *display = to_intel_display(connector); 2150 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2151 struct intel_hdcp *hdcp = &connector->hdcp; 2152 enum port port = dig_port->base.port; 2153 enum transcoder cpu_transcoder; 2154 int ret = 0; 2155 2156 mutex_lock(&hdcp->mutex); 2157 mutex_lock(&dig_port->hdcp.mutex); 2158 cpu_transcoder = hdcp->cpu_transcoder; 2159 2160 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2161 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2162 !hdcp->hdcp2_encrypted) { 2163 ret = -EINVAL; 2164 goto out; 2165 } 2166 2167 if (drm_WARN_ON(display->drm, 2168 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2169 drm_err(display->drm, 2170 "HDCP2.2 link stopped the encryption, %x\n", 2171 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2172 ret = -ENXIO; 2173 _intel_hdcp2_disable(connector, true); 2174 intel_hdcp_update_value(connector, 2175 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2176 true); 2177 goto out; 2178 } 2179 2180 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2181 if (ret == HDCP_LINK_PROTECTED) { 2182 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2183 intel_hdcp_update_value(connector, 2184 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2185 true); 2186 } 2187 goto out; 2188 } 2189 2190 if (ret == HDCP_TOPOLOGY_CHANGE) { 2191 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2192 goto out; 2193 2194 drm_dbg_kms(display->drm, 2195 "HDCP2.2 Downstream topology change\n"); 2196 2197 ret = hdcp2_authenticate_repeater_topology(connector); 2198 if (!ret) { 2199 intel_hdcp_update_value(connector, 2200 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2201 true); 2202 goto out; 2203 } 2204 2205 drm_dbg_kms(display->drm, 2206 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2207 connector->base.base.id, connector->base.name, 2208 ret); 2209 } else { 2210 drm_dbg_kms(display->drm, 2211 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2212 connector->base.base.id, connector->base.name); 2213 } 2214 2215 ret = _intel_hdcp2_disable(connector, true); 2216 if (ret) { 2217 drm_err(display->drm, 2218 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2219 connector->base.base.id, connector->base.name, ret); 2220 intel_hdcp_update_value(connector, 2221 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2222 goto out; 2223 } 2224 2225 intel_hdcp_update_value(connector, 2226 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2227 out: 2228 mutex_unlock(&dig_port->hdcp.mutex); 2229 mutex_unlock(&hdcp->mutex); 2230 return ret; 2231 } 2232 2233 static void intel_hdcp_check_work(struct work_struct *work) 2234 { 2235 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2236 struct intel_hdcp, 2237 check_work); 2238 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2239 struct intel_display *display = to_intel_display(connector); 2240 2241 if (drm_connector_is_unregistered(&connector->base)) 2242 return; 2243 2244 if (!intel_hdcp2_check_link(connector)) 2245 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2246 DRM_HDCP2_CHECK_PERIOD_MS); 2247 else if (!intel_hdcp_check_link(connector)) 2248 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2249 DRM_HDCP_CHECK_PERIOD_MS); 2250 } 2251 2252 static int i915_hdcp_component_bind(struct device *drv_kdev, 2253 struct device *mei_kdev, void *data) 2254 { 2255 struct intel_display *display = to_intel_display(drv_kdev); 2256 2257 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2258 mutex_lock(&display->hdcp.hdcp_mutex); 2259 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2260 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2261 mutex_unlock(&display->hdcp.hdcp_mutex); 2262 2263 return 0; 2264 } 2265 2266 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2267 struct device *mei_kdev, void *data) 2268 { 2269 struct intel_display *display = to_intel_display(drv_kdev); 2270 2271 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2272 mutex_lock(&display->hdcp.hdcp_mutex); 2273 display->hdcp.arbiter = NULL; 2274 mutex_unlock(&display->hdcp.hdcp_mutex); 2275 } 2276 2277 static const struct component_ops i915_hdcp_ops = { 2278 .bind = i915_hdcp_component_bind, 2279 .unbind = i915_hdcp_component_unbind, 2280 }; 2281 2282 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2283 { 2284 switch (port) { 2285 case PORT_A: 2286 return HDCP_DDI_A; 2287 case PORT_B ... PORT_F: 2288 return (enum hdcp_ddi)port; 2289 default: 2290 return HDCP_DDI_INVALID_PORT; 2291 } 2292 } 2293 2294 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2295 { 2296 switch (cpu_transcoder) { 2297 case TRANSCODER_A ... TRANSCODER_D: 2298 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2299 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2300 return HDCP_INVALID_TRANSCODER; 2301 } 2302 } 2303 2304 static int initialize_hdcp_port_data(struct intel_connector *connector, 2305 struct intel_digital_port *dig_port, 2306 const struct intel_hdcp_shim *shim) 2307 { 2308 struct intel_display *display = to_intel_display(connector); 2309 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2310 enum port port = dig_port->base.port; 2311 2312 if (DISPLAY_VER(display) < 12) 2313 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2314 else 2315 /* 2316 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2317 * with zero(INVALID PORT index). 2318 */ 2319 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2320 2321 /* 2322 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2323 * is initialized to zero (invalid transcoder index). This will be 2324 * retained for <Gen12 forever. 2325 */ 2326 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2327 2328 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2329 data->protocol = (u8)shim->protocol; 2330 2331 if (!data->streams) 2332 data->streams = kcalloc(INTEL_NUM_PIPES(display), 2333 sizeof(struct hdcp2_streamid_type), 2334 GFP_KERNEL); 2335 if (!data->streams) { 2336 drm_err(display->drm, "Out of Memory\n"); 2337 return -ENOMEM; 2338 } 2339 2340 return 0; 2341 } 2342 2343 static bool is_hdcp2_supported(struct intel_display *display) 2344 { 2345 if (USE_HDCP_GSC(display)) 2346 return true; 2347 2348 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2349 return false; 2350 2351 return DISPLAY_VER(display) >= 10 || 2352 display->platform.kabylake || 2353 display->platform.coffeelake || 2354 display->platform.cometlake; 2355 } 2356 2357 void intel_hdcp_component_init(struct intel_display *display) 2358 { 2359 int ret; 2360 2361 if (!is_hdcp2_supported(display)) 2362 return; 2363 2364 mutex_lock(&display->hdcp.hdcp_mutex); 2365 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2366 2367 display->hdcp.comp_added = true; 2368 mutex_unlock(&display->hdcp.hdcp_mutex); 2369 if (USE_HDCP_GSC(display)) 2370 ret = intel_hdcp_gsc_init(display); 2371 else 2372 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2373 I915_COMPONENT_HDCP); 2374 2375 if (ret < 0) { 2376 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2377 ret); 2378 mutex_lock(&display->hdcp.hdcp_mutex); 2379 display->hdcp.comp_added = false; 2380 mutex_unlock(&display->hdcp.hdcp_mutex); 2381 return; 2382 } 2383 } 2384 2385 static void intel_hdcp2_init(struct intel_connector *connector, 2386 struct intel_digital_port *dig_port, 2387 const struct intel_hdcp_shim *shim) 2388 { 2389 struct intel_display *display = to_intel_display(connector); 2390 struct intel_hdcp *hdcp = &connector->hdcp; 2391 int ret; 2392 2393 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2394 if (ret) { 2395 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2396 return; 2397 } 2398 2399 hdcp->hdcp2_supported = true; 2400 } 2401 2402 int intel_hdcp_init(struct intel_connector *connector, 2403 struct intel_digital_port *dig_port, 2404 const struct intel_hdcp_shim *shim) 2405 { 2406 struct intel_display *display = to_intel_display(connector); 2407 struct intel_hdcp *hdcp = &connector->hdcp; 2408 int ret; 2409 2410 if (!shim) 2411 return -EINVAL; 2412 2413 if (is_hdcp2_supported(display)) 2414 intel_hdcp2_init(connector, dig_port, shim); 2415 2416 ret = drm_connector_attach_content_protection_property(&connector->base, 2417 hdcp->hdcp2_supported); 2418 if (ret) { 2419 hdcp->hdcp2_supported = false; 2420 kfree(dig_port->hdcp.port_data.streams); 2421 return ret; 2422 } 2423 2424 hdcp->shim = shim; 2425 mutex_init(&hdcp->mutex); 2426 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2427 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2428 init_waitqueue_head(&hdcp->cp_irq_queue); 2429 2430 return 0; 2431 } 2432 2433 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2434 struct intel_encoder *encoder, 2435 const struct intel_crtc_state *pipe_config, 2436 const struct drm_connector_state *conn_state) 2437 { 2438 struct intel_display *display = to_intel_display(encoder); 2439 struct intel_connector *connector = 2440 to_intel_connector(conn_state->connector); 2441 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2442 struct intel_hdcp *hdcp = &connector->hdcp; 2443 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2444 int ret = -EINVAL; 2445 2446 if (!hdcp->shim) 2447 return -ENOENT; 2448 2449 if (!connector->encoder) { 2450 drm_err(display->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n", 2451 connector->base.base.id, connector->base.name); 2452 return -ENODEV; 2453 } 2454 2455 mutex_lock(&hdcp->mutex); 2456 mutex_lock(&dig_port->hdcp.mutex); 2457 drm_WARN_ON(display->drm, 2458 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2459 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2460 2461 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2462 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2463 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2464 } else { 2465 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2466 hdcp->stream_transcoder = INVALID_TRANSCODER; 2467 } 2468 2469 if (DISPLAY_VER(display) >= 12) 2470 dig_port->hdcp.port_data.hdcp_transcoder = 2471 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2472 2473 /* 2474 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2475 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2476 */ 2477 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2478 ret = _intel_hdcp2_enable(state, connector); 2479 if (!ret) 2480 check_link_interval = 2481 DRM_HDCP2_CHECK_PERIOD_MS; 2482 } 2483 2484 if (hdcp->force_hdcp14) 2485 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2486 2487 /* 2488 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2489 * be attempted. 2490 */ 2491 if (ret && intel_hdcp_get_capability(connector) && 2492 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2493 ret = intel_hdcp1_enable(connector); 2494 } 2495 2496 if (!ret) { 2497 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2498 check_link_interval); 2499 intel_hdcp_update_value(connector, 2500 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2501 true); 2502 } 2503 2504 mutex_unlock(&dig_port->hdcp.mutex); 2505 mutex_unlock(&hdcp->mutex); 2506 return ret; 2507 } 2508 2509 void intel_hdcp_enable(struct intel_atomic_state *state, 2510 struct intel_encoder *encoder, 2511 const struct intel_crtc_state *crtc_state, 2512 const struct drm_connector_state *conn_state) 2513 { 2514 struct intel_connector *connector = 2515 to_intel_connector(conn_state->connector); 2516 struct intel_hdcp *hdcp = &connector->hdcp; 2517 2518 /* 2519 * Enable hdcp if it's desired or if userspace is enabled and 2520 * driver set its state to undesired 2521 */ 2522 if (conn_state->content_protection == 2523 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2524 (conn_state->content_protection == 2525 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2526 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2527 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2528 } 2529 2530 int intel_hdcp_disable(struct intel_connector *connector) 2531 { 2532 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2533 struct intel_hdcp *hdcp = &connector->hdcp; 2534 int ret = 0; 2535 2536 if (!hdcp->shim) 2537 return -ENOENT; 2538 2539 mutex_lock(&hdcp->mutex); 2540 mutex_lock(&dig_port->hdcp.mutex); 2541 2542 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2543 goto out; 2544 2545 intel_hdcp_update_value(connector, 2546 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2547 if (hdcp->hdcp2_encrypted) 2548 ret = _intel_hdcp2_disable(connector, false); 2549 else if (hdcp->hdcp_encrypted) 2550 ret = _intel_hdcp_disable(connector); 2551 2552 out: 2553 mutex_unlock(&dig_port->hdcp.mutex); 2554 mutex_unlock(&hdcp->mutex); 2555 cancel_delayed_work_sync(&hdcp->check_work); 2556 return ret; 2557 } 2558 2559 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2560 struct intel_encoder *encoder, 2561 const struct intel_crtc_state *crtc_state, 2562 const struct drm_connector_state *conn_state) 2563 { 2564 struct intel_connector *connector = 2565 to_intel_connector(conn_state->connector); 2566 struct intel_hdcp *hdcp = &connector->hdcp; 2567 bool content_protection_type_changed, desired_and_not_enabled = false; 2568 struct intel_display *display = to_intel_display(connector); 2569 2570 if (!connector->hdcp.shim) 2571 return; 2572 2573 content_protection_type_changed = 2574 (conn_state->hdcp_content_type != hdcp->content_type && 2575 conn_state->content_protection != 2576 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2577 2578 /* 2579 * During the HDCP encryption session if Type change is requested, 2580 * disable the HDCP and re-enable it with new TYPE value. 2581 */ 2582 if (conn_state->content_protection == 2583 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2584 content_protection_type_changed) 2585 intel_hdcp_disable(connector); 2586 2587 /* 2588 * Mark the hdcp state as DESIRED after the hdcp disable of type 2589 * change procedure. 2590 */ 2591 if (content_protection_type_changed) { 2592 mutex_lock(&hdcp->mutex); 2593 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2594 drm_connector_get(&connector->base); 2595 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2596 drm_connector_put(&connector->base); 2597 mutex_unlock(&hdcp->mutex); 2598 } 2599 2600 if (conn_state->content_protection == 2601 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2602 mutex_lock(&hdcp->mutex); 2603 /* Avoid enabling hdcp, if it already ENABLED */ 2604 desired_and_not_enabled = 2605 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2606 mutex_unlock(&hdcp->mutex); 2607 /* 2608 * If HDCP already ENABLED and CP property is DESIRED, schedule 2609 * prop_work to update correct CP property to user space. 2610 */ 2611 if (!desired_and_not_enabled && !content_protection_type_changed) { 2612 drm_connector_get(&connector->base); 2613 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2614 drm_connector_put(&connector->base); 2615 2616 } 2617 } 2618 2619 if (desired_and_not_enabled || content_protection_type_changed) 2620 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2621 } 2622 2623 void intel_hdcp_cancel_works(struct intel_connector *connector) 2624 { 2625 if (!connector->hdcp.shim) 2626 return; 2627 2628 cancel_delayed_work_sync(&connector->hdcp.check_work); 2629 cancel_work_sync(&connector->hdcp.prop_work); 2630 } 2631 2632 void intel_hdcp_component_fini(struct intel_display *display) 2633 { 2634 mutex_lock(&display->hdcp.hdcp_mutex); 2635 if (!display->hdcp.comp_added) { 2636 mutex_unlock(&display->hdcp.hdcp_mutex); 2637 return; 2638 } 2639 2640 display->hdcp.comp_added = false; 2641 mutex_unlock(&display->hdcp.hdcp_mutex); 2642 2643 if (USE_HDCP_GSC(display)) 2644 intel_hdcp_gsc_fini(display); 2645 else 2646 component_del(display->drm->dev, &i915_hdcp_ops); 2647 } 2648 2649 void intel_hdcp_cleanup(struct intel_connector *connector) 2650 { 2651 struct intel_hdcp *hdcp = &connector->hdcp; 2652 2653 if (!hdcp->shim) 2654 return; 2655 2656 /* 2657 * If the connector is registered, it's possible userspace could kick 2658 * off another HDCP enable, which would re-spawn the workers. 2659 */ 2660 drm_WARN_ON(connector->base.dev, 2661 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2662 2663 /* 2664 * Now that the connector is not registered, check_work won't be run, 2665 * but cancel any outstanding instances of it 2666 */ 2667 cancel_delayed_work_sync(&hdcp->check_work); 2668 2669 /* 2670 * We don't cancel prop_work in the same way as check_work since it 2671 * requires connection_mutex which could be held while calling this 2672 * function. Instead, we rely on the connector references grabbed before 2673 * scheduling prop_work to ensure the connector is alive when prop_work 2674 * is run. So if we're in the destroy path (which is where this 2675 * function should be called), we're "guaranteed" that prop_work is not 2676 * active (tl;dr This Should Never Happen). 2677 */ 2678 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2679 2680 mutex_lock(&hdcp->mutex); 2681 hdcp->shim = NULL; 2682 mutex_unlock(&hdcp->mutex); 2683 } 2684 2685 void intel_hdcp_atomic_check(struct drm_connector *connector, 2686 struct drm_connector_state *old_state, 2687 struct drm_connector_state *new_state) 2688 { 2689 u64 old_cp = old_state->content_protection; 2690 u64 new_cp = new_state->content_protection; 2691 struct drm_crtc_state *crtc_state; 2692 2693 if (!new_state->crtc) { 2694 /* 2695 * If the connector is being disabled with CP enabled, mark it 2696 * desired so it's re-enabled when the connector is brought back 2697 */ 2698 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2699 new_state->content_protection = 2700 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2701 return; 2702 } 2703 2704 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2705 new_state->crtc); 2706 /* 2707 * Fix the HDCP uapi content protection state in case of modeset. 2708 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2709 * need to be sent if there is transition from ENABLED->DESIRED. 2710 */ 2711 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2712 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2713 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2714 new_state->content_protection = 2715 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2716 2717 /* 2718 * Nothing to do if the state didn't change, or HDCP was activated since 2719 * the last commit. And also no change in hdcp content type. 2720 */ 2721 if (old_cp == new_cp || 2722 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2723 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2724 if (old_state->hdcp_content_type == 2725 new_state->hdcp_content_type) 2726 return; 2727 } 2728 2729 crtc_state->mode_changed = true; 2730 } 2731 2732 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2733 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2734 { 2735 struct intel_hdcp *hdcp = &connector->hdcp; 2736 struct intel_display *display = to_intel_display(connector); 2737 2738 if (!hdcp->shim) 2739 return; 2740 2741 atomic_inc(&connector->hdcp.cp_irq_count); 2742 wake_up_all(&connector->hdcp.cp_irq_queue); 2743 2744 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0); 2745 } 2746 2747 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2748 bool remote_req) 2749 { 2750 bool hdcp_cap = false, hdcp2_cap = false; 2751 2752 if (!connector->hdcp.shim) { 2753 seq_puts(m, "No Connector Support"); 2754 goto out; 2755 } 2756 2757 if (remote_req) { 2758 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2759 } else { 2760 hdcp_cap = intel_hdcp_get_capability(connector); 2761 hdcp2_cap = intel_hdcp2_get_capability(connector); 2762 } 2763 2764 if (hdcp_cap) 2765 seq_puts(m, "HDCP1.4 "); 2766 if (hdcp2_cap) 2767 seq_puts(m, "HDCP2.2 "); 2768 2769 if (!hdcp_cap && !hdcp2_cap) 2770 seq_puts(m, "None"); 2771 2772 out: 2773 seq_puts(m, "\n"); 2774 } 2775 2776 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2777 { 2778 seq_puts(m, "\tHDCP version: "); 2779 if (connector->mst.dp) { 2780 __intel_hdcp_info(m, connector, true); 2781 seq_puts(m, "\tMST Hub HDCP version: "); 2782 } 2783 __intel_hdcp_info(m, connector, false); 2784 } 2785 2786 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2787 { 2788 struct intel_connector *connector = m->private; 2789 struct intel_display *display = to_intel_display(connector); 2790 int ret; 2791 2792 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2793 if (ret) 2794 return ret; 2795 2796 if (!connector->base.encoder || 2797 connector->base.status != connector_status_connected) { 2798 ret = -ENODEV; 2799 goto out; 2800 } 2801 2802 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2803 connector->base.base.id); 2804 __intel_hdcp_info(m, connector, false); 2805 2806 out: 2807 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2808 2809 return ret; 2810 } 2811 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2812 2813 static ssize_t intel_hdcp_force_14_write(struct file *file, 2814 const char __user *ubuf, 2815 size_t len, loff_t *offp) 2816 { 2817 struct seq_file *m = file->private_data; 2818 struct intel_connector *connector = m->private; 2819 struct intel_hdcp *hdcp = &connector->hdcp; 2820 bool force_hdcp14 = false; 2821 int ret; 2822 2823 if (len == 0) 2824 return 0; 2825 2826 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2827 if (ret < 0) 2828 return ret; 2829 2830 hdcp->force_hdcp14 = force_hdcp14; 2831 *offp += len; 2832 2833 return len; 2834 } 2835 2836 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2837 { 2838 struct intel_connector *connector = m->private; 2839 struct intel_display *display = to_intel_display(connector); 2840 struct intel_encoder *encoder = intel_attached_encoder(connector); 2841 struct intel_hdcp *hdcp = &connector->hdcp; 2842 struct drm_crtc *crtc; 2843 int ret; 2844 2845 if (!encoder) 2846 return -ENODEV; 2847 2848 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2849 if (ret) 2850 return ret; 2851 2852 crtc = connector->base.state->crtc; 2853 if (connector->base.status != connector_status_connected || !crtc) { 2854 ret = -ENODEV; 2855 goto out; 2856 } 2857 2858 seq_printf(m, "%s\n", 2859 str_yes_no(hdcp->force_hdcp14)); 2860 out: 2861 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2862 2863 return ret; 2864 } 2865 2866 static int intel_hdcp_force_14_open(struct inode *inode, 2867 struct file *file) 2868 { 2869 return single_open(file, intel_hdcp_force_14_show, 2870 inode->i_private); 2871 } 2872 2873 static const struct file_operations intel_hdcp_force_14_fops = { 2874 .owner = THIS_MODULE, 2875 .open = intel_hdcp_force_14_open, 2876 .read = seq_read, 2877 .llseek = seq_lseek, 2878 .release = single_release, 2879 .write = intel_hdcp_force_14_write 2880 }; 2881 2882 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2883 { 2884 struct dentry *root = connector->base.debugfs_entry; 2885 int connector_type = connector->base.connector_type; 2886 2887 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2888 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2889 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2890 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2891 connector, &intel_hdcp_sink_capability_fops); 2892 debugfs_create_file("i915_force_hdcp14", 0644, root, 2893 connector, &intel_hdcp_force_14_fops); 2894 } 2895 } 2896