1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2017 Google, Inc. 4 * Copyright _ 2017-2019, Intel Corporation. 5 * 6 * Authors: 7 * Sean Paul <seanpaul@chromium.org> 8 * Ramalingam C <ramalingam.c@intel.com> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/debugfs.h> 13 #include <linux/i2c.h> 14 #include <linux/iopoll.h> 15 #include <linux/random.h> 16 17 #include <drm/display/drm_hdcp_helper.h> 18 #include <drm/drm_print.h> 19 #include <drm/intel/i915_component.h> 20 21 #include "i915_reg.h" 22 #include "i915_utils.h" 23 #include "intel_connector.h" 24 #include "intel_de.h" 25 #include "intel_display_power.h" 26 #include "intel_display_power_well.h" 27 #include "intel_display_regs.h" 28 #include "intel_display_rpm.h" 29 #include "intel_display_types.h" 30 #include "intel_dp_mst.h" 31 #include "intel_hdcp.h" 32 #include "intel_hdcp_gsc.h" 33 #include "intel_hdcp_gsc_message.h" 34 #include "intel_hdcp_regs.h" 35 #include "intel_hdcp_shim.h" 36 #include "intel_pcode.h" 37 #include "intel_step.h" 38 39 #define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14) 40 41 #define KEY_LOAD_TRIES 5 42 #define HDCP2_LC_RETRY_CNT 3 43 44 static void 45 intel_hdcp_adjust_hdcp_line_rekeying(struct intel_encoder *encoder, 46 struct intel_hdcp *hdcp, 47 bool enable) 48 { 49 struct intel_display *display = to_intel_display(encoder); 50 i915_reg_t rekey_reg; 51 u32 rekey_bit = 0; 52 53 /* Here we assume HDMI is in TMDS mode of operation */ 54 if (!intel_encoder_is_hdmi(encoder)) 55 return; 56 57 if (DISPLAY_VER(display) >= 30) { 58 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 59 rekey_bit = XE3_TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 60 } else if (IS_DISPLAY_VERx100_STEP(display, 1401, STEP_B0, STEP_FOREVER) || 61 IS_DISPLAY_VERx100_STEP(display, 2000, STEP_B0, STEP_FOREVER)) { 62 rekey_reg = TRANS_DDI_FUNC_CTL(display, hdcp->cpu_transcoder); 63 rekey_bit = TRANS_DDI_HDCP_LINE_REKEY_DISABLE; 64 } else if (IS_DISPLAY_VERx100_STEP(display, 1400, STEP_D0, STEP_FOREVER)) { 65 rekey_reg = CHICKEN_TRANS(display, hdcp->cpu_transcoder); 66 rekey_bit = HDCP_LINE_REKEY_DISABLE; 67 } 68 69 if (rekey_bit) 70 intel_de_rmw(display, rekey_reg, rekey_bit, enable ? 0 : rekey_bit); 71 } 72 73 static int intel_conn_to_vcpi(struct intel_atomic_state *state, 74 struct intel_connector *connector) 75 { 76 struct drm_dp_mst_topology_mgr *mgr; 77 struct drm_dp_mst_atomic_payload *payload; 78 struct drm_dp_mst_topology_state *mst_state; 79 int vcpi = 0; 80 81 /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ 82 if (!connector->mst.port) 83 return 0; 84 mgr = connector->mst.port->mgr; 85 86 drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); 87 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); 88 payload = drm_atomic_get_mst_payload_state(mst_state, connector->mst.port); 89 if (drm_WARN_ON(mgr->dev, !payload)) 90 goto out; 91 92 vcpi = payload->vcpi; 93 if (drm_WARN_ON(mgr->dev, vcpi < 0)) { 94 vcpi = 0; 95 goto out; 96 } 97 out: 98 return vcpi; 99 } 100 101 /* 102 * intel_hdcp_required_content_stream selects the most highest common possible HDCP 103 * content_type for all streams in DP MST topology because security f/w doesn't 104 * have any provision to mark content_type for each stream separately, it marks 105 * all available streams with the content_type proivided at the time of port 106 * authentication. This may prohibit the userspace to use type1 content on 107 * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in 108 * DP MST topology. Though it is not compulsory, security fw should change its 109 * policy to mark different content_types for different streams. 110 */ 111 static int 112 intel_hdcp_required_content_stream(struct intel_atomic_state *state, 113 struct intel_digital_port *dig_port) 114 { 115 struct intel_display *display = to_intel_display(state); 116 struct drm_connector_list_iter conn_iter; 117 struct intel_digital_port *conn_dig_port; 118 struct intel_connector *connector; 119 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 120 bool enforce_type0 = false; 121 int k; 122 123 if (dig_port->hdcp.auth_status) 124 return 0; 125 126 data->k = 0; 127 128 if (!dig_port->hdcp.mst_type1_capable) 129 enforce_type0 = true; 130 131 drm_connector_list_iter_begin(display->drm, &conn_iter); 132 for_each_intel_connector_iter(connector, &conn_iter) { 133 if (connector->base.status == connector_status_disconnected) 134 continue; 135 136 if (!intel_encoder_is_mst(intel_attached_encoder(connector))) 137 continue; 138 139 conn_dig_port = intel_attached_dig_port(connector); 140 if (conn_dig_port != dig_port) 141 continue; 142 143 data->streams[data->k].stream_id = 144 intel_conn_to_vcpi(state, connector); 145 data->k++; 146 147 /* if there is only one active stream */ 148 if (intel_dp_mst_active_streams(&dig_port->dp) <= 1) 149 break; 150 } 151 drm_connector_list_iter_end(&conn_iter); 152 153 if (drm_WARN_ON(display->drm, data->k > INTEL_NUM_PIPES(display) || data->k == 0)) 154 return -EINVAL; 155 156 /* 157 * Apply common protection level across all streams in DP MST Topology. 158 * Use highest supported content type for all streams in DP MST Topology. 159 */ 160 for (k = 0; k < data->k; k++) 161 data->streams[k].stream_type = 162 enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; 163 164 return 0; 165 } 166 167 static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, 168 struct intel_connector *connector) 169 { 170 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 171 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 172 struct intel_hdcp *hdcp = &connector->hdcp; 173 174 if (intel_encoder_is_mst(intel_attached_encoder(connector))) 175 return intel_hdcp_required_content_stream(state, dig_port); 176 177 data->k = 1; 178 data->streams[0].stream_id = 0; 179 data->streams[0].stream_type = hdcp->content_type; 180 181 return 0; 182 } 183 184 static 185 bool intel_hdcp_is_ksv_valid(u8 *ksv) 186 { 187 int i, ones = 0; 188 /* KSV has 20 1's and 20 0's */ 189 for (i = 0; i < DRM_HDCP_KSV_LEN; i++) 190 ones += hweight8(ksv[i]); 191 if (ones != 20) 192 return false; 193 194 return true; 195 } 196 197 static 198 int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, 199 const struct intel_hdcp_shim *shim, u8 *bksv) 200 { 201 struct intel_display *display = to_intel_display(dig_port); 202 int ret, i, tries = 2; 203 204 /* HDCP spec states that we must retry the bksv if it is invalid */ 205 for (i = 0; i < tries; i++) { 206 ret = shim->read_bksv(dig_port, bksv); 207 if (ret) 208 return ret; 209 if (intel_hdcp_is_ksv_valid(bksv)) 210 break; 211 } 212 if (i == tries) { 213 drm_dbg_kms(display->drm, "Bksv is invalid\n"); 214 return -ENODEV; 215 } 216 217 return 0; 218 } 219 220 /* Is HDCP1.4 capable on Platform and Sink */ 221 static bool intel_hdcp_get_capability(struct intel_connector *connector) 222 { 223 struct intel_digital_port *dig_port; 224 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 225 bool capable = false; 226 u8 bksv[5]; 227 228 if (!intel_attached_encoder(connector)) 229 return capable; 230 231 dig_port = intel_attached_dig_port(connector); 232 233 if (!shim) 234 return capable; 235 236 if (shim->hdcp_get_capability) { 237 shim->hdcp_get_capability(dig_port, &capable); 238 } else { 239 if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) 240 capable = true; 241 } 242 243 return capable; 244 } 245 246 /* 247 * Check if the source has all the building blocks ready to make 248 * HDCP 2.2 work 249 */ 250 static bool intel_hdcp2_prerequisite(struct intel_connector *connector) 251 { 252 struct intel_display *display = to_intel_display(connector); 253 struct intel_hdcp *hdcp = &connector->hdcp; 254 255 /* I915 support for HDCP2.2 */ 256 if (!hdcp->hdcp2_supported) 257 return false; 258 259 /* If MTL+ make sure gsc is loaded and proxy is setup */ 260 if (USE_HDCP_GSC(display)) { 261 if (!intel_hdcp_gsc_check_status(display->drm)) 262 return false; 263 } 264 265 /* MEI/GSC interface is solid depending on which is used */ 266 mutex_lock(&display->hdcp.hdcp_mutex); 267 if (!display->hdcp.comp_added || !display->hdcp.arbiter) { 268 mutex_unlock(&display->hdcp.hdcp_mutex); 269 return false; 270 } 271 mutex_unlock(&display->hdcp.hdcp_mutex); 272 273 return true; 274 } 275 276 /* Is HDCP2.2 capable on Platform and Sink */ 277 static bool intel_hdcp2_get_capability(struct intel_connector *connector) 278 { 279 struct intel_hdcp *hdcp = &connector->hdcp; 280 bool capable = false; 281 282 if (!intel_hdcp2_prerequisite(connector)) 283 return false; 284 285 /* Sink's capability for HDCP2.2 */ 286 hdcp->shim->hdcp_2_2_get_capability(connector, &capable); 287 288 return capable; 289 } 290 291 static void intel_hdcp_get_remote_capability(struct intel_connector *connector, 292 bool *hdcp_capable, 293 bool *hdcp2_capable) 294 { 295 struct intel_hdcp *hdcp = &connector->hdcp; 296 297 if (!hdcp->shim->get_remote_hdcp_capability) 298 return; 299 300 hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, 301 hdcp2_capable); 302 303 if (!intel_hdcp2_prerequisite(connector)) 304 *hdcp2_capable = false; 305 } 306 307 static bool intel_hdcp_in_use(struct intel_display *display, 308 enum transcoder cpu_transcoder, enum port port) 309 { 310 return intel_de_read(display, 311 HDCP_STATUS(display, cpu_transcoder, port)) & 312 HDCP_STATUS_ENC; 313 } 314 315 static bool intel_hdcp2_in_use(struct intel_display *display, 316 enum transcoder cpu_transcoder, enum port port) 317 { 318 return intel_de_read(display, 319 HDCP2_STATUS(display, cpu_transcoder, port)) & 320 LINK_ENCRYPTION_STATUS; 321 } 322 323 static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, 324 const struct intel_hdcp_shim *shim) 325 { 326 int ret, read_ret; 327 bool ksv_ready; 328 329 /* Poll for ksv list ready (spec says max time allowed is 5s) */ 330 ret = poll_timeout_us(read_ret = shim->read_ksv_ready(dig_port, &ksv_ready), 331 read_ret || ksv_ready, 332 100 * 1000, 5 * 1000 * 1000, false); 333 if (ret) 334 return ret; 335 if (read_ret) 336 return read_ret; 337 338 return 0; 339 } 340 341 static bool hdcp_key_loadable(struct intel_display *display) 342 { 343 enum i915_power_well_id id; 344 bool enabled = false; 345 346 /* 347 * On HSW and BDW, Display HW loads the Key as soon as Display resumes. 348 * On all BXT+, SW can load the keys only when the PW#1 is turned on. 349 */ 350 if (display->platform.haswell || display->platform.broadwell) 351 id = HSW_DISP_PW_GLOBAL; 352 else 353 id = SKL_DISP_PW_1; 354 355 /* PG1 (power well #1) needs to be enabled */ 356 with_intel_display_rpm(display) 357 enabled = intel_display_power_well_is_enabled(display, id); 358 359 /* 360 * Another req for hdcp key loadability is enabled state of pll for 361 * cdclk. Without active crtc we won't land here. So we are assuming that 362 * cdclk is already on. 363 */ 364 365 return enabled; 366 } 367 368 static void intel_hdcp_clear_keys(struct intel_display *display) 369 { 370 intel_de_write(display, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); 371 intel_de_write(display, HDCP_KEY_STATUS, 372 HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); 373 } 374 375 static int intel_hdcp_load_keys(struct intel_display *display) 376 { 377 int ret; 378 u32 val; 379 380 val = intel_de_read(display, HDCP_KEY_STATUS); 381 if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) 382 return 0; 383 384 /* 385 * On HSW and BDW HW loads the HDCP1.4 Key when Display comes 386 * out of reset. So if Key is not already loaded, its an error state. 387 */ 388 if (display->platform.haswell || display->platform.broadwell) 389 if (!(intel_de_read(display, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) 390 return -ENXIO; 391 392 /* 393 * Initiate loading the HDCP key from fuses. 394 * 395 * BXT+ platforms, HDCP key needs to be loaded by SW. Only display 396 * version 9 platforms (minus BXT) differ in the key load trigger 397 * process from other platforms. These platforms use the GT Driver 398 * Mailbox interface. 399 */ 400 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) { 401 ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1); 402 if (ret) { 403 drm_err(display->drm, 404 "Failed to initiate HDCP key load (%d)\n", 405 ret); 406 return ret; 407 } 408 } else { 409 intel_de_write(display, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); 410 } 411 412 /* Wait for the keys to load (500us) */ 413 ret = intel_de_wait_custom(display, HDCP_KEY_STATUS, 414 HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, 415 10, 1, &val); 416 if (ret) 417 return ret; 418 else if (!(val & HDCP_KEY_LOAD_STATUS)) 419 return -ENXIO; 420 421 /* Send Aksv over to PCH display for use in authentication */ 422 intel_de_write(display, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); 423 424 return 0; 425 } 426 427 /* Returns updated SHA-1 index */ 428 static int intel_write_sha_text(struct intel_display *display, u32 sha_text) 429 { 430 intel_de_write(display, HDCP_SHA_TEXT, sha_text); 431 if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { 432 drm_err(display->drm, "Timed out waiting for SHA1 ready\n"); 433 return -ETIMEDOUT; 434 } 435 return 0; 436 } 437 438 static 439 u32 intel_hdcp_get_repeater_ctl(struct intel_display *display, 440 enum transcoder cpu_transcoder, enum port port) 441 { 442 if (DISPLAY_VER(display) >= 12) { 443 switch (cpu_transcoder) { 444 case TRANSCODER_A: 445 return HDCP_TRANSA_REP_PRESENT | 446 HDCP_TRANSA_SHA1_M0; 447 case TRANSCODER_B: 448 return HDCP_TRANSB_REP_PRESENT | 449 HDCP_TRANSB_SHA1_M0; 450 case TRANSCODER_C: 451 return HDCP_TRANSC_REP_PRESENT | 452 HDCP_TRANSC_SHA1_M0; 453 case TRANSCODER_D: 454 return HDCP_TRANSD_REP_PRESENT | 455 HDCP_TRANSD_SHA1_M0; 456 default: 457 drm_err(display->drm, "Unknown transcoder %d\n", 458 cpu_transcoder); 459 return 0; 460 } 461 } 462 463 switch (port) { 464 case PORT_A: 465 return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; 466 case PORT_B: 467 return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; 468 case PORT_C: 469 return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; 470 case PORT_D: 471 return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; 472 case PORT_E: 473 return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; 474 default: 475 drm_err(display->drm, "Unknown port %d\n", port); 476 return 0; 477 } 478 } 479 480 static 481 int intel_hdcp_validate_v_prime(struct intel_connector *connector, 482 const struct intel_hdcp_shim *shim, 483 u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) 484 { 485 struct intel_display *display = to_intel_display(connector); 486 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 487 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 488 enum port port = dig_port->base.port; 489 u32 vprime, sha_text, sha_leftovers, rep_ctl; 490 int ret, i, j, sha_idx; 491 492 /* Process V' values from the receiver */ 493 for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { 494 ret = shim->read_v_prime_part(dig_port, i, &vprime); 495 if (ret) 496 return ret; 497 intel_de_write(display, HDCP_SHA_V_PRIME(i), vprime); 498 } 499 500 /* 501 * We need to write the concatenation of all device KSVs, BINFO (DP) || 502 * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte 503 * stream is written via the HDCP_SHA_TEXT register in 32-bit 504 * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This 505 * index will keep track of our progress through the 64 bytes as well as 506 * helping us work the 40-bit KSVs through our 32-bit register. 507 * 508 * NOTE: data passed via HDCP_SHA_TEXT should be big-endian 509 */ 510 sha_idx = 0; 511 sha_text = 0; 512 sha_leftovers = 0; 513 rep_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port); 514 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 515 for (i = 0; i < num_downstream; i++) { 516 unsigned int sha_empty; 517 u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; 518 519 /* Fill up the empty slots in sha_text and write it out */ 520 sha_empty = sizeof(sha_text) - sha_leftovers; 521 for (j = 0; j < sha_empty; j++) { 522 u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); 523 sha_text |= ksv[j] << off; 524 } 525 526 ret = intel_write_sha_text(display, sha_text); 527 if (ret < 0) 528 return ret; 529 530 /* Programming guide writes this every 64 bytes */ 531 sha_idx += sizeof(sha_text); 532 if (!(sha_idx % 64)) 533 intel_de_write(display, HDCP_REP_CTL, 534 rep_ctl | HDCP_SHA1_TEXT_32); 535 536 /* Store the leftover bytes from the ksv in sha_text */ 537 sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; 538 sha_text = 0; 539 for (j = 0; j < sha_leftovers; j++) 540 sha_text |= ksv[sha_empty + j] << 541 ((sizeof(sha_text) - j - 1) * 8); 542 543 /* 544 * If we still have room in sha_text for more data, continue. 545 * Otherwise, write it out immediately. 546 */ 547 if (sizeof(sha_text) > sha_leftovers) 548 continue; 549 550 ret = intel_write_sha_text(display, sha_text); 551 if (ret < 0) 552 return ret; 553 sha_leftovers = 0; 554 sha_text = 0; 555 sha_idx += sizeof(sha_text); 556 } 557 558 /* 559 * We need to write BINFO/BSTATUS, and M0 now. Depending on how many 560 * bytes are leftover from the last ksv, we might be able to fit them 561 * all in sha_text (first 2 cases), or we might need to split them up 562 * into 2 writes (last 2 cases). 563 */ 564 if (sha_leftovers == 0) { 565 /* Write 16 bits of text, 16 bits of M0 */ 566 intel_de_write(display, HDCP_REP_CTL, 567 rep_ctl | HDCP_SHA1_TEXT_16); 568 ret = intel_write_sha_text(display, 569 bstatus[0] << 8 | bstatus[1]); 570 if (ret < 0) 571 return ret; 572 sha_idx += sizeof(sha_text); 573 574 /* Write 32 bits of M0 */ 575 intel_de_write(display, HDCP_REP_CTL, 576 rep_ctl | HDCP_SHA1_TEXT_0); 577 ret = intel_write_sha_text(display, 0); 578 if (ret < 0) 579 return ret; 580 sha_idx += sizeof(sha_text); 581 582 /* Write 16 bits of M0 */ 583 intel_de_write(display, HDCP_REP_CTL, 584 rep_ctl | HDCP_SHA1_TEXT_16); 585 ret = intel_write_sha_text(display, 0); 586 if (ret < 0) 587 return ret; 588 sha_idx += sizeof(sha_text); 589 590 } else if (sha_leftovers == 1) { 591 /* Write 24 bits of text, 8 bits of M0 */ 592 intel_de_write(display, HDCP_REP_CTL, 593 rep_ctl | HDCP_SHA1_TEXT_24); 594 sha_text |= bstatus[0] << 16 | bstatus[1] << 8; 595 /* Only 24-bits of data, must be in the LSB */ 596 sha_text = (sha_text & 0xffffff00) >> 8; 597 ret = intel_write_sha_text(display, sha_text); 598 if (ret < 0) 599 return ret; 600 sha_idx += sizeof(sha_text); 601 602 /* Write 32 bits of M0 */ 603 intel_de_write(display, HDCP_REP_CTL, 604 rep_ctl | HDCP_SHA1_TEXT_0); 605 ret = intel_write_sha_text(display, 0); 606 if (ret < 0) 607 return ret; 608 sha_idx += sizeof(sha_text); 609 610 /* Write 24 bits of M0 */ 611 intel_de_write(display, HDCP_REP_CTL, 612 rep_ctl | HDCP_SHA1_TEXT_8); 613 ret = intel_write_sha_text(display, 0); 614 if (ret < 0) 615 return ret; 616 sha_idx += sizeof(sha_text); 617 618 } else if (sha_leftovers == 2) { 619 /* Write 32 bits of text */ 620 intel_de_write(display, HDCP_REP_CTL, 621 rep_ctl | HDCP_SHA1_TEXT_32); 622 sha_text |= bstatus[0] << 8 | bstatus[1]; 623 ret = intel_write_sha_text(display, sha_text); 624 if (ret < 0) 625 return ret; 626 sha_idx += sizeof(sha_text); 627 628 /* Write 64 bits of M0 */ 629 intel_de_write(display, HDCP_REP_CTL, 630 rep_ctl | HDCP_SHA1_TEXT_0); 631 for (i = 0; i < 2; i++) { 632 ret = intel_write_sha_text(display, 0); 633 if (ret < 0) 634 return ret; 635 sha_idx += sizeof(sha_text); 636 } 637 638 /* 639 * Terminate the SHA-1 stream by hand. For the other leftover 640 * cases this is appended by the hardware. 641 */ 642 intel_de_write(display, HDCP_REP_CTL, 643 rep_ctl | HDCP_SHA1_TEXT_32); 644 sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; 645 ret = intel_write_sha_text(display, sha_text); 646 if (ret < 0) 647 return ret; 648 sha_idx += sizeof(sha_text); 649 } else if (sha_leftovers == 3) { 650 /* Write 32 bits of text (filled from LSB) */ 651 intel_de_write(display, HDCP_REP_CTL, 652 rep_ctl | HDCP_SHA1_TEXT_32); 653 sha_text |= bstatus[0]; 654 ret = intel_write_sha_text(display, sha_text); 655 if (ret < 0) 656 return ret; 657 sha_idx += sizeof(sha_text); 658 659 /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ 660 intel_de_write(display, HDCP_REP_CTL, 661 rep_ctl | HDCP_SHA1_TEXT_8); 662 ret = intel_write_sha_text(display, bstatus[1]); 663 if (ret < 0) 664 return ret; 665 sha_idx += sizeof(sha_text); 666 667 /* Write 32 bits of M0 */ 668 intel_de_write(display, HDCP_REP_CTL, 669 rep_ctl | HDCP_SHA1_TEXT_0); 670 ret = intel_write_sha_text(display, 0); 671 if (ret < 0) 672 return ret; 673 sha_idx += sizeof(sha_text); 674 675 /* Write 8 bits of M0 */ 676 intel_de_write(display, HDCP_REP_CTL, 677 rep_ctl | HDCP_SHA1_TEXT_24); 678 ret = intel_write_sha_text(display, 0); 679 if (ret < 0) 680 return ret; 681 sha_idx += sizeof(sha_text); 682 } else { 683 drm_dbg_kms(display->drm, "Invalid number of leftovers %d\n", 684 sha_leftovers); 685 return -EINVAL; 686 } 687 688 intel_de_write(display, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); 689 /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ 690 while ((sha_idx % 64) < (64 - sizeof(sha_text))) { 691 ret = intel_write_sha_text(display, 0); 692 if (ret < 0) 693 return ret; 694 sha_idx += sizeof(sha_text); 695 } 696 697 /* 698 * Last write gets the length of the concatenation in bits. That is: 699 * - 5 bytes per device 700 * - 10 bytes for BINFO/BSTATUS(2), M0(8) 701 */ 702 sha_text = (num_downstream * 5 + 10) * 8; 703 ret = intel_write_sha_text(display, sha_text); 704 if (ret < 0) 705 return ret; 706 707 /* Tell the HW we're done with the hash and wait for it to ACK */ 708 intel_de_write(display, HDCP_REP_CTL, 709 rep_ctl | HDCP_SHA1_COMPLETE_HASH); 710 if (intel_de_wait_for_set(display, HDCP_REP_CTL, 711 HDCP_SHA1_COMPLETE, 1)) { 712 drm_err(display->drm, "Timed out waiting for SHA1 complete\n"); 713 return -ETIMEDOUT; 714 } 715 if (!(intel_de_read(display, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { 716 drm_dbg_kms(display->drm, "SHA-1 mismatch, HDCP failed\n"); 717 return -ENXIO; 718 } 719 720 return 0; 721 } 722 723 /* Implements Part 2 of the HDCP authorization procedure */ 724 static 725 int intel_hdcp_auth_downstream(struct intel_connector *connector) 726 { 727 struct intel_display *display = to_intel_display(connector); 728 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 729 const struct intel_hdcp_shim *shim = connector->hdcp.shim; 730 u8 bstatus[2], num_downstream, *ksv_fifo; 731 int ret, i, tries = 3; 732 733 ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); 734 if (ret) { 735 drm_dbg_kms(display->drm, 736 "KSV list failed to become ready (%d)\n", ret); 737 return ret; 738 } 739 740 ret = shim->read_bstatus(dig_port, bstatus); 741 if (ret) 742 return ret; 743 744 if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || 745 DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { 746 drm_dbg_kms(display->drm, "Max Topology Limit Exceeded\n"); 747 return -EPERM; 748 } 749 750 /* 751 * When repeater reports 0 device count, HDCP1.4 spec allows disabling 752 * the HDCP encryption. That implies that repeater can't have its own 753 * display. As there is no consumption of encrypted content in the 754 * repeater with 0 downstream devices, we are failing the 755 * authentication. 756 */ 757 num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); 758 if (num_downstream == 0) { 759 drm_dbg_kms(display->drm, 760 "Repeater with zero downstream devices\n"); 761 return -EINVAL; 762 } 763 764 ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); 765 if (!ksv_fifo) { 766 drm_dbg_kms(display->drm, "Out of mem: ksv_fifo\n"); 767 return -ENOMEM; 768 } 769 770 ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); 771 if (ret) 772 goto err; 773 774 if (drm_hdcp_check_ksvs_revoked(display->drm, ksv_fifo, 775 num_downstream) > 0) { 776 drm_err(display->drm, "Revoked Ksv(s) in ksv_fifo\n"); 777 ret = -EPERM; 778 goto err; 779 } 780 781 /* 782 * When V prime mismatches, DP Spec mandates re-read of 783 * V prime atleast twice. 784 */ 785 for (i = 0; i < tries; i++) { 786 ret = intel_hdcp_validate_v_prime(connector, shim, 787 ksv_fifo, num_downstream, 788 bstatus); 789 if (!ret) 790 break; 791 } 792 793 if (i == tries) { 794 drm_dbg_kms(display->drm, 795 "V Prime validation failed.(%d)\n", ret); 796 goto err; 797 } 798 799 drm_dbg_kms(display->drm, "HDCP is enabled (%d downstream devices)\n", 800 num_downstream); 801 ret = 0; 802 err: 803 kfree(ksv_fifo); 804 return ret; 805 } 806 807 /* Implements Part 1 of the HDCP authorization procedure */ 808 static int intel_hdcp_auth(struct intel_connector *connector) 809 { 810 struct intel_display *display = to_intel_display(connector); 811 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 812 struct intel_hdcp *hdcp = &connector->hdcp; 813 const struct intel_hdcp_shim *shim = hdcp->shim; 814 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; 815 enum port port = dig_port->base.port; 816 unsigned long r0_prime_gen_start; 817 int ret, i, tries = 2; 818 u32 val; 819 union { 820 u32 reg[2]; 821 u8 shim[DRM_HDCP_AN_LEN]; 822 } an; 823 union { 824 u32 reg[2]; 825 u8 shim[DRM_HDCP_KSV_LEN]; 826 } bksv; 827 union { 828 u32 reg; 829 u8 shim[DRM_HDCP_RI_LEN]; 830 } ri; 831 bool repeater_present, hdcp_capable; 832 833 /* 834 * Detects whether the display is HDCP capable. Although we check for 835 * valid Bksv below, the HDCP over DP spec requires that we check 836 * whether the display supports HDCP before we write An. For HDMI 837 * displays, this is not necessary. 838 */ 839 if (shim->hdcp_get_capability) { 840 ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); 841 if (ret) 842 return ret; 843 if (!hdcp_capable) { 844 drm_dbg_kms(display->drm, 845 "Panel is not HDCP capable\n"); 846 return -EINVAL; 847 } 848 } 849 850 /* Initialize An with 2 random values and acquire it */ 851 for (i = 0; i < 2; i++) 852 intel_de_write(display, 853 HDCP_ANINIT(display, cpu_transcoder, port), 854 get_random_u32()); 855 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 856 HDCP_CONF_CAPTURE_AN); 857 858 /* Wait for An to be acquired */ 859 if (intel_de_wait_for_set(display, 860 HDCP_STATUS(display, cpu_transcoder, port), 861 HDCP_STATUS_AN_READY, 1)) { 862 drm_err(display->drm, "Timed out waiting for An\n"); 863 return -ETIMEDOUT; 864 } 865 866 an.reg[0] = intel_de_read(display, 867 HDCP_ANLO(display, cpu_transcoder, port)); 868 an.reg[1] = intel_de_read(display, 869 HDCP_ANHI(display, cpu_transcoder, port)); 870 ret = shim->write_an_aksv(dig_port, an.shim); 871 if (ret) 872 return ret; 873 874 r0_prime_gen_start = jiffies; 875 876 memset(&bksv, 0, sizeof(bksv)); 877 878 ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); 879 if (ret < 0) 880 return ret; 881 882 if (drm_hdcp_check_ksvs_revoked(display->drm, bksv.shim, 1) > 0) { 883 drm_err(display->drm, "BKSV is revoked\n"); 884 return -EPERM; 885 } 886 887 intel_de_write(display, HDCP_BKSVLO(display, cpu_transcoder, port), 888 bksv.reg[0]); 889 intel_de_write(display, HDCP_BKSVHI(display, cpu_transcoder, port), 890 bksv.reg[1]); 891 892 ret = shim->repeater_present(dig_port, &repeater_present); 893 if (ret) 894 return ret; 895 if (repeater_present) 896 intel_de_write(display, HDCP_REP_CTL, 897 intel_hdcp_get_repeater_ctl(display, cpu_transcoder, port)); 898 899 ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); 900 if (ret) 901 return ret; 902 903 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 904 HDCP_CONF_AUTH_AND_ENC); 905 906 /* Wait for R0 ready */ 907 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 908 val & (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 909 100, 1000, false); 910 if (ret) { 911 drm_err(display->drm, "Timed out waiting for R0 ready\n"); 912 return -ETIMEDOUT; 913 } 914 915 /* 916 * Wait for R0' to become available. The spec says 100ms from Aksv, but 917 * some monitors can take longer than this. We'll set the timeout at 918 * 300ms just to be sure. 919 * 920 * On DP, there's an R0_READY bit available but no such bit 921 * exists on HDMI. Since the upper-bound is the same, we'll just do 922 * the stupid thing instead of polling on one and not the other. 923 */ 924 wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); 925 926 tries = 3; 927 928 /* 929 * DP HDCP Spec mandates the two more reattempt to read R0, incase 930 * of R0 mismatch. 931 */ 932 for (i = 0; i < tries; i++) { 933 ri.reg = 0; 934 ret = shim->read_ri_prime(dig_port, ri.shim); 935 if (ret) 936 return ret; 937 intel_de_write(display, 938 HDCP_RPRIME(display, cpu_transcoder, port), 939 ri.reg); 940 941 /* Wait for Ri prime match */ 942 ret = poll_timeout_us(val = intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)), 943 val & (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 944 100, 1000, false); 945 if (!ret) 946 break; 947 } 948 949 if (i == tries) { 950 drm_dbg_kms(display->drm, 951 "Timed out waiting for Ri prime match (%x)\n", val); 952 return -ETIMEDOUT; 953 } 954 955 /* Wait for encryption confirmation */ 956 if (intel_de_wait_for_set(display, 957 HDCP_STATUS(display, cpu_transcoder, port), 958 HDCP_STATUS_ENC, 959 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 960 drm_err(display->drm, "Timed out waiting for encryption\n"); 961 return -ETIMEDOUT; 962 } 963 964 /* DP MST Auth Part 1 Step 2.a and Step 2.b */ 965 if (shim->stream_encryption) { 966 ret = shim->stream_encryption(connector, true); 967 if (ret) { 968 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", 969 connector->base.base.id, connector->base.name); 970 return ret; 971 } 972 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", 973 transcoder_name(hdcp->stream_transcoder)); 974 } 975 976 if (repeater_present) 977 return intel_hdcp_auth_downstream(connector); 978 979 drm_dbg_kms(display->drm, "HDCP is enabled (no repeater present)\n"); 980 return 0; 981 } 982 983 static int _intel_hdcp_disable(struct intel_connector *connector) 984 { 985 struct intel_display *display = to_intel_display(connector); 986 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 987 struct intel_hdcp *hdcp = &connector->hdcp; 988 enum port port = dig_port->base.port; 989 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 990 u32 repeater_ctl; 991 int ret; 992 993 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", 994 connector->base.base.id, connector->base.name); 995 996 if (hdcp->shim->stream_encryption) { 997 ret = hdcp->shim->stream_encryption(connector, false); 998 if (ret) { 999 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", 1000 connector->base.base.id, connector->base.name); 1001 return ret; 1002 } 1003 drm_dbg_kms(display->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", 1004 transcoder_name(hdcp->stream_transcoder)); 1005 /* 1006 * If there are other connectors on this port using HDCP, 1007 * don't disable it until it disabled HDCP encryption for 1008 * all connectors in MST topology. 1009 */ 1010 if (dig_port->hdcp.num_streams > 0) 1011 return 0; 1012 } 1013 1014 hdcp->hdcp_encrypted = false; 1015 intel_de_write(display, HDCP_CONF(display, cpu_transcoder, port), 0); 1016 if (intel_de_wait_for_clear(display, 1017 HDCP_STATUS(display, cpu_transcoder, port), 1018 ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 1019 drm_err(display->drm, 1020 "Failed to disable HDCP, timeout clearing status\n"); 1021 return -ETIMEDOUT; 1022 } 1023 1024 repeater_ctl = intel_hdcp_get_repeater_ctl(display, cpu_transcoder, 1025 port); 1026 intel_de_rmw(display, HDCP_REP_CTL, repeater_ctl, 0); 1027 1028 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); 1029 if (ret) { 1030 drm_err(display->drm, "Failed to disable HDCP signalling\n"); 1031 return ret; 1032 } 1033 1034 drm_dbg_kms(display->drm, "HDCP is disabled\n"); 1035 return 0; 1036 } 1037 1038 static int intel_hdcp1_enable(struct intel_connector *connector) 1039 { 1040 struct intel_display *display = to_intel_display(connector); 1041 struct intel_hdcp *hdcp = &connector->hdcp; 1042 int i, ret, tries = 3; 1043 1044 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", 1045 connector->base.base.id, connector->base.name); 1046 1047 if (!hdcp_key_loadable(display)) { 1048 drm_err(display->drm, "HDCP key Load is not possible\n"); 1049 return -ENXIO; 1050 } 1051 1052 for (i = 0; i < KEY_LOAD_TRIES; i++) { 1053 ret = intel_hdcp_load_keys(display); 1054 if (!ret) 1055 break; 1056 intel_hdcp_clear_keys(display); 1057 } 1058 if (ret) { 1059 drm_err(display->drm, "Could not load HDCP keys, (%d)\n", 1060 ret); 1061 return ret; 1062 } 1063 1064 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, true); 1065 1066 /* Incase of authentication failures, HDCP spec expects reauth. */ 1067 for (i = 0; i < tries; i++) { 1068 ret = intel_hdcp_auth(connector); 1069 if (!ret) { 1070 hdcp->hdcp_encrypted = true; 1071 return 0; 1072 } 1073 1074 drm_dbg_kms(display->drm, "HDCP Auth failure (%d)\n", ret); 1075 1076 /* Ensuring HDCP encryption and signalling are stopped. */ 1077 _intel_hdcp_disable(connector); 1078 } 1079 1080 drm_dbg_kms(display->drm, 1081 "HDCP authentication failed (%d tries/%d)\n", tries, ret); 1082 return ret; 1083 } 1084 1085 static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) 1086 { 1087 return container_of(hdcp, struct intel_connector, hdcp); 1088 } 1089 1090 static void intel_hdcp_update_value(struct intel_connector *connector, 1091 u64 value, bool update_property) 1092 { 1093 struct intel_display *display = to_intel_display(connector); 1094 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1095 struct intel_hdcp *hdcp = &connector->hdcp; 1096 1097 drm_WARN_ON(display->drm, !mutex_is_locked(&hdcp->mutex)); 1098 1099 if (hdcp->value == value) 1100 return; 1101 1102 drm_WARN_ON(display->drm, !mutex_is_locked(&dig_port->hdcp.mutex)); 1103 1104 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1105 if (!drm_WARN_ON(display->drm, dig_port->hdcp.num_streams == 0)) 1106 dig_port->hdcp.num_streams--; 1107 } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 1108 dig_port->hdcp.num_streams++; 1109 } 1110 1111 hdcp->value = value; 1112 if (update_property) { 1113 drm_connector_get(&connector->base); 1114 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 1115 drm_connector_put(&connector->base); 1116 } 1117 } 1118 1119 /* Implements Part 3 of the HDCP authorization procedure */ 1120 static int intel_hdcp_check_link(struct intel_connector *connector) 1121 { 1122 struct intel_display *display = to_intel_display(connector); 1123 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1124 struct intel_hdcp *hdcp = &connector->hdcp; 1125 enum port port = dig_port->base.port; 1126 enum transcoder cpu_transcoder; 1127 int ret = 0; 1128 1129 mutex_lock(&hdcp->mutex); 1130 mutex_lock(&dig_port->hdcp.mutex); 1131 1132 cpu_transcoder = hdcp->cpu_transcoder; 1133 1134 /* Check_link valid only when HDCP1.4 is enabled */ 1135 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 1136 !hdcp->hdcp_encrypted) { 1137 ret = -EINVAL; 1138 goto out; 1139 } 1140 1141 if (drm_WARN_ON(display->drm, 1142 !intel_hdcp_in_use(display, cpu_transcoder, port))) { 1143 drm_err(display->drm, 1144 "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", 1145 connector->base.base.id, connector->base.name, 1146 intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port))); 1147 ret = -ENXIO; 1148 intel_hdcp_update_value(connector, 1149 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1150 true); 1151 goto out; 1152 } 1153 1154 if (hdcp->shim->check_link(dig_port, connector)) { 1155 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 1156 intel_hdcp_update_value(connector, 1157 DRM_MODE_CONTENT_PROTECTION_ENABLED, true); 1158 } 1159 goto out; 1160 } 1161 1162 drm_dbg_kms(display->drm, 1163 "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", 1164 connector->base.base.id, connector->base.name); 1165 1166 ret = _intel_hdcp_disable(connector); 1167 if (ret) { 1168 drm_err(display->drm, "Failed to disable hdcp (%d)\n", ret); 1169 intel_hdcp_update_value(connector, 1170 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1171 true); 1172 goto out; 1173 } 1174 1175 ret = intel_hdcp1_enable(connector); 1176 if (ret) { 1177 drm_err(display->drm, "Failed to enable hdcp (%d)\n", ret); 1178 intel_hdcp_update_value(connector, 1179 DRM_MODE_CONTENT_PROTECTION_DESIRED, 1180 true); 1181 goto out; 1182 } 1183 1184 out: 1185 mutex_unlock(&dig_port->hdcp.mutex); 1186 mutex_unlock(&hdcp->mutex); 1187 return ret; 1188 } 1189 1190 static void intel_hdcp_prop_work(struct work_struct *work) 1191 { 1192 struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, 1193 prop_work); 1194 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 1195 struct intel_display *display = to_intel_display(connector); 1196 1197 drm_modeset_lock(&display->drm->mode_config.connection_mutex, NULL); 1198 mutex_lock(&hdcp->mutex); 1199 1200 /* 1201 * This worker is only used to flip between ENABLED/DESIRED. Either of 1202 * those to UNDESIRED is handled by core. If value == UNDESIRED, 1203 * we're running just after hdcp has been disabled, so just exit 1204 */ 1205 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 1206 drm_hdcp_update_content_protection(&connector->base, 1207 hdcp->value); 1208 1209 mutex_unlock(&hdcp->mutex); 1210 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 1211 1212 drm_connector_put(&connector->base); 1213 } 1214 1215 bool is_hdcp_supported(struct intel_display *display, enum port port) 1216 { 1217 return DISPLAY_RUNTIME_INFO(display)->has_hdcp && 1218 (DISPLAY_VER(display) >= 12 || port < PORT_E); 1219 } 1220 1221 static int 1222 hdcp2_prepare_ake_init(struct intel_connector *connector, 1223 struct hdcp2_ake_init *ake_data) 1224 { 1225 struct intel_display *display = to_intel_display(connector); 1226 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1227 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1228 struct i915_hdcp_arbiter *arbiter; 1229 int ret; 1230 1231 mutex_lock(&display->hdcp.hdcp_mutex); 1232 arbiter = display->hdcp.arbiter; 1233 1234 if (!arbiter || !arbiter->ops) { 1235 mutex_unlock(&display->hdcp.hdcp_mutex); 1236 return -EINVAL; 1237 } 1238 1239 ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); 1240 if (ret) 1241 drm_dbg_kms(display->drm, "Prepare_ake_init failed. %d\n", 1242 ret); 1243 mutex_unlock(&display->hdcp.hdcp_mutex); 1244 1245 return ret; 1246 } 1247 1248 static int 1249 hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, 1250 struct hdcp2_ake_send_cert *rx_cert, 1251 bool *paired, 1252 struct hdcp2_ake_no_stored_km *ek_pub_km, 1253 size_t *msg_sz) 1254 { 1255 struct intel_display *display = to_intel_display(connector); 1256 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1257 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1258 struct i915_hdcp_arbiter *arbiter; 1259 int ret; 1260 1261 mutex_lock(&display->hdcp.hdcp_mutex); 1262 arbiter = display->hdcp.arbiter; 1263 1264 if (!arbiter || !arbiter->ops) { 1265 mutex_unlock(&display->hdcp.hdcp_mutex); 1266 return -EINVAL; 1267 } 1268 1269 ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, 1270 rx_cert, paired, 1271 ek_pub_km, msg_sz); 1272 if (ret < 0) 1273 drm_dbg_kms(display->drm, "Verify rx_cert failed. %d\n", 1274 ret); 1275 mutex_unlock(&display->hdcp.hdcp_mutex); 1276 1277 return ret; 1278 } 1279 1280 static int hdcp2_verify_hprime(struct intel_connector *connector, 1281 struct hdcp2_ake_send_hprime *rx_hprime) 1282 { 1283 struct intel_display *display = to_intel_display(connector); 1284 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1285 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1286 struct i915_hdcp_arbiter *arbiter; 1287 int ret; 1288 1289 mutex_lock(&display->hdcp.hdcp_mutex); 1290 arbiter = display->hdcp.arbiter; 1291 1292 if (!arbiter || !arbiter->ops) { 1293 mutex_unlock(&display->hdcp.hdcp_mutex); 1294 return -EINVAL; 1295 } 1296 1297 ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); 1298 if (ret < 0) 1299 drm_dbg_kms(display->drm, "Verify hprime failed. %d\n", ret); 1300 mutex_unlock(&display->hdcp.hdcp_mutex); 1301 1302 return ret; 1303 } 1304 1305 static int 1306 hdcp2_store_pairing_info(struct intel_connector *connector, 1307 struct hdcp2_ake_send_pairing_info *pairing_info) 1308 { 1309 struct intel_display *display = to_intel_display(connector); 1310 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1311 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1312 struct i915_hdcp_arbiter *arbiter; 1313 int ret; 1314 1315 mutex_lock(&display->hdcp.hdcp_mutex); 1316 arbiter = display->hdcp.arbiter; 1317 1318 if (!arbiter || !arbiter->ops) { 1319 mutex_unlock(&display->hdcp.hdcp_mutex); 1320 return -EINVAL; 1321 } 1322 1323 ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); 1324 if (ret < 0) 1325 drm_dbg_kms(display->drm, "Store pairing info failed. %d\n", 1326 ret); 1327 mutex_unlock(&display->hdcp.hdcp_mutex); 1328 1329 return ret; 1330 } 1331 1332 static int 1333 hdcp2_prepare_lc_init(struct intel_connector *connector, 1334 struct hdcp2_lc_init *lc_init) 1335 { 1336 struct intel_display *display = to_intel_display(connector); 1337 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1338 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1339 struct i915_hdcp_arbiter *arbiter; 1340 int ret; 1341 1342 mutex_lock(&display->hdcp.hdcp_mutex); 1343 arbiter = display->hdcp.arbiter; 1344 1345 if (!arbiter || !arbiter->ops) { 1346 mutex_unlock(&display->hdcp.hdcp_mutex); 1347 return -EINVAL; 1348 } 1349 1350 ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); 1351 if (ret < 0) 1352 drm_dbg_kms(display->drm, "Prepare lc_init failed. %d\n", 1353 ret); 1354 mutex_unlock(&display->hdcp.hdcp_mutex); 1355 1356 return ret; 1357 } 1358 1359 static int 1360 hdcp2_verify_lprime(struct intel_connector *connector, 1361 struct hdcp2_lc_send_lprime *rx_lprime) 1362 { 1363 struct intel_display *display = to_intel_display(connector); 1364 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1365 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1366 struct i915_hdcp_arbiter *arbiter; 1367 int ret; 1368 1369 mutex_lock(&display->hdcp.hdcp_mutex); 1370 arbiter = display->hdcp.arbiter; 1371 1372 if (!arbiter || !arbiter->ops) { 1373 mutex_unlock(&display->hdcp.hdcp_mutex); 1374 return -EINVAL; 1375 } 1376 1377 ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); 1378 if (ret < 0) 1379 drm_dbg_kms(display->drm, "Verify L_Prime failed. %d\n", 1380 ret); 1381 mutex_unlock(&display->hdcp.hdcp_mutex); 1382 1383 return ret; 1384 } 1385 1386 static int hdcp2_prepare_skey(struct intel_connector *connector, 1387 struct hdcp2_ske_send_eks *ske_data) 1388 { 1389 struct intel_display *display = to_intel_display(connector); 1390 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1391 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1392 struct i915_hdcp_arbiter *arbiter; 1393 int ret; 1394 1395 mutex_lock(&display->hdcp.hdcp_mutex); 1396 arbiter = display->hdcp.arbiter; 1397 1398 if (!arbiter || !arbiter->ops) { 1399 mutex_unlock(&display->hdcp.hdcp_mutex); 1400 return -EINVAL; 1401 } 1402 1403 ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); 1404 if (ret < 0) 1405 drm_dbg_kms(display->drm, "Get session key failed. %d\n", 1406 ret); 1407 mutex_unlock(&display->hdcp.hdcp_mutex); 1408 1409 return ret; 1410 } 1411 1412 static int 1413 hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, 1414 struct hdcp2_rep_send_receiverid_list 1415 *rep_topology, 1416 struct hdcp2_rep_send_ack *rep_send_ack) 1417 { 1418 struct intel_display *display = to_intel_display(connector); 1419 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1420 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1421 struct i915_hdcp_arbiter *arbiter; 1422 int ret; 1423 1424 mutex_lock(&display->hdcp.hdcp_mutex); 1425 arbiter = display->hdcp.arbiter; 1426 1427 if (!arbiter || !arbiter->ops) { 1428 mutex_unlock(&display->hdcp.hdcp_mutex); 1429 return -EINVAL; 1430 } 1431 1432 ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, 1433 data, 1434 rep_topology, 1435 rep_send_ack); 1436 if (ret < 0) 1437 drm_dbg_kms(display->drm, 1438 "Verify rep topology failed. %d\n", ret); 1439 mutex_unlock(&display->hdcp.hdcp_mutex); 1440 1441 return ret; 1442 } 1443 1444 static int 1445 hdcp2_verify_mprime(struct intel_connector *connector, 1446 struct hdcp2_rep_stream_ready *stream_ready) 1447 { 1448 struct intel_display *display = to_intel_display(connector); 1449 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1450 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1451 struct i915_hdcp_arbiter *arbiter; 1452 int ret; 1453 1454 mutex_lock(&display->hdcp.hdcp_mutex); 1455 arbiter = display->hdcp.arbiter; 1456 1457 if (!arbiter || !arbiter->ops) { 1458 mutex_unlock(&display->hdcp.hdcp_mutex); 1459 return -EINVAL; 1460 } 1461 1462 ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); 1463 if (ret < 0) 1464 drm_dbg_kms(display->drm, "Verify mprime failed. %d\n", ret); 1465 mutex_unlock(&display->hdcp.hdcp_mutex); 1466 1467 return ret; 1468 } 1469 1470 static int hdcp2_authenticate_port(struct intel_connector *connector) 1471 { 1472 struct intel_display *display = to_intel_display(connector); 1473 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1474 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1475 struct i915_hdcp_arbiter *arbiter; 1476 int ret; 1477 1478 mutex_lock(&display->hdcp.hdcp_mutex); 1479 arbiter = display->hdcp.arbiter; 1480 1481 if (!arbiter || !arbiter->ops) { 1482 mutex_unlock(&display->hdcp.hdcp_mutex); 1483 return -EINVAL; 1484 } 1485 1486 ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); 1487 if (ret < 0) 1488 drm_dbg_kms(display->drm, "Enable hdcp auth failed. %d\n", 1489 ret); 1490 mutex_unlock(&display->hdcp.hdcp_mutex); 1491 1492 return ret; 1493 } 1494 1495 static int hdcp2_close_session(struct intel_connector *connector) 1496 { 1497 struct intel_display *display = to_intel_display(connector); 1498 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1499 struct i915_hdcp_arbiter *arbiter; 1500 int ret; 1501 1502 mutex_lock(&display->hdcp.hdcp_mutex); 1503 arbiter = display->hdcp.arbiter; 1504 1505 if (!arbiter || !arbiter->ops) { 1506 mutex_unlock(&display->hdcp.hdcp_mutex); 1507 return -EINVAL; 1508 } 1509 1510 ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, 1511 &dig_port->hdcp.port_data); 1512 mutex_unlock(&display->hdcp.hdcp_mutex); 1513 1514 return ret; 1515 } 1516 1517 static int hdcp2_deauthenticate_port(struct intel_connector *connector) 1518 { 1519 return hdcp2_close_session(connector); 1520 } 1521 1522 /* Authentication flow starts from here */ 1523 static int hdcp2_authentication_key_exchange(struct intel_connector *connector) 1524 { 1525 struct intel_display *display = to_intel_display(connector); 1526 struct intel_digital_port *dig_port = 1527 intel_attached_dig_port(connector); 1528 struct intel_hdcp *hdcp = &connector->hdcp; 1529 union { 1530 struct hdcp2_ake_init ake_init; 1531 struct hdcp2_ake_send_cert send_cert; 1532 struct hdcp2_ake_no_stored_km no_stored_km; 1533 struct hdcp2_ake_send_hprime send_hprime; 1534 struct hdcp2_ake_send_pairing_info pairing_info; 1535 } msgs; 1536 const struct intel_hdcp_shim *shim = hdcp->shim; 1537 size_t size; 1538 int ret, i, max_retries; 1539 1540 /* Init for seq_num */ 1541 hdcp->seq_num_v = 0; 1542 hdcp->seq_num_m = 0; 1543 1544 if (intel_encoder_is_dp(&dig_port->base) || 1545 intel_encoder_is_mst(&dig_port->base)) 1546 max_retries = 10; 1547 else 1548 max_retries = 1; 1549 1550 ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); 1551 if (ret < 0) 1552 return ret; 1553 1554 /* 1555 * Retry the first read and write to downstream at least 10 times 1556 * with a 50ms delay if not hdcp2 capable for DP/DPMST encoders 1557 * (dock decides to stop advertising hdcp2 capability for some reason). 1558 * The reason being that during suspend resume dock usually keeps the 1559 * HDCP2 registers inaccessible causing AUX error. This wouldn't be a 1560 * big problem if the userspace just kept retrying with some delay while 1561 * it continues to play low value content but most userspace applications 1562 * end up throwing an error when it receives one from KMD. This makes 1563 * sure we give the dock and the sink devices to complete its power cycle 1564 * and then try HDCP authentication. The values of 10 and delay of 50ms 1565 * was decided based on multiple trial and errors. 1566 */ 1567 for (i = 0; i < max_retries; i++) { 1568 if (!intel_hdcp2_get_capability(connector)) { 1569 msleep(50); 1570 continue; 1571 } 1572 1573 ret = shim->write_2_2_msg(connector, &msgs.ake_init, 1574 sizeof(msgs.ake_init)); 1575 if (ret < 0) 1576 continue; 1577 1578 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, 1579 &msgs.send_cert, sizeof(msgs.send_cert)); 1580 if (ret > 0) 1581 break; 1582 } 1583 1584 if (ret < 0) 1585 return ret; 1586 1587 if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { 1588 drm_dbg_kms(display->drm, "cert.rx_caps dont claim HDCP2.2\n"); 1589 return -EINVAL; 1590 } 1591 1592 hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); 1593 1594 if (drm_hdcp_check_ksvs_revoked(display->drm, 1595 msgs.send_cert.cert_rx.receiver_id, 1596 1) > 0) { 1597 drm_err(display->drm, "Receiver ID is revoked\n"); 1598 return -EPERM; 1599 } 1600 1601 /* 1602 * Here msgs.no_stored_km will hold msgs corresponding to the km 1603 * stored also. 1604 */ 1605 ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, 1606 &hdcp->is_paired, 1607 &msgs.no_stored_km, &size); 1608 if (ret < 0) 1609 return ret; 1610 1611 ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); 1612 if (ret < 0) 1613 return ret; 1614 1615 ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, 1616 &msgs.send_hprime, sizeof(msgs.send_hprime)); 1617 if (ret < 0) 1618 return ret; 1619 1620 ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); 1621 if (ret < 0) 1622 return ret; 1623 1624 if (!hdcp->is_paired) { 1625 /* Pairing is required */ 1626 ret = shim->read_2_2_msg(connector, 1627 HDCP_2_2_AKE_SEND_PAIRING_INFO, 1628 &msgs.pairing_info, 1629 sizeof(msgs.pairing_info)); 1630 if (ret < 0) 1631 return ret; 1632 1633 ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); 1634 if (ret < 0) 1635 return ret; 1636 hdcp->is_paired = true; 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int hdcp2_locality_check(struct intel_connector *connector) 1643 { 1644 struct intel_hdcp *hdcp = &connector->hdcp; 1645 union { 1646 struct hdcp2_lc_init lc_init; 1647 struct hdcp2_lc_send_lprime send_lprime; 1648 } msgs; 1649 const struct intel_hdcp_shim *shim = hdcp->shim; 1650 int tries = HDCP2_LC_RETRY_CNT, ret, i; 1651 1652 for (i = 0; i < tries; i++) { 1653 ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); 1654 if (ret < 0) 1655 continue; 1656 1657 ret = shim->write_2_2_msg(connector, &msgs.lc_init, 1658 sizeof(msgs.lc_init)); 1659 if (ret < 0) 1660 continue; 1661 1662 ret = shim->read_2_2_msg(connector, 1663 HDCP_2_2_LC_SEND_LPRIME, 1664 &msgs.send_lprime, 1665 sizeof(msgs.send_lprime)); 1666 if (ret < 0) 1667 continue; 1668 1669 ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); 1670 if (!ret) 1671 break; 1672 } 1673 1674 return ret; 1675 } 1676 1677 static int hdcp2_session_key_exchange(struct intel_connector *connector) 1678 { 1679 struct intel_hdcp *hdcp = &connector->hdcp; 1680 struct hdcp2_ske_send_eks send_eks; 1681 int ret; 1682 1683 ret = hdcp2_prepare_skey(connector, &send_eks); 1684 if (ret < 0) 1685 return ret; 1686 1687 ret = hdcp->shim->write_2_2_msg(connector, &send_eks, 1688 sizeof(send_eks)); 1689 if (ret < 0) 1690 return ret; 1691 1692 return 0; 1693 } 1694 1695 static 1696 int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1697 { 1698 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1699 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1700 struct intel_hdcp *hdcp = &connector->hdcp; 1701 union { 1702 struct hdcp2_rep_stream_manage stream_manage; 1703 struct hdcp2_rep_stream_ready stream_ready; 1704 } msgs; 1705 const struct intel_hdcp_shim *shim = hdcp->shim; 1706 int ret, streams_size_delta, i; 1707 1708 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) 1709 return -ERANGE; 1710 1711 /* Prepare RepeaterAuth_Stream_Manage msg */ 1712 msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; 1713 drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); 1714 1715 msgs.stream_manage.k = cpu_to_be16(data->k); 1716 1717 for (i = 0; i < data->k; i++) { 1718 msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; 1719 msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; 1720 } 1721 1722 streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * 1723 sizeof(struct hdcp2_streamid_type); 1724 /* Send it to Repeater */ 1725 ret = shim->write_2_2_msg(connector, &msgs.stream_manage, 1726 sizeof(msgs.stream_manage) - streams_size_delta); 1727 if (ret < 0) 1728 goto out; 1729 1730 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, 1731 &msgs.stream_ready, sizeof(msgs.stream_ready)); 1732 if (ret < 0) 1733 goto out; 1734 1735 data->seq_num_m = hdcp->seq_num_m; 1736 1737 ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); 1738 1739 out: 1740 hdcp->seq_num_m++; 1741 1742 return ret; 1743 } 1744 1745 static 1746 int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) 1747 { 1748 struct intel_display *display = to_intel_display(connector); 1749 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1750 struct intel_hdcp *hdcp = &connector->hdcp; 1751 union { 1752 struct hdcp2_rep_send_receiverid_list recvid_list; 1753 struct hdcp2_rep_send_ack rep_ack; 1754 } msgs; 1755 const struct intel_hdcp_shim *shim = hdcp->shim; 1756 u32 seq_num_v, device_cnt; 1757 u8 *rx_info; 1758 int ret; 1759 1760 ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, 1761 &msgs.recvid_list, sizeof(msgs.recvid_list)); 1762 if (ret < 0) 1763 return ret; 1764 1765 rx_info = msgs.recvid_list.rx_info; 1766 1767 if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || 1768 HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { 1769 drm_dbg_kms(display->drm, "Topology Max Size Exceeded\n"); 1770 return -EINVAL; 1771 } 1772 1773 /* 1774 * MST topology is not Type 1 capable if it contains a downstream 1775 * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. 1776 */ 1777 dig_port->hdcp.mst_type1_capable = 1778 !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && 1779 !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); 1780 1781 if (!dig_port->hdcp.mst_type1_capable && hdcp->content_type) { 1782 drm_dbg_kms(display->drm, 1783 "HDCP1.x or 2.0 Legacy Device Downstream\n"); 1784 return -EINVAL; 1785 } 1786 1787 /* Converting and Storing the seq_num_v to local variable as DWORD */ 1788 seq_num_v = 1789 drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); 1790 1791 if (!hdcp->hdcp2_encrypted && seq_num_v) { 1792 drm_dbg_kms(display->drm, 1793 "Non zero Seq_num_v at first RecvId_List msg\n"); 1794 return -EINVAL; 1795 } 1796 1797 if (seq_num_v < hdcp->seq_num_v) { 1798 /* Roll over of the seq_num_v from repeater. Reauthenticate. */ 1799 drm_dbg_kms(display->drm, "Seq_num_v roll over.\n"); 1800 return -EINVAL; 1801 } 1802 1803 device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 1804 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 1805 if (drm_hdcp_check_ksvs_revoked(display->drm, 1806 msgs.recvid_list.receiver_ids, 1807 device_cnt) > 0) { 1808 drm_err(display->drm, "Revoked receiver ID(s) is in list\n"); 1809 return -EPERM; 1810 } 1811 1812 ret = hdcp2_verify_rep_topology_prepare_ack(connector, 1813 &msgs.recvid_list, 1814 &msgs.rep_ack); 1815 if (ret < 0) 1816 return ret; 1817 1818 hdcp->seq_num_v = seq_num_v; 1819 ret = shim->write_2_2_msg(connector, &msgs.rep_ack, 1820 sizeof(msgs.rep_ack)); 1821 if (ret < 0) 1822 return ret; 1823 1824 return 0; 1825 } 1826 1827 static int hdcp2_authenticate_sink(struct intel_connector *connector) 1828 { 1829 struct intel_display *display = to_intel_display(connector); 1830 struct intel_hdcp *hdcp = &connector->hdcp; 1831 const struct intel_hdcp_shim *shim = hdcp->shim; 1832 int ret; 1833 1834 ret = hdcp2_authentication_key_exchange(connector); 1835 if (ret < 0) { 1836 drm_dbg_kms(display->drm, "AKE Failed. Err : %d\n", ret); 1837 return ret; 1838 } 1839 1840 ret = hdcp2_locality_check(connector); 1841 if (ret < 0) { 1842 drm_dbg_kms(display->drm, 1843 "Locality Check failed. Err : %d\n", ret); 1844 return ret; 1845 } 1846 1847 ret = hdcp2_session_key_exchange(connector); 1848 if (ret < 0) { 1849 drm_dbg_kms(display->drm, "SKE Failed. Err : %d\n", ret); 1850 return ret; 1851 } 1852 1853 if (shim->config_stream_type) { 1854 ret = shim->config_stream_type(connector, 1855 hdcp->is_repeater, 1856 hdcp->content_type); 1857 if (ret < 0) 1858 return ret; 1859 } 1860 1861 if (hdcp->is_repeater) { 1862 ret = hdcp2_authenticate_repeater_topology(connector); 1863 if (ret < 0) { 1864 drm_dbg_kms(display->drm, 1865 "Repeater Auth Failed. Err: %d\n", ret); 1866 return ret; 1867 } 1868 } 1869 1870 return ret; 1871 } 1872 1873 static int hdcp2_enable_stream_encryption(struct intel_connector *connector) 1874 { 1875 struct intel_display *display = to_intel_display(connector); 1876 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1877 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 1878 struct intel_hdcp *hdcp = &connector->hdcp; 1879 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1880 enum port port = dig_port->base.port; 1881 int ret = 0; 1882 1883 if (!(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1884 LINK_ENCRYPTION_STATUS)) { 1885 drm_err(display->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", 1886 connector->base.base.id, connector->base.name); 1887 ret = -EPERM; 1888 goto link_recover; 1889 } 1890 1891 if (hdcp->shim->stream_2_2_encryption) { 1892 ret = hdcp->shim->stream_2_2_encryption(connector, true); 1893 if (ret) { 1894 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", 1895 connector->base.base.id, connector->base.name); 1896 return ret; 1897 } 1898 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", 1899 transcoder_name(hdcp->stream_transcoder)); 1900 } 1901 1902 return 0; 1903 1904 link_recover: 1905 if (hdcp2_deauthenticate_port(connector) < 0) 1906 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 1907 1908 dig_port->hdcp.auth_status = false; 1909 data->k = 0; 1910 1911 return ret; 1912 } 1913 1914 static int hdcp2_enable_encryption(struct intel_connector *connector) 1915 { 1916 struct intel_display *display = to_intel_display(connector); 1917 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1918 struct intel_hdcp *hdcp = &connector->hdcp; 1919 enum port port = dig_port->base.port; 1920 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1921 int ret; 1922 1923 drm_WARN_ON(display->drm, 1924 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1925 LINK_ENCRYPTION_STATUS); 1926 if (hdcp->shim->toggle_signalling) { 1927 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1928 true); 1929 if (ret) { 1930 drm_err(display->drm, 1931 "Failed to enable HDCP signalling. %d\n", 1932 ret); 1933 return ret; 1934 } 1935 } 1936 1937 if (intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1938 LINK_AUTH_STATUS) 1939 /* Link is Authenticated. Now set for Encryption */ 1940 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1941 0, CTL_LINK_ENCRYPTION_REQ); 1942 1943 ret = intel_de_wait_for_set(display, 1944 HDCP2_STATUS(display, cpu_transcoder, 1945 port), 1946 LINK_ENCRYPTION_STATUS, 1947 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1948 dig_port->hdcp.auth_status = true; 1949 1950 return ret; 1951 } 1952 1953 static int hdcp2_disable_encryption(struct intel_connector *connector) 1954 { 1955 struct intel_display *display = to_intel_display(connector); 1956 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 1957 struct intel_hdcp *hdcp = &connector->hdcp; 1958 enum port port = dig_port->base.port; 1959 enum transcoder cpu_transcoder = hdcp->cpu_transcoder; 1960 int ret; 1961 1962 drm_WARN_ON(display->drm, 1963 !(intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port)) & 1964 LINK_ENCRYPTION_STATUS)); 1965 1966 intel_de_rmw(display, HDCP2_CTL(display, cpu_transcoder, port), 1967 CTL_LINK_ENCRYPTION_REQ, 0); 1968 1969 ret = intel_de_wait_for_clear(display, 1970 HDCP2_STATUS(display, cpu_transcoder, 1971 port), 1972 LINK_ENCRYPTION_STATUS, 1973 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); 1974 if (ret == -ETIMEDOUT) 1975 drm_dbg_kms(display->drm, "Disable Encryption Timedout"); 1976 1977 if (hdcp->shim->toggle_signalling) { 1978 ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, 1979 false); 1980 if (ret) { 1981 drm_err(display->drm, 1982 "Failed to disable HDCP signalling. %d\n", 1983 ret); 1984 return ret; 1985 } 1986 } 1987 1988 return ret; 1989 } 1990 1991 static int 1992 hdcp2_propagate_stream_management_info(struct intel_connector *connector) 1993 { 1994 struct intel_display *display = to_intel_display(connector); 1995 int i, tries = 3, ret; 1996 1997 if (!connector->hdcp.is_repeater) 1998 return 0; 1999 2000 for (i = 0; i < tries; i++) { 2001 ret = _hdcp2_propagate_stream_management_info(connector); 2002 if (!ret) 2003 break; 2004 2005 /* Lets restart the auth incase of seq_num_m roll over */ 2006 if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { 2007 drm_dbg_kms(display->drm, 2008 "seq_num_m roll over.(%d)\n", ret); 2009 break; 2010 } 2011 2012 drm_dbg_kms(display->drm, 2013 "HDCP2 stream management %d of %d Failed.(%d)\n", 2014 i + 1, tries, ret); 2015 } 2016 2017 return ret; 2018 } 2019 2020 static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, 2021 struct intel_connector *connector) 2022 { 2023 struct intel_display *display = to_intel_display(connector); 2024 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2025 int ret = 0, i, tries = 3; 2026 2027 for (i = 0; i < tries && !dig_port->hdcp.auth_status; i++) { 2028 ret = hdcp2_authenticate_sink(connector); 2029 if (!ret) { 2030 ret = intel_hdcp_prepare_streams(state, connector); 2031 if (ret) { 2032 drm_dbg_kms(display->drm, 2033 "Prepare stream failed.(%d)\n", 2034 ret); 2035 break; 2036 } 2037 2038 ret = hdcp2_propagate_stream_management_info(connector); 2039 if (ret) { 2040 drm_dbg_kms(display->drm, 2041 "Stream management failed.(%d)\n", 2042 ret); 2043 break; 2044 } 2045 2046 ret = hdcp2_authenticate_port(connector); 2047 if (!ret) 2048 break; 2049 drm_dbg_kms(display->drm, "HDCP2 port auth failed.(%d)\n", 2050 ret); 2051 } 2052 2053 /* Clearing the mei hdcp session */ 2054 drm_dbg_kms(display->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", 2055 i + 1, tries, ret); 2056 if (hdcp2_deauthenticate_port(connector) < 0) 2057 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2058 } 2059 2060 if (!ret && !dig_port->hdcp.auth_status) { 2061 /* 2062 * Ensuring the required 200mSec min time interval between 2063 * Session Key Exchange and encryption. 2064 */ 2065 msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); 2066 ret = hdcp2_enable_encryption(connector); 2067 if (ret < 0) { 2068 drm_dbg_kms(display->drm, 2069 "Encryption Enable Failed.(%d)\n", ret); 2070 if (hdcp2_deauthenticate_port(connector) < 0) 2071 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2072 } 2073 } 2074 2075 if (!ret) 2076 ret = hdcp2_enable_stream_encryption(connector); 2077 2078 return ret; 2079 } 2080 2081 static int _intel_hdcp2_enable(struct intel_atomic_state *state, 2082 struct intel_connector *connector) 2083 { 2084 struct intel_display *display = to_intel_display(connector); 2085 struct intel_hdcp *hdcp = &connector->hdcp; 2086 int ret; 2087 2088 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", 2089 connector->base.base.id, connector->base.name, 2090 hdcp->content_type); 2091 2092 intel_hdcp_adjust_hdcp_line_rekeying(connector->encoder, hdcp, false); 2093 2094 ret = hdcp2_authenticate_and_encrypt(state, connector); 2095 if (ret) { 2096 drm_dbg_kms(display->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", 2097 hdcp->content_type, ret); 2098 return ret; 2099 } 2100 2101 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", 2102 connector->base.base.id, connector->base.name, 2103 hdcp->content_type); 2104 2105 hdcp->hdcp2_encrypted = true; 2106 return 0; 2107 } 2108 2109 static int 2110 _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) 2111 { 2112 struct intel_display *display = to_intel_display(connector); 2113 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2114 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2115 struct intel_hdcp *hdcp = &connector->hdcp; 2116 int ret; 2117 2118 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", 2119 connector->base.base.id, connector->base.name); 2120 2121 if (hdcp->shim->stream_2_2_encryption) { 2122 ret = hdcp->shim->stream_2_2_encryption(connector, false); 2123 if (ret) { 2124 drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", 2125 connector->base.base.id, connector->base.name); 2126 return ret; 2127 } 2128 drm_dbg_kms(display->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", 2129 transcoder_name(hdcp->stream_transcoder)); 2130 2131 if (dig_port->hdcp.num_streams > 0 && !hdcp2_link_recovery) 2132 return 0; 2133 } 2134 2135 ret = hdcp2_disable_encryption(connector); 2136 2137 if (hdcp2_deauthenticate_port(connector) < 0) 2138 drm_dbg_kms(display->drm, "Port deauth failed.\n"); 2139 2140 connector->hdcp.hdcp2_encrypted = false; 2141 dig_port->hdcp.auth_status = false; 2142 data->k = 0; 2143 2144 return ret; 2145 } 2146 2147 /* Implements the Link Integrity Check for HDCP2.2 */ 2148 static int intel_hdcp2_check_link(struct intel_connector *connector) 2149 { 2150 struct intel_display *display = to_intel_display(connector); 2151 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2152 struct intel_hdcp *hdcp = &connector->hdcp; 2153 enum port port = dig_port->base.port; 2154 enum transcoder cpu_transcoder; 2155 int ret = 0; 2156 2157 mutex_lock(&hdcp->mutex); 2158 mutex_lock(&dig_port->hdcp.mutex); 2159 cpu_transcoder = hdcp->cpu_transcoder; 2160 2161 /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ 2162 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || 2163 !hdcp->hdcp2_encrypted) { 2164 ret = -EINVAL; 2165 goto out; 2166 } 2167 2168 if (drm_WARN_ON(display->drm, 2169 !intel_hdcp2_in_use(display, cpu_transcoder, port))) { 2170 drm_err(display->drm, 2171 "HDCP2.2 link stopped the encryption, %x\n", 2172 intel_de_read(display, HDCP2_STATUS(display, cpu_transcoder, port))); 2173 ret = -ENXIO; 2174 _intel_hdcp2_disable(connector, true); 2175 intel_hdcp_update_value(connector, 2176 DRM_MODE_CONTENT_PROTECTION_DESIRED, 2177 true); 2178 goto out; 2179 } 2180 2181 ret = hdcp->shim->check_2_2_link(dig_port, connector); 2182 if (ret == HDCP_LINK_PROTECTED) { 2183 if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { 2184 intel_hdcp_update_value(connector, 2185 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2186 true); 2187 } 2188 goto out; 2189 } 2190 2191 if (ret == HDCP_TOPOLOGY_CHANGE) { 2192 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2193 goto out; 2194 2195 drm_dbg_kms(display->drm, 2196 "HDCP2.2 Downstream topology change\n"); 2197 2198 ret = hdcp2_authenticate_repeater_topology(connector); 2199 if (!ret) { 2200 intel_hdcp_update_value(connector, 2201 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2202 true); 2203 goto out; 2204 } 2205 2206 drm_dbg_kms(display->drm, 2207 "[CONNECTOR:%d:%s] Repeater topology auth failed.(%d)\n", 2208 connector->base.base.id, connector->base.name, 2209 ret); 2210 } else { 2211 drm_dbg_kms(display->drm, 2212 "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", 2213 connector->base.base.id, connector->base.name); 2214 } 2215 2216 ret = _intel_hdcp2_disable(connector, true); 2217 if (ret) { 2218 drm_err(display->drm, 2219 "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", 2220 connector->base.base.id, connector->base.name, ret); 2221 intel_hdcp_update_value(connector, 2222 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2223 goto out; 2224 } 2225 2226 intel_hdcp_update_value(connector, 2227 DRM_MODE_CONTENT_PROTECTION_DESIRED, true); 2228 out: 2229 mutex_unlock(&dig_port->hdcp.mutex); 2230 mutex_unlock(&hdcp->mutex); 2231 return ret; 2232 } 2233 2234 static void intel_hdcp_check_work(struct work_struct *work) 2235 { 2236 struct intel_hdcp *hdcp = container_of(to_delayed_work(work), 2237 struct intel_hdcp, 2238 check_work); 2239 struct intel_connector *connector = intel_hdcp_to_connector(hdcp); 2240 struct intel_display *display = to_intel_display(connector); 2241 2242 if (drm_connector_is_unregistered(&connector->base)) 2243 return; 2244 2245 if (!intel_hdcp2_check_link(connector)) 2246 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2247 DRM_HDCP2_CHECK_PERIOD_MS); 2248 else if (!intel_hdcp_check_link(connector)) 2249 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2250 DRM_HDCP_CHECK_PERIOD_MS); 2251 } 2252 2253 static int i915_hdcp_component_bind(struct device *drv_kdev, 2254 struct device *mei_kdev, void *data) 2255 { 2256 struct intel_display *display = to_intel_display(drv_kdev); 2257 2258 drm_dbg(display->drm, "I915 HDCP comp bind\n"); 2259 mutex_lock(&display->hdcp.hdcp_mutex); 2260 display->hdcp.arbiter = (struct i915_hdcp_arbiter *)data; 2261 display->hdcp.arbiter->hdcp_dev = mei_kdev; 2262 mutex_unlock(&display->hdcp.hdcp_mutex); 2263 2264 return 0; 2265 } 2266 2267 static void i915_hdcp_component_unbind(struct device *drv_kdev, 2268 struct device *mei_kdev, void *data) 2269 { 2270 struct intel_display *display = to_intel_display(drv_kdev); 2271 2272 drm_dbg(display->drm, "I915 HDCP comp unbind\n"); 2273 mutex_lock(&display->hdcp.hdcp_mutex); 2274 display->hdcp.arbiter = NULL; 2275 mutex_unlock(&display->hdcp.hdcp_mutex); 2276 } 2277 2278 static const struct component_ops i915_hdcp_ops = { 2279 .bind = i915_hdcp_component_bind, 2280 .unbind = i915_hdcp_component_unbind, 2281 }; 2282 2283 static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) 2284 { 2285 switch (port) { 2286 case PORT_A: 2287 return HDCP_DDI_A; 2288 case PORT_B ... PORT_F: 2289 return (enum hdcp_ddi)port; 2290 default: 2291 return HDCP_DDI_INVALID_PORT; 2292 } 2293 } 2294 2295 static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) 2296 { 2297 switch (cpu_transcoder) { 2298 case TRANSCODER_A ... TRANSCODER_D: 2299 return (enum hdcp_transcoder)(cpu_transcoder | 0x10); 2300 default: /* eDP, DSI TRANSCODERS are non HDCP capable */ 2301 return HDCP_INVALID_TRANSCODER; 2302 } 2303 } 2304 2305 static int initialize_hdcp_port_data(struct intel_connector *connector, 2306 struct intel_digital_port *dig_port, 2307 const struct intel_hdcp_shim *shim) 2308 { 2309 struct intel_display *display = to_intel_display(connector); 2310 struct hdcp_port_data *data = &dig_port->hdcp.port_data; 2311 enum port port = dig_port->base.port; 2312 2313 if (DISPLAY_VER(display) < 12) 2314 data->hdcp_ddi = intel_get_hdcp_ddi_index(port); 2315 else 2316 /* 2317 * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled 2318 * with zero(INVALID PORT index). 2319 */ 2320 data->hdcp_ddi = HDCP_DDI_INVALID_PORT; 2321 2322 /* 2323 * As associated transcoder is set and modified at modeset, here hdcp_transcoder 2324 * is initialized to zero (invalid transcoder index). This will be 2325 * retained for <Gen12 forever. 2326 */ 2327 data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; 2328 2329 data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; 2330 data->protocol = (u8)shim->protocol; 2331 2332 if (!data->streams) 2333 data->streams = kcalloc(INTEL_NUM_PIPES(display), 2334 sizeof(struct hdcp2_streamid_type), 2335 GFP_KERNEL); 2336 if (!data->streams) { 2337 drm_err(display->drm, "Out of Memory\n"); 2338 return -ENOMEM; 2339 } 2340 2341 return 0; 2342 } 2343 2344 static bool is_hdcp2_supported(struct intel_display *display) 2345 { 2346 if (USE_HDCP_GSC(display)) 2347 return true; 2348 2349 if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) 2350 return false; 2351 2352 return DISPLAY_VER(display) >= 10 || 2353 display->platform.kabylake || 2354 display->platform.coffeelake || 2355 display->platform.cometlake; 2356 } 2357 2358 void intel_hdcp_component_init(struct intel_display *display) 2359 { 2360 int ret; 2361 2362 if (!is_hdcp2_supported(display)) 2363 return; 2364 2365 mutex_lock(&display->hdcp.hdcp_mutex); 2366 drm_WARN_ON(display->drm, display->hdcp.comp_added); 2367 2368 display->hdcp.comp_added = true; 2369 mutex_unlock(&display->hdcp.hdcp_mutex); 2370 if (USE_HDCP_GSC(display)) 2371 ret = intel_hdcp_gsc_init(display); 2372 else 2373 ret = component_add_typed(display->drm->dev, &i915_hdcp_ops, 2374 I915_COMPONENT_HDCP); 2375 2376 if (ret < 0) { 2377 drm_dbg_kms(display->drm, "Failed at fw component add(%d)\n", 2378 ret); 2379 mutex_lock(&display->hdcp.hdcp_mutex); 2380 display->hdcp.comp_added = false; 2381 mutex_unlock(&display->hdcp.hdcp_mutex); 2382 return; 2383 } 2384 } 2385 2386 static void intel_hdcp2_init(struct intel_connector *connector, 2387 struct intel_digital_port *dig_port, 2388 const struct intel_hdcp_shim *shim) 2389 { 2390 struct intel_display *display = to_intel_display(connector); 2391 struct intel_hdcp *hdcp = &connector->hdcp; 2392 int ret; 2393 2394 ret = initialize_hdcp_port_data(connector, dig_port, shim); 2395 if (ret) { 2396 drm_dbg_kms(display->drm, "Mei hdcp data init failed\n"); 2397 return; 2398 } 2399 2400 hdcp->hdcp2_supported = true; 2401 } 2402 2403 int intel_hdcp_init(struct intel_connector *connector, 2404 struct intel_digital_port *dig_port, 2405 const struct intel_hdcp_shim *shim) 2406 { 2407 struct intel_display *display = to_intel_display(connector); 2408 struct intel_hdcp *hdcp = &connector->hdcp; 2409 int ret; 2410 2411 if (!shim) 2412 return -EINVAL; 2413 2414 if (is_hdcp2_supported(display)) 2415 intel_hdcp2_init(connector, dig_port, shim); 2416 2417 ret = drm_connector_attach_content_protection_property(&connector->base, 2418 hdcp->hdcp2_supported); 2419 if (ret) { 2420 hdcp->hdcp2_supported = false; 2421 kfree(dig_port->hdcp.port_data.streams); 2422 return ret; 2423 } 2424 2425 hdcp->shim = shim; 2426 mutex_init(&hdcp->mutex); 2427 INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); 2428 INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); 2429 init_waitqueue_head(&hdcp->cp_irq_queue); 2430 2431 return 0; 2432 } 2433 2434 static int _intel_hdcp_enable(struct intel_atomic_state *state, 2435 struct intel_encoder *encoder, 2436 const struct intel_crtc_state *pipe_config, 2437 const struct drm_connector_state *conn_state) 2438 { 2439 struct intel_display *display = to_intel_display(encoder); 2440 struct intel_connector *connector = 2441 to_intel_connector(conn_state->connector); 2442 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2443 struct intel_hdcp *hdcp = &connector->hdcp; 2444 unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; 2445 int ret = -EINVAL; 2446 2447 if (!hdcp->shim) 2448 return -ENOENT; 2449 2450 mutex_lock(&hdcp->mutex); 2451 mutex_lock(&dig_port->hdcp.mutex); 2452 drm_WARN_ON(display->drm, 2453 hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); 2454 hdcp->content_type = (u8)conn_state->hdcp_content_type; 2455 2456 if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { 2457 hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; 2458 hdcp->stream_transcoder = pipe_config->cpu_transcoder; 2459 } else { 2460 hdcp->cpu_transcoder = pipe_config->cpu_transcoder; 2461 hdcp->stream_transcoder = INVALID_TRANSCODER; 2462 } 2463 2464 if (DISPLAY_VER(display) >= 12) 2465 dig_port->hdcp.port_data.hdcp_transcoder = 2466 intel_get_hdcp_transcoder(hdcp->cpu_transcoder); 2467 2468 /* 2469 * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup 2470 * is capable of HDCP2.2, it is preferred to use HDCP2.2. 2471 */ 2472 if (!hdcp->force_hdcp14 && intel_hdcp2_get_capability(connector)) { 2473 ret = _intel_hdcp2_enable(state, connector); 2474 if (!ret) 2475 check_link_interval = 2476 DRM_HDCP2_CHECK_PERIOD_MS; 2477 } 2478 2479 if (hdcp->force_hdcp14) 2480 drm_dbg_kms(display->drm, "Forcing HDCP 1.4\n"); 2481 2482 /* 2483 * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will 2484 * be attempted. 2485 */ 2486 if (ret && intel_hdcp_get_capability(connector) && 2487 hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { 2488 ret = intel_hdcp1_enable(connector); 2489 } 2490 2491 if (!ret) { 2492 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 2493 check_link_interval); 2494 intel_hdcp_update_value(connector, 2495 DRM_MODE_CONTENT_PROTECTION_ENABLED, 2496 true); 2497 } 2498 2499 mutex_unlock(&dig_port->hdcp.mutex); 2500 mutex_unlock(&hdcp->mutex); 2501 return ret; 2502 } 2503 2504 void intel_hdcp_enable(struct intel_atomic_state *state, 2505 struct intel_encoder *encoder, 2506 const struct intel_crtc_state *crtc_state, 2507 const struct drm_connector_state *conn_state) 2508 { 2509 struct intel_connector *connector = 2510 to_intel_connector(conn_state->connector); 2511 struct intel_hdcp *hdcp = &connector->hdcp; 2512 2513 /* 2514 * Enable hdcp if it's desired or if userspace is enabled and 2515 * driver set its state to undesired 2516 */ 2517 if (conn_state->content_protection == 2518 DRM_MODE_CONTENT_PROTECTION_DESIRED || 2519 (conn_state->content_protection == 2520 DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == 2521 DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2522 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2523 } 2524 2525 int intel_hdcp_disable(struct intel_connector *connector) 2526 { 2527 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 2528 struct intel_hdcp *hdcp = &connector->hdcp; 2529 int ret = 0; 2530 2531 if (!hdcp->shim) 2532 return -ENOENT; 2533 2534 mutex_lock(&hdcp->mutex); 2535 mutex_lock(&dig_port->hdcp.mutex); 2536 2537 if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) 2538 goto out; 2539 2540 intel_hdcp_update_value(connector, 2541 DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); 2542 if (hdcp->hdcp2_encrypted) 2543 ret = _intel_hdcp2_disable(connector, false); 2544 else if (hdcp->hdcp_encrypted) 2545 ret = _intel_hdcp_disable(connector); 2546 2547 out: 2548 mutex_unlock(&dig_port->hdcp.mutex); 2549 mutex_unlock(&hdcp->mutex); 2550 cancel_delayed_work_sync(&hdcp->check_work); 2551 return ret; 2552 } 2553 2554 void intel_hdcp_update_pipe(struct intel_atomic_state *state, 2555 struct intel_encoder *encoder, 2556 const struct intel_crtc_state *crtc_state, 2557 const struct drm_connector_state *conn_state) 2558 { 2559 struct intel_connector *connector = 2560 to_intel_connector(conn_state->connector); 2561 struct intel_hdcp *hdcp = &connector->hdcp; 2562 bool content_protection_type_changed, desired_and_not_enabled = false; 2563 struct intel_display *display = to_intel_display(connector); 2564 2565 if (!connector->hdcp.shim) 2566 return; 2567 2568 content_protection_type_changed = 2569 (conn_state->hdcp_content_type != hdcp->content_type && 2570 conn_state->content_protection != 2571 DRM_MODE_CONTENT_PROTECTION_UNDESIRED); 2572 2573 /* 2574 * During the HDCP encryption session if Type change is requested, 2575 * disable the HDCP and re-enable it with new TYPE value. 2576 */ 2577 if (conn_state->content_protection == 2578 DRM_MODE_CONTENT_PROTECTION_UNDESIRED || 2579 content_protection_type_changed) 2580 intel_hdcp_disable(connector); 2581 2582 /* 2583 * Mark the hdcp state as DESIRED after the hdcp disable of type 2584 * change procedure. 2585 */ 2586 if (content_protection_type_changed) { 2587 mutex_lock(&hdcp->mutex); 2588 hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2589 drm_connector_get(&connector->base); 2590 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2591 drm_connector_put(&connector->base); 2592 mutex_unlock(&hdcp->mutex); 2593 } 2594 2595 if (conn_state->content_protection == 2596 DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2597 mutex_lock(&hdcp->mutex); 2598 /* Avoid enabling hdcp, if it already ENABLED */ 2599 desired_and_not_enabled = 2600 hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; 2601 mutex_unlock(&hdcp->mutex); 2602 /* 2603 * If HDCP already ENABLED and CP property is DESIRED, schedule 2604 * prop_work to update correct CP property to user space. 2605 */ 2606 if (!desired_and_not_enabled && !content_protection_type_changed) { 2607 drm_connector_get(&connector->base); 2608 if (!queue_work(display->wq.unordered, &hdcp->prop_work)) 2609 drm_connector_put(&connector->base); 2610 2611 } 2612 } 2613 2614 if (desired_and_not_enabled || content_protection_type_changed) 2615 _intel_hdcp_enable(state, encoder, crtc_state, conn_state); 2616 } 2617 2618 void intel_hdcp_cancel_works(struct intel_connector *connector) 2619 { 2620 if (!connector->hdcp.shim) 2621 return; 2622 2623 cancel_delayed_work_sync(&connector->hdcp.check_work); 2624 cancel_work_sync(&connector->hdcp.prop_work); 2625 } 2626 2627 void intel_hdcp_component_fini(struct intel_display *display) 2628 { 2629 mutex_lock(&display->hdcp.hdcp_mutex); 2630 if (!display->hdcp.comp_added) { 2631 mutex_unlock(&display->hdcp.hdcp_mutex); 2632 return; 2633 } 2634 2635 display->hdcp.comp_added = false; 2636 mutex_unlock(&display->hdcp.hdcp_mutex); 2637 2638 if (USE_HDCP_GSC(display)) 2639 intel_hdcp_gsc_fini(display); 2640 else 2641 component_del(display->drm->dev, &i915_hdcp_ops); 2642 } 2643 2644 void intel_hdcp_cleanup(struct intel_connector *connector) 2645 { 2646 struct intel_hdcp *hdcp = &connector->hdcp; 2647 2648 if (!hdcp->shim) 2649 return; 2650 2651 /* 2652 * If the connector is registered, it's possible userspace could kick 2653 * off another HDCP enable, which would re-spawn the workers. 2654 */ 2655 drm_WARN_ON(connector->base.dev, 2656 connector->base.registration_state == DRM_CONNECTOR_REGISTERED); 2657 2658 /* 2659 * Now that the connector is not registered, check_work won't be run, 2660 * but cancel any outstanding instances of it 2661 */ 2662 cancel_delayed_work_sync(&hdcp->check_work); 2663 2664 /* 2665 * We don't cancel prop_work in the same way as check_work since it 2666 * requires connection_mutex which could be held while calling this 2667 * function. Instead, we rely on the connector references grabbed before 2668 * scheduling prop_work to ensure the connector is alive when prop_work 2669 * is run. So if we're in the destroy path (which is where this 2670 * function should be called), we're "guaranteed" that prop_work is not 2671 * active (tl;dr This Should Never Happen). 2672 */ 2673 drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); 2674 2675 mutex_lock(&hdcp->mutex); 2676 hdcp->shim = NULL; 2677 mutex_unlock(&hdcp->mutex); 2678 } 2679 2680 void intel_hdcp_atomic_check(struct drm_connector *connector, 2681 struct drm_connector_state *old_state, 2682 struct drm_connector_state *new_state) 2683 { 2684 u64 old_cp = old_state->content_protection; 2685 u64 new_cp = new_state->content_protection; 2686 struct drm_crtc_state *crtc_state; 2687 2688 if (!new_state->crtc) { 2689 /* 2690 * If the connector is being disabled with CP enabled, mark it 2691 * desired so it's re-enabled when the connector is brought back 2692 */ 2693 if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) 2694 new_state->content_protection = 2695 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2696 return; 2697 } 2698 2699 crtc_state = drm_atomic_get_new_crtc_state(new_state->state, 2700 new_state->crtc); 2701 /* 2702 * Fix the HDCP uapi content protection state in case of modeset. 2703 * FIXME: As per HDCP content protection property uapi doc, an uevent() 2704 * need to be sent if there is transition from ENABLED->DESIRED. 2705 */ 2706 if (drm_atomic_crtc_needs_modeset(crtc_state) && 2707 (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && 2708 new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) 2709 new_state->content_protection = 2710 DRM_MODE_CONTENT_PROTECTION_DESIRED; 2711 2712 /* 2713 * Nothing to do if the state didn't change, or HDCP was activated since 2714 * the last commit. And also no change in hdcp content type. 2715 */ 2716 if (old_cp == new_cp || 2717 (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && 2718 new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { 2719 if (old_state->hdcp_content_type == 2720 new_state->hdcp_content_type) 2721 return; 2722 } 2723 2724 crtc_state->mode_changed = true; 2725 } 2726 2727 /* Handles the CP_IRQ raised from the DP HDCP sink */ 2728 void intel_hdcp_handle_cp_irq(struct intel_connector *connector) 2729 { 2730 struct intel_hdcp *hdcp = &connector->hdcp; 2731 struct intel_display *display = to_intel_display(connector); 2732 2733 if (!hdcp->shim) 2734 return; 2735 2736 atomic_inc(&connector->hdcp.cp_irq_count); 2737 wake_up_all(&connector->hdcp.cp_irq_queue); 2738 2739 queue_delayed_work(display->wq.unordered, &hdcp->check_work, 0); 2740 } 2741 2742 static void __intel_hdcp_info(struct seq_file *m, struct intel_connector *connector, 2743 bool remote_req) 2744 { 2745 bool hdcp_cap = false, hdcp2_cap = false; 2746 2747 if (!connector->hdcp.shim) { 2748 seq_puts(m, "No Connector Support"); 2749 goto out; 2750 } 2751 2752 if (remote_req) { 2753 intel_hdcp_get_remote_capability(connector, &hdcp_cap, &hdcp2_cap); 2754 } else { 2755 hdcp_cap = intel_hdcp_get_capability(connector); 2756 hdcp2_cap = intel_hdcp2_get_capability(connector); 2757 } 2758 2759 if (hdcp_cap) 2760 seq_puts(m, "HDCP1.4 "); 2761 if (hdcp2_cap) 2762 seq_puts(m, "HDCP2.2 "); 2763 2764 if (!hdcp_cap && !hdcp2_cap) 2765 seq_puts(m, "None"); 2766 2767 out: 2768 seq_puts(m, "\n"); 2769 } 2770 2771 void intel_hdcp_info(struct seq_file *m, struct intel_connector *connector) 2772 { 2773 seq_puts(m, "\tHDCP version: "); 2774 if (connector->mst.dp) { 2775 __intel_hdcp_info(m, connector, true); 2776 seq_puts(m, "\tMST Hub HDCP version: "); 2777 } 2778 __intel_hdcp_info(m, connector, false); 2779 } 2780 2781 static int intel_hdcp_sink_capability_show(struct seq_file *m, void *data) 2782 { 2783 struct intel_connector *connector = m->private; 2784 struct intel_display *display = to_intel_display(connector); 2785 int ret; 2786 2787 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2788 if (ret) 2789 return ret; 2790 2791 if (!connector->base.encoder || 2792 connector->base.status != connector_status_connected) { 2793 ret = -ENODEV; 2794 goto out; 2795 } 2796 2797 seq_printf(m, "%s:%d HDCP version: ", connector->base.name, 2798 connector->base.base.id); 2799 __intel_hdcp_info(m, connector, false); 2800 2801 out: 2802 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2803 2804 return ret; 2805 } 2806 DEFINE_SHOW_ATTRIBUTE(intel_hdcp_sink_capability); 2807 2808 static ssize_t intel_hdcp_force_14_write(struct file *file, 2809 const char __user *ubuf, 2810 size_t len, loff_t *offp) 2811 { 2812 struct seq_file *m = file->private_data; 2813 struct intel_connector *connector = m->private; 2814 struct intel_hdcp *hdcp = &connector->hdcp; 2815 bool force_hdcp14 = false; 2816 int ret; 2817 2818 if (len == 0) 2819 return 0; 2820 2821 ret = kstrtobool_from_user(ubuf, len, &force_hdcp14); 2822 if (ret < 0) 2823 return ret; 2824 2825 hdcp->force_hdcp14 = force_hdcp14; 2826 *offp += len; 2827 2828 return len; 2829 } 2830 2831 static int intel_hdcp_force_14_show(struct seq_file *m, void *data) 2832 { 2833 struct intel_connector *connector = m->private; 2834 struct intel_display *display = to_intel_display(connector); 2835 struct intel_encoder *encoder = intel_attached_encoder(connector); 2836 struct intel_hdcp *hdcp = &connector->hdcp; 2837 struct drm_crtc *crtc; 2838 int ret; 2839 2840 if (!encoder) 2841 return -ENODEV; 2842 2843 ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 2844 if (ret) 2845 return ret; 2846 2847 crtc = connector->base.state->crtc; 2848 if (connector->base.status != connector_status_connected || !crtc) { 2849 ret = -ENODEV; 2850 goto out; 2851 } 2852 2853 seq_printf(m, "%s\n", 2854 str_yes_no(hdcp->force_hdcp14)); 2855 out: 2856 drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 2857 2858 return ret; 2859 } 2860 2861 static int intel_hdcp_force_14_open(struct inode *inode, 2862 struct file *file) 2863 { 2864 return single_open(file, intel_hdcp_force_14_show, 2865 inode->i_private); 2866 } 2867 2868 static const struct file_operations intel_hdcp_force_14_fops = { 2869 .owner = THIS_MODULE, 2870 .open = intel_hdcp_force_14_open, 2871 .read = seq_read, 2872 .llseek = seq_lseek, 2873 .release = single_release, 2874 .write = intel_hdcp_force_14_write 2875 }; 2876 2877 void intel_hdcp_connector_debugfs_add(struct intel_connector *connector) 2878 { 2879 struct dentry *root = connector->base.debugfs_entry; 2880 int connector_type = connector->base.connector_type; 2881 2882 if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || 2883 connector_type == DRM_MODE_CONNECTOR_HDMIA || 2884 connector_type == DRM_MODE_CONNECTOR_HDMIB) { 2885 debugfs_create_file("i915_hdcp_sink_capability", 0444, root, 2886 connector, &intel_hdcp_sink_capability_fops); 2887 debugfs_create_file("i915_force_hdcp14", 0644, root, 2888 connector, &intel_hdcp_force_14_fops); 2889 } 2890 } 2891