1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GMBUS_REGS_H__ 7 #define __INTEL_GMBUS_REGS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base) 12 13 #define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio)) 14 #define GPIO_CLOCK_DIR_MASK (1 << 0) 15 #define GPIO_CLOCK_DIR_IN (0 << 1) 16 #define GPIO_CLOCK_DIR_OUT (1 << 1) 17 #define GPIO_CLOCK_VAL_MASK (1 << 2) 18 #define GPIO_CLOCK_VAL_OUT (1 << 3) 19 #define GPIO_CLOCK_VAL_IN (1 << 4) 20 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5) 21 #define GPIO_DATA_DIR_MASK (1 << 8) 22 #define GPIO_DATA_DIR_IN (0 << 9) 23 #define GPIO_DATA_DIR_OUT (1 << 9) 24 #define GPIO_DATA_VAL_MASK (1 << 10) 25 #define GPIO_DATA_VAL_OUT (1 << 11) 26 #define GPIO_DATA_VAL_IN (1 << 12) 27 #define GPIO_DATA_PULLUP_DISABLE (1 << 13) 28 29 /* clock/port select */ 30 #define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100) 31 #define GMBUS_AKSV_SELECT (1 << 11) 32 #define GMBUS_RATE_100KHZ (0 << 8) 33 #define GMBUS_RATE_50KHZ (1 << 8) 34 #define GMBUS_RATE_400KHZ (2 << 8) /* reserved on Pineview */ 35 #define GMBUS_RATE_1MHZ (3 << 8) /* reserved on Pineview */ 36 #define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */ 37 #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6) 38 39 /* command/status */ 40 #define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104) 41 #define GMBUS_SW_CLR_INT (1 << 31) 42 #define GMBUS_SW_RDY (1 << 30) 43 #define GMBUS_ENT (1 << 29) /* enable timeout */ 44 #define GMBUS_CYCLE_NONE (0 << 25) 45 #define GMBUS_CYCLE_WAIT (1 << 25) 46 #define GMBUS_CYCLE_INDEX (2 << 25) 47 #define GMBUS_CYCLE_STOP (4 << 25) 48 #define GMBUS_BYTE_COUNT_SHIFT 16 49 #define GMBUS_BYTE_COUNT_MAX 256U 50 #define GEN9_GMBUS_BYTE_COUNT_MAX 511U 51 #define GMBUS_SLAVE_INDEX_SHIFT 8 52 #define GMBUS_SLAVE_ADDR_SHIFT 1 53 #define GMBUS_SLAVE_READ (1 << 0) 54 #define GMBUS_SLAVE_WRITE (0 << 0) 55 56 /* status */ 57 #define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108) 58 #define GMBUS_INUSE (1 << 15) 59 #define GMBUS_HW_WAIT_PHASE (1 << 14) 60 #define GMBUS_STALL_TIMEOUT (1 << 13) 61 #define GMBUS_INT (1 << 12) 62 #define GMBUS_HW_RDY (1 << 11) 63 #define GMBUS_SATOER (1 << 10) 64 #define GMBUS_ACTIVE (1 << 9) 65 66 /* data buffer bytes 3-0 */ 67 #define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c) 68 69 /* interrupt mask (Pineview+) */ 70 #define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110) 71 #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4) 72 #define GMBUS_NAK_EN (1 << 3) 73 #define GMBUS_IDLE_EN (1 << 2) 74 #define GMBUS_HW_WAIT_EN (1 << 1) 75 #define GMBUS_HW_RDY_EN (1 << 0) 76 77 /* byte index */ 78 #define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120) 79 #define GMBUS_2BYTE_INDEX_EN (1 << 31) 80 81 #endif /* __INTEL_GMBUS_REGS_H__ */ 82