1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_types.h" 41 #include "intel_gmbus.h" 42 #include "intel_gmbus_regs.h" 43 44 struct intel_gmbus { 45 struct i2c_adapter adapter; 46 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 47 u32 force_bit; 48 u32 reg0; 49 i915_reg_t gpio_reg; 50 struct i2c_algo_bit_data bit_algo; 51 struct intel_display *display; 52 }; 53 54 enum gmbus_gpio { 55 GPIOA, 56 GPIOB, 57 GPIOC, 58 GPIOD, 59 GPIOE, 60 GPIOF, 61 GPIOG, 62 GPIOH, 63 __GPIOI_UNUSED, 64 GPIOJ, 65 GPIOK, 66 GPIOL, 67 GPIOM, 68 GPION, 69 GPIOO, 70 }; 71 72 struct gmbus_pin { 73 const char *name; 74 enum gmbus_gpio gpio; 75 }; 76 77 /* Map gmbus pin pairs to names and registers. */ 78 static const struct gmbus_pin gmbus_pins[] = { 79 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 80 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 81 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 82 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 83 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 84 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 85 }; 86 87 static const struct gmbus_pin gmbus_pins_bdw[] = { 88 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 89 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 90 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 91 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 92 }; 93 94 static const struct gmbus_pin gmbus_pins_skl[] = { 95 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 96 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 97 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 98 }; 99 100 static const struct gmbus_pin gmbus_pins_bxt[] = { 101 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 102 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 103 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 104 }; 105 106 static const struct gmbus_pin gmbus_pins_cnp[] = { 107 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 108 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 109 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 110 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 111 }; 112 113 static const struct gmbus_pin gmbus_pins_icp[] = { 114 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 115 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 116 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 117 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 118 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 119 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 120 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 121 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 122 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 123 }; 124 125 static const struct gmbus_pin gmbus_pins_dg1[] = { 126 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 127 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 128 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 129 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 130 }; 131 132 static const struct gmbus_pin gmbus_pins_dg2[] = { 133 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 134 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 135 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 136 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 137 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 138 }; 139 140 static const struct gmbus_pin gmbus_pins_mtp[] = { 141 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 142 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 143 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 144 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 145 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 146 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 147 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 148 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 149 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 150 }; 151 152 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, 153 unsigned int pin) 154 { 155 struct drm_i915_private *i915 = to_i915(display->drm); 156 const struct gmbus_pin *pins; 157 size_t size; 158 159 if (INTEL_PCH_TYPE(i915) >= PCH_MTL) { 160 pins = gmbus_pins_mtp; 161 size = ARRAY_SIZE(gmbus_pins_mtp); 162 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { 163 pins = gmbus_pins_dg2; 164 size = ARRAY_SIZE(gmbus_pins_dg2); 165 } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { 166 pins = gmbus_pins_dg1; 167 size = ARRAY_SIZE(gmbus_pins_dg1); 168 } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { 169 pins = gmbus_pins_icp; 170 size = ARRAY_SIZE(gmbus_pins_icp); 171 } else if (HAS_PCH_CNP(i915)) { 172 pins = gmbus_pins_cnp; 173 size = ARRAY_SIZE(gmbus_pins_cnp); 174 } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) { 175 pins = gmbus_pins_bxt; 176 size = ARRAY_SIZE(gmbus_pins_bxt); 177 } else if (DISPLAY_VER(display) == 9) { 178 pins = gmbus_pins_skl; 179 size = ARRAY_SIZE(gmbus_pins_skl); 180 } else if (IS_BROADWELL(i915)) { 181 pins = gmbus_pins_bdw; 182 size = ARRAY_SIZE(gmbus_pins_bdw); 183 } else { 184 pins = gmbus_pins; 185 size = ARRAY_SIZE(gmbus_pins); 186 } 187 188 if (pin >= size || !pins[pin].name) 189 return NULL; 190 191 return &pins[pin]; 192 } 193 194 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) 195 { 196 return get_gmbus_pin(display, pin); 197 } 198 199 /* Intel GPIO access functions */ 200 201 #define I2C_RISEFALL_TIME 10 202 203 static inline struct intel_gmbus * 204 to_intel_gmbus(struct i2c_adapter *i2c) 205 { 206 return container_of(i2c, struct intel_gmbus, adapter); 207 } 208 209 void 210 intel_gmbus_reset(struct intel_display *display) 211 { 212 intel_de_write(display, GMBUS0(display), 0); 213 intel_de_write(display, GMBUS4(display), 0); 214 } 215 216 static void pnv_gmbus_clock_gating(struct intel_display *display, 217 bool enable) 218 { 219 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 220 intel_de_rmw(display, DSPCLK_GATE_D(display), 221 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 222 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 223 } 224 225 static void pch_gmbus_clock_gating(struct intel_display *display, 226 bool enable) 227 { 228 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 229 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 231 } 232 233 static void bxt_gmbus_clock_gating(struct intel_display *display, 234 bool enable) 235 { 236 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 237 !enable ? BXT_GMBUS_GATING_DIS : 0); 238 } 239 240 static u32 get_reserved(struct intel_gmbus *bus) 241 { 242 struct intel_display *display = bus->display; 243 struct drm_i915_private *i915 = to_i915(display->drm); 244 u32 reserved = 0; 245 246 /* On most chips, these bits must be preserved in software. */ 247 if (!IS_I830(i915) && !IS_I845G(i915)) 248 reserved = intel_de_read_notrace(display, bus->gpio_reg) & 249 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 250 251 return reserved; 252 } 253 254 static int get_clock(void *data) 255 { 256 struct intel_gmbus *bus = data; 257 struct intel_display *display = bus->display; 258 u32 reserved = get_reserved(bus); 259 260 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 261 intel_de_write_notrace(display, bus->gpio_reg, reserved); 262 263 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 264 } 265 266 static int get_data(void *data) 267 { 268 struct intel_gmbus *bus = data; 269 struct intel_display *display = bus->display; 270 u32 reserved = get_reserved(bus); 271 272 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 273 intel_de_write_notrace(display, bus->gpio_reg, reserved); 274 275 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 276 } 277 278 static void set_clock(void *data, int state_high) 279 { 280 struct intel_gmbus *bus = data; 281 struct intel_display *display = bus->display; 282 u32 reserved = get_reserved(bus); 283 u32 clock_bits; 284 285 if (state_high) 286 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 287 else 288 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 289 GPIO_CLOCK_VAL_MASK; 290 291 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); 292 intel_de_posting_read(display, bus->gpio_reg); 293 } 294 295 static void set_data(void *data, int state_high) 296 { 297 struct intel_gmbus *bus = data; 298 struct intel_display *display = bus->display; 299 u32 reserved = get_reserved(bus); 300 u32 data_bits; 301 302 if (state_high) 303 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 304 else 305 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 306 GPIO_DATA_VAL_MASK; 307 308 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); 309 intel_de_posting_read(display, bus->gpio_reg); 310 } 311 312 static int 313 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 314 { 315 struct intel_gmbus *bus = to_intel_gmbus(adapter); 316 struct intel_display *display = bus->display; 317 struct drm_i915_private *i915 = to_i915(display->drm); 318 319 intel_gmbus_reset(display); 320 321 if (IS_PINEVIEW(i915)) 322 pnv_gmbus_clock_gating(display, false); 323 324 set_data(bus, 1); 325 set_clock(bus, 1); 326 udelay(I2C_RISEFALL_TIME); 327 return 0; 328 } 329 330 static void 331 intel_gpio_post_xfer(struct i2c_adapter *adapter) 332 { 333 struct intel_gmbus *bus = to_intel_gmbus(adapter); 334 struct intel_display *display = bus->display; 335 struct drm_i915_private *i915 = to_i915(display->drm); 336 337 set_data(bus, 1); 338 set_clock(bus, 1); 339 340 if (IS_PINEVIEW(i915)) 341 pnv_gmbus_clock_gating(display, true); 342 } 343 344 static void 345 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 346 { 347 struct i2c_algo_bit_data *algo; 348 349 algo = &bus->bit_algo; 350 351 bus->gpio_reg = gpio_reg; 352 bus->adapter.algo_data = algo; 353 algo->setsda = set_data; 354 algo->setscl = set_clock; 355 algo->getsda = get_data; 356 algo->getscl = get_clock; 357 algo->pre_xfer = intel_gpio_pre_xfer; 358 algo->post_xfer = intel_gpio_post_xfer; 359 algo->udelay = I2C_RISEFALL_TIME; 360 algo->timeout = usecs_to_jiffies(2200); 361 algo->data = bus; 362 } 363 364 static bool has_gmbus_irq(struct intel_display *display) 365 { 366 struct drm_i915_private *i915 = to_i915(display->drm); 367 /* 368 * encoder->shutdown() may want to use GMBUS 369 * after irqs have already been disabled. 370 */ 371 return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915); 372 } 373 374 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) 375 { 376 DEFINE_WAIT(wait); 377 u32 gmbus2; 378 int ret; 379 380 /* Important: The hw handles only the first bit, so set only one! Since 381 * we also need to check for NAKs besides the hw ready/idle signal, we 382 * need to wake up periodically and check that ourselves. 383 */ 384 if (!has_gmbus_irq(display)) 385 irq_en = 0; 386 387 add_wait_queue(&display->gmbus.wait_queue, &wait); 388 intel_de_write_fw(display, GMBUS4(display), irq_en); 389 390 status |= GMBUS_SATOER; 391 ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, 392 2); 393 if (ret) 394 ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, 395 50); 396 397 intel_de_write_fw(display, GMBUS4(display), 0); 398 remove_wait_queue(&display->gmbus.wait_queue, &wait); 399 400 if (gmbus2 & GMBUS_SATOER) 401 return -ENXIO; 402 403 return ret; 404 } 405 406 static int 407 gmbus_wait_idle(struct intel_display *display) 408 { 409 DEFINE_WAIT(wait); 410 u32 irq_enable; 411 int ret; 412 413 /* Important: The hw handles only the first bit, so set only one! */ 414 irq_enable = 0; 415 if (has_gmbus_irq(display)) 416 irq_enable = GMBUS_IDLE_EN; 417 418 add_wait_queue(&display->gmbus.wait_queue, &wait); 419 intel_de_write_fw(display, GMBUS4(display), irq_enable); 420 421 ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10); 422 423 intel_de_write_fw(display, GMBUS4(display), 0); 424 remove_wait_queue(&display->gmbus.wait_queue, &wait); 425 426 return ret; 427 } 428 429 static unsigned int gmbus_max_xfer_size(struct intel_display *display) 430 { 431 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 432 GMBUS_BYTE_COUNT_MAX; 433 } 434 435 static int 436 gmbus_xfer_read_chunk(struct intel_display *display, 437 unsigned short addr, u8 *buf, unsigned int len, 438 u32 gmbus0_reg, u32 gmbus1_index) 439 { 440 unsigned int size = len; 441 bool burst_read = len > gmbus_max_xfer_size(display); 442 bool extra_byte_added = false; 443 444 if (burst_read) { 445 /* 446 * As per HW Spec, for 512Bytes need to read extra Byte and 447 * Ignore the extra byte read. 448 */ 449 if (len == 512) { 450 extra_byte_added = true; 451 len++; 452 } 453 size = len % 256 + 256; 454 intel_de_write_fw(display, GMBUS0(display), 455 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 456 } 457 458 intel_de_write_fw(display, GMBUS1(display), 459 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 460 while (len) { 461 int ret; 462 u32 val, loop = 0; 463 464 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 465 if (ret) 466 return ret; 467 468 val = intel_de_read_fw(display, GMBUS3(display)); 469 do { 470 if (extra_byte_added && len == 1) 471 break; 472 473 *buf++ = val & 0xff; 474 val >>= 8; 475 } while (--len && ++loop < 4); 476 477 if (burst_read && len == size - 4) 478 /* Reset the override bit */ 479 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); 480 } 481 482 return 0; 483 } 484 485 /* 486 * HW spec says that 512Bytes in Burst read need special treatment. 487 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 488 * an I2C target, which supports such a lengthy burst read too for experiments. 489 * 490 * So until things get clarified on HW support, to avoid the burst read length 491 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 492 */ 493 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 494 495 static int 496 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 497 u32 gmbus0_reg, u32 gmbus1_index) 498 { 499 u8 *buf = msg->buf; 500 unsigned int rx_size = msg->len; 501 unsigned int len; 502 int ret; 503 504 do { 505 if (HAS_GMBUS_BURST_READ(display)) 506 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 507 else 508 len = min(rx_size, gmbus_max_xfer_size(display)); 509 510 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, 511 gmbus0_reg, gmbus1_index); 512 if (ret) 513 return ret; 514 515 rx_size -= len; 516 buf += len; 517 } while (rx_size != 0); 518 519 return 0; 520 } 521 522 static int 523 gmbus_xfer_write_chunk(struct intel_display *display, 524 unsigned short addr, u8 *buf, unsigned int len, 525 u32 gmbus1_index) 526 { 527 unsigned int chunk_size = len; 528 u32 val, loop; 529 530 val = loop = 0; 531 while (len && loop < 4) { 532 val |= *buf++ << (8 * loop++); 533 len -= 1; 534 } 535 536 intel_de_write_fw(display, GMBUS3(display), val); 537 intel_de_write_fw(display, GMBUS1(display), 538 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 539 while (len) { 540 int ret; 541 542 val = loop = 0; 543 do { 544 val |= *buf++ << (8 * loop); 545 } while (--len && ++loop < 4); 546 547 intel_de_write_fw(display, GMBUS3(display), val); 548 549 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 550 if (ret) 551 return ret; 552 } 553 554 return 0; 555 } 556 557 static int 558 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, 559 u32 gmbus1_index) 560 { 561 u8 *buf = msg->buf; 562 unsigned int tx_size = msg->len; 563 unsigned int len; 564 int ret; 565 566 do { 567 len = min(tx_size, gmbus_max_xfer_size(display)); 568 569 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, 570 gmbus1_index); 571 if (ret) 572 return ret; 573 574 buf += len; 575 tx_size -= len; 576 } while (tx_size != 0); 577 578 return 0; 579 } 580 581 /* 582 * The gmbus controller can combine a 1 or 2 byte write with another read/write 583 * that immediately follows it by using an "INDEX" cycle. 584 */ 585 static bool 586 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 587 { 588 return (i + 1 < num && 589 msgs[i].addr == msgs[i + 1].addr && 590 !(msgs[i].flags & I2C_M_RD) && 591 (msgs[i].len == 1 || msgs[i].len == 2) && 592 msgs[i + 1].len > 0); 593 } 594 595 static int 596 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, 597 u32 gmbus0_reg) 598 { 599 u32 gmbus1_index = 0; 600 u32 gmbus5 = 0; 601 int ret; 602 603 if (msgs[0].len == 2) 604 gmbus5 = GMBUS_2BYTE_INDEX_EN | 605 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 606 if (msgs[0].len == 1) 607 gmbus1_index = GMBUS_CYCLE_INDEX | 608 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 609 610 /* GMBUS5 holds 16-bit index */ 611 if (gmbus5) 612 intel_de_write_fw(display, GMBUS5(display), gmbus5); 613 614 if (msgs[1].flags & I2C_M_RD) 615 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, 616 gmbus1_index); 617 else 618 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); 619 620 /* Clear GMBUS5 after each index transfer */ 621 if (gmbus5) 622 intel_de_write_fw(display, GMBUS5(display), 0); 623 624 return ret; 625 } 626 627 static int 628 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 629 u32 gmbus0_source) 630 { 631 struct intel_gmbus *bus = to_intel_gmbus(adapter); 632 struct intel_display *display = bus->display; 633 struct drm_i915_private *i915 = to_i915(display->drm); 634 int i = 0, inc, try = 0; 635 int ret = 0; 636 637 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 638 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 639 bxt_gmbus_clock_gating(display, false); 640 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 641 pch_gmbus_clock_gating(display, false); 642 643 retry: 644 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); 645 646 for (; i < num; i += inc) { 647 inc = 1; 648 if (gmbus_is_index_xfer(msgs, i, num)) { 649 ret = gmbus_index_xfer(display, &msgs[i], 650 gmbus0_source | bus->reg0); 651 inc = 2; /* an index transmission is two msgs */ 652 } else if (msgs[i].flags & I2C_M_RD) { 653 ret = gmbus_xfer_read(display, &msgs[i], 654 gmbus0_source | bus->reg0, 0); 655 } else { 656 ret = gmbus_xfer_write(display, &msgs[i], 0); 657 } 658 659 if (!ret) 660 ret = gmbus_wait(display, 661 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 662 if (ret == -ETIMEDOUT) 663 goto timeout; 664 else if (ret) 665 goto clear_err; 666 } 667 668 /* Generate a STOP condition on the bus. Note that gmbus can't generata 669 * a STOP on the very first cycle. To simplify the code we 670 * unconditionally generate the STOP condition with an additional gmbus 671 * cycle. */ 672 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 673 674 /* Mark the GMBUS interface as disabled after waiting for idle. 675 * We will re-enable it at the start of the next xfer, 676 * till then let it sleep. 677 */ 678 if (gmbus_wait_idle(display)) { 679 drm_dbg_kms(display->drm, 680 "GMBUS [%s] timed out waiting for idle\n", 681 adapter->name); 682 ret = -ETIMEDOUT; 683 } 684 intel_de_write_fw(display, GMBUS0(display), 0); 685 ret = ret ?: i; 686 goto out; 687 688 clear_err: 689 /* 690 * Wait for bus to IDLE before clearing NAK. 691 * If we clear the NAK while bus is still active, then it will stay 692 * active and the next transaction may fail. 693 * 694 * If no ACK is received during the address phase of a transaction, the 695 * adapter must report -ENXIO. It is not clear what to return if no ACK 696 * is received at other times. But we have to be careful to not return 697 * spurious -ENXIO because that will prevent i2c and drm edid functions 698 * from retrying. So return -ENXIO only when gmbus properly quiescents - 699 * timing out seems to happen when there _is_ a ddc chip present, but 700 * it's slow responding and only answers on the 2nd retry. 701 */ 702 ret = -ENXIO; 703 if (gmbus_wait_idle(display)) { 704 drm_dbg_kms(display->drm, 705 "GMBUS [%s] timed out after NAK\n", 706 adapter->name); 707 ret = -ETIMEDOUT; 708 } 709 710 /* Toggle the Software Clear Interrupt bit. This has the effect 711 * of resetting the GMBUS controller and so clearing the 712 * BUS_ERROR raised by the target's NAK. 713 */ 714 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); 715 intel_de_write_fw(display, GMBUS1(display), 0); 716 intel_de_write_fw(display, GMBUS0(display), 0); 717 718 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 719 adapter->name, msgs[i].addr, 720 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 721 722 /* 723 * Passive adapters sometimes NAK the first probe. Retry the first 724 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 725 * has retries internally. See also the retry loop in 726 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 727 */ 728 if (ret == -ENXIO && i == 0 && try++ == 0) { 729 drm_dbg_kms(display->drm, 730 "GMBUS [%s] NAK on first message, retry\n", 731 adapter->name); 732 goto retry; 733 } 734 735 goto out; 736 737 timeout: 738 drm_dbg_kms(display->drm, 739 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 740 bus->adapter.name, bus->reg0 & 0xff); 741 intel_de_write_fw(display, GMBUS0(display), 0); 742 743 /* 744 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 745 * instead. Use EAGAIN to have i2c core retry. 746 */ 747 ret = -EAGAIN; 748 749 out: 750 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 751 if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) 752 bxt_gmbus_clock_gating(display, true); 753 else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915)) 754 pch_gmbus_clock_gating(display, true); 755 756 return ret; 757 } 758 759 static int 760 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 761 { 762 struct intel_gmbus *bus = to_intel_gmbus(adapter); 763 struct intel_display *display = bus->display; 764 struct drm_i915_private *i915 = to_i915(display->drm); 765 intel_wakeref_t wakeref; 766 int ret; 767 768 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 769 770 if (bus->force_bit) { 771 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 772 if (ret < 0) 773 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 774 } else { 775 ret = do_gmbus_xfer(adapter, msgs, num, 0); 776 if (ret == -EAGAIN) 777 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 778 } 779 780 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 781 782 return ret; 783 } 784 785 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 786 { 787 struct intel_gmbus *bus = to_intel_gmbus(adapter); 788 struct intel_display *display = bus->display; 789 struct drm_i915_private *i915 = to_i915(display->drm); 790 u8 cmd = DRM_HDCP_DDC_AKSV; 791 u8 buf[DRM_HDCP_KSV_LEN] = {}; 792 struct i2c_msg msgs[] = { 793 { 794 .addr = DRM_HDCP_DDC_ADDR, 795 .flags = 0, 796 .len = sizeof(cmd), 797 .buf = &cmd, 798 }, 799 { 800 .addr = DRM_HDCP_DDC_ADDR, 801 .flags = 0, 802 .len = sizeof(buf), 803 .buf = buf, 804 } 805 }; 806 intel_wakeref_t wakeref; 807 int ret; 808 809 wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS); 810 mutex_lock(&display->gmbus.mutex); 811 812 /* 813 * In order to output Aksv to the receiver, use an indexed write to 814 * pass the i2c command, and tell GMBUS to use the HW-provided value 815 * instead of sourcing GMBUS3 for the data. 816 */ 817 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 818 819 mutex_unlock(&display->gmbus.mutex); 820 intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref); 821 822 return ret; 823 } 824 825 static u32 gmbus_func(struct i2c_adapter *adapter) 826 { 827 return i2c_bit_algo.functionality(adapter) & 828 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 829 /* I2C_FUNC_10BIT_ADDR | */ 830 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 831 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 832 } 833 834 static const struct i2c_algorithm gmbus_algorithm = { 835 .master_xfer = gmbus_xfer, 836 .functionality = gmbus_func 837 }; 838 839 static void gmbus_lock_bus(struct i2c_adapter *adapter, 840 unsigned int flags) 841 { 842 struct intel_gmbus *bus = to_intel_gmbus(adapter); 843 struct intel_display *display = bus->display; 844 845 mutex_lock(&display->gmbus.mutex); 846 } 847 848 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 849 unsigned int flags) 850 { 851 struct intel_gmbus *bus = to_intel_gmbus(adapter); 852 struct intel_display *display = bus->display; 853 854 return mutex_trylock(&display->gmbus.mutex); 855 } 856 857 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 858 unsigned int flags) 859 { 860 struct intel_gmbus *bus = to_intel_gmbus(adapter); 861 struct intel_display *display = bus->display; 862 863 mutex_unlock(&display->gmbus.mutex); 864 } 865 866 static const struct i2c_lock_operations gmbus_lock_ops = { 867 .lock_bus = gmbus_lock_bus, 868 .trylock_bus = gmbus_trylock_bus, 869 .unlock_bus = gmbus_unlock_bus, 870 }; 871 872 /** 873 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 874 * @display: display device 875 */ 876 int intel_gmbus_setup(struct intel_display *display) 877 { 878 struct drm_i915_private *i915 = to_i915(display->drm); 879 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 880 unsigned int pin; 881 int ret; 882 883 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 884 display->gmbus.mmio_base = VLV_DISPLAY_BASE; 885 else if (!HAS_GMCH(display)) 886 /* 887 * Broxton uses the same PCH offsets for South Display Engine, 888 * even though it doesn't have a PCH. 889 */ 890 display->gmbus.mmio_base = PCH_DISPLAY_BASE; 891 892 mutex_init(&display->gmbus.mutex); 893 init_waitqueue_head(&display->gmbus.wait_queue); 894 895 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 896 const struct gmbus_pin *gmbus_pin; 897 struct intel_gmbus *bus; 898 899 gmbus_pin = get_gmbus_pin(display, pin); 900 if (!gmbus_pin) 901 continue; 902 903 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 904 if (!bus) { 905 ret = -ENOMEM; 906 goto err; 907 } 908 909 bus->adapter.owner = THIS_MODULE; 910 snprintf(bus->adapter.name, 911 sizeof(bus->adapter.name), 912 "i915 gmbus %s", gmbus_pin->name); 913 914 bus->adapter.dev.parent = &pdev->dev; 915 bus->display = display; 916 917 bus->adapter.algo = &gmbus_algorithm; 918 bus->adapter.lock_ops = &gmbus_lock_ops; 919 920 /* 921 * We wish to retry with bit banging 922 * after a timed out GMBUS attempt. 923 */ 924 bus->adapter.retries = 1; 925 926 /* By default use a conservative clock rate */ 927 bus->reg0 = pin | GMBUS_RATE_100KHZ; 928 929 /* gmbus seems to be broken on i830 */ 930 if (IS_I830(i915)) 931 bus->force_bit = 1; 932 933 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); 934 935 ret = i2c_add_adapter(&bus->adapter); 936 if (ret) { 937 kfree(bus); 938 goto err; 939 } 940 941 display->gmbus.bus[pin] = bus; 942 } 943 944 intel_gmbus_reset(display); 945 946 return 0; 947 948 err: 949 intel_gmbus_teardown(display); 950 951 return ret; 952 } 953 954 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, 955 unsigned int pin) 956 { 957 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || 958 !display->gmbus.bus[pin])) 959 return NULL; 960 961 return &display->gmbus.bus[pin]->adapter; 962 } 963 964 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 965 { 966 struct intel_gmbus *bus = to_intel_gmbus(adapter); 967 struct intel_display *display = bus->display; 968 969 mutex_lock(&display->gmbus.mutex); 970 971 bus->force_bit += force_bit ? 1 : -1; 972 drm_dbg_kms(display->drm, 973 "%sabling bit-banging on %s. force bit now %d\n", 974 force_bit ? "en" : "dis", adapter->name, 975 bus->force_bit); 976 977 mutex_unlock(&display->gmbus.mutex); 978 } 979 980 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 981 { 982 struct intel_gmbus *bus = to_intel_gmbus(adapter); 983 984 return bus->force_bit; 985 } 986 987 void intel_gmbus_teardown(struct intel_display *display) 988 { 989 unsigned int pin; 990 991 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 992 struct intel_gmbus *bus; 993 994 bus = display->gmbus.bus[pin]; 995 if (!bus) 996 continue; 997 998 i2c_del_adapter(&bus->adapter); 999 1000 kfree(bus); 1001 display->gmbus.bus[pin] = NULL; 1002 } 1003 } 1004 1005 void intel_gmbus_irq_handler(struct intel_display *display) 1006 { 1007 wake_up_all(&display->gmbus.wait_queue); 1008 } 1009