1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 #include <linux/iopoll.h> 34 35 #include <drm/drm_print.h> 36 #include <drm/display/drm_hdcp_helper.h> 37 38 #include "intel_de.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_types.h" 41 #include "intel_display_wa.h" 42 #include "intel_gmbus.h" 43 #include "intel_gmbus_regs.h" 44 #include "intel_parent.h" 45 46 struct intel_gmbus { 47 struct i2c_adapter adapter; 48 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 49 u32 force_bit; 50 u32 reg0; 51 i915_reg_t gpio_reg; 52 struct i2c_algo_bit_data bit_algo; 53 struct intel_display *display; 54 }; 55 56 enum gmbus_gpio { 57 GPIOA, 58 GPIOB, 59 GPIOC, 60 GPIOD, 61 GPIOE, 62 GPIOF, 63 GPIOG, 64 GPIOH, 65 __GPIOI_UNUSED, 66 GPIOJ, 67 GPIOK, 68 GPIOL, 69 GPIOM, 70 GPION, 71 GPIOO, 72 }; 73 74 struct gmbus_pin { 75 const char *name; 76 enum gmbus_gpio gpio; 77 }; 78 79 /* Map gmbus pin pairs to names and registers. */ 80 static const struct gmbus_pin gmbus_pins[] = { 81 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 82 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 83 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 84 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 85 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 86 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 87 }; 88 89 static const struct gmbus_pin gmbus_pins_bdw[] = { 90 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 91 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 92 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 93 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 94 }; 95 96 static const struct gmbus_pin gmbus_pins_skl[] = { 97 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 98 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 99 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 100 }; 101 102 static const struct gmbus_pin gmbus_pins_bxt[] = { 103 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 104 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 105 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 106 }; 107 108 static const struct gmbus_pin gmbus_pins_cnp[] = { 109 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 110 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 111 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 112 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 113 }; 114 115 static const struct gmbus_pin gmbus_pins_icp[] = { 116 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 117 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 118 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 119 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 120 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 121 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 122 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 123 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 124 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 125 }; 126 127 static const struct gmbus_pin gmbus_pins_dg1[] = { 128 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 129 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 130 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 131 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 132 }; 133 134 static const struct gmbus_pin gmbus_pins_dg2[] = { 135 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 136 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 137 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 138 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 139 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 140 }; 141 142 static const struct gmbus_pin gmbus_pins_mtp[] = { 143 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 144 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 145 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 146 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 147 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 148 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 149 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 150 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 151 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 152 }; 153 154 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, 155 unsigned int pin) 156 { 157 const struct gmbus_pin *pins; 158 size_t size; 159 160 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { 161 pins = gmbus_pins_mtp; 162 size = ARRAY_SIZE(gmbus_pins_mtp); 163 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { 164 pins = gmbus_pins_dg2; 165 size = ARRAY_SIZE(gmbus_pins_dg2); 166 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { 167 pins = gmbus_pins_dg1; 168 size = ARRAY_SIZE(gmbus_pins_dg1); 169 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { 170 pins = gmbus_pins_icp; 171 size = ARRAY_SIZE(gmbus_pins_icp); 172 } else if (HAS_PCH_CNP(display)) { 173 pins = gmbus_pins_cnp; 174 size = ARRAY_SIZE(gmbus_pins_cnp); 175 } else if (display->platform.geminilake || display->platform.broxton) { 176 pins = gmbus_pins_bxt; 177 size = ARRAY_SIZE(gmbus_pins_bxt); 178 } else if (DISPLAY_VER(display) == 9) { 179 pins = gmbus_pins_skl; 180 size = ARRAY_SIZE(gmbus_pins_skl); 181 } else if (display->platform.broadwell) { 182 pins = gmbus_pins_bdw; 183 size = ARRAY_SIZE(gmbus_pins_bdw); 184 } else { 185 pins = gmbus_pins; 186 size = ARRAY_SIZE(gmbus_pins); 187 } 188 189 if (pin >= size || !pins[pin].name) 190 return NULL; 191 192 return &pins[pin]; 193 } 194 195 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) 196 { 197 return get_gmbus_pin(display, pin); 198 } 199 200 /* Intel GPIO access functions */ 201 202 #define I2C_RISEFALL_TIME 10 203 204 static inline struct intel_gmbus * 205 to_intel_gmbus(struct i2c_adapter *i2c) 206 { 207 return container_of(i2c, struct intel_gmbus, adapter); 208 } 209 210 void 211 intel_gmbus_reset(struct intel_display *display) 212 { 213 intel_de_write(display, GMBUS0(display), 0); 214 intel_de_write(display, GMBUS4(display), 0); 215 } 216 217 static void pnv_gmbus_clock_gating(struct intel_display *display, 218 bool enable) 219 { 220 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 221 intel_de_rmw(display, DSPCLK_GATE_D, 222 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 223 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 224 } 225 226 static void pch_gmbus_clock_gating(struct intel_display *display, 227 bool enable) 228 { 229 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 230 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 231 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 232 } 233 234 static void bxt_gmbus_clock_gating(struct intel_display *display, 235 bool enable) 236 { 237 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 238 !enable ? BXT_GMBUS_GATING_DIS : 0); 239 } 240 241 static u32 get_reserved(struct intel_gmbus *bus) 242 { 243 struct intel_display *display = bus->display; 244 u32 preserve_bits = 0; 245 246 if (display->platform.i830 || display->platform.i845g) 247 return 0; 248 249 /* On most chips, these bits must be preserved in software. */ 250 preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE; 251 252 /* Wa_16025573575: the masks bits need to be preserved through out */ 253 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 254 preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 255 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 256 257 return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits; 258 } 259 260 static int get_clock(void *data) 261 { 262 struct intel_gmbus *bus = data; 263 struct intel_display *display = bus->display; 264 u32 reserved = get_reserved(bus); 265 266 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 267 intel_de_write_notrace(display, bus->gpio_reg, reserved); 268 269 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 270 } 271 272 static int get_data(void *data) 273 { 274 struct intel_gmbus *bus = data; 275 struct intel_display *display = bus->display; 276 u32 reserved = get_reserved(bus); 277 278 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 279 intel_de_write_notrace(display, bus->gpio_reg, reserved); 280 281 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 282 } 283 284 static void set_clock(void *data, int state_high) 285 { 286 struct intel_gmbus *bus = data; 287 struct intel_display *display = bus->display; 288 u32 reserved = get_reserved(bus); 289 u32 clock_bits; 290 291 if (state_high) 292 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 293 else 294 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 295 GPIO_CLOCK_VAL_MASK; 296 297 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); 298 intel_de_posting_read(display, bus->gpio_reg); 299 } 300 301 static void set_data(void *data, int state_high) 302 { 303 struct intel_gmbus *bus = data; 304 struct intel_display *display = bus->display; 305 u32 reserved = get_reserved(bus); 306 u32 data_bits; 307 308 if (state_high) 309 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 310 else 311 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 312 GPIO_DATA_VAL_MASK; 313 314 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); 315 intel_de_posting_read(display, bus->gpio_reg); 316 } 317 318 static void 319 ptl_handle_mask_bits(struct intel_gmbus *bus, bool set) 320 { 321 struct intel_display *display = bus->display; 322 u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg); 323 u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 324 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 325 if (set) 326 reg_val |= mask_bits; 327 else 328 reg_val &= ~mask_bits; 329 330 intel_de_write_notrace(display, bus->gpio_reg, reg_val); 331 intel_de_posting_read(display, bus->gpio_reg); 332 } 333 334 static int 335 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 336 { 337 struct intel_gmbus *bus = to_intel_gmbus(adapter); 338 struct intel_display *display = bus->display; 339 340 intel_gmbus_reset(display); 341 342 if (display->platform.pineview) 343 pnv_gmbus_clock_gating(display, false); 344 345 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 346 ptl_handle_mask_bits(bus, true); 347 348 set_data(bus, 1); 349 set_clock(bus, 1); 350 udelay(I2C_RISEFALL_TIME); 351 return 0; 352 } 353 354 static void 355 intel_gpio_post_xfer(struct i2c_adapter *adapter) 356 { 357 struct intel_gmbus *bus = to_intel_gmbus(adapter); 358 struct intel_display *display = bus->display; 359 360 set_data(bus, 1); 361 set_clock(bus, 1); 362 363 if (display->platform.pineview) 364 pnv_gmbus_clock_gating(display, true); 365 366 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 367 ptl_handle_mask_bits(bus, false); 368 } 369 370 static void 371 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 372 { 373 struct i2c_algo_bit_data *algo; 374 375 algo = &bus->bit_algo; 376 377 bus->gpio_reg = gpio_reg; 378 bus->adapter.algo_data = algo; 379 algo->setsda = set_data; 380 algo->setscl = set_clock; 381 algo->getsda = get_data; 382 algo->getscl = get_clock; 383 algo->pre_xfer = intel_gpio_pre_xfer; 384 algo->post_xfer = intel_gpio_post_xfer; 385 algo->udelay = I2C_RISEFALL_TIME; 386 algo->timeout = usecs_to_jiffies(2200); 387 algo->data = bus; 388 } 389 390 static bool has_gmbus_irq(struct intel_display *display) 391 { 392 /* 393 * encoder->shutdown() may want to use GMBUS 394 * after irqs have already been disabled. 395 */ 396 return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display); 397 } 398 399 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) 400 { 401 DEFINE_WAIT(wait); 402 u32 gmbus2; 403 int ret; 404 405 /* Important: The hw handles only the first bit, so set only one! Since 406 * we also need to check for NAKs besides the hw ready/idle signal, we 407 * need to wake up periodically and check that ourselves. 408 */ 409 if (!has_gmbus_irq(display)) 410 irq_en = 0; 411 412 add_wait_queue(&display->gmbus.wait_queue, &wait); 413 intel_de_write_fw(display, GMBUS4(display), irq_en); 414 415 status |= GMBUS_SATOER; 416 417 ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 418 gmbus2 & status, 419 0, 2, false); 420 if (ret) 421 ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 422 gmbus2 & status, 423 500, 50 * 1000, false); 424 425 intel_de_write_fw(display, GMBUS4(display), 0); 426 remove_wait_queue(&display->gmbus.wait_queue, &wait); 427 428 if (gmbus2 & GMBUS_SATOER) 429 return -ENXIO; 430 431 return ret; 432 } 433 434 static int 435 gmbus_wait_idle(struct intel_display *display) 436 { 437 DEFINE_WAIT(wait); 438 u32 irq_enable; 439 int ret; 440 441 /* Important: The hw handles only the first bit, so set only one! */ 442 irq_enable = 0; 443 if (has_gmbus_irq(display)) 444 irq_enable = GMBUS_IDLE_EN; 445 446 add_wait_queue(&display->gmbus.wait_queue, &wait); 447 intel_de_write_fw(display, GMBUS4(display), irq_enable); 448 449 ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL); 450 451 intel_de_write_fw(display, GMBUS4(display), 0); 452 remove_wait_queue(&display->gmbus.wait_queue, &wait); 453 454 return ret; 455 } 456 457 static unsigned int gmbus_max_xfer_size(struct intel_display *display) 458 { 459 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 460 GMBUS_BYTE_COUNT_MAX; 461 } 462 463 static int 464 gmbus_xfer_read_chunk(struct intel_display *display, 465 unsigned short addr, u8 *buf, unsigned int len, 466 u32 gmbus0_reg, u32 gmbus1_index) 467 { 468 unsigned int size = len; 469 bool burst_read = len > gmbus_max_xfer_size(display); 470 bool extra_byte_added = false; 471 472 if (burst_read) { 473 /* 474 * As per HW Spec, for 512Bytes need to read extra Byte and 475 * Ignore the extra byte read. 476 */ 477 if (len == 512) { 478 extra_byte_added = true; 479 len++; 480 } 481 size = len % 256 + 256; 482 intel_de_write_fw(display, GMBUS0(display), 483 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 484 } 485 486 intel_de_write_fw(display, GMBUS1(display), 487 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 488 while (len) { 489 int ret; 490 u32 val, loop = 0; 491 492 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 493 if (ret) 494 return ret; 495 496 val = intel_de_read_fw(display, GMBUS3(display)); 497 do { 498 if (extra_byte_added && len == 1) 499 break; 500 501 *buf++ = val & 0xff; 502 val >>= 8; 503 } while (--len && ++loop < 4); 504 505 if (burst_read && len == size - 4) 506 /* Reset the override bit */ 507 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); 508 } 509 510 return 0; 511 } 512 513 /* 514 * HW spec says that 512Bytes in Burst read need special treatment. 515 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 516 * an I2C target, which supports such a lengthy burst read too for experiments. 517 * 518 * So until things get clarified on HW support, to avoid the burst read length 519 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 520 */ 521 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 522 523 static int 524 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 525 u32 gmbus0_reg, u32 gmbus1_index) 526 { 527 u8 *buf = msg->buf; 528 unsigned int rx_size = msg->len; 529 unsigned int len; 530 int ret; 531 532 do { 533 if (HAS_GMBUS_BURST_READ(display)) 534 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 535 else 536 len = min(rx_size, gmbus_max_xfer_size(display)); 537 538 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, 539 gmbus0_reg, gmbus1_index); 540 if (ret) 541 return ret; 542 543 rx_size -= len; 544 buf += len; 545 } while (rx_size != 0); 546 547 return 0; 548 } 549 550 static int 551 gmbus_xfer_write_chunk(struct intel_display *display, 552 unsigned short addr, u8 *buf, unsigned int len, 553 u32 gmbus1_index) 554 { 555 unsigned int chunk_size = len; 556 u32 val, loop; 557 558 val = loop = 0; 559 while (len && loop < 4) { 560 val |= *buf++ << (8 * loop++); 561 len -= 1; 562 } 563 564 intel_de_write_fw(display, GMBUS3(display), val); 565 intel_de_write_fw(display, GMBUS1(display), 566 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 567 while (len) { 568 int ret; 569 570 val = loop = 0; 571 do { 572 val |= *buf++ << (8 * loop); 573 } while (--len && ++loop < 4); 574 575 intel_de_write_fw(display, GMBUS3(display), val); 576 577 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 578 if (ret) 579 return ret; 580 } 581 582 return 0; 583 } 584 585 static int 586 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, 587 u32 gmbus1_index) 588 { 589 u8 *buf = msg->buf; 590 unsigned int tx_size = msg->len; 591 unsigned int len; 592 int ret; 593 594 do { 595 len = min(tx_size, gmbus_max_xfer_size(display)); 596 597 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, 598 gmbus1_index); 599 if (ret) 600 return ret; 601 602 buf += len; 603 tx_size -= len; 604 } while (tx_size != 0); 605 606 return 0; 607 } 608 609 /* 610 * The gmbus controller can combine a 1 or 2 byte write with another read/write 611 * that immediately follows it by using an "INDEX" cycle. 612 */ 613 static bool 614 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 615 { 616 return (i + 1 < num && 617 msgs[i].addr == msgs[i + 1].addr && 618 !(msgs[i].flags & I2C_M_RD) && 619 (msgs[i].len == 1 || msgs[i].len == 2) && 620 msgs[i + 1].len > 0); 621 } 622 623 static int 624 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, 625 u32 gmbus0_reg) 626 { 627 u32 gmbus1_index = 0; 628 u32 gmbus5 = 0; 629 int ret; 630 631 if (msgs[0].len == 2) 632 gmbus5 = GMBUS_2BYTE_INDEX_EN | 633 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 634 if (msgs[0].len == 1) 635 gmbus1_index = GMBUS_CYCLE_INDEX | 636 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 637 638 /* GMBUS5 holds 16-bit index */ 639 if (gmbus5) 640 intel_de_write_fw(display, GMBUS5(display), gmbus5); 641 642 if (msgs[1].flags & I2C_M_RD) 643 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, 644 gmbus1_index); 645 else 646 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); 647 648 /* Clear GMBUS5 after each index transfer */ 649 if (gmbus5) 650 intel_de_write_fw(display, GMBUS5(display), 0); 651 652 return ret; 653 } 654 655 static int 656 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 657 u32 gmbus0_source) 658 { 659 struct intel_gmbus *bus = to_intel_gmbus(adapter); 660 struct intel_display *display = bus->display; 661 int i = 0, inc, try = 0; 662 int ret = 0; 663 664 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 665 if (display->platform.geminilake || display->platform.broxton) 666 bxt_gmbus_clock_gating(display, false); 667 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 668 pch_gmbus_clock_gating(display, false); 669 670 retry: 671 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); 672 673 for (; i < num; i += inc) { 674 inc = 1; 675 if (gmbus_is_index_xfer(msgs, i, num)) { 676 ret = gmbus_index_xfer(display, &msgs[i], 677 gmbus0_source | bus->reg0); 678 inc = 2; /* an index transmission is two msgs */ 679 } else if (msgs[i].flags & I2C_M_RD) { 680 ret = gmbus_xfer_read(display, &msgs[i], 681 gmbus0_source | bus->reg0, 0); 682 } else { 683 ret = gmbus_xfer_write(display, &msgs[i], 0); 684 } 685 686 if (!ret) 687 ret = gmbus_wait(display, 688 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 689 if (ret == -ETIMEDOUT) 690 goto timeout; 691 else if (ret) 692 goto clear_err; 693 } 694 695 /* Generate a STOP condition on the bus. Note that gmbus can't generata 696 * a STOP on the very first cycle. To simplify the code we 697 * unconditionally generate the STOP condition with an additional gmbus 698 * cycle. */ 699 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 700 701 /* Mark the GMBUS interface as disabled after waiting for idle. 702 * We will re-enable it at the start of the next xfer, 703 * till then let it sleep. 704 */ 705 if (gmbus_wait_idle(display)) { 706 drm_dbg_kms(display->drm, 707 "GMBUS [%s] timed out waiting for idle\n", 708 adapter->name); 709 ret = -ETIMEDOUT; 710 } 711 intel_de_write_fw(display, GMBUS0(display), 0); 712 ret = ret ?: i; 713 goto out; 714 715 clear_err: 716 /* 717 * Wait for bus to IDLE before clearing NAK. 718 * If we clear the NAK while bus is still active, then it will stay 719 * active and the next transaction may fail. 720 * 721 * If no ACK is received during the address phase of a transaction, the 722 * adapter must report -ENXIO. It is not clear what to return if no ACK 723 * is received at other times. But we have to be careful to not return 724 * spurious -ENXIO because that will prevent i2c and drm edid functions 725 * from retrying. So return -ENXIO only when gmbus properly quiescents - 726 * timing out seems to happen when there _is_ a ddc chip present, but 727 * it's slow responding and only answers on the 2nd retry. 728 */ 729 ret = -ENXIO; 730 if (gmbus_wait_idle(display)) { 731 drm_dbg_kms(display->drm, 732 "GMBUS [%s] timed out after NAK\n", 733 adapter->name); 734 ret = -ETIMEDOUT; 735 } 736 737 /* Toggle the Software Clear Interrupt bit. This has the effect 738 * of resetting the GMBUS controller and so clearing the 739 * BUS_ERROR raised by the target's NAK. 740 */ 741 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); 742 intel_de_write_fw(display, GMBUS1(display), 0); 743 intel_de_write_fw(display, GMBUS0(display), 0); 744 745 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 746 adapter->name, msgs[i].addr, 747 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 748 749 /* 750 * Passive adapters sometimes NAK the first probe. Retry the first 751 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 752 * has retries internally. See also the retry loop in 753 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 754 */ 755 if (ret == -ENXIO && i == 0 && try++ == 0) { 756 drm_dbg_kms(display->drm, 757 "GMBUS [%s] NAK on first message, retry\n", 758 adapter->name); 759 goto retry; 760 } 761 762 goto out; 763 764 timeout: 765 drm_dbg_kms(display->drm, 766 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 767 bus->adapter.name, bus->reg0 & 0xff); 768 intel_de_write_fw(display, GMBUS0(display), 0); 769 770 /* 771 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 772 * instead. Use EAGAIN to have i2c core retry. 773 */ 774 ret = -EAGAIN; 775 776 out: 777 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 778 if (display->platform.geminilake || display->platform.broxton) 779 bxt_gmbus_clock_gating(display, true); 780 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 781 pch_gmbus_clock_gating(display, true); 782 783 return ret; 784 } 785 786 static int 787 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 788 { 789 struct intel_gmbus *bus = to_intel_gmbus(adapter); 790 struct intel_display *display = bus->display; 791 struct ref_tracker *wakeref; 792 int ret; 793 794 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 795 796 if (bus->force_bit) { 797 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 798 if (ret < 0) 799 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 800 } else { 801 ret = do_gmbus_xfer(adapter, msgs, num, 0); 802 if (ret == -EAGAIN) 803 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 804 } 805 806 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 807 808 return ret; 809 } 810 811 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 812 { 813 struct intel_gmbus *bus = to_intel_gmbus(adapter); 814 struct intel_display *display = bus->display; 815 u8 cmd = DRM_HDCP_DDC_AKSV; 816 u8 buf[DRM_HDCP_KSV_LEN] = {}; 817 struct i2c_msg msgs[] = { 818 { 819 .addr = DRM_HDCP_DDC_ADDR, 820 .flags = 0, 821 .len = sizeof(cmd), 822 .buf = &cmd, 823 }, 824 { 825 .addr = DRM_HDCP_DDC_ADDR, 826 .flags = 0, 827 .len = sizeof(buf), 828 .buf = buf, 829 } 830 }; 831 struct ref_tracker *wakeref; 832 int ret; 833 834 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 835 mutex_lock(&display->gmbus.mutex); 836 837 /* 838 * In order to output Aksv to the receiver, use an indexed write to 839 * pass the i2c command, and tell GMBUS to use the HW-provided value 840 * instead of sourcing GMBUS3 for the data. 841 */ 842 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 843 844 mutex_unlock(&display->gmbus.mutex); 845 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 846 847 return ret; 848 } 849 850 static u32 gmbus_func(struct i2c_adapter *adapter) 851 { 852 return i2c_bit_algo.functionality(adapter) & 853 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 854 /* I2C_FUNC_10BIT_ADDR | */ 855 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 856 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 857 } 858 859 static const struct i2c_algorithm gmbus_algorithm = { 860 .master_xfer = gmbus_xfer, 861 .functionality = gmbus_func 862 }; 863 864 static void gmbus_lock_bus(struct i2c_adapter *adapter, 865 unsigned int flags) 866 { 867 struct intel_gmbus *bus = to_intel_gmbus(adapter); 868 struct intel_display *display = bus->display; 869 870 mutex_lock(&display->gmbus.mutex); 871 } 872 873 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 874 unsigned int flags) 875 { 876 struct intel_gmbus *bus = to_intel_gmbus(adapter); 877 struct intel_display *display = bus->display; 878 879 return mutex_trylock(&display->gmbus.mutex); 880 } 881 882 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 883 unsigned int flags) 884 { 885 struct intel_gmbus *bus = to_intel_gmbus(adapter); 886 struct intel_display *display = bus->display; 887 888 mutex_unlock(&display->gmbus.mutex); 889 } 890 891 static const struct i2c_lock_operations gmbus_lock_ops = { 892 .lock_bus = gmbus_lock_bus, 893 .trylock_bus = gmbus_trylock_bus, 894 .unlock_bus = gmbus_unlock_bus, 895 }; 896 897 /** 898 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 899 * @display: display device 900 */ 901 int intel_gmbus_setup(struct intel_display *display) 902 { 903 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 904 unsigned int pin; 905 int ret; 906 907 if (display->platform.valleyview || display->platform.cherryview) 908 display->gmbus.mmio_base = VLV_DISPLAY_BASE; 909 else if (!HAS_GMCH(display)) 910 /* 911 * Broxton uses the same PCH offsets for South Display Engine, 912 * even though it doesn't have a PCH. 913 */ 914 display->gmbus.mmio_base = PCH_DISPLAY_BASE; 915 916 mutex_init(&display->gmbus.mutex); 917 init_waitqueue_head(&display->gmbus.wait_queue); 918 919 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 920 const struct gmbus_pin *gmbus_pin; 921 struct intel_gmbus *bus; 922 923 gmbus_pin = get_gmbus_pin(display, pin); 924 if (!gmbus_pin) 925 continue; 926 927 bus = kzalloc_obj(*bus); 928 if (!bus) { 929 ret = -ENOMEM; 930 goto err; 931 } 932 933 bus->adapter.owner = THIS_MODULE; 934 snprintf(bus->adapter.name, 935 sizeof(bus->adapter.name), 936 "i915 gmbus %s", gmbus_pin->name); 937 938 bus->adapter.dev.parent = &pdev->dev; 939 bus->display = display; 940 941 bus->adapter.algo = &gmbus_algorithm; 942 bus->adapter.lock_ops = &gmbus_lock_ops; 943 944 /* 945 * We wish to retry with bit banging 946 * after a timed out GMBUS attempt. 947 */ 948 bus->adapter.retries = 1; 949 950 /* By default use a conservative clock rate */ 951 bus->reg0 = pin | GMBUS_RATE_100KHZ; 952 953 /* gmbus seems to be broken on i830 */ 954 if (display->platform.i830) 955 bus->force_bit = 1; 956 957 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); 958 959 ret = i2c_add_adapter(&bus->adapter); 960 if (ret) { 961 kfree(bus); 962 goto err; 963 } 964 965 display->gmbus.bus[pin] = bus; 966 } 967 968 intel_gmbus_reset(display); 969 970 return 0; 971 972 err: 973 intel_gmbus_teardown(display); 974 975 return ret; 976 } 977 978 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, 979 unsigned int pin) 980 { 981 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || 982 !display->gmbus.bus[pin])) 983 return NULL; 984 985 return &display->gmbus.bus[pin]->adapter; 986 } 987 988 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 989 { 990 struct intel_gmbus *bus = to_intel_gmbus(adapter); 991 struct intel_display *display = bus->display; 992 993 mutex_lock(&display->gmbus.mutex); 994 995 bus->force_bit += force_bit ? 1 : -1; 996 drm_dbg_kms(display->drm, 997 "%sabling bit-banging on %s. force bit now %d\n", 998 force_bit ? "en" : "dis", adapter->name, 999 bus->force_bit); 1000 1001 mutex_unlock(&display->gmbus.mutex); 1002 } 1003 1004 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1005 { 1006 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1007 1008 return bus->force_bit; 1009 } 1010 1011 void intel_gmbus_teardown(struct intel_display *display) 1012 { 1013 unsigned int pin; 1014 1015 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 1016 struct intel_gmbus *bus; 1017 1018 bus = display->gmbus.bus[pin]; 1019 if (!bus) 1020 continue; 1021 1022 i2c_del_adapter(&bus->adapter); 1023 1024 kfree(bus); 1025 display->gmbus.bus[pin] = NULL; 1026 } 1027 } 1028 1029 void intel_gmbus_irq_handler(struct intel_display *display) 1030 { 1031 wake_up_all(&display->gmbus.wait_queue); 1032 } 1033