1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/drm_hdcp.h> 35 36 #include "i915_drv.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_gmbus.h" 40 41 struct gmbus_pin { 42 const char *name; 43 enum i915_gpio gpio; 44 }; 45 46 /* Map gmbus pin pairs to names and registers. */ 47 static const struct gmbus_pin gmbus_pins[] = { 48 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 49 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 50 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 51 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 52 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 53 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 54 }; 55 56 static const struct gmbus_pin gmbus_pins_bdw[] = { 57 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 58 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 59 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 60 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 61 }; 62 63 static const struct gmbus_pin gmbus_pins_skl[] = { 64 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 65 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 66 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 67 }; 68 69 static const struct gmbus_pin gmbus_pins_bxt[] = { 70 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 71 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 72 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 73 }; 74 75 static const struct gmbus_pin gmbus_pins_cnp[] = { 76 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 77 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 78 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 79 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 80 }; 81 82 static const struct gmbus_pin gmbus_pins_icp[] = { 83 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 84 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 85 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 86 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 87 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 88 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 89 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 90 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 91 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 92 }; 93 94 static const struct gmbus_pin gmbus_pins_dg1[] = { 95 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 96 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 97 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 98 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 99 }; 100 101 /* pin is expected to be valid */ 102 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, 103 unsigned int pin) 104 { 105 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 106 return &gmbus_pins_dg1[pin]; 107 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 108 return &gmbus_pins_icp[pin]; 109 else if (HAS_PCH_CNP(dev_priv)) 110 return &gmbus_pins_cnp[pin]; 111 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 112 return &gmbus_pins_bxt[pin]; 113 else if (DISPLAY_VER(dev_priv) == 9) 114 return &gmbus_pins_skl[pin]; 115 else if (IS_BROADWELL(dev_priv)) 116 return &gmbus_pins_bdw[pin]; 117 else 118 return &gmbus_pins[pin]; 119 } 120 121 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, 122 unsigned int pin) 123 { 124 unsigned int size; 125 126 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) 127 size = ARRAY_SIZE(gmbus_pins_dg1); 128 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) 129 size = ARRAY_SIZE(gmbus_pins_icp); 130 else if (HAS_PCH_CNP(dev_priv)) 131 size = ARRAY_SIZE(gmbus_pins_cnp); 132 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 133 size = ARRAY_SIZE(gmbus_pins_bxt); 134 else if (DISPLAY_VER(dev_priv) == 9) 135 size = ARRAY_SIZE(gmbus_pins_skl); 136 else if (IS_BROADWELL(dev_priv)) 137 size = ARRAY_SIZE(gmbus_pins_bdw); 138 else 139 size = ARRAY_SIZE(gmbus_pins); 140 141 return pin < size && get_gmbus_pin(dev_priv, pin)->name; 142 } 143 144 /* Intel GPIO access functions */ 145 146 #define I2C_RISEFALL_TIME 10 147 148 static inline struct intel_gmbus * 149 to_intel_gmbus(struct i2c_adapter *i2c) 150 { 151 return container_of(i2c, struct intel_gmbus, adapter); 152 } 153 154 void 155 intel_gmbus_reset(struct drm_i915_private *dev_priv) 156 { 157 intel_de_write(dev_priv, GMBUS0, 0); 158 intel_de_write(dev_priv, GMBUS4, 0); 159 } 160 161 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv, 162 bool enable) 163 { 164 u32 val; 165 166 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 167 val = intel_de_read(dev_priv, DSPCLK_GATE_D); 168 if (!enable) 169 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 170 else 171 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE; 172 intel_de_write(dev_priv, DSPCLK_GATE_D, val); 173 } 174 175 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv, 176 bool enable) 177 { 178 u32 val; 179 180 val = intel_de_read(dev_priv, SOUTH_DSPCLK_GATE_D); 181 if (!enable) 182 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 183 else 184 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE; 185 intel_de_write(dev_priv, SOUTH_DSPCLK_GATE_D, val); 186 } 187 188 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv, 189 bool enable) 190 { 191 u32 val; 192 193 val = intel_de_read(dev_priv, GEN9_CLKGATE_DIS_4); 194 if (!enable) 195 val |= BXT_GMBUS_GATING_DIS; 196 else 197 val &= ~BXT_GMBUS_GATING_DIS; 198 intel_de_write(dev_priv, GEN9_CLKGATE_DIS_4, val); 199 } 200 201 static u32 get_reserved(struct intel_gmbus *bus) 202 { 203 struct drm_i915_private *i915 = bus->dev_priv; 204 struct intel_uncore *uncore = &i915->uncore; 205 u32 reserved = 0; 206 207 /* On most chips, these bits must be preserved in software. */ 208 if (!IS_I830(i915) && !IS_I845G(i915)) 209 reserved = intel_uncore_read_notrace(uncore, bus->gpio_reg) & 210 (GPIO_DATA_PULLUP_DISABLE | 211 GPIO_CLOCK_PULLUP_DISABLE); 212 213 return reserved; 214 } 215 216 static int get_clock(void *data) 217 { 218 struct intel_gmbus *bus = data; 219 struct intel_uncore *uncore = &bus->dev_priv->uncore; 220 u32 reserved = get_reserved(bus); 221 222 intel_uncore_write_notrace(uncore, 223 bus->gpio_reg, 224 reserved | GPIO_CLOCK_DIR_MASK); 225 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 226 227 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 228 GPIO_CLOCK_VAL_IN) != 0; 229 } 230 231 static int get_data(void *data) 232 { 233 struct intel_gmbus *bus = data; 234 struct intel_uncore *uncore = &bus->dev_priv->uncore; 235 u32 reserved = get_reserved(bus); 236 237 intel_uncore_write_notrace(uncore, 238 bus->gpio_reg, 239 reserved | GPIO_DATA_DIR_MASK); 240 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved); 241 242 return (intel_uncore_read_notrace(uncore, bus->gpio_reg) & 243 GPIO_DATA_VAL_IN) != 0; 244 } 245 246 static void set_clock(void *data, int state_high) 247 { 248 struct intel_gmbus *bus = data; 249 struct intel_uncore *uncore = &bus->dev_priv->uncore; 250 u32 reserved = get_reserved(bus); 251 u32 clock_bits; 252 253 if (state_high) 254 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 255 else 256 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 257 GPIO_CLOCK_VAL_MASK; 258 259 intel_uncore_write_notrace(uncore, 260 bus->gpio_reg, 261 reserved | clock_bits); 262 intel_uncore_posting_read(uncore, bus->gpio_reg); 263 } 264 265 static void set_data(void *data, int state_high) 266 { 267 struct intel_gmbus *bus = data; 268 struct intel_uncore *uncore = &bus->dev_priv->uncore; 269 u32 reserved = get_reserved(bus); 270 u32 data_bits; 271 272 if (state_high) 273 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 274 else 275 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 276 GPIO_DATA_VAL_MASK; 277 278 intel_uncore_write_notrace(uncore, bus->gpio_reg, reserved | data_bits); 279 intel_uncore_posting_read(uncore, bus->gpio_reg); 280 } 281 282 static int 283 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 284 { 285 struct intel_gmbus *bus = container_of(adapter, 286 struct intel_gmbus, 287 adapter); 288 struct drm_i915_private *dev_priv = bus->dev_priv; 289 290 intel_gmbus_reset(dev_priv); 291 292 if (IS_PINEVIEW(dev_priv)) 293 pnv_gmbus_clock_gating(dev_priv, false); 294 295 set_data(bus, 1); 296 set_clock(bus, 1); 297 udelay(I2C_RISEFALL_TIME); 298 return 0; 299 } 300 301 static void 302 intel_gpio_post_xfer(struct i2c_adapter *adapter) 303 { 304 struct intel_gmbus *bus = container_of(adapter, 305 struct intel_gmbus, 306 adapter); 307 struct drm_i915_private *dev_priv = bus->dev_priv; 308 309 set_data(bus, 1); 310 set_clock(bus, 1); 311 312 if (IS_PINEVIEW(dev_priv)) 313 pnv_gmbus_clock_gating(dev_priv, true); 314 } 315 316 static void 317 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin) 318 { 319 struct drm_i915_private *dev_priv = bus->dev_priv; 320 struct i2c_algo_bit_data *algo; 321 322 algo = &bus->bit_algo; 323 324 bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio); 325 bus->adapter.algo_data = algo; 326 algo->setsda = set_data; 327 algo->setscl = set_clock; 328 algo->getsda = get_data; 329 algo->getscl = get_clock; 330 algo->pre_xfer = intel_gpio_pre_xfer; 331 algo->post_xfer = intel_gpio_post_xfer; 332 algo->udelay = I2C_RISEFALL_TIME; 333 algo->timeout = usecs_to_jiffies(2200); 334 algo->data = bus; 335 } 336 337 static bool has_gmbus_irq(struct drm_i915_private *i915) 338 { 339 /* 340 * encoder->shutdown() may want to use GMBUS 341 * after irqs have already been disabled. 342 */ 343 return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915); 344 } 345 346 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en) 347 { 348 DEFINE_WAIT(wait); 349 u32 gmbus2; 350 int ret; 351 352 /* Important: The hw handles only the first bit, so set only one! Since 353 * we also need to check for NAKs besides the hw ready/idle signal, we 354 * need to wake up periodically and check that ourselves. 355 */ 356 if (!has_gmbus_irq(dev_priv)) 357 irq_en = 0; 358 359 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 360 intel_de_write_fw(dev_priv, GMBUS4, irq_en); 361 362 status |= GMBUS_SATOER; 363 ret = wait_for_us((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 364 2); 365 if (ret) 366 ret = wait_for((gmbus2 = intel_de_read_fw(dev_priv, GMBUS2)) & status, 367 50); 368 369 intel_de_write_fw(dev_priv, GMBUS4, 0); 370 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 371 372 if (gmbus2 & GMBUS_SATOER) 373 return -ENXIO; 374 375 return ret; 376 } 377 378 static int 379 gmbus_wait_idle(struct drm_i915_private *dev_priv) 380 { 381 DEFINE_WAIT(wait); 382 u32 irq_enable; 383 int ret; 384 385 /* Important: The hw handles only the first bit, so set only one! */ 386 irq_enable = 0; 387 if (has_gmbus_irq(dev_priv)) 388 irq_enable = GMBUS_IDLE_EN; 389 390 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 391 intel_de_write_fw(dev_priv, GMBUS4, irq_enable); 392 393 ret = intel_wait_for_register_fw(&dev_priv->uncore, 394 GMBUS2, GMBUS_ACTIVE, 0, 395 10); 396 397 intel_de_write_fw(dev_priv, GMBUS4, 0); 398 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait); 399 400 return ret; 401 } 402 403 static unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) 404 { 405 return DISPLAY_VER(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 406 GMBUS_BYTE_COUNT_MAX; 407 } 408 409 static int 410 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv, 411 unsigned short addr, u8 *buf, unsigned int len, 412 u32 gmbus0_reg, u32 gmbus1_index) 413 { 414 unsigned int size = len; 415 bool burst_read = len > gmbus_max_xfer_size(dev_priv); 416 bool extra_byte_added = false; 417 418 if (burst_read) { 419 /* 420 * As per HW Spec, for 512Bytes need to read extra Byte and 421 * Ignore the extra byte read. 422 */ 423 if (len == 512) { 424 extra_byte_added = true; 425 len++; 426 } 427 size = len % 256 + 256; 428 intel_de_write_fw(dev_priv, GMBUS0, 429 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 430 } 431 432 intel_de_write_fw(dev_priv, GMBUS1, 433 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 434 while (len) { 435 int ret; 436 u32 val, loop = 0; 437 438 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 439 if (ret) 440 return ret; 441 442 val = intel_de_read_fw(dev_priv, GMBUS3); 443 do { 444 if (extra_byte_added && len == 1) 445 break; 446 447 *buf++ = val & 0xff; 448 val >>= 8; 449 } while (--len && ++loop < 4); 450 451 if (burst_read && len == size - 4) 452 /* Reset the override bit */ 453 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_reg); 454 } 455 456 return 0; 457 } 458 459 /* 460 * HW spec says that 512Bytes in Burst read need special treatment. 461 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 462 * an I2C slave, which supports such a lengthy burst read too for experiments. 463 * 464 * So until things get clarified on HW support, to avoid the burst read length 465 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 466 */ 467 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 468 469 static int 470 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 471 u32 gmbus0_reg, u32 gmbus1_index) 472 { 473 u8 *buf = msg->buf; 474 unsigned int rx_size = msg->len; 475 unsigned int len; 476 int ret; 477 478 do { 479 if (HAS_GMBUS_BURST_READ(dev_priv)) 480 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 481 else 482 len = min(rx_size, gmbus_max_xfer_size(dev_priv)); 483 484 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len, 485 gmbus0_reg, gmbus1_index); 486 if (ret) 487 return ret; 488 489 rx_size -= len; 490 buf += len; 491 } while (rx_size != 0); 492 493 return 0; 494 } 495 496 static int 497 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv, 498 unsigned short addr, u8 *buf, unsigned int len, 499 u32 gmbus1_index) 500 { 501 unsigned int chunk_size = len; 502 u32 val, loop; 503 504 val = loop = 0; 505 while (len && loop < 4) { 506 val |= *buf++ << (8 * loop++); 507 len -= 1; 508 } 509 510 intel_de_write_fw(dev_priv, GMBUS3, val); 511 intel_de_write_fw(dev_priv, GMBUS1, 512 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 513 while (len) { 514 int ret; 515 516 val = loop = 0; 517 do { 518 val |= *buf++ << (8 * loop); 519 } while (--len && ++loop < 4); 520 521 intel_de_write_fw(dev_priv, GMBUS3, val); 522 523 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 524 if (ret) 525 return ret; 526 } 527 528 return 0; 529 } 530 531 static int 532 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg, 533 u32 gmbus1_index) 534 { 535 u8 *buf = msg->buf; 536 unsigned int tx_size = msg->len; 537 unsigned int len; 538 int ret; 539 540 do { 541 len = min(tx_size, gmbus_max_xfer_size(dev_priv)); 542 543 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len, 544 gmbus1_index); 545 if (ret) 546 return ret; 547 548 buf += len; 549 tx_size -= len; 550 } while (tx_size != 0); 551 552 return 0; 553 } 554 555 /* 556 * The gmbus controller can combine a 1 or 2 byte write with another read/write 557 * that immediately follows it by using an "INDEX" cycle. 558 */ 559 static bool 560 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 561 { 562 return (i + 1 < num && 563 msgs[i].addr == msgs[i + 1].addr && 564 !(msgs[i].flags & I2C_M_RD) && 565 (msgs[i].len == 1 || msgs[i].len == 2) && 566 msgs[i + 1].len > 0); 567 } 568 569 static int 570 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs, 571 u32 gmbus0_reg) 572 { 573 u32 gmbus1_index = 0; 574 u32 gmbus5 = 0; 575 int ret; 576 577 if (msgs[0].len == 2) 578 gmbus5 = GMBUS_2BYTE_INDEX_EN | 579 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 580 if (msgs[0].len == 1) 581 gmbus1_index = GMBUS_CYCLE_INDEX | 582 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 583 584 /* GMBUS5 holds 16-bit index */ 585 if (gmbus5) 586 intel_de_write_fw(dev_priv, GMBUS5, gmbus5); 587 588 if (msgs[1].flags & I2C_M_RD) 589 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg, 590 gmbus1_index); 591 else 592 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index); 593 594 /* Clear GMBUS5 after each index transfer */ 595 if (gmbus5) 596 intel_de_write_fw(dev_priv, GMBUS5, 0); 597 598 return ret; 599 } 600 601 static int 602 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 603 u32 gmbus0_source) 604 { 605 struct intel_gmbus *bus = container_of(adapter, 606 struct intel_gmbus, 607 adapter); 608 struct drm_i915_private *dev_priv = bus->dev_priv; 609 int i = 0, inc, try = 0; 610 int ret = 0; 611 612 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 613 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 614 bxt_gmbus_clock_gating(dev_priv, false); 615 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 616 pch_gmbus_clock_gating(dev_priv, false); 617 618 retry: 619 intel_de_write_fw(dev_priv, GMBUS0, gmbus0_source | bus->reg0); 620 621 for (; i < num; i += inc) { 622 inc = 1; 623 if (gmbus_is_index_xfer(msgs, i, num)) { 624 ret = gmbus_index_xfer(dev_priv, &msgs[i], 625 gmbus0_source | bus->reg0); 626 inc = 2; /* an index transmission is two msgs */ 627 } else if (msgs[i].flags & I2C_M_RD) { 628 ret = gmbus_xfer_read(dev_priv, &msgs[i], 629 gmbus0_source | bus->reg0, 0); 630 } else { 631 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0); 632 } 633 634 if (!ret) 635 ret = gmbus_wait(dev_priv, 636 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 637 if (ret == -ETIMEDOUT) 638 goto timeout; 639 else if (ret) 640 goto clear_err; 641 } 642 643 /* Generate a STOP condition on the bus. Note that gmbus can't generata 644 * a STOP on the very first cycle. To simplify the code we 645 * unconditionally generate the STOP condition with an additional gmbus 646 * cycle. */ 647 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 648 649 /* Mark the GMBUS interface as disabled after waiting for idle. 650 * We will re-enable it at the start of the next xfer, 651 * till then let it sleep. 652 */ 653 if (gmbus_wait_idle(dev_priv)) { 654 drm_dbg_kms(&dev_priv->drm, 655 "GMBUS [%s] timed out waiting for idle\n", 656 adapter->name); 657 ret = -ETIMEDOUT; 658 } 659 intel_de_write_fw(dev_priv, GMBUS0, 0); 660 ret = ret ?: i; 661 goto out; 662 663 clear_err: 664 /* 665 * Wait for bus to IDLE before clearing NAK. 666 * If we clear the NAK while bus is still active, then it will stay 667 * active and the next transaction may fail. 668 * 669 * If no ACK is received during the address phase of a transaction, the 670 * adapter must report -ENXIO. It is not clear what to return if no ACK 671 * is received at other times. But we have to be careful to not return 672 * spurious -ENXIO because that will prevent i2c and drm edid functions 673 * from retrying. So return -ENXIO only when gmbus properly quiescents - 674 * timing out seems to happen when there _is_ a ddc chip present, but 675 * it's slow responding and only answers on the 2nd retry. 676 */ 677 ret = -ENXIO; 678 if (gmbus_wait_idle(dev_priv)) { 679 drm_dbg_kms(&dev_priv->drm, 680 "GMBUS [%s] timed out after NAK\n", 681 adapter->name); 682 ret = -ETIMEDOUT; 683 } 684 685 /* Toggle the Software Clear Interrupt bit. This has the effect 686 * of resetting the GMBUS controller and so clearing the 687 * BUS_ERROR raised by the slave's NAK. 688 */ 689 intel_de_write_fw(dev_priv, GMBUS1, GMBUS_SW_CLR_INT); 690 intel_de_write_fw(dev_priv, GMBUS1, 0); 691 intel_de_write_fw(dev_priv, GMBUS0, 0); 692 693 drm_dbg_kms(&dev_priv->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 694 adapter->name, msgs[i].addr, 695 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 696 697 /* 698 * Passive adapters sometimes NAK the first probe. Retry the first 699 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 700 * has retries internally. See also the retry loop in 701 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 702 */ 703 if (ret == -ENXIO && i == 0 && try++ == 0) { 704 drm_dbg_kms(&dev_priv->drm, 705 "GMBUS [%s] NAK on first message, retry\n", 706 adapter->name); 707 goto retry; 708 } 709 710 goto out; 711 712 timeout: 713 drm_dbg_kms(&dev_priv->drm, 714 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 715 bus->adapter.name, bus->reg0 & 0xff); 716 intel_de_write_fw(dev_priv, GMBUS0, 0); 717 718 /* 719 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 720 * instead. Use EAGAIN to have i2c core retry. 721 */ 722 ret = -EAGAIN; 723 724 out: 725 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 726 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 727 bxt_gmbus_clock_gating(dev_priv, true); 728 else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_CNP(dev_priv)) 729 pch_gmbus_clock_gating(dev_priv, true); 730 731 return ret; 732 } 733 734 static int 735 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 736 { 737 struct intel_gmbus *bus = 738 container_of(adapter, struct intel_gmbus, adapter); 739 struct drm_i915_private *dev_priv = bus->dev_priv; 740 intel_wakeref_t wakeref; 741 int ret; 742 743 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 744 745 if (bus->force_bit) { 746 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 747 if (ret < 0) 748 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 749 } else { 750 ret = do_gmbus_xfer(adapter, msgs, num, 0); 751 if (ret == -EAGAIN) 752 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 753 } 754 755 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 756 757 return ret; 758 } 759 760 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 761 { 762 struct intel_gmbus *bus = 763 container_of(adapter, struct intel_gmbus, adapter); 764 struct drm_i915_private *dev_priv = bus->dev_priv; 765 u8 cmd = DRM_HDCP_DDC_AKSV; 766 u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; 767 struct i2c_msg msgs[] = { 768 { 769 .addr = DRM_HDCP_DDC_ADDR, 770 .flags = 0, 771 .len = sizeof(cmd), 772 .buf = &cmd, 773 }, 774 { 775 .addr = DRM_HDCP_DDC_ADDR, 776 .flags = 0, 777 .len = sizeof(buf), 778 .buf = buf, 779 } 780 }; 781 intel_wakeref_t wakeref; 782 int ret; 783 784 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); 785 mutex_lock(&dev_priv->gmbus_mutex); 786 787 /* 788 * In order to output Aksv to the receiver, use an indexed write to 789 * pass the i2c command, and tell GMBUS to use the HW-provided value 790 * instead of sourcing GMBUS3 for the data. 791 */ 792 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 793 794 mutex_unlock(&dev_priv->gmbus_mutex); 795 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); 796 797 return ret; 798 } 799 800 static u32 gmbus_func(struct i2c_adapter *adapter) 801 { 802 return i2c_bit_algo.functionality(adapter) & 803 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 804 /* I2C_FUNC_10BIT_ADDR | */ 805 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 806 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 807 } 808 809 static const struct i2c_algorithm gmbus_algorithm = { 810 .master_xfer = gmbus_xfer, 811 .functionality = gmbus_func 812 }; 813 814 static void gmbus_lock_bus(struct i2c_adapter *adapter, 815 unsigned int flags) 816 { 817 struct intel_gmbus *bus = to_intel_gmbus(adapter); 818 struct drm_i915_private *dev_priv = bus->dev_priv; 819 820 mutex_lock(&dev_priv->gmbus_mutex); 821 } 822 823 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 824 unsigned int flags) 825 { 826 struct intel_gmbus *bus = to_intel_gmbus(adapter); 827 struct drm_i915_private *dev_priv = bus->dev_priv; 828 829 return mutex_trylock(&dev_priv->gmbus_mutex); 830 } 831 832 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 833 unsigned int flags) 834 { 835 struct intel_gmbus *bus = to_intel_gmbus(adapter); 836 struct drm_i915_private *dev_priv = bus->dev_priv; 837 838 mutex_unlock(&dev_priv->gmbus_mutex); 839 } 840 841 static const struct i2c_lock_operations gmbus_lock_ops = { 842 .lock_bus = gmbus_lock_bus, 843 .trylock_bus = gmbus_trylock_bus, 844 .unlock_bus = gmbus_unlock_bus, 845 }; 846 847 /** 848 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 849 * @dev_priv: i915 device private 850 */ 851 int intel_gmbus_setup(struct drm_i915_private *dev_priv) 852 { 853 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 854 struct intel_gmbus *bus; 855 unsigned int pin; 856 int ret; 857 858 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 859 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; 860 else if (!HAS_GMCH(dev_priv)) 861 /* 862 * Broxton uses the same PCH offsets for South Display Engine, 863 * even though it doesn't have a PCH. 864 */ 865 dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE; 866 867 mutex_init(&dev_priv->gmbus_mutex); 868 init_waitqueue_head(&dev_priv->gmbus_wait_queue); 869 870 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 871 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 872 continue; 873 874 bus = &dev_priv->gmbus[pin]; 875 876 bus->adapter.owner = THIS_MODULE; 877 bus->adapter.class = I2C_CLASS_DDC; 878 snprintf(bus->adapter.name, 879 sizeof(bus->adapter.name), 880 "i915 gmbus %s", 881 get_gmbus_pin(dev_priv, pin)->name); 882 883 bus->adapter.dev.parent = &pdev->dev; 884 bus->dev_priv = dev_priv; 885 886 bus->adapter.algo = &gmbus_algorithm; 887 bus->adapter.lock_ops = &gmbus_lock_ops; 888 889 /* 890 * We wish to retry with bit banging 891 * after a timed out GMBUS attempt. 892 */ 893 bus->adapter.retries = 1; 894 895 /* By default use a conservative clock rate */ 896 bus->reg0 = pin | GMBUS_RATE_100KHZ; 897 898 /* gmbus seems to be broken on i830 */ 899 if (IS_I830(dev_priv)) 900 bus->force_bit = 1; 901 902 intel_gpio_setup(bus, pin); 903 904 ret = i2c_add_adapter(&bus->adapter); 905 if (ret) 906 goto err; 907 } 908 909 intel_gmbus_reset(dev_priv); 910 911 return 0; 912 913 err: 914 while (pin--) { 915 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 916 continue; 917 918 bus = &dev_priv->gmbus[pin]; 919 i2c_del_adapter(&bus->adapter); 920 } 921 return ret; 922 } 923 924 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, 925 unsigned int pin) 926 { 927 if (drm_WARN_ON(&dev_priv->drm, 928 !intel_gmbus_is_valid_pin(dev_priv, pin))) 929 return NULL; 930 931 return &dev_priv->gmbus[pin].adapter; 932 } 933 934 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed) 935 { 936 struct intel_gmbus *bus = to_intel_gmbus(adapter); 937 938 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed; 939 } 940 941 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 942 { 943 struct intel_gmbus *bus = to_intel_gmbus(adapter); 944 struct drm_i915_private *dev_priv = bus->dev_priv; 945 946 mutex_lock(&dev_priv->gmbus_mutex); 947 948 bus->force_bit += force_bit ? 1 : -1; 949 drm_dbg_kms(&dev_priv->drm, 950 "%sabling bit-banging on %s. force bit now %d\n", 951 force_bit ? "en" : "dis", adapter->name, 952 bus->force_bit); 953 954 mutex_unlock(&dev_priv->gmbus_mutex); 955 } 956 957 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 958 { 959 struct intel_gmbus *bus = to_intel_gmbus(adapter); 960 961 return bus->force_bit; 962 } 963 964 void intel_gmbus_teardown(struct drm_i915_private *dev_priv) 965 { 966 struct intel_gmbus *bus; 967 unsigned int pin; 968 969 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) { 970 if (!intel_gmbus_is_valid_pin(dev_priv, pin)) 971 continue; 972 973 bus = &dev_priv->gmbus[pin]; 974 i2c_del_adapter(&bus->adapter); 975 } 976 } 977