1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 34 #include <drm/display/drm_hdcp_helper.h> 35 36 #include "i915_drv.h" 37 #include "i915_irq.h" 38 #include "i915_reg.h" 39 #include "intel_de.h" 40 #include "intel_display_regs.h" 41 #include "intel_display_types.h" 42 #include "intel_gmbus.h" 43 #include "intel_gmbus_regs.h" 44 45 struct intel_gmbus { 46 struct i2c_adapter adapter; 47 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 48 u32 force_bit; 49 u32 reg0; 50 i915_reg_t gpio_reg; 51 struct i2c_algo_bit_data bit_algo; 52 struct intel_display *display; 53 }; 54 55 enum gmbus_gpio { 56 GPIOA, 57 GPIOB, 58 GPIOC, 59 GPIOD, 60 GPIOE, 61 GPIOF, 62 GPIOG, 63 GPIOH, 64 __GPIOI_UNUSED, 65 GPIOJ, 66 GPIOK, 67 GPIOL, 68 GPIOM, 69 GPION, 70 GPIOO, 71 }; 72 73 struct gmbus_pin { 74 const char *name; 75 enum gmbus_gpio gpio; 76 }; 77 78 /* Map gmbus pin pairs to names and registers. */ 79 static const struct gmbus_pin gmbus_pins[] = { 80 [GMBUS_PIN_SSC] = { "ssc", GPIOB }, 81 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 82 [GMBUS_PIN_PANEL] = { "panel", GPIOC }, 83 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 84 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 85 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 86 }; 87 88 static const struct gmbus_pin gmbus_pins_bdw[] = { 89 [GMBUS_PIN_VGADDC] = { "vga", GPIOA }, 90 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 91 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 92 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 93 }; 94 95 static const struct gmbus_pin gmbus_pins_skl[] = { 96 [GMBUS_PIN_DPC] = { "dpc", GPIOD }, 97 [GMBUS_PIN_DPB] = { "dpb", GPIOE }, 98 [GMBUS_PIN_DPD] = { "dpd", GPIOF }, 99 }; 100 101 static const struct gmbus_pin gmbus_pins_bxt[] = { 102 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 103 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 104 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 105 }; 106 107 static const struct gmbus_pin gmbus_pins_cnp[] = { 108 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB }, 109 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC }, 110 [GMBUS_PIN_3_BXT] = { "misc", GPIOD }, 111 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 112 }; 113 114 static const struct gmbus_pin gmbus_pins_icp[] = { 115 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 116 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 117 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 118 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 119 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 120 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 121 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 122 [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION }, 123 [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO }, 124 }; 125 126 static const struct gmbus_pin gmbus_pins_dg1[] = { 127 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 128 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 129 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 130 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 131 }; 132 133 static const struct gmbus_pin gmbus_pins_dg2[] = { 134 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 135 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 136 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 137 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 138 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 139 }; 140 141 static const struct gmbus_pin gmbus_pins_mtp[] = { 142 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB }, 143 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC }, 144 [GMBUS_PIN_3_BXT] = { "dpc", GPIOD }, 145 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE }, 146 [GMBUS_PIN_5_MTP] = { "dpe", GPIOF }, 147 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ }, 148 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK }, 149 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL }, 150 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM }, 151 }; 152 153 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, 154 unsigned int pin) 155 { 156 const struct gmbus_pin *pins; 157 size_t size; 158 159 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { 160 pins = gmbus_pins_mtp; 161 size = ARRAY_SIZE(gmbus_pins_mtp); 162 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { 163 pins = gmbus_pins_dg2; 164 size = ARRAY_SIZE(gmbus_pins_dg2); 165 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { 166 pins = gmbus_pins_dg1; 167 size = ARRAY_SIZE(gmbus_pins_dg1); 168 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { 169 pins = gmbus_pins_icp; 170 size = ARRAY_SIZE(gmbus_pins_icp); 171 } else if (HAS_PCH_CNP(display)) { 172 pins = gmbus_pins_cnp; 173 size = ARRAY_SIZE(gmbus_pins_cnp); 174 } else if (display->platform.geminilake || display->platform.broxton) { 175 pins = gmbus_pins_bxt; 176 size = ARRAY_SIZE(gmbus_pins_bxt); 177 } else if (DISPLAY_VER(display) == 9) { 178 pins = gmbus_pins_skl; 179 size = ARRAY_SIZE(gmbus_pins_skl); 180 } else if (display->platform.broadwell) { 181 pins = gmbus_pins_bdw; 182 size = ARRAY_SIZE(gmbus_pins_bdw); 183 } else { 184 pins = gmbus_pins; 185 size = ARRAY_SIZE(gmbus_pins); 186 } 187 188 if (pin >= size || !pins[pin].name) 189 return NULL; 190 191 return &pins[pin]; 192 } 193 194 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) 195 { 196 return get_gmbus_pin(display, pin); 197 } 198 199 /* Intel GPIO access functions */ 200 201 #define I2C_RISEFALL_TIME 10 202 203 static inline struct intel_gmbus * 204 to_intel_gmbus(struct i2c_adapter *i2c) 205 { 206 return container_of(i2c, struct intel_gmbus, adapter); 207 } 208 209 void 210 intel_gmbus_reset(struct intel_display *display) 211 { 212 intel_de_write(display, GMBUS0(display), 0); 213 intel_de_write(display, GMBUS4(display), 0); 214 } 215 216 static void pnv_gmbus_clock_gating(struct intel_display *display, 217 bool enable) 218 { 219 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 220 intel_de_rmw(display, DSPCLK_GATE_D(display), 221 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 222 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 223 } 224 225 static void pch_gmbus_clock_gating(struct intel_display *display, 226 bool enable) 227 { 228 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 229 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 230 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 231 } 232 233 static void bxt_gmbus_clock_gating(struct intel_display *display, 234 bool enable) 235 { 236 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 237 !enable ? BXT_GMBUS_GATING_DIS : 0); 238 } 239 240 static u32 get_reserved(struct intel_gmbus *bus) 241 { 242 struct intel_display *display = bus->display; 243 u32 reserved = 0; 244 245 /* On most chips, these bits must be preserved in software. */ 246 if (!display->platform.i830 && !display->platform.i845g) 247 reserved = intel_de_read_notrace(display, bus->gpio_reg) & 248 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 249 250 return reserved; 251 } 252 253 static int get_clock(void *data) 254 { 255 struct intel_gmbus *bus = data; 256 struct intel_display *display = bus->display; 257 u32 reserved = get_reserved(bus); 258 259 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 260 intel_de_write_notrace(display, bus->gpio_reg, reserved); 261 262 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 263 } 264 265 static int get_data(void *data) 266 { 267 struct intel_gmbus *bus = data; 268 struct intel_display *display = bus->display; 269 u32 reserved = get_reserved(bus); 270 271 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 272 intel_de_write_notrace(display, bus->gpio_reg, reserved); 273 274 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 275 } 276 277 static void set_clock(void *data, int state_high) 278 { 279 struct intel_gmbus *bus = data; 280 struct intel_display *display = bus->display; 281 u32 reserved = get_reserved(bus); 282 u32 clock_bits; 283 284 if (state_high) 285 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 286 else 287 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 288 GPIO_CLOCK_VAL_MASK; 289 290 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); 291 intel_de_posting_read(display, bus->gpio_reg); 292 } 293 294 static void set_data(void *data, int state_high) 295 { 296 struct intel_gmbus *bus = data; 297 struct intel_display *display = bus->display; 298 u32 reserved = get_reserved(bus); 299 u32 data_bits; 300 301 if (state_high) 302 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 303 else 304 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 305 GPIO_DATA_VAL_MASK; 306 307 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); 308 intel_de_posting_read(display, bus->gpio_reg); 309 } 310 311 static int 312 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 313 { 314 struct intel_gmbus *bus = to_intel_gmbus(adapter); 315 struct intel_display *display = bus->display; 316 317 intel_gmbus_reset(display); 318 319 if (display->platform.pineview) 320 pnv_gmbus_clock_gating(display, false); 321 322 set_data(bus, 1); 323 set_clock(bus, 1); 324 udelay(I2C_RISEFALL_TIME); 325 return 0; 326 } 327 328 static void 329 intel_gpio_post_xfer(struct i2c_adapter *adapter) 330 { 331 struct intel_gmbus *bus = to_intel_gmbus(adapter); 332 struct intel_display *display = bus->display; 333 334 set_data(bus, 1); 335 set_clock(bus, 1); 336 337 if (display->platform.pineview) 338 pnv_gmbus_clock_gating(display, true); 339 } 340 341 static void 342 intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg) 343 { 344 struct i2c_algo_bit_data *algo; 345 346 algo = &bus->bit_algo; 347 348 bus->gpio_reg = gpio_reg; 349 bus->adapter.algo_data = algo; 350 algo->setsda = set_data; 351 algo->setscl = set_clock; 352 algo->getsda = get_data; 353 algo->getscl = get_clock; 354 algo->pre_xfer = intel_gpio_pre_xfer; 355 algo->post_xfer = intel_gpio_post_xfer; 356 algo->udelay = I2C_RISEFALL_TIME; 357 algo->timeout = usecs_to_jiffies(2200); 358 algo->data = bus; 359 } 360 361 static bool has_gmbus_irq(struct intel_display *display) 362 { 363 struct drm_i915_private *i915 = to_i915(display->drm); 364 /* 365 * encoder->shutdown() may want to use GMBUS 366 * after irqs have already been disabled. 367 */ 368 return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915); 369 } 370 371 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) 372 { 373 DEFINE_WAIT(wait); 374 u32 gmbus2; 375 int ret; 376 377 /* Important: The hw handles only the first bit, so set only one! Since 378 * we also need to check for NAKs besides the hw ready/idle signal, we 379 * need to wake up periodically and check that ourselves. 380 */ 381 if (!has_gmbus_irq(display)) 382 irq_en = 0; 383 384 add_wait_queue(&display->gmbus.wait_queue, &wait); 385 intel_de_write_fw(display, GMBUS4(display), irq_en); 386 387 status |= GMBUS_SATOER; 388 ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, 389 2); 390 if (ret) 391 ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status, 392 50); 393 394 intel_de_write_fw(display, GMBUS4(display), 0); 395 remove_wait_queue(&display->gmbus.wait_queue, &wait); 396 397 if (gmbus2 & GMBUS_SATOER) 398 return -ENXIO; 399 400 return ret; 401 } 402 403 static int 404 gmbus_wait_idle(struct intel_display *display) 405 { 406 DEFINE_WAIT(wait); 407 u32 irq_enable; 408 int ret; 409 410 /* Important: The hw handles only the first bit, so set only one! */ 411 irq_enable = 0; 412 if (has_gmbus_irq(display)) 413 irq_enable = GMBUS_IDLE_EN; 414 415 add_wait_queue(&display->gmbus.wait_queue, &wait); 416 intel_de_write_fw(display, GMBUS4(display), irq_enable); 417 418 ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL); 419 420 intel_de_write_fw(display, GMBUS4(display), 0); 421 remove_wait_queue(&display->gmbus.wait_queue, &wait); 422 423 return ret; 424 } 425 426 static unsigned int gmbus_max_xfer_size(struct intel_display *display) 427 { 428 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 429 GMBUS_BYTE_COUNT_MAX; 430 } 431 432 static int 433 gmbus_xfer_read_chunk(struct intel_display *display, 434 unsigned short addr, u8 *buf, unsigned int len, 435 u32 gmbus0_reg, u32 gmbus1_index) 436 { 437 unsigned int size = len; 438 bool burst_read = len > gmbus_max_xfer_size(display); 439 bool extra_byte_added = false; 440 441 if (burst_read) { 442 /* 443 * As per HW Spec, for 512Bytes need to read extra Byte and 444 * Ignore the extra byte read. 445 */ 446 if (len == 512) { 447 extra_byte_added = true; 448 len++; 449 } 450 size = len % 256 + 256; 451 intel_de_write_fw(display, GMBUS0(display), 452 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 453 } 454 455 intel_de_write_fw(display, GMBUS1(display), 456 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 457 while (len) { 458 int ret; 459 u32 val, loop = 0; 460 461 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 462 if (ret) 463 return ret; 464 465 val = intel_de_read_fw(display, GMBUS3(display)); 466 do { 467 if (extra_byte_added && len == 1) 468 break; 469 470 *buf++ = val & 0xff; 471 val >>= 8; 472 } while (--len && ++loop < 4); 473 474 if (burst_read && len == size - 4) 475 /* Reset the override bit */ 476 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); 477 } 478 479 return 0; 480 } 481 482 /* 483 * HW spec says that 512Bytes in Burst read need special treatment. 484 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 485 * an I2C target, which supports such a lengthy burst read too for experiments. 486 * 487 * So until things get clarified on HW support, to avoid the burst read length 488 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 489 */ 490 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 491 492 static int 493 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 494 u32 gmbus0_reg, u32 gmbus1_index) 495 { 496 u8 *buf = msg->buf; 497 unsigned int rx_size = msg->len; 498 unsigned int len; 499 int ret; 500 501 do { 502 if (HAS_GMBUS_BURST_READ(display)) 503 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 504 else 505 len = min(rx_size, gmbus_max_xfer_size(display)); 506 507 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, 508 gmbus0_reg, gmbus1_index); 509 if (ret) 510 return ret; 511 512 rx_size -= len; 513 buf += len; 514 } while (rx_size != 0); 515 516 return 0; 517 } 518 519 static int 520 gmbus_xfer_write_chunk(struct intel_display *display, 521 unsigned short addr, u8 *buf, unsigned int len, 522 u32 gmbus1_index) 523 { 524 unsigned int chunk_size = len; 525 u32 val, loop; 526 527 val = loop = 0; 528 while (len && loop < 4) { 529 val |= *buf++ << (8 * loop++); 530 len -= 1; 531 } 532 533 intel_de_write_fw(display, GMBUS3(display), val); 534 intel_de_write_fw(display, GMBUS1(display), 535 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 536 while (len) { 537 int ret; 538 539 val = loop = 0; 540 do { 541 val |= *buf++ << (8 * loop); 542 } while (--len && ++loop < 4); 543 544 intel_de_write_fw(display, GMBUS3(display), val); 545 546 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 547 if (ret) 548 return ret; 549 } 550 551 return 0; 552 } 553 554 static int 555 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, 556 u32 gmbus1_index) 557 { 558 u8 *buf = msg->buf; 559 unsigned int tx_size = msg->len; 560 unsigned int len; 561 int ret; 562 563 do { 564 len = min(tx_size, gmbus_max_xfer_size(display)); 565 566 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, 567 gmbus1_index); 568 if (ret) 569 return ret; 570 571 buf += len; 572 tx_size -= len; 573 } while (tx_size != 0); 574 575 return 0; 576 } 577 578 /* 579 * The gmbus controller can combine a 1 or 2 byte write with another read/write 580 * that immediately follows it by using an "INDEX" cycle. 581 */ 582 static bool 583 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 584 { 585 return (i + 1 < num && 586 msgs[i].addr == msgs[i + 1].addr && 587 !(msgs[i].flags & I2C_M_RD) && 588 (msgs[i].len == 1 || msgs[i].len == 2) && 589 msgs[i + 1].len > 0); 590 } 591 592 static int 593 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, 594 u32 gmbus0_reg) 595 { 596 u32 gmbus1_index = 0; 597 u32 gmbus5 = 0; 598 int ret; 599 600 if (msgs[0].len == 2) 601 gmbus5 = GMBUS_2BYTE_INDEX_EN | 602 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 603 if (msgs[0].len == 1) 604 gmbus1_index = GMBUS_CYCLE_INDEX | 605 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 606 607 /* GMBUS5 holds 16-bit index */ 608 if (gmbus5) 609 intel_de_write_fw(display, GMBUS5(display), gmbus5); 610 611 if (msgs[1].flags & I2C_M_RD) 612 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, 613 gmbus1_index); 614 else 615 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); 616 617 /* Clear GMBUS5 after each index transfer */ 618 if (gmbus5) 619 intel_de_write_fw(display, GMBUS5(display), 0); 620 621 return ret; 622 } 623 624 static int 625 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 626 u32 gmbus0_source) 627 { 628 struct intel_gmbus *bus = to_intel_gmbus(adapter); 629 struct intel_display *display = bus->display; 630 int i = 0, inc, try = 0; 631 int ret = 0; 632 633 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 634 if (display->platform.geminilake || display->platform.broxton) 635 bxt_gmbus_clock_gating(display, false); 636 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 637 pch_gmbus_clock_gating(display, false); 638 639 retry: 640 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); 641 642 for (; i < num; i += inc) { 643 inc = 1; 644 if (gmbus_is_index_xfer(msgs, i, num)) { 645 ret = gmbus_index_xfer(display, &msgs[i], 646 gmbus0_source | bus->reg0); 647 inc = 2; /* an index transmission is two msgs */ 648 } else if (msgs[i].flags & I2C_M_RD) { 649 ret = gmbus_xfer_read(display, &msgs[i], 650 gmbus0_source | bus->reg0, 0); 651 } else { 652 ret = gmbus_xfer_write(display, &msgs[i], 0); 653 } 654 655 if (!ret) 656 ret = gmbus_wait(display, 657 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 658 if (ret == -ETIMEDOUT) 659 goto timeout; 660 else if (ret) 661 goto clear_err; 662 } 663 664 /* Generate a STOP condition on the bus. Note that gmbus can't generata 665 * a STOP on the very first cycle. To simplify the code we 666 * unconditionally generate the STOP condition with an additional gmbus 667 * cycle. */ 668 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 669 670 /* Mark the GMBUS interface as disabled after waiting for idle. 671 * We will re-enable it at the start of the next xfer, 672 * till then let it sleep. 673 */ 674 if (gmbus_wait_idle(display)) { 675 drm_dbg_kms(display->drm, 676 "GMBUS [%s] timed out waiting for idle\n", 677 adapter->name); 678 ret = -ETIMEDOUT; 679 } 680 intel_de_write_fw(display, GMBUS0(display), 0); 681 ret = ret ?: i; 682 goto out; 683 684 clear_err: 685 /* 686 * Wait for bus to IDLE before clearing NAK. 687 * If we clear the NAK while bus is still active, then it will stay 688 * active and the next transaction may fail. 689 * 690 * If no ACK is received during the address phase of a transaction, the 691 * adapter must report -ENXIO. It is not clear what to return if no ACK 692 * is received at other times. But we have to be careful to not return 693 * spurious -ENXIO because that will prevent i2c and drm edid functions 694 * from retrying. So return -ENXIO only when gmbus properly quiescents - 695 * timing out seems to happen when there _is_ a ddc chip present, but 696 * it's slow responding and only answers on the 2nd retry. 697 */ 698 ret = -ENXIO; 699 if (gmbus_wait_idle(display)) { 700 drm_dbg_kms(display->drm, 701 "GMBUS [%s] timed out after NAK\n", 702 adapter->name); 703 ret = -ETIMEDOUT; 704 } 705 706 /* Toggle the Software Clear Interrupt bit. This has the effect 707 * of resetting the GMBUS controller and so clearing the 708 * BUS_ERROR raised by the target's NAK. 709 */ 710 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); 711 intel_de_write_fw(display, GMBUS1(display), 0); 712 intel_de_write_fw(display, GMBUS0(display), 0); 713 714 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 715 adapter->name, msgs[i].addr, 716 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 717 718 /* 719 * Passive adapters sometimes NAK the first probe. Retry the first 720 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 721 * has retries internally. See also the retry loop in 722 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 723 */ 724 if (ret == -ENXIO && i == 0 && try++ == 0) { 725 drm_dbg_kms(display->drm, 726 "GMBUS [%s] NAK on first message, retry\n", 727 adapter->name); 728 goto retry; 729 } 730 731 goto out; 732 733 timeout: 734 drm_dbg_kms(display->drm, 735 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 736 bus->adapter.name, bus->reg0 & 0xff); 737 intel_de_write_fw(display, GMBUS0(display), 0); 738 739 /* 740 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 741 * instead. Use EAGAIN to have i2c core retry. 742 */ 743 ret = -EAGAIN; 744 745 out: 746 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 747 if (display->platform.geminilake || display->platform.broxton) 748 bxt_gmbus_clock_gating(display, true); 749 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 750 pch_gmbus_clock_gating(display, true); 751 752 return ret; 753 } 754 755 static int 756 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 757 { 758 struct intel_gmbus *bus = to_intel_gmbus(adapter); 759 struct intel_display *display = bus->display; 760 intel_wakeref_t wakeref; 761 int ret; 762 763 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 764 765 if (bus->force_bit) { 766 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 767 if (ret < 0) 768 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 769 } else { 770 ret = do_gmbus_xfer(adapter, msgs, num, 0); 771 if (ret == -EAGAIN) 772 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 773 } 774 775 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 776 777 return ret; 778 } 779 780 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 781 { 782 struct intel_gmbus *bus = to_intel_gmbus(adapter); 783 struct intel_display *display = bus->display; 784 u8 cmd = DRM_HDCP_DDC_AKSV; 785 u8 buf[DRM_HDCP_KSV_LEN] = {}; 786 struct i2c_msg msgs[] = { 787 { 788 .addr = DRM_HDCP_DDC_ADDR, 789 .flags = 0, 790 .len = sizeof(cmd), 791 .buf = &cmd, 792 }, 793 { 794 .addr = DRM_HDCP_DDC_ADDR, 795 .flags = 0, 796 .len = sizeof(buf), 797 .buf = buf, 798 } 799 }; 800 intel_wakeref_t wakeref; 801 int ret; 802 803 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 804 mutex_lock(&display->gmbus.mutex); 805 806 /* 807 * In order to output Aksv to the receiver, use an indexed write to 808 * pass the i2c command, and tell GMBUS to use the HW-provided value 809 * instead of sourcing GMBUS3 for the data. 810 */ 811 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 812 813 mutex_unlock(&display->gmbus.mutex); 814 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 815 816 return ret; 817 } 818 819 static u32 gmbus_func(struct i2c_adapter *adapter) 820 { 821 return i2c_bit_algo.functionality(adapter) & 822 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 823 /* I2C_FUNC_10BIT_ADDR | */ 824 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 825 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 826 } 827 828 static const struct i2c_algorithm gmbus_algorithm = { 829 .master_xfer = gmbus_xfer, 830 .functionality = gmbus_func 831 }; 832 833 static void gmbus_lock_bus(struct i2c_adapter *adapter, 834 unsigned int flags) 835 { 836 struct intel_gmbus *bus = to_intel_gmbus(adapter); 837 struct intel_display *display = bus->display; 838 839 mutex_lock(&display->gmbus.mutex); 840 } 841 842 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 843 unsigned int flags) 844 { 845 struct intel_gmbus *bus = to_intel_gmbus(adapter); 846 struct intel_display *display = bus->display; 847 848 return mutex_trylock(&display->gmbus.mutex); 849 } 850 851 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 852 unsigned int flags) 853 { 854 struct intel_gmbus *bus = to_intel_gmbus(adapter); 855 struct intel_display *display = bus->display; 856 857 mutex_unlock(&display->gmbus.mutex); 858 } 859 860 static const struct i2c_lock_operations gmbus_lock_ops = { 861 .lock_bus = gmbus_lock_bus, 862 .trylock_bus = gmbus_trylock_bus, 863 .unlock_bus = gmbus_unlock_bus, 864 }; 865 866 /** 867 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 868 * @display: display device 869 */ 870 int intel_gmbus_setup(struct intel_display *display) 871 { 872 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 873 unsigned int pin; 874 int ret; 875 876 if (display->platform.valleyview || display->platform.cherryview) 877 display->gmbus.mmio_base = VLV_DISPLAY_BASE; 878 else if (!HAS_GMCH(display)) 879 /* 880 * Broxton uses the same PCH offsets for South Display Engine, 881 * even though it doesn't have a PCH. 882 */ 883 display->gmbus.mmio_base = PCH_DISPLAY_BASE; 884 885 mutex_init(&display->gmbus.mutex); 886 init_waitqueue_head(&display->gmbus.wait_queue); 887 888 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 889 const struct gmbus_pin *gmbus_pin; 890 struct intel_gmbus *bus; 891 892 gmbus_pin = get_gmbus_pin(display, pin); 893 if (!gmbus_pin) 894 continue; 895 896 bus = kzalloc(sizeof(*bus), GFP_KERNEL); 897 if (!bus) { 898 ret = -ENOMEM; 899 goto err; 900 } 901 902 bus->adapter.owner = THIS_MODULE; 903 snprintf(bus->adapter.name, 904 sizeof(bus->adapter.name), 905 "i915 gmbus %s", gmbus_pin->name); 906 907 bus->adapter.dev.parent = &pdev->dev; 908 bus->display = display; 909 910 bus->adapter.algo = &gmbus_algorithm; 911 bus->adapter.lock_ops = &gmbus_lock_ops; 912 913 /* 914 * We wish to retry with bit banging 915 * after a timed out GMBUS attempt. 916 */ 917 bus->adapter.retries = 1; 918 919 /* By default use a conservative clock rate */ 920 bus->reg0 = pin | GMBUS_RATE_100KHZ; 921 922 /* gmbus seems to be broken on i830 */ 923 if (display->platform.i830) 924 bus->force_bit = 1; 925 926 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); 927 928 ret = i2c_add_adapter(&bus->adapter); 929 if (ret) { 930 kfree(bus); 931 goto err; 932 } 933 934 display->gmbus.bus[pin] = bus; 935 } 936 937 intel_gmbus_reset(display); 938 939 return 0; 940 941 err: 942 intel_gmbus_teardown(display); 943 944 return ret; 945 } 946 947 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, 948 unsigned int pin) 949 { 950 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || 951 !display->gmbus.bus[pin])) 952 return NULL; 953 954 return &display->gmbus.bus[pin]->adapter; 955 } 956 957 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 958 { 959 struct intel_gmbus *bus = to_intel_gmbus(adapter); 960 struct intel_display *display = bus->display; 961 962 mutex_lock(&display->gmbus.mutex); 963 964 bus->force_bit += force_bit ? 1 : -1; 965 drm_dbg_kms(display->drm, 966 "%sabling bit-banging on %s. force bit now %d\n", 967 force_bit ? "en" : "dis", adapter->name, 968 bus->force_bit); 969 970 mutex_unlock(&display->gmbus.mutex); 971 } 972 973 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 974 { 975 struct intel_gmbus *bus = to_intel_gmbus(adapter); 976 977 return bus->force_bit; 978 } 979 980 void intel_gmbus_teardown(struct intel_display *display) 981 { 982 unsigned int pin; 983 984 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 985 struct intel_gmbus *bus; 986 987 bus = display->gmbus.bus[pin]; 988 if (!bus) 989 continue; 990 991 i2c_del_adapter(&bus->adapter); 992 993 kfree(bus); 994 display->gmbus.bus[pin] = NULL; 995 } 996 } 997 998 void intel_gmbus_irq_handler(struct intel_display *display) 999 { 1000 wake_up_all(&display->gmbus.wait_queue); 1001 } 1002