1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 */ 29 30 #include <linux/export.h> 31 #include <linux/i2c-algo-bit.h> 32 #include <linux/i2c.h> 33 #include <linux/iopoll.h> 34 35 #include <drm/drm_print.h> 36 #include <drm/display/drm_hdcp_helper.h> 37 38 #include "intel_de.h" 39 #include "intel_display_regs.h" 40 #include "intel_display_types.h" 41 #include "intel_display_wa.h" 42 #include "intel_gmbus.h" 43 #include "intel_gmbus_regs.h" 44 #include "intel_parent.h" 45 46 struct intel_gmbus { 47 struct i2c_adapter adapter; 48 #define GMBUS_FORCE_BIT_RETRY (1U << 31) 49 u32 force_bit; 50 u32 reg0; 51 intel_reg_t gpio_reg; 52 struct i2c_algo_bit_data bit_algo; 53 struct intel_display *display; 54 }; 55 56 enum gmbus_gpio { 57 GPIO_0, 58 GPIO_1, 59 GPIO_2, 60 GPIO_3, 61 GPIO_4, 62 GPIO_5, 63 GPIO_6, 64 GPIO_7, 65 GPIO_8, 66 GPIO_9, 67 GPIO_10, 68 GPIO_11, 69 GPIO_12, 70 GPIO_13, 71 GPIO_14, 72 }; 73 74 struct gmbus_pin { 75 const char *name; 76 enum gmbus_gpio gpio; 77 }; 78 79 /* Map gmbus pin pairs to names and registers. */ 80 static const struct gmbus_pin gmbus_pins[] = { 81 [GMBUS_PIN_SSC] = { "ssc", GPIO_1 }, 82 [GMBUS_PIN_VGADDC] = { "vga", GPIO_0 }, 83 [GMBUS_PIN_PANEL] = { "panel", GPIO_2 }, 84 [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, 85 [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, 86 [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, 87 }; 88 89 static const struct gmbus_pin gmbus_pins_lpt_h[] = { 90 [GMBUS_PIN_VGADDC] = { "vga", GPIO_0 }, 91 [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, 92 [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, 93 [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, 94 }; 95 96 static const struct gmbus_pin gmbus_pins_lpt_lp[] = { 97 [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, 98 [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, 99 }; 100 101 static const struct gmbus_pin gmbus_pins_spt[] = { 102 [GMBUS_PIN_DPC] = { "dpc", GPIO_3 }, 103 [GMBUS_PIN_DPB] = { "dpb", GPIO_4 }, 104 [GMBUS_PIN_DPD] = { "dpd", GPIO_5 }, 105 }; 106 107 static const struct gmbus_pin gmbus_pins_bxt[] = { 108 [GMBUS_PIN_1] = { "dpb", GPIO_1 }, 109 [GMBUS_PIN_2] = { "dpc", GPIO_2 }, 110 [GMBUS_PIN_3] = { "misc", GPIO_3 }, 111 }; 112 113 static const struct gmbus_pin gmbus_pins_cnp[] = { 114 [GMBUS_PIN_1] = { "dpb", GPIO_1 }, 115 [GMBUS_PIN_2] = { "dpc", GPIO_2 }, 116 [GMBUS_PIN_3] = { "misc", GPIO_3 }, 117 [GMBUS_PIN_4] = { "dpd", GPIO_4 }, 118 }; 119 120 static const struct gmbus_pin gmbus_pins_icp[] = { 121 [GMBUS_PIN_1] = { "dpa", GPIO_1 }, 122 [GMBUS_PIN_2] = { "dpb", GPIO_2 }, 123 [GMBUS_PIN_3] = { "dpc", GPIO_3 }, 124 [GMBUS_PIN_9_TC1] = { "tc1", GPIO_9 }, 125 [GMBUS_PIN_10_TC2] = { "tc2", GPIO_10 }, 126 [GMBUS_PIN_11_TC3] = { "tc3", GPIO_11 }, 127 [GMBUS_PIN_12_TC4] = { "tc4", GPIO_12 }, 128 [GMBUS_PIN_13_TC5] = { "tc5", GPIO_13 }, 129 [GMBUS_PIN_14_TC6] = { "tc6", GPIO_14 }, 130 }; 131 132 static const struct gmbus_pin gmbus_pins_dg1[] = { 133 [GMBUS_PIN_1] = { "dpa", GPIO_1 }, 134 [GMBUS_PIN_2] = { "dpb", GPIO_2 }, 135 [GMBUS_PIN_3] = { "dpc", GPIO_3 }, 136 [GMBUS_PIN_4] = { "dpd", GPIO_4 }, 137 }; 138 139 static const struct gmbus_pin gmbus_pins_dg2[] = { 140 [GMBUS_PIN_1] = { "dpa", GPIO_1 }, 141 [GMBUS_PIN_2] = { "dpb", GPIO_2 }, 142 [GMBUS_PIN_3] = { "dpc", GPIO_3 }, 143 [GMBUS_PIN_4] = { "dpd", GPIO_4 }, 144 [GMBUS_PIN_9_TC1] = { "tc1", GPIO_9 }, 145 }; 146 147 static const struct gmbus_pin gmbus_pins_mtp[] = { 148 [GMBUS_PIN_1] = { "dpa", GPIO_1 }, 149 [GMBUS_PIN_2] = { "dpb", GPIO_2 }, 150 [GMBUS_PIN_3] = { "dpc", GPIO_3 }, 151 [GMBUS_PIN_4] = { "dpd", GPIO_4 }, 152 [GMBUS_PIN_5] = { "dpe", GPIO_5 }, 153 [GMBUS_PIN_9_TC1] = { "tc1", GPIO_9 }, 154 [GMBUS_PIN_10_TC2] = { "tc2", GPIO_10 }, 155 [GMBUS_PIN_11_TC3] = { "tc3", GPIO_11 }, 156 [GMBUS_PIN_12_TC4] = { "tc4", GPIO_12 }, 157 }; 158 159 static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display, 160 unsigned int pin) 161 { 162 const struct gmbus_pin *pins; 163 size_t size; 164 165 if (INTEL_PCH_TYPE(display) >= PCH_MTL) { 166 pins = gmbus_pins_mtp; 167 size = ARRAY_SIZE(gmbus_pins_mtp); 168 } else if (INTEL_PCH_TYPE(display) >= PCH_DG2) { 169 pins = gmbus_pins_dg2; 170 size = ARRAY_SIZE(gmbus_pins_dg2); 171 } else if (INTEL_PCH_TYPE(display) >= PCH_DG1) { 172 pins = gmbus_pins_dg1; 173 size = ARRAY_SIZE(gmbus_pins_dg1); 174 } else if (INTEL_PCH_TYPE(display) >= PCH_ICP) { 175 pins = gmbus_pins_icp; 176 size = ARRAY_SIZE(gmbus_pins_icp); 177 } else if (HAS_PCH_CNP(display)) { 178 pins = gmbus_pins_cnp; 179 size = ARRAY_SIZE(gmbus_pins_cnp); 180 } else if (display->platform.geminilake || display->platform.broxton) { 181 pins = gmbus_pins_bxt; 182 size = ARRAY_SIZE(gmbus_pins_bxt); 183 } else if (HAS_PCH_SPT(display)) { 184 pins = gmbus_pins_spt; 185 size = ARRAY_SIZE(gmbus_pins_spt); 186 } else if (HAS_PCH_LPT_LP(display)) { 187 pins = gmbus_pins_lpt_lp; 188 size = ARRAY_SIZE(gmbus_pins_lpt_lp); 189 } else if (HAS_PCH_LPT(display)) { 190 pins = gmbus_pins_lpt_h; 191 size = ARRAY_SIZE(gmbus_pins_lpt_h); 192 } else { 193 pins = gmbus_pins; 194 size = ARRAY_SIZE(gmbus_pins); 195 } 196 197 if (pin >= size || !pins[pin].name) 198 return NULL; 199 200 return &pins[pin]; 201 } 202 203 bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin) 204 { 205 return get_gmbus_pin(display, pin); 206 } 207 208 /* Intel GPIO access functions */ 209 210 #define I2C_RISEFALL_TIME 10 211 212 static inline struct intel_gmbus * 213 to_intel_gmbus(struct i2c_adapter *i2c) 214 { 215 return container_of(i2c, struct intel_gmbus, adapter); 216 } 217 218 void 219 intel_gmbus_reset(struct intel_display *display) 220 { 221 intel_de_write(display, GMBUS0(display), 0); 222 intel_de_write(display, GMBUS4(display), 0); 223 } 224 225 static void pnv_gmbus_clock_gating(struct intel_display *display, 226 bool enable) 227 { 228 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 229 intel_de_rmw(display, DSPCLK_GATE_D, 230 PNV_GMBUSUNIT_CLOCK_GATE_DISABLE, 231 !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 232 } 233 234 static void pch_gmbus_clock_gating(struct intel_display *display, 235 bool enable) 236 { 237 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 238 PCH_GMBUSUNIT_CLOCK_GATE_DISABLE, 239 !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0); 240 } 241 242 static void bxt_gmbus_clock_gating(struct intel_display *display, 243 bool enable) 244 { 245 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS, 246 !enable ? BXT_GMBUS_GATING_DIS : 0); 247 } 248 249 static u32 get_reserved(struct intel_gmbus *bus) 250 { 251 struct intel_display *display = bus->display; 252 u32 preserve_bits = 0; 253 254 if (display->platform.i830 || display->platform.i845g) 255 return 0; 256 257 /* On most chips, these bits must be preserved in software. */ 258 preserve_bits |= GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE; 259 260 /* Wa_16025573575: the masks bits need to be preserved through out */ 261 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 262 preserve_bits |= GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 263 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 264 265 return intel_de_read_notrace(display, bus->gpio_reg) & preserve_bits; 266 } 267 268 static int get_clock(void *data) 269 { 270 struct intel_gmbus *bus = data; 271 struct intel_display *display = bus->display; 272 u32 reserved = get_reserved(bus); 273 274 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK); 275 intel_de_write_notrace(display, bus->gpio_reg, reserved); 276 277 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0; 278 } 279 280 static int get_data(void *data) 281 { 282 struct intel_gmbus *bus = data; 283 struct intel_display *display = bus->display; 284 u32 reserved = get_reserved(bus); 285 286 intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK); 287 intel_de_write_notrace(display, bus->gpio_reg, reserved); 288 289 return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0; 290 } 291 292 static void set_clock(void *data, int state_high) 293 { 294 struct intel_gmbus *bus = data; 295 struct intel_display *display = bus->display; 296 u32 reserved = get_reserved(bus); 297 u32 clock_bits; 298 299 if (state_high) 300 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 301 else 302 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 303 GPIO_CLOCK_VAL_MASK; 304 305 intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits); 306 intel_de_posting_read(display, bus->gpio_reg); 307 } 308 309 static void set_data(void *data, int state_high) 310 { 311 struct intel_gmbus *bus = data; 312 struct intel_display *display = bus->display; 313 u32 reserved = get_reserved(bus); 314 u32 data_bits; 315 316 if (state_high) 317 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 318 else 319 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 320 GPIO_DATA_VAL_MASK; 321 322 intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits); 323 intel_de_posting_read(display, bus->gpio_reg); 324 } 325 326 static void 327 ptl_handle_mask_bits(struct intel_gmbus *bus, bool set) 328 { 329 struct intel_display *display = bus->display; 330 u32 reg_val = intel_de_read_notrace(display, bus->gpio_reg); 331 u32 mask_bits = GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK | 332 GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; 333 if (set) 334 reg_val |= mask_bits; 335 else 336 reg_val &= ~mask_bits; 337 338 intel_de_write_notrace(display, bus->gpio_reg, reg_val); 339 intel_de_posting_read(display, bus->gpio_reg); 340 } 341 342 static int 343 intel_gpio_pre_xfer(struct i2c_adapter *adapter) 344 { 345 struct intel_gmbus *bus = to_intel_gmbus(adapter); 346 struct intel_display *display = bus->display; 347 348 intel_gmbus_reset(display); 349 350 if (display->platform.pineview) 351 pnv_gmbus_clock_gating(display, false); 352 353 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 354 ptl_handle_mask_bits(bus, true); 355 356 set_data(bus, 1); 357 set_clock(bus, 1); 358 udelay(I2C_RISEFALL_TIME); 359 return 0; 360 } 361 362 static void 363 intel_gpio_post_xfer(struct i2c_adapter *adapter) 364 { 365 struct intel_gmbus *bus = to_intel_gmbus(adapter); 366 struct intel_display *display = bus->display; 367 368 set_data(bus, 1); 369 set_clock(bus, 1); 370 371 if (display->platform.pineview) 372 pnv_gmbus_clock_gating(display, true); 373 374 if (intel_display_wa(display, INTEL_DISPLAY_WA_16025573575)) 375 ptl_handle_mask_bits(bus, false); 376 } 377 378 static void 379 intel_gpio_setup(struct intel_gmbus *bus, intel_reg_t gpio_reg) 380 { 381 struct i2c_algo_bit_data *algo; 382 383 algo = &bus->bit_algo; 384 385 bus->gpio_reg = gpio_reg; 386 bus->adapter.algo_data = algo; 387 algo->setsda = set_data; 388 algo->setscl = set_clock; 389 algo->getsda = get_data; 390 algo->getscl = get_clock; 391 algo->pre_xfer = intel_gpio_pre_xfer; 392 algo->post_xfer = intel_gpio_post_xfer; 393 algo->udelay = I2C_RISEFALL_TIME; 394 algo->timeout = usecs_to_jiffies(2200); 395 algo->data = bus; 396 } 397 398 static bool has_gmbus_irq(struct intel_display *display) 399 { 400 /* 401 * encoder->shutdown() may want to use GMBUS 402 * after irqs have already been disabled. 403 */ 404 return HAS_GMBUS_IRQ(display) && intel_parent_irq_enabled(display); 405 } 406 407 static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en) 408 { 409 DEFINE_WAIT(wait); 410 u32 gmbus2; 411 int ret; 412 413 /* Important: The hw handles only the first bit, so set only one! Since 414 * we also need to check for NAKs besides the hw ready/idle signal, we 415 * need to wake up periodically and check that ourselves. 416 */ 417 if (!has_gmbus_irq(display)) 418 irq_en = 0; 419 420 add_wait_queue(&display->gmbus.wait_queue, &wait); 421 intel_de_write_fw(display, GMBUS4(display), irq_en); 422 423 status |= GMBUS_SATOER; 424 425 ret = poll_timeout_us_atomic(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 426 gmbus2 & status, 427 0, 2, false); 428 if (ret) 429 ret = poll_timeout_us(gmbus2 = intel_de_read_fw(display, GMBUS2(display)), 430 gmbus2 & status, 431 500, 50 * 1000, false); 432 433 intel_de_write_fw(display, GMBUS4(display), 0); 434 remove_wait_queue(&display->gmbus.wait_queue, &wait); 435 436 if (gmbus2 & GMBUS_SATOER) 437 return -ENXIO; 438 439 return ret; 440 } 441 442 static int 443 gmbus_wait_idle(struct intel_display *display) 444 { 445 DEFINE_WAIT(wait); 446 u32 irq_enable; 447 int ret; 448 449 /* Important: The hw handles only the first bit, so set only one! */ 450 irq_enable = 0; 451 if (has_gmbus_irq(display)) 452 irq_enable = GMBUS_IDLE_EN; 453 454 add_wait_queue(&display->gmbus.wait_queue, &wait); 455 intel_de_write_fw(display, GMBUS4(display), irq_enable); 456 457 ret = intel_de_wait_fw_ms(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10, NULL); 458 459 intel_de_write_fw(display, GMBUS4(display), 0); 460 remove_wait_queue(&display->gmbus.wait_queue, &wait); 461 462 return ret; 463 } 464 465 static unsigned int gmbus_max_xfer_size(struct intel_display *display) 466 { 467 return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : 468 GMBUS_BYTE_COUNT_MAX; 469 } 470 471 static int 472 gmbus_xfer_read_chunk(struct intel_display *display, 473 unsigned short addr, u8 *buf, unsigned int len, 474 u32 gmbus0_reg, u32 gmbus1_index) 475 { 476 unsigned int size = len; 477 bool burst_read = len > gmbus_max_xfer_size(display); 478 bool extra_byte_added = false; 479 480 if (burst_read) { 481 /* 482 * As per HW Spec, for 512Bytes need to read extra Byte and 483 * Ignore the extra byte read. 484 */ 485 if (len == 512) { 486 extra_byte_added = true; 487 len++; 488 } 489 size = len % 256 + 256; 490 intel_de_write_fw(display, GMBUS0(display), 491 gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE); 492 } 493 494 intel_de_write_fw(display, GMBUS1(display), 495 gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); 496 while (len) { 497 int ret; 498 u32 val, loop = 0; 499 500 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 501 if (ret) 502 return ret; 503 504 val = intel_de_read_fw(display, GMBUS3(display)); 505 do { 506 if (extra_byte_added && len == 1) { 507 len--; 508 break; 509 } 510 511 *buf++ = val & 0xff; 512 val >>= 8; 513 } while (--len && ++loop < 4); 514 515 if (burst_read && len == size - 4) 516 /* Reset the override bit */ 517 intel_de_write_fw(display, GMBUS0(display), gmbus0_reg); 518 } 519 520 return 0; 521 } 522 523 /* 524 * HW spec says that 512Bytes in Burst read need special treatment. 525 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate 526 * an I2C target, which supports such a lengthy burst read too for experiments. 527 * 528 * So until things get clarified on HW support, to avoid the burst read length 529 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes. 530 */ 531 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U 532 533 static int 534 gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg, 535 u32 gmbus0_reg, u32 gmbus1_index) 536 { 537 u8 *buf = msg->buf; 538 unsigned int rx_size = msg->len; 539 unsigned int len; 540 int ret; 541 542 do { 543 if (HAS_GMBUS_BURST_READ(display)) 544 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN); 545 else 546 len = min(rx_size, gmbus_max_xfer_size(display)); 547 548 ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len, 549 gmbus0_reg, gmbus1_index); 550 if (ret) 551 return ret; 552 553 rx_size -= len; 554 buf += len; 555 } while (rx_size != 0); 556 557 return 0; 558 } 559 560 static int 561 gmbus_xfer_write_chunk(struct intel_display *display, 562 unsigned short addr, u8 *buf, unsigned int len, 563 u32 gmbus1_index) 564 { 565 unsigned int chunk_size = len; 566 u32 val, loop; 567 568 val = loop = 0; 569 while (len && loop < 4) { 570 val |= *buf++ << (8 * loop++); 571 len -= 1; 572 } 573 574 intel_de_write_fw(display, GMBUS3(display), val); 575 intel_de_write_fw(display, GMBUS1(display), 576 gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 577 while (len) { 578 int ret; 579 580 val = loop = 0; 581 do { 582 val |= *buf++ << (8 * loop); 583 } while (--len && ++loop < 4); 584 585 intel_de_write_fw(display, GMBUS3(display), val); 586 587 ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN); 588 if (ret) 589 return ret; 590 } 591 592 return 0; 593 } 594 595 static int 596 gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg, 597 u32 gmbus1_index) 598 { 599 u8 *buf = msg->buf; 600 unsigned int tx_size = msg->len; 601 unsigned int len; 602 int ret; 603 604 do { 605 len = min(tx_size, gmbus_max_xfer_size(display)); 606 607 ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len, 608 gmbus1_index); 609 if (ret) 610 return ret; 611 612 buf += len; 613 tx_size -= len; 614 } while (tx_size != 0); 615 616 return 0; 617 } 618 619 /* 620 * The gmbus controller can combine a 1 or 2 byte write with another read/write 621 * that immediately follows it by using an "INDEX" cycle. 622 */ 623 static bool 624 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num) 625 { 626 return (i + 1 < num && 627 msgs[i].addr == msgs[i + 1].addr && 628 !(msgs[i].flags & I2C_M_RD) && 629 (msgs[i].len == 1 || msgs[i].len == 2) && 630 msgs[i + 1].len > 0); 631 } 632 633 static int 634 gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs, 635 u32 gmbus0_reg) 636 { 637 u32 gmbus1_index = 0; 638 u32 gmbus5 = 0; 639 int ret; 640 641 if (msgs[0].len == 2) 642 gmbus5 = GMBUS_2BYTE_INDEX_EN | 643 msgs[0].buf[1] | (msgs[0].buf[0] << 8); 644 if (msgs[0].len == 1) 645 gmbus1_index = GMBUS_CYCLE_INDEX | 646 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT); 647 648 /* GMBUS5 holds 16-bit index */ 649 if (gmbus5) 650 intel_de_write_fw(display, GMBUS5(display), gmbus5); 651 652 if (msgs[1].flags & I2C_M_RD) 653 ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg, 654 gmbus1_index); 655 else 656 ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index); 657 658 /* Clear GMBUS5 after each index transfer */ 659 if (gmbus5) 660 intel_de_write_fw(display, GMBUS5(display), 0); 661 662 return ret; 663 } 664 665 static int 666 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, 667 u32 gmbus0_source) 668 { 669 struct intel_gmbus *bus = to_intel_gmbus(adapter); 670 struct intel_display *display = bus->display; 671 int i = 0, inc, try = 0; 672 int ret = 0; 673 674 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 675 if (display->platform.geminilake || display->platform.broxton) 676 bxt_gmbus_clock_gating(display, false); 677 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 678 pch_gmbus_clock_gating(display, false); 679 680 retry: 681 intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0); 682 683 for (; i < num; i += inc) { 684 inc = 1; 685 if (gmbus_is_index_xfer(msgs, i, num)) { 686 ret = gmbus_index_xfer(display, &msgs[i], 687 gmbus0_source | bus->reg0); 688 inc = 2; /* an index transmission is two msgs */ 689 } else if (msgs[i].flags & I2C_M_RD) { 690 ret = gmbus_xfer_read(display, &msgs[i], 691 gmbus0_source | bus->reg0, 0); 692 } else { 693 ret = gmbus_xfer_write(display, &msgs[i], 0); 694 } 695 696 if (!ret) 697 ret = gmbus_wait(display, 698 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN); 699 if (ret == -ETIMEDOUT) 700 goto timeout; 701 else if (ret) 702 goto clear_err; 703 } 704 705 /* Generate a STOP condition on the bus. Note that gmbus can't generate 706 * a STOP on the very first cycle. To simplify the code we 707 * unconditionally generate the STOP condition with an additional gmbus 708 * cycle. */ 709 intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY); 710 711 /* Mark the GMBUS interface as disabled after waiting for idle. 712 * We will re-enable it at the start of the next xfer, 713 * till then let it sleep. 714 */ 715 if (gmbus_wait_idle(display)) { 716 drm_dbg_kms(display->drm, 717 "GMBUS [%s] timed out waiting for idle\n", 718 adapter->name); 719 ret = -ETIMEDOUT; 720 } 721 intel_de_write_fw(display, GMBUS0(display), 0); 722 ret = ret ?: i; 723 goto out; 724 725 clear_err: 726 /* 727 * Wait for bus to IDLE before clearing NAK. 728 * If we clear the NAK while bus is still active, then it will stay 729 * active and the next transaction may fail. 730 * 731 * If no ACK is received during the address phase of a transaction, the 732 * adapter must report -ENXIO. It is not clear what to return if no ACK 733 * is received at other times. But we have to be careful to not return 734 * spurious -ENXIO because that will prevent i2c and drm edid functions 735 * from retrying. So return -ENXIO only when gmbus properly quiescents - 736 * timing out seems to happen when there _is_ a ddc chip present, but 737 * it's slow responding and only answers on the 2nd retry. 738 */ 739 ret = -ENXIO; 740 if (gmbus_wait_idle(display)) { 741 drm_dbg_kms(display->drm, 742 "GMBUS [%s] timed out after NAK\n", 743 adapter->name); 744 ret = -ETIMEDOUT; 745 } 746 747 /* Toggle the Software Clear Interrupt bit. This has the effect 748 * of resetting the GMBUS controller and so clearing the 749 * BUS_ERROR raised by the target's NAK. 750 */ 751 intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT); 752 intel_de_write_fw(display, GMBUS1(display), 0); 753 intel_de_write_fw(display, GMBUS0(display), 0); 754 755 drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n", 756 adapter->name, msgs[i].addr, 757 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len); 758 759 /* 760 * Passive adapters sometimes NAK the first probe. Retry the first 761 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm 762 * has retries internally. See also the retry loop in 763 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO. 764 */ 765 if (ret == -ENXIO && i == 0 && try++ == 0) { 766 drm_dbg_kms(display->drm, 767 "GMBUS [%s] NAK on first message, retry\n", 768 adapter->name); 769 goto retry; 770 } 771 772 goto out; 773 774 timeout: 775 drm_dbg_kms(display->drm, 776 "GMBUS [%s] timed out, falling back to bit banging on pin %d\n", 777 bus->adapter.name, bus->reg0 & 0xff); 778 intel_de_write_fw(display, GMBUS0(display), 0); 779 780 /* 781 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging 782 * instead. Use EAGAIN to have i2c core retry. 783 */ 784 ret = -EAGAIN; 785 786 out: 787 /* Display WA #0868: skl,bxt,kbl,cfl,glk */ 788 if (display->platform.geminilake || display->platform.broxton) 789 bxt_gmbus_clock_gating(display, true); 790 else if (HAS_PCH_SPT(display) || HAS_PCH_CNP(display)) 791 pch_gmbus_clock_gating(display, true); 792 793 return ret; 794 } 795 796 static int 797 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num) 798 { 799 struct intel_gmbus *bus = to_intel_gmbus(adapter); 800 struct intel_display *display = bus->display; 801 struct ref_tracker *wakeref; 802 int ret; 803 804 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 805 806 if (bus->force_bit) { 807 ret = i2c_bit_algo.master_xfer(adapter, msgs, num); 808 if (ret < 0) 809 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY; 810 } else { 811 ret = do_gmbus_xfer(adapter, msgs, num, 0); 812 if (ret == -EAGAIN) 813 bus->force_bit |= GMBUS_FORCE_BIT_RETRY; 814 } 815 816 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 817 818 return ret; 819 } 820 821 int intel_gmbus_output_aksv(struct i2c_adapter *adapter) 822 { 823 struct intel_gmbus *bus = to_intel_gmbus(adapter); 824 struct intel_display *display = bus->display; 825 u8 cmd = DRM_HDCP_DDC_AKSV; 826 u8 buf[DRM_HDCP_KSV_LEN] = {}; 827 struct i2c_msg msgs[] = { 828 { 829 .addr = DRM_HDCP_DDC_ADDR, 830 .flags = 0, 831 .len = sizeof(cmd), 832 .buf = &cmd, 833 }, 834 { 835 .addr = DRM_HDCP_DDC_ADDR, 836 .flags = 0, 837 .len = sizeof(buf), 838 .buf = buf, 839 } 840 }; 841 struct ref_tracker *wakeref; 842 int ret; 843 844 wakeref = intel_display_power_get(display, POWER_DOMAIN_GMBUS); 845 mutex_lock(&display->gmbus.mutex); 846 847 /* 848 * In order to output Aksv to the receiver, use an indexed write to 849 * pass the i2c command, and tell GMBUS to use the HW-provided value 850 * instead of sourcing GMBUS3 for the data. 851 */ 852 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT); 853 854 mutex_unlock(&display->gmbus.mutex); 855 intel_display_power_put(display, POWER_DOMAIN_GMBUS, wakeref); 856 857 return ret; 858 } 859 860 static u32 gmbus_func(struct i2c_adapter *adapter) 861 { 862 return i2c_bit_algo.functionality(adapter) & 863 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 864 /* I2C_FUNC_10BIT_ADDR | */ 865 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 866 I2C_FUNC_SMBUS_BLOCK_PROC_CALL); 867 } 868 869 static const struct i2c_algorithm gmbus_algorithm = { 870 .master_xfer = gmbus_xfer, 871 .functionality = gmbus_func 872 }; 873 874 static void gmbus_lock_bus(struct i2c_adapter *adapter, 875 unsigned int flags) 876 { 877 struct intel_gmbus *bus = to_intel_gmbus(adapter); 878 struct intel_display *display = bus->display; 879 880 mutex_lock(&display->gmbus.mutex); 881 } 882 883 static int gmbus_trylock_bus(struct i2c_adapter *adapter, 884 unsigned int flags) 885 { 886 struct intel_gmbus *bus = to_intel_gmbus(adapter); 887 struct intel_display *display = bus->display; 888 889 return mutex_trylock(&display->gmbus.mutex); 890 } 891 892 static void gmbus_unlock_bus(struct i2c_adapter *adapter, 893 unsigned int flags) 894 { 895 struct intel_gmbus *bus = to_intel_gmbus(adapter); 896 struct intel_display *display = bus->display; 897 898 mutex_unlock(&display->gmbus.mutex); 899 } 900 901 static const struct i2c_lock_operations gmbus_lock_ops = { 902 .lock_bus = gmbus_lock_bus, 903 .trylock_bus = gmbus_trylock_bus, 904 .unlock_bus = gmbus_unlock_bus, 905 }; 906 907 /** 908 * intel_gmbus_setup - instantiate all Intel i2c GMBuses 909 * @display: display device 910 */ 911 int intel_gmbus_setup(struct intel_display *display) 912 { 913 struct pci_dev *pdev = to_pci_dev(display->drm->dev); 914 unsigned int pin; 915 int ret; 916 917 if (display->platform.valleyview || display->platform.cherryview) 918 display->gmbus.mmio_base = VLV_DISPLAY_BASE; 919 else if (!HAS_GMCH(display)) 920 /* 921 * Broxton uses the same PCH offsets for South Display Engine, 922 * even though it doesn't have a PCH. 923 */ 924 display->gmbus.mmio_base = PCH_DISPLAY_BASE; 925 926 mutex_init(&display->gmbus.mutex); 927 init_waitqueue_head(&display->gmbus.wait_queue); 928 929 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 930 const struct gmbus_pin *gmbus_pin; 931 struct intel_gmbus *bus; 932 933 gmbus_pin = get_gmbus_pin(display, pin); 934 if (!gmbus_pin) 935 continue; 936 937 bus = kzalloc_obj(*bus); 938 if (!bus) { 939 ret = -ENOMEM; 940 goto err; 941 } 942 943 bus->adapter.owner = THIS_MODULE; 944 snprintf(bus->adapter.name, 945 sizeof(bus->adapter.name), 946 "i915 gmbus %s", gmbus_pin->name); 947 948 bus->adapter.dev.parent = &pdev->dev; 949 bus->display = display; 950 951 bus->adapter.algo = &gmbus_algorithm; 952 bus->adapter.lock_ops = &gmbus_lock_ops; 953 954 /* 955 * We wish to retry with bit banging 956 * after a timed out GMBUS attempt. 957 */ 958 bus->adapter.retries = 1; 959 960 /* By default use a conservative clock rate */ 961 bus->reg0 = pin | GMBUS_RATE_100KHZ; 962 963 /* gmbus seems to be broken on i830 */ 964 if (display->platform.i830) 965 bus->force_bit = 1; 966 967 intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio)); 968 969 ret = i2c_add_adapter(&bus->adapter); 970 if (ret) { 971 kfree(bus); 972 goto err; 973 } 974 975 display->gmbus.bus[pin] = bus; 976 } 977 978 intel_gmbus_reset(display); 979 980 return 0; 981 982 err: 983 intel_gmbus_teardown(display); 984 985 return ret; 986 } 987 988 struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display, 989 unsigned int pin) 990 { 991 if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) || 992 !display->gmbus.bus[pin])) 993 return NULL; 994 995 return &display->gmbus.bus[pin]->adapter; 996 } 997 998 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) 999 { 1000 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1001 struct intel_display *display = bus->display; 1002 1003 mutex_lock(&display->gmbus.mutex); 1004 1005 bus->force_bit += force_bit ? 1 : -1; 1006 drm_dbg_kms(display->drm, 1007 "%sabling bit-banging on %s. force bit now %d\n", 1008 force_bit ? "en" : "dis", adapter->name, 1009 bus->force_bit); 1010 1011 mutex_unlock(&display->gmbus.mutex); 1012 } 1013 1014 bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) 1015 { 1016 struct intel_gmbus *bus = to_intel_gmbus(adapter); 1017 1018 return bus->force_bit; 1019 } 1020 1021 void intel_gmbus_teardown(struct intel_display *display) 1022 { 1023 unsigned int pin; 1024 1025 for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) { 1026 struct intel_gmbus *bus; 1027 1028 bus = display->gmbus.bus[pin]; 1029 if (!bus) 1030 continue; 1031 1032 i2c_del_adapter(&bus->adapter); 1033 1034 kfree(bus); 1035 display->gmbus.bus[pin] = NULL; 1036 } 1037 } 1038 1039 void intel_gmbus_irq_handler(struct intel_display *display) 1040 { 1041 wake_up_all(&display->gmbus.wait_queue); 1042 } 1043