1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/string_helpers.h> 7 8 #include "i915_reg.h" 9 #include "intel_atomic.h" 10 #include "intel_crtc.h" 11 #include "intel_ddi.h" 12 #include "intel_de.h" 13 #include "intel_display_types.h" 14 #include "intel_fdi.h" 15 #include "intel_fdi_regs.h" 16 #include "intel_link_bw.h" 17 18 struct intel_fdi_funcs { 19 void (*fdi_link_train)(struct intel_crtc *crtc, 20 const struct intel_crtc_state *crtc_state); 21 }; 22 23 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 24 enum pipe pipe, bool state) 25 { 26 bool cur_state; 27 28 if (HAS_DDI(dev_priv)) { 29 /* 30 * DDI does not have a specific FDI_TX register. 31 * 32 * FDI is never fed from EDP transcoder 33 * so pipe->transcoder cast is fine here. 34 */ 35 enum transcoder cpu_transcoder = (enum transcoder)pipe; 36 cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; 37 } else { 38 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; 39 } 40 I915_STATE_WARN(dev_priv, cur_state != state, 41 "FDI TX state assertion failure (expected %s, current %s)\n", 42 str_on_off(state), str_on_off(cur_state)); 43 } 44 45 void assert_fdi_tx_enabled(struct drm_i915_private *i915, enum pipe pipe) 46 { 47 assert_fdi_tx(i915, pipe, true); 48 } 49 50 void assert_fdi_tx_disabled(struct drm_i915_private *i915, enum pipe pipe) 51 { 52 assert_fdi_tx(i915, pipe, false); 53 } 54 55 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 56 enum pipe pipe, bool state) 57 { 58 bool cur_state; 59 60 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; 61 I915_STATE_WARN(dev_priv, cur_state != state, 62 "FDI RX state assertion failure (expected %s, current %s)\n", 63 str_on_off(state), str_on_off(cur_state)); 64 } 65 66 void assert_fdi_rx_enabled(struct drm_i915_private *i915, enum pipe pipe) 67 { 68 assert_fdi_rx(i915, pipe, true); 69 } 70 71 void assert_fdi_rx_disabled(struct drm_i915_private *i915, enum pipe pipe) 72 { 73 assert_fdi_rx(i915, pipe, false); 74 } 75 76 void assert_fdi_tx_pll_enabled(struct drm_i915_private *i915, 77 enum pipe pipe) 78 { 79 bool cur_state; 80 81 /* ILK FDI PLL is always enabled */ 82 if (IS_IRONLAKE(i915)) 83 return; 84 85 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 86 if (HAS_DDI(i915)) 87 return; 88 89 cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; 90 I915_STATE_WARN(i915, !cur_state, 91 "FDI TX PLL assertion failure, should be active but is disabled\n"); 92 } 93 94 static void assert_fdi_rx_pll(struct drm_i915_private *i915, 95 enum pipe pipe, bool state) 96 { 97 bool cur_state; 98 99 cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; 100 I915_STATE_WARN(i915, cur_state != state, 101 "FDI RX PLL assertion failure (expected %s, current %s)\n", 102 str_on_off(state), str_on_off(cur_state)); 103 } 104 105 void assert_fdi_rx_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 106 { 107 assert_fdi_rx_pll(i915, pipe, true); 108 } 109 110 void assert_fdi_rx_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 111 { 112 assert_fdi_rx_pll(i915, pipe, false); 113 } 114 115 void intel_fdi_link_train(struct intel_crtc *crtc, 116 const struct intel_crtc_state *crtc_state) 117 { 118 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 119 120 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); 121 } 122 123 /** 124 * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs 125 * @state: intel atomic state 126 * 127 * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is 128 * known to affect the available FDI BW for the former CRTC. In practice this 129 * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by 130 * CRTC C) and CRTC C is getting disabled. 131 * 132 * Returns 0 in case of success, or a negative error code otherwise. 133 */ 134 int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state) 135 { 136 struct drm_i915_private *i915 = to_i915(state->base.dev); 137 const struct intel_crtc_state *old_crtc_state; 138 const struct intel_crtc_state *new_crtc_state; 139 struct intel_crtc *crtc; 140 141 if (!IS_IVYBRIDGE(i915) || INTEL_NUM_PIPES(i915) != 3) 142 return 0; 143 144 crtc = intel_crtc_for_pipe(i915, PIPE_C); 145 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 146 if (!new_crtc_state) 147 return 0; 148 149 if (!intel_crtc_needs_modeset(new_crtc_state)) 150 return 0; 151 152 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 153 if (!old_crtc_state->fdi_lanes) 154 return 0; 155 156 crtc = intel_crtc_for_pipe(i915, PIPE_B); 157 new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 158 if (IS_ERR(new_crtc_state)) 159 return PTR_ERR(new_crtc_state); 160 161 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 162 if (!old_crtc_state->fdi_lanes) 163 return 0; 164 165 return intel_modeset_pipes_in_mask_early(state, 166 "FDI link BW decrease on pipe C", 167 BIT(PIPE_B)); 168 } 169 170 /* units of 100MHz */ 171 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) 172 { 173 if (crtc_state->hw.enable && crtc_state->has_pch_encoder) 174 return crtc_state->fdi_lanes; 175 176 return 0; 177 } 178 179 static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, 180 struct intel_crtc_state *pipe_config, 181 enum pipe *pipe_to_reduce) 182 { 183 struct drm_i915_private *dev_priv = to_i915(dev); 184 struct drm_atomic_state *state = pipe_config->uapi.state; 185 struct intel_crtc *other_crtc; 186 struct intel_crtc_state *other_crtc_state; 187 188 *pipe_to_reduce = pipe; 189 190 drm_dbg_kms(&dev_priv->drm, 191 "checking fdi config on pipe %c, lanes %i\n", 192 pipe_name(pipe), pipe_config->fdi_lanes); 193 if (pipe_config->fdi_lanes > 4) { 194 drm_dbg_kms(&dev_priv->drm, 195 "invalid fdi lane config on pipe %c: %i lanes\n", 196 pipe_name(pipe), pipe_config->fdi_lanes); 197 return -EINVAL; 198 } 199 200 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 201 if (pipe_config->fdi_lanes > 2) { 202 drm_dbg_kms(&dev_priv->drm, 203 "only 2 lanes on haswell, required: %i lanes\n", 204 pipe_config->fdi_lanes); 205 return -EINVAL; 206 } else { 207 return 0; 208 } 209 } 210 211 if (INTEL_NUM_PIPES(dev_priv) == 2) 212 return 0; 213 214 /* Ivybridge 3 pipe is really complicated */ 215 switch (pipe) { 216 case PIPE_A: 217 return 0; 218 case PIPE_B: 219 if (pipe_config->fdi_lanes <= 2) 220 return 0; 221 222 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_C); 223 other_crtc_state = 224 intel_atomic_get_crtc_state(state, other_crtc); 225 if (IS_ERR(other_crtc_state)) 226 return PTR_ERR(other_crtc_state); 227 228 if (pipe_required_fdi_lanes(other_crtc_state) > 0) { 229 drm_dbg_kms(&dev_priv->drm, 230 "invalid shared fdi lane config on pipe %c: %i lanes\n", 231 pipe_name(pipe), pipe_config->fdi_lanes); 232 return -EINVAL; 233 } 234 return 0; 235 case PIPE_C: 236 if (pipe_config->fdi_lanes > 2) { 237 drm_dbg_kms(&dev_priv->drm, 238 "only 2 lanes on pipe %c: required %i lanes\n", 239 pipe_name(pipe), pipe_config->fdi_lanes); 240 return -EINVAL; 241 } 242 243 other_crtc = intel_crtc_for_pipe(dev_priv, PIPE_B); 244 other_crtc_state = 245 intel_atomic_get_crtc_state(state, other_crtc); 246 if (IS_ERR(other_crtc_state)) 247 return PTR_ERR(other_crtc_state); 248 249 if (pipe_required_fdi_lanes(other_crtc_state) > 2) { 250 drm_dbg_kms(&dev_priv->drm, 251 "fdi link B uses too many lanes to enable link C\n"); 252 253 *pipe_to_reduce = PIPE_B; 254 255 return -EINVAL; 256 } 257 return 0; 258 default: 259 MISSING_CASE(pipe); 260 return 0; 261 } 262 } 263 264 void intel_fdi_pll_freq_update(struct drm_i915_private *i915) 265 { 266 if (IS_IRONLAKE(i915)) { 267 u32 fdi_pll_clk = 268 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; 269 270 i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000; 271 } else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) { 272 i915->display.fdi.pll_freq = 270000; 273 } else { 274 return; 275 } 276 277 drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq); 278 } 279 280 int intel_fdi_link_freq(struct drm_i915_private *i915, 281 const struct intel_crtc_state *pipe_config) 282 { 283 if (HAS_DDI(i915)) 284 return pipe_config->port_clock; /* SPLL */ 285 else 286 return i915->display.fdi.pll_freq; 287 } 288 289 /** 290 * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp 291 * @crtc_state: the crtc state 292 * 293 * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can 294 * call this function during state computation in the simple case where the 295 * link bpp will always match the pipe bpp. This is the case for all non-DP 296 * encoders, while DP encoders will use a link bpp lower than pipe bpp in case 297 * of DSC compression. 298 * 299 * Returns %true in case of success, %false if pipe bpp would need to be 300 * reduced below its valid range. 301 */ 302 bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state) 303 { 304 int pipe_bpp = min(crtc_state->pipe_bpp, 305 to_bpp_int(crtc_state->max_link_bpp_x16)); 306 307 pipe_bpp = rounddown(pipe_bpp, 2 * 3); 308 309 if (pipe_bpp < 6 * 3) 310 return false; 311 312 crtc_state->pipe_bpp = pipe_bpp; 313 314 return true; 315 } 316 317 int ilk_fdi_compute_config(struct intel_crtc *crtc, 318 struct intel_crtc_state *pipe_config) 319 { 320 struct drm_device *dev = crtc->base.dev; 321 struct drm_i915_private *i915 = to_i915(dev); 322 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 323 int lane, link_bw, fdi_dotclock; 324 325 /* FDI is a binary signal running at ~2.7GHz, encoding 326 * each output octet as 10 bits. The actual frequency 327 * is stored as a divider into a 100MHz clock, and the 328 * mode pixel clock is stored in units of 1KHz. 329 * Hence the bw of each lane in terms of the mode signal 330 * is: 331 */ 332 link_bw = intel_fdi_link_freq(i915, pipe_config); 333 334 fdi_dotclock = adjusted_mode->crtc_clock; 335 336 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, 337 pipe_config->pipe_bpp); 338 339 pipe_config->fdi_lanes = lane; 340 341 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, 342 link_bw, &pipe_config->fdi_m_n, false); 343 344 return 0; 345 } 346 347 static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state, 348 struct intel_crtc *crtc, 349 struct intel_crtc_state *pipe_config, 350 struct intel_link_bw_limits *limits) 351 { 352 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 353 enum pipe pipe_to_reduce; 354 int ret; 355 356 ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config, 357 &pipe_to_reduce); 358 if (ret != -EINVAL) 359 return ret; 360 361 ret = intel_link_bw_reduce_bpp(state, limits, 362 BIT(pipe_to_reduce), 363 "FDI link BW"); 364 365 return ret ? : -EAGAIN; 366 } 367 368 /** 369 * intel_fdi_atomic_check_link - check all modeset FDI link configuration 370 * @state: intel atomic state 371 * @limits: link BW limits 372 * 373 * Check the link configuration for all modeset FDI outputs. If the 374 * configuration is invalid @limits will be updated if possible to 375 * reduce the total BW, after which the configuration for all CRTCs in 376 * @state must be recomputed with the updated @limits. 377 * 378 * Returns: 379 * - 0 if the confugration is valid 380 * - %-EAGAIN, if the configuration is invalid and @limits got updated 381 * with fallback values with which the configuration of all CRTCs 382 * in @state must be recomputed 383 * - Other negative error, if the configuration is invalid without a 384 * fallback possibility, or the check failed for another reason 385 */ 386 int intel_fdi_atomic_check_link(struct intel_atomic_state *state, 387 struct intel_link_bw_limits *limits) 388 { 389 struct intel_crtc *crtc; 390 struct intel_crtc_state *crtc_state; 391 int i; 392 393 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { 394 int ret; 395 396 if (!crtc_state->has_pch_encoder || 397 !intel_crtc_needs_modeset(crtc_state) || 398 !crtc_state->hw.enable) 399 continue; 400 401 ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits); 402 if (ret) 403 return ret; 404 } 405 406 return 0; 407 } 408 409 static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable) 410 { 411 u32 temp; 412 413 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); 414 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) 415 return; 416 417 drm_WARN_ON(&dev_priv->drm, 418 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & 419 FDI_RX_ENABLE); 420 drm_WARN_ON(&dev_priv->drm, 421 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & 422 FDI_RX_ENABLE); 423 424 temp &= ~FDI_BC_BIFURCATION_SELECT; 425 if (enable) 426 temp |= FDI_BC_BIFURCATION_SELECT; 427 428 drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n", 429 enable ? "en" : "dis"); 430 intel_de_write(dev_priv, SOUTH_CHICKEN1, temp); 431 intel_de_posting_read(dev_priv, SOUTH_CHICKEN1); 432 } 433 434 static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) 435 { 436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 437 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 438 439 switch (crtc->pipe) { 440 case PIPE_A: 441 break; 442 case PIPE_B: 443 if (crtc_state->fdi_lanes > 2) 444 cpt_set_fdi_bc_bifurcation(dev_priv, false); 445 else 446 cpt_set_fdi_bc_bifurcation(dev_priv, true); 447 448 break; 449 case PIPE_C: 450 cpt_set_fdi_bc_bifurcation(dev_priv, true); 451 452 break; 453 default: 454 MISSING_CASE(crtc->pipe); 455 } 456 } 457 458 void intel_fdi_normal_train(struct intel_crtc *crtc) 459 { 460 struct drm_device *dev = crtc->base.dev; 461 struct drm_i915_private *dev_priv = to_i915(dev); 462 enum pipe pipe = crtc->pipe; 463 i915_reg_t reg; 464 u32 temp; 465 466 /* enable normal train */ 467 reg = FDI_TX_CTL(pipe); 468 temp = intel_de_read(dev_priv, reg); 469 if (IS_IVYBRIDGE(dev_priv)) { 470 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 471 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 472 } else { 473 temp &= ~FDI_LINK_TRAIN_NONE; 474 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 475 } 476 intel_de_write(dev_priv, reg, temp); 477 478 reg = FDI_RX_CTL(pipe); 479 temp = intel_de_read(dev_priv, reg); 480 if (HAS_PCH_CPT(dev_priv)) { 481 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 482 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 483 } else { 484 temp &= ~FDI_LINK_TRAIN_NONE; 485 temp |= FDI_LINK_TRAIN_NONE; 486 } 487 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 488 489 /* wait one idle pattern time */ 490 intel_de_posting_read(dev_priv, reg); 491 udelay(1000); 492 493 /* IVB wants error correction enabled */ 494 if (IS_IVYBRIDGE(dev_priv)) 495 intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); 496 } 497 498 /* The FDI link training functions for ILK/Ibexpeak. */ 499 static void ilk_fdi_link_train(struct intel_crtc *crtc, 500 const struct intel_crtc_state *crtc_state) 501 { 502 struct drm_device *dev = crtc->base.dev; 503 struct drm_i915_private *dev_priv = to_i915(dev); 504 enum pipe pipe = crtc->pipe; 505 i915_reg_t reg; 506 u32 temp, tries; 507 508 /* 509 * Write the TU size bits before fdi link training, so that error 510 * detection works. 511 */ 512 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 513 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 514 515 /* FDI needs bits from pipe first */ 516 assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder); 517 518 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 519 for train result */ 520 reg = FDI_RX_IMR(pipe); 521 temp = intel_de_read(dev_priv, reg); 522 temp &= ~FDI_RX_SYMBOL_LOCK; 523 temp &= ~FDI_RX_BIT_LOCK; 524 intel_de_write(dev_priv, reg, temp); 525 intel_de_read(dev_priv, reg); 526 udelay(150); 527 528 /* enable CPU FDI TX and PCH FDI RX */ 529 reg = FDI_TX_CTL(pipe); 530 temp = intel_de_read(dev_priv, reg); 531 temp &= ~FDI_DP_PORT_WIDTH_MASK; 532 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 533 temp &= ~FDI_LINK_TRAIN_NONE; 534 temp |= FDI_LINK_TRAIN_PATTERN_1; 535 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 536 537 reg = FDI_RX_CTL(pipe); 538 temp = intel_de_read(dev_priv, reg); 539 temp &= ~FDI_LINK_TRAIN_NONE; 540 temp |= FDI_LINK_TRAIN_PATTERN_1; 541 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 542 543 intel_de_posting_read(dev_priv, reg); 544 udelay(150); 545 546 /* Ironlake workaround, enable clock pointer after FDI enable*/ 547 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 548 FDI_RX_PHASE_SYNC_POINTER_OVR); 549 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 550 FDI_RX_PHASE_SYNC_POINTER_OVR | FDI_RX_PHASE_SYNC_POINTER_EN); 551 552 reg = FDI_RX_IIR(pipe); 553 for (tries = 0; tries < 5; tries++) { 554 temp = intel_de_read(dev_priv, reg); 555 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 556 557 if ((temp & FDI_RX_BIT_LOCK)) { 558 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n"); 559 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK); 560 break; 561 } 562 } 563 if (tries == 5) 564 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); 565 566 /* Train 2 */ 567 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 568 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); 569 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 570 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2); 571 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 572 udelay(150); 573 574 reg = FDI_RX_IIR(pipe); 575 for (tries = 0; tries < 5; tries++) { 576 temp = intel_de_read(dev_priv, reg); 577 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 578 579 if (temp & FDI_RX_SYMBOL_LOCK) { 580 intel_de_write(dev_priv, reg, 581 temp | FDI_RX_SYMBOL_LOCK); 582 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n"); 583 break; 584 } 585 } 586 if (tries == 5) 587 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); 588 589 drm_dbg_kms(&dev_priv->drm, "FDI train done\n"); 590 591 } 592 593 static const int snb_b_fdi_train_param[] = { 594 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 595 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 596 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 597 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 598 }; 599 600 /* The FDI link training functions for SNB/Cougarpoint. */ 601 static void gen6_fdi_link_train(struct intel_crtc *crtc, 602 const struct intel_crtc_state *crtc_state) 603 { 604 struct drm_device *dev = crtc->base.dev; 605 struct drm_i915_private *dev_priv = to_i915(dev); 606 enum pipe pipe = crtc->pipe; 607 i915_reg_t reg; 608 u32 temp, i, retry; 609 610 /* 611 * Write the TU size bits before fdi link training, so that error 612 * detection works. 613 */ 614 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 615 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 616 617 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 618 for train result */ 619 reg = FDI_RX_IMR(pipe); 620 temp = intel_de_read(dev_priv, reg); 621 temp &= ~FDI_RX_SYMBOL_LOCK; 622 temp &= ~FDI_RX_BIT_LOCK; 623 intel_de_write(dev_priv, reg, temp); 624 625 intel_de_posting_read(dev_priv, reg); 626 udelay(150); 627 628 /* enable CPU FDI TX and PCH FDI RX */ 629 reg = FDI_TX_CTL(pipe); 630 temp = intel_de_read(dev_priv, reg); 631 temp &= ~FDI_DP_PORT_WIDTH_MASK; 632 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 633 temp &= ~FDI_LINK_TRAIN_NONE; 634 temp |= FDI_LINK_TRAIN_PATTERN_1; 635 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 636 /* SNB-B */ 637 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 638 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 639 640 intel_de_write(dev_priv, FDI_RX_MISC(pipe), 641 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 642 643 reg = FDI_RX_CTL(pipe); 644 temp = intel_de_read(dev_priv, reg); 645 if (HAS_PCH_CPT(dev_priv)) { 646 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 647 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 648 } else { 649 temp &= ~FDI_LINK_TRAIN_NONE; 650 temp |= FDI_LINK_TRAIN_PATTERN_1; 651 } 652 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 653 654 intel_de_posting_read(dev_priv, reg); 655 udelay(150); 656 657 for (i = 0; i < 4; i++) { 658 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 659 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); 660 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 661 udelay(500); 662 663 for (retry = 0; retry < 5; retry++) { 664 reg = FDI_RX_IIR(pipe); 665 temp = intel_de_read(dev_priv, reg); 666 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 667 if (temp & FDI_RX_BIT_LOCK) { 668 intel_de_write(dev_priv, reg, 669 temp | FDI_RX_BIT_LOCK); 670 drm_dbg_kms(&dev_priv->drm, 671 "FDI train 1 done.\n"); 672 break; 673 } 674 udelay(50); 675 } 676 if (retry < 5) 677 break; 678 } 679 if (i == 4) 680 drm_err(&dev_priv->drm, "FDI train 1 fail!\n"); 681 682 /* Train 2 */ 683 reg = FDI_TX_CTL(pipe); 684 temp = intel_de_read(dev_priv, reg); 685 temp &= ~FDI_LINK_TRAIN_NONE; 686 temp |= FDI_LINK_TRAIN_PATTERN_2; 687 if (IS_SANDYBRIDGE(dev_priv)) { 688 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 689 /* SNB-B */ 690 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 691 } 692 intel_de_write(dev_priv, reg, temp); 693 694 reg = FDI_RX_CTL(pipe); 695 temp = intel_de_read(dev_priv, reg); 696 if (HAS_PCH_CPT(dev_priv)) { 697 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 698 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 699 } else { 700 temp &= ~FDI_LINK_TRAIN_NONE; 701 temp |= FDI_LINK_TRAIN_PATTERN_2; 702 } 703 intel_de_write(dev_priv, reg, temp); 704 705 intel_de_posting_read(dev_priv, reg); 706 udelay(150); 707 708 for (i = 0; i < 4; i++) { 709 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 710 FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]); 711 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 712 udelay(500); 713 714 for (retry = 0; retry < 5; retry++) { 715 reg = FDI_RX_IIR(pipe); 716 temp = intel_de_read(dev_priv, reg); 717 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 718 if (temp & FDI_RX_SYMBOL_LOCK) { 719 intel_de_write(dev_priv, reg, 720 temp | FDI_RX_SYMBOL_LOCK); 721 drm_dbg_kms(&dev_priv->drm, 722 "FDI train 2 done.\n"); 723 break; 724 } 725 udelay(50); 726 } 727 if (retry < 5) 728 break; 729 } 730 if (i == 4) 731 drm_err(&dev_priv->drm, "FDI train 2 fail!\n"); 732 733 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); 734 } 735 736 /* Manual link training for Ivy Bridge A0 parts */ 737 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, 738 const struct intel_crtc_state *crtc_state) 739 { 740 struct drm_device *dev = crtc->base.dev; 741 struct drm_i915_private *dev_priv = to_i915(dev); 742 enum pipe pipe = crtc->pipe; 743 i915_reg_t reg; 744 u32 temp, i, j; 745 746 ivb_update_fdi_bc_bifurcation(crtc_state); 747 748 /* 749 * Write the TU size bits before fdi link training, so that error 750 * detection works. 751 */ 752 intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), 753 intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 754 755 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 756 for train result */ 757 reg = FDI_RX_IMR(pipe); 758 temp = intel_de_read(dev_priv, reg); 759 temp &= ~FDI_RX_SYMBOL_LOCK; 760 temp &= ~FDI_RX_BIT_LOCK; 761 intel_de_write(dev_priv, reg, temp); 762 763 intel_de_posting_read(dev_priv, reg); 764 udelay(150); 765 766 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n", 767 intel_de_read(dev_priv, FDI_RX_IIR(pipe))); 768 769 /* Try each vswing and preemphasis setting twice before moving on */ 770 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { 771 /* disable first in case we need to retry */ 772 reg = FDI_TX_CTL(pipe); 773 temp = intel_de_read(dev_priv, reg); 774 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 775 temp &= ~FDI_TX_ENABLE; 776 intel_de_write(dev_priv, reg, temp); 777 778 reg = FDI_RX_CTL(pipe); 779 temp = intel_de_read(dev_priv, reg); 780 temp &= ~FDI_LINK_TRAIN_AUTO; 781 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 782 temp &= ~FDI_RX_ENABLE; 783 intel_de_write(dev_priv, reg, temp); 784 785 /* enable CPU FDI TX and PCH FDI RX */ 786 reg = FDI_TX_CTL(pipe); 787 temp = intel_de_read(dev_priv, reg); 788 temp &= ~FDI_DP_PORT_WIDTH_MASK; 789 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 790 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 792 temp |= snb_b_fdi_train_param[j/2]; 793 temp |= FDI_COMPOSITE_SYNC; 794 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE); 795 796 intel_de_write(dev_priv, FDI_RX_MISC(pipe), 797 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 798 799 reg = FDI_RX_CTL(pipe); 800 temp = intel_de_read(dev_priv, reg); 801 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 802 temp |= FDI_COMPOSITE_SYNC; 803 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE); 804 805 intel_de_posting_read(dev_priv, reg); 806 udelay(1); /* should be 0.5us */ 807 808 for (i = 0; i < 4; i++) { 809 reg = FDI_RX_IIR(pipe); 810 temp = intel_de_read(dev_priv, reg); 811 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 812 813 if (temp & FDI_RX_BIT_LOCK || 814 (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK)) { 815 intel_de_write(dev_priv, reg, 816 temp | FDI_RX_BIT_LOCK); 817 drm_dbg_kms(&dev_priv->drm, 818 "FDI train 1 done, level %i.\n", 819 i); 820 break; 821 } 822 udelay(1); /* should be 0.5us */ 823 } 824 if (i == 4) { 825 drm_dbg_kms(&dev_priv->drm, 826 "FDI train 1 fail on vswing %d\n", j / 2); 827 continue; 828 } 829 830 /* Train 2 */ 831 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 832 FDI_LINK_TRAIN_NONE_IVB, 833 FDI_LINK_TRAIN_PATTERN_2_IVB); 834 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), 835 FDI_LINK_TRAIN_PATTERN_MASK_CPT, 836 FDI_LINK_TRAIN_PATTERN_2_CPT); 837 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 838 udelay(2); /* should be 1.5us */ 839 840 for (i = 0; i < 4; i++) { 841 reg = FDI_RX_IIR(pipe); 842 temp = intel_de_read(dev_priv, reg); 843 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp); 844 845 if (temp & FDI_RX_SYMBOL_LOCK || 846 (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK)) { 847 intel_de_write(dev_priv, reg, 848 temp | FDI_RX_SYMBOL_LOCK); 849 drm_dbg_kms(&dev_priv->drm, 850 "FDI train 2 done, level %i.\n", 851 i); 852 goto train_done; 853 } 854 udelay(2); /* should be 1.5us */ 855 } 856 if (i == 4) 857 drm_dbg_kms(&dev_priv->drm, 858 "FDI train 2 fail on vswing %d\n", j / 2); 859 } 860 861 train_done: 862 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n"); 863 } 864 865 /* Starting with Haswell, different DDI ports can work in FDI mode for 866 * connection to the PCH-located connectors. For this, it is necessary to train 867 * both the DDI port and PCH receiver for the desired DDI buffer settings. 868 * 869 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 870 * please note that when FDI mode is active on DDI E, it shares 2 lines with 871 * DDI A (which is used for eDP) 872 */ 873 void hsw_fdi_link_train(struct intel_encoder *encoder, 874 const struct intel_crtc_state *crtc_state) 875 { 876 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 877 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 878 u32 temp, i, rx_ctl_val; 879 int n_entries; 880 881 encoder->get_buf_trans(encoder, crtc_state, &n_entries); 882 883 hsw_prepare_dp_ddi_buffers(encoder, crtc_state); 884 885 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 886 * mode set "sequence for CRT port" document: 887 * - TP1 to TP2 time with the default value 888 * - FDI delay to 90h 889 * 890 * WaFDIAutoLinkSetTimingOverrride:hsw 891 */ 892 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), 893 FDI_RX_PWRDN_LANE1_VAL(2) | 894 FDI_RX_PWRDN_LANE0_VAL(2) | 895 FDI_RX_TP1_TO_TP2_48 | 896 FDI_RX_FDI_DELAY_90); 897 898 /* Enable the PCH Receiver FDI PLL */ 899 rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 900 FDI_RX_PLL_ENABLE | 901 FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 902 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 903 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 904 udelay(220); 905 906 /* Switch from Rawclk to PCDclk */ 907 rx_ctl_val |= FDI_PCDCLK; 908 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 909 910 /* Configure Port Clock Select */ 911 drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); 912 intel_ddi_enable_clock(encoder, crtc_state); 913 914 /* Start the training iterating through available voltages and emphasis, 915 * testing each value twice. */ 916 for (i = 0; i < n_entries * 2; i++) { 917 /* Configure DP_TP_CTL with auto-training */ 918 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 919 DP_TP_CTL_FDI_AUTOTRAIN | 920 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 921 DP_TP_CTL_LINK_TRAIN_PAT1 | 922 DP_TP_CTL_ENABLE); 923 924 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 925 * DDI E does not support port reversal, the functionality is 926 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 927 * port reversal bit */ 928 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), 929 DDI_BUF_CTL_ENABLE | 930 ((crtc_state->fdi_lanes - 1) << 1) | 931 DDI_BUF_TRANS_SELECT(i / 2)); 932 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 933 934 udelay(600); 935 936 /* Program PCH FDI Receiver TU */ 937 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); 938 939 /* Enable PCH FDI Receiver with auto-training */ 940 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 941 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 942 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 943 944 /* Wait for FDI receiver lane calibration */ 945 udelay(30); 946 947 /* Unset FDI_RX_MISC pwrdn lanes */ 948 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 949 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0); 950 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 951 952 /* Wait for FDI auto training time */ 953 udelay(5); 954 955 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E)); 956 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 957 drm_dbg_kms(&dev_priv->drm, 958 "FDI link training done on step %d\n", i); 959 break; 960 } 961 962 /* 963 * Leave things enabled even if we failed to train FDI. 964 * Results in less fireworks from the state checker. 965 */ 966 if (i == n_entries * 2 - 1) { 967 drm_err(&dev_priv->drm, "FDI link training failed!\n"); 968 break; 969 } 970 971 rx_ctl_val &= ~FDI_RX_ENABLE; 972 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); 973 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); 974 975 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); 976 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E)); 977 978 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 979 intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); 980 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E)); 981 982 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 983 984 /* Reset FDI_RX_MISC pwrdn lanes */ 985 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 986 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 987 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); 988 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A)); 989 } 990 991 /* Enable normal pixel sending for FDI */ 992 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), 993 DP_TP_CTL_FDI_AUTOTRAIN | 994 DP_TP_CTL_LINK_TRAIN_NORMAL | 995 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 996 DP_TP_CTL_ENABLE); 997 } 998 999 void hsw_fdi_disable(struct intel_encoder *encoder) 1000 { 1001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1002 1003 /* 1004 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) 1005 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, 1006 * step 13 is the correct place for it. Step 18 is where it was 1007 * originally before the BUN. 1008 */ 1009 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0); 1010 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); 1011 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 1012 intel_ddi_disable_clock(encoder); 1013 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), 1014 FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 1015 FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2)); 1016 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0); 1017 intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0); 1018 } 1019 1020 void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) 1021 { 1022 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1023 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1024 enum pipe pipe = crtc->pipe; 1025 i915_reg_t reg; 1026 u32 temp; 1027 1028 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 1029 reg = FDI_RX_CTL(pipe); 1030 temp = intel_de_read(dev_priv, reg); 1031 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); 1032 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); 1033 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; 1034 intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); 1035 1036 intel_de_posting_read(dev_priv, reg); 1037 udelay(200); 1038 1039 /* Switch from Rawclk to PCDclk */ 1040 intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK); 1041 intel_de_posting_read(dev_priv, reg); 1042 udelay(200); 1043 1044 /* Enable CPU FDI TX PLL, always on for Ironlake */ 1045 reg = FDI_TX_CTL(pipe); 1046 temp = intel_de_read(dev_priv, reg); 1047 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 1048 intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE); 1049 1050 intel_de_posting_read(dev_priv, reg); 1051 udelay(100); 1052 } 1053 } 1054 1055 void ilk_fdi_pll_disable(struct intel_crtc *crtc) 1056 { 1057 struct drm_device *dev = crtc->base.dev; 1058 struct drm_i915_private *dev_priv = to_i915(dev); 1059 enum pipe pipe = crtc->pipe; 1060 1061 /* Switch from PCDclk to Rawclk */ 1062 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0); 1063 1064 /* Disable CPU FDI TX PLL */ 1065 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0); 1066 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 1067 udelay(100); 1068 1069 /* Wait for the clocks to turn off. */ 1070 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0); 1071 intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe)); 1072 udelay(100); 1073 } 1074 1075 void ilk_fdi_disable(struct intel_crtc *crtc) 1076 { 1077 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1078 enum pipe pipe = crtc->pipe; 1079 i915_reg_t reg; 1080 u32 temp; 1081 1082 /* disable CPU FDI tx and PCH FDI rx */ 1083 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0); 1084 intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe)); 1085 1086 reg = FDI_RX_CTL(pipe); 1087 temp = intel_de_read(dev_priv, reg); 1088 temp &= ~(0x7 << 16); 1089 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; 1090 intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); 1091 1092 intel_de_posting_read(dev_priv, reg); 1093 udelay(100); 1094 1095 /* Ironlake workaround, disable clock pointer after downing FDI */ 1096 if (HAS_PCH_IBX(dev_priv)) 1097 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe), 1098 FDI_RX_PHASE_SYNC_POINTER_OVR); 1099 1100 /* still set train pattern 1 */ 1101 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), 1102 FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1); 1103 1104 reg = FDI_RX_CTL(pipe); 1105 temp = intel_de_read(dev_priv, reg); 1106 if (HAS_PCH_CPT(dev_priv)) { 1107 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 1108 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 1109 } else { 1110 temp &= ~FDI_LINK_TRAIN_NONE; 1111 temp |= FDI_LINK_TRAIN_PATTERN_1; 1112 } 1113 /* BPC in FDI rx is consistent with that in TRANSCONF */ 1114 temp &= ~(0x07 << 16); 1115 temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; 1116 intel_de_write(dev_priv, reg, temp); 1117 1118 intel_de_posting_read(dev_priv, reg); 1119 udelay(100); 1120 } 1121 1122 static const struct intel_fdi_funcs ilk_funcs = { 1123 .fdi_link_train = ilk_fdi_link_train, 1124 }; 1125 1126 static const struct intel_fdi_funcs gen6_funcs = { 1127 .fdi_link_train = gen6_fdi_link_train, 1128 }; 1129 1130 static const struct intel_fdi_funcs ivb_funcs = { 1131 .fdi_link_train = ivb_manual_fdi_link_train, 1132 }; 1133 1134 void 1135 intel_fdi_init_hook(struct drm_i915_private *dev_priv) 1136 { 1137 if (IS_IRONLAKE(dev_priv)) { 1138 dev_priv->display.funcs.fdi = &ilk_funcs; 1139 } else if (IS_SANDYBRIDGE(dev_priv)) { 1140 dev_priv->display.funcs.fdi = &gen6_funcs; 1141 } else if (IS_IVYBRIDGE(dev_priv)) { 1142 /* FIXME: detect B0+ stepping and use auto training */ 1143 dev_priv->display.funcs.fdi = &ivb_funcs; 1144 } 1145 } 1146