1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include <linux/debugfs.h> 42 #include <linux/string_helpers.h> 43 44 #include <drm/drm_blend.h> 45 #include <drm/drm_fourcc.h> 46 #include <drm/drm_print.h> 47 48 #include "i915_vma.h" 49 #include "i9xx_plane_regs.h" 50 #include "intel_de.h" 51 #include "intel_display_device.h" 52 #include "intel_display_regs.h" 53 #include "intel_display_rpm.h" 54 #include "intel_display_trace.h" 55 #include "intel_display_types.h" 56 #include "intel_display_utils.h" 57 #include "intel_display_wa.h" 58 #include "intel_fbc.h" 59 #include "intel_fbc_regs.h" 60 #include "intel_frontbuffer.h" 61 #include "intel_parent.h" 62 #include "intel_step.h" 63 64 #define for_each_fbc_id(__display, __fbc_id) \ 65 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ 66 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id)) 67 68 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ 69 for_each_fbc_id((__display), (__fbc_id)) \ 70 for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)]) 71 72 #define FBC_SYS_CACHE_ID_NONE I915_MAX_FBCS 73 74 struct intel_fbc_funcs { 75 void (*activate)(struct intel_fbc *fbc); 76 void (*deactivate)(struct intel_fbc *fbc); 77 bool (*is_active)(struct intel_fbc *fbc); 78 bool (*is_compressing)(struct intel_fbc *fbc); 79 void (*nuke)(struct intel_fbc *fbc); 80 void (*program_cfb)(struct intel_fbc *fbc); 81 void (*set_false_color)(struct intel_fbc *fbc, bool enable); 82 }; 83 84 struct intel_fbc_state { 85 struct intel_plane *plane; 86 unsigned int cfb_stride; 87 unsigned int cfb_size; 88 unsigned int fence_y_offset; 89 u16 override_cfb_stride; 90 u16 interval; 91 s8 fence_id; 92 struct drm_rect dirty_rect; 93 }; 94 95 struct intel_fbc { 96 struct intel_display *display; 97 const struct intel_fbc_funcs *funcs; 98 99 /* This is always the outer lock when overlapping with stolen_lock */ 100 struct mutex lock; 101 unsigned int busy_bits; 102 103 struct intel_stolen_node *compressed_fb; 104 struct intel_stolen_node *compressed_llb; 105 106 enum intel_fbc_id id; 107 108 u8 limit; 109 110 bool false_color; 111 112 bool active; 113 bool activated; 114 bool flip_pending; 115 116 bool underrun_detected; 117 struct work_struct underrun_work; 118 119 /* 120 * This structure contains everything that's relevant to program the 121 * hardware registers. When we want to figure out if we need to disable 122 * and re-enable FBC for a new configuration we just check if there's 123 * something different in the struct. The genx_fbc_activate functions 124 * are supposed to read from it in order to program the registers. 125 */ 126 struct intel_fbc_state state; 127 const char *no_fbc_reason; 128 }; 129 130 static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) 131 { 132 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 133 struct intel_plane *primary = NULL; 134 135 primary = to_intel_plane(crtc->base.primary); 136 137 if (drm_WARN_ON(display->drm, !primary)) 138 return NULL; 139 140 return primary->fbc; 141 } 142 143 /* plane stride in pixels */ 144 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) 145 { 146 const struct drm_framebuffer *fb = plane_state->hw.fb; 147 unsigned int stride; 148 149 stride = plane_state->view.color_plane[0].mapping_stride; 150 if (!drm_rotation_90_or_270(plane_state->hw.rotation)) 151 stride /= fb->format->cpp[0]; 152 153 return stride; 154 } 155 156 static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state) 157 { 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int cpp = fb->format->cpp[0]; 160 161 return max(cpp, 4); 162 } 163 164 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 165 static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state) 166 { 167 unsigned int cpp = intel_fbc_cfb_cpp(plane_state); 168 169 return intel_fbc_plane_stride(plane_state) * cpp; 170 } 171 172 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ 173 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, 174 unsigned int cpp, unsigned int width) 175 { 176 unsigned int limit = 4; /* 1:4 compression limit is the worst case */ 177 unsigned int height = 4; /* FBC segment is 4 lines */ 178 unsigned int stride; 179 180 /* minimum segment stride we can use */ 181 stride = width * cpp * height / limit; 182 183 /* 184 * Wa_16011863758: icl+ 185 * Avoid some hardware segment address miscalculation. 186 */ 187 if (DISPLAY_VER(display) >= 11) 188 stride += 64; 189 190 /* 191 * At least some of the platforms require each 4 line segment to 192 * be 512 byte aligned. Just do it always for simplicity. 193 */ 194 stride = ALIGN(stride, 512); 195 196 /* convert back to single line equivalent with 1:1 compression limit */ 197 return stride * limit / height; 198 } 199 200 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ 201 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, 202 unsigned int cpp, unsigned int width, 203 unsigned int stride) 204 { 205 /* 206 * At least some of the platforms require each 4 line segment to 207 * be 512 byte aligned. Aligning each line to 512 bytes guarantees 208 * that regardless of the compression limit we choose later. 209 */ 210 if (DISPLAY_VER(display) >= 9) 211 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); 212 else 213 return stride; 214 } 215 216 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 217 { 218 struct intel_display *display = to_intel_display(plane_state); 219 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 220 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 221 unsigned int cpp = intel_fbc_cfb_cpp(plane_state); 222 223 return _intel_fbc_cfb_stride(display, cpp, width, stride); 224 } 225 226 /* 227 * Maximum height the hardware will compress, on HSW+ 228 * additional lines (up to the actual plane height) will 229 * remain uncompressed. 230 */ 231 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) 232 { 233 if (DISPLAY_VER(display) >= 8) 234 return 2560; 235 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 236 return 2048; 237 else 238 return 1536; 239 } 240 241 static unsigned int _intel_fbc_cfb_size(struct intel_display *display, 242 unsigned int height, unsigned int stride) 243 { 244 return min(height, intel_fbc_max_cfb_height(display)) * stride; 245 } 246 247 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 248 { 249 struct intel_display *display = to_intel_display(plane_state); 250 unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; 251 252 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); 253 } 254 255 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 256 { 257 struct intel_display *display = to_intel_display(plane_state); 258 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 259 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 260 const struct drm_framebuffer *fb = plane_state->hw.fb; 261 262 /* 263 * Override stride in 64 byte units per 4 line segment. 264 * 265 * Gen9 hw miscalculates cfb stride for linear as 266 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so 267 * we always need to use the override there. 268 * 269 * wa_14022269668 For bmg, always program the FBC_STRIDE before fbc enable 270 */ 271 if (stride != stride_aligned || 272 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) || 273 display->platform.battlemage) 274 return stride_aligned * 4 / 64; 275 276 return 0; 277 } 278 279 static bool intel_fbc_has_fences(struct intel_display *display) 280 { 281 return intel_parent_has_fenced_regions(display); 282 } 283 284 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) 285 { 286 struct intel_display *display = fbc->display; 287 const struct intel_fbc_state *fbc_state = &fbc->state; 288 unsigned int cfb_stride; 289 u32 fbc_ctl; 290 291 cfb_stride = fbc_state->cfb_stride / fbc->limit; 292 293 /* FBC_CTL wants 32B or 64B units */ 294 if (DISPLAY_VER(display) == 2) 295 cfb_stride = (cfb_stride / 32) - 1; 296 else 297 cfb_stride = (cfb_stride / 64) - 1; 298 299 fbc_ctl = FBC_CTL_PERIODIC | 300 FBC_CTL_INTERVAL(fbc_state->interval) | 301 FBC_CTL_STRIDE(cfb_stride); 302 303 if (display->platform.i945gm) 304 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 305 306 if (fbc_state->fence_id >= 0) 307 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id); 308 309 return fbc_ctl; 310 } 311 312 static u32 i965_fbc_ctl2(struct intel_fbc *fbc) 313 { 314 const struct intel_fbc_state *fbc_state = &fbc->state; 315 u32 fbc_ctl2; 316 317 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | 318 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); 319 320 if (fbc_state->fence_id >= 0) 321 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN; 322 323 return fbc_ctl2; 324 } 325 326 static void i8xx_fbc_deactivate(struct intel_fbc *fbc) 327 { 328 struct intel_display *display = fbc->display; 329 u32 fbc_ctl; 330 331 /* Disable compression */ 332 fbc_ctl = intel_de_read(display, FBC_CONTROL); 333 if ((fbc_ctl & FBC_CTL_EN) == 0) 334 return; 335 336 fbc_ctl &= ~FBC_CTL_EN; 337 intel_de_write(display, FBC_CONTROL, fbc_ctl); 338 339 /* Wait for compressing bit to clear */ 340 if (intel_de_wait_for_clear_ms(display, FBC_STATUS, 341 FBC_STAT_COMPRESSING, 10)) { 342 drm_dbg_kms(display->drm, "FBC idle timed out\n"); 343 return; 344 } 345 } 346 347 static void i8xx_fbc_activate(struct intel_fbc *fbc) 348 { 349 struct intel_display *display = fbc->display; 350 const struct intel_fbc_state *fbc_state = &fbc->state; 351 int i; 352 353 /* Clear old tags */ 354 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 355 intel_de_write(display, FBC_TAG(i), 0); 356 357 if (DISPLAY_VER(display) == 4) { 358 intel_de_write(display, FBC_CONTROL2, 359 i965_fbc_ctl2(fbc)); 360 intel_de_write(display, FBC_FENCE_OFF, 361 fbc_state->fence_y_offset); 362 } 363 364 intel_de_write(display, FBC_CONTROL, 365 FBC_CTL_EN | i8xx_fbc_ctl(fbc)); 366 } 367 368 static bool i8xx_fbc_is_active(struct intel_fbc *fbc) 369 { 370 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; 371 } 372 373 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) 374 { 375 return intel_de_read(fbc->display, FBC_STATUS) & 376 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); 377 } 378 379 static void i8xx_fbc_nuke(struct intel_fbc *fbc) 380 { 381 struct intel_display *display = fbc->display; 382 struct intel_fbc_state *fbc_state = &fbc->state; 383 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 384 385 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 386 intel_de_read_fw(display, DSPADDR(display, i9xx_plane))); 387 } 388 389 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) 390 { 391 struct intel_display *display = fbc->display; 392 393 drm_WARN_ON(display->drm, 394 range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 395 intel_parent_stolen_node_offset(display, fbc->compressed_fb), 396 U32_MAX)); 397 drm_WARN_ON(display->drm, 398 range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 399 intel_parent_stolen_node_offset(display, fbc->compressed_llb), 400 U32_MAX)); 401 intel_de_write(display, FBC_CFB_BASE, 402 intel_parent_stolen_node_address(display, fbc->compressed_fb)); 403 intel_de_write(display, FBC_LL_BASE, 404 intel_parent_stolen_node_address(display, fbc->compressed_llb)); 405 } 406 407 static const struct intel_fbc_funcs i8xx_fbc_funcs = { 408 .activate = i8xx_fbc_activate, 409 .deactivate = i8xx_fbc_deactivate, 410 .is_active = i8xx_fbc_is_active, 411 .is_compressing = i8xx_fbc_is_compressing, 412 .nuke = i8xx_fbc_nuke, 413 .program_cfb = i8xx_fbc_program_cfb, 414 }; 415 416 static void i965_fbc_nuke(struct intel_fbc *fbc) 417 { 418 struct intel_display *display = fbc->display; 419 struct intel_fbc_state *fbc_state = &fbc->state; 420 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 421 422 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 423 intel_de_read_fw(display, DSPSURF(display, i9xx_plane))); 424 } 425 426 static const struct intel_fbc_funcs i965_fbc_funcs = { 427 .activate = i8xx_fbc_activate, 428 .deactivate = i8xx_fbc_deactivate, 429 .is_active = i8xx_fbc_is_active, 430 .is_compressing = i8xx_fbc_is_compressing, 431 .nuke = i965_fbc_nuke, 432 .program_cfb = i8xx_fbc_program_cfb, 433 }; 434 435 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) 436 { 437 switch (fbc->limit) { 438 default: 439 MISSING_CASE(fbc->limit); 440 fallthrough; 441 case 1: 442 return DPFC_CTL_LIMIT_1X; 443 case 2: 444 return DPFC_CTL_LIMIT_2X; 445 case 4: 446 return DPFC_CTL_LIMIT_4X; 447 } 448 } 449 450 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) 451 { 452 struct intel_display *display = fbc->display; 453 const struct intel_fbc_state *fbc_state = &fbc->state; 454 u32 dpfc_ctl; 455 456 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | 457 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); 458 459 if (display->platform.g4x) 460 dpfc_ctl |= DPFC_CTL_SR_EN; 461 462 if (fbc_state->fence_id >= 0) { 463 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; 464 465 if (DISPLAY_VER(display) < 6) 466 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); 467 } 468 469 return dpfc_ctl; 470 } 471 472 static void g4x_fbc_activate(struct intel_fbc *fbc) 473 { 474 struct intel_display *display = fbc->display; 475 const struct intel_fbc_state *fbc_state = &fbc->state; 476 477 intel_de_write(display, DPFC_FENCE_YOFF, 478 fbc_state->fence_y_offset); 479 480 intel_de_write(display, DPFC_CONTROL, 481 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 482 } 483 484 static void g4x_fbc_deactivate(struct intel_fbc *fbc) 485 { 486 struct intel_display *display = fbc->display; 487 u32 dpfc_ctl; 488 489 /* Disable compression */ 490 dpfc_ctl = intel_de_read(display, DPFC_CONTROL); 491 if (dpfc_ctl & DPFC_CTL_EN) { 492 dpfc_ctl &= ~DPFC_CTL_EN; 493 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); 494 } 495 } 496 497 static bool g4x_fbc_is_active(struct intel_fbc *fbc) 498 { 499 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; 500 } 501 502 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) 503 { 504 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 505 } 506 507 static void g4x_fbc_program_cfb(struct intel_fbc *fbc) 508 { 509 struct intel_display *display = fbc->display; 510 511 intel_de_write(display, DPFC_CB_BASE, 512 intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 513 } 514 515 static const struct intel_fbc_funcs g4x_fbc_funcs = { 516 .activate = g4x_fbc_activate, 517 .deactivate = g4x_fbc_deactivate, 518 .is_active = g4x_fbc_is_active, 519 .is_compressing = g4x_fbc_is_compressing, 520 .nuke = i965_fbc_nuke, 521 .program_cfb = g4x_fbc_program_cfb, 522 }; 523 524 static void ilk_fbc_activate(struct intel_fbc *fbc) 525 { 526 struct intel_display *display = fbc->display; 527 struct intel_fbc_state *fbc_state = &fbc->state; 528 529 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), 530 fbc_state->fence_y_offset); 531 532 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 533 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 534 } 535 536 static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc, 537 bool disable) 538 { 539 struct intel_display *display = fbc->display; 540 541 if (display->platform.dg2) 542 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS, 543 disable ? DG2_DPFC_GATING_DIS : 0); 544 else if (DISPLAY_VER(display) >= 14) 545 intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id), 546 MTL_DPFC_GATING_DIS, 547 disable ? MTL_DPFC_GATING_DIS : 0); 548 } 549 550 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 551 { 552 struct intel_display *display = fbc->display; 553 u32 dpfc_ctl; 554 555 if (HAS_FBC_DIRTY_RECT(display)) 556 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); 557 558 /* Disable compression */ 559 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); 560 if (dpfc_ctl & DPFC_CTL_EN) { 561 dpfc_ctl &= ~DPFC_CTL_EN; 562 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 563 } 564 } 565 566 static bool ilk_fbc_is_active(struct intel_fbc *fbc) 567 { 568 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; 569 } 570 571 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) 572 { 573 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; 574 } 575 576 static void ilk_fbc_program_cfb(struct intel_fbc *fbc) 577 { 578 struct intel_display *display = fbc->display; 579 580 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), 581 intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 582 } 583 584 static const struct intel_fbc_funcs ilk_fbc_funcs = { 585 .activate = ilk_fbc_activate, 586 .deactivate = ilk_fbc_deactivate, 587 .is_active = ilk_fbc_is_active, 588 .is_compressing = ilk_fbc_is_compressing, 589 .nuke = i965_fbc_nuke, 590 .program_cfb = ilk_fbc_program_cfb, 591 }; 592 593 static void snb_fbc_program_fence(struct intel_fbc *fbc) 594 { 595 struct intel_display *display = fbc->display; 596 const struct intel_fbc_state *fbc_state = &fbc->state; 597 u32 ctl = 0; 598 599 if (fbc_state->fence_id >= 0) 600 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); 601 602 intel_de_write(display, SNB_DPFC_CTL_SA, ctl); 603 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 604 } 605 606 static void snb_fbc_activate(struct intel_fbc *fbc) 607 { 608 snb_fbc_program_fence(fbc); 609 610 ilk_fbc_activate(fbc); 611 } 612 613 static void snb_fbc_nuke(struct intel_fbc *fbc) 614 { 615 struct intel_display *display = fbc->display; 616 617 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); 618 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); 619 } 620 621 static const struct intel_fbc_funcs snb_fbc_funcs = { 622 .activate = snb_fbc_activate, 623 .deactivate = ilk_fbc_deactivate, 624 .is_active = ilk_fbc_is_active, 625 .is_compressing = ilk_fbc_is_compressing, 626 .nuke = snb_fbc_nuke, 627 .program_cfb = ilk_fbc_program_cfb, 628 }; 629 630 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) 631 { 632 struct intel_display *display = fbc->display; 633 const struct intel_fbc_state *fbc_state = &fbc->state; 634 u32 val = 0; 635 636 if (fbc_state->override_cfb_stride) 637 val |= FBC_STRIDE_OVERRIDE | 638 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 639 640 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); 641 } 642 643 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) 644 { 645 struct intel_display *display = fbc->display; 646 const struct intel_fbc_state *fbc_state = &fbc->state; 647 u32 val = 0; 648 649 /* Display WA #0529: skl, kbl, bxt. */ 650 if (fbc_state->override_cfb_stride) 651 val |= CHICKEN_FBC_STRIDE_OVERRIDE | 652 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 653 654 intel_de_rmw(display, CHICKEN_MISC_4, 655 CHICKEN_FBC_STRIDE_OVERRIDE | 656 CHICKEN_FBC_STRIDE_MASK, val); 657 } 658 659 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) 660 { 661 struct intel_display *display = fbc->display; 662 const struct intel_fbc_state *fbc_state = &fbc->state; 663 u32 dpfc_ctl; 664 665 dpfc_ctl = g4x_dpfc_ctl_limit(fbc); 666 667 if (display->platform.ivybridge) 668 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); 669 670 if (DISPLAY_VER(display) >= 20) 671 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); 672 673 if (fbc_state->fence_id >= 0) 674 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; 675 676 if (fbc->false_color) 677 dpfc_ctl |= DPFC_CTL_FALSE_COLOR; 678 679 return dpfc_ctl; 680 } 681 682 static void ivb_fbc_activate(struct intel_fbc *fbc) 683 { 684 struct intel_display *display = fbc->display; 685 u32 dpfc_ctl; 686 687 if (DISPLAY_VER(display) >= 10) 688 glk_fbc_program_cfb_stride(fbc); 689 else if (DISPLAY_VER(display) == 9) 690 skl_fbc_program_cfb_stride(fbc); 691 692 if (intel_fbc_has_fences(display)) 693 snb_fbc_program_fence(fbc); 694 695 /* wa_14019417088 Alternative WA*/ 696 dpfc_ctl = ivb_dpfc_ctl(fbc); 697 if (DISPLAY_VER(display) >= 20) 698 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 699 700 if (HAS_FBC_DIRTY_RECT(display)) 701 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 702 FBC_DIRTY_RECT_EN); 703 704 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 705 DPFC_CTL_EN | dpfc_ctl); 706 } 707 708 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) 709 { 710 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; 711 } 712 713 static void ivb_fbc_set_false_color(struct intel_fbc *fbc, 714 bool enable) 715 { 716 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), 717 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); 718 } 719 720 static const struct intel_fbc_funcs ivb_fbc_funcs = { 721 .activate = ivb_fbc_activate, 722 .deactivate = ilk_fbc_deactivate, 723 .is_active = ilk_fbc_is_active, 724 .is_compressing = ivb_fbc_is_compressing, 725 .nuke = snb_fbc_nuke, 726 .program_cfb = ilk_fbc_program_cfb, 727 .set_false_color = ivb_fbc_set_false_color, 728 }; 729 730 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc) 731 { 732 return fbc->funcs->is_active(fbc); 733 } 734 735 static void intel_fbc_hw_activate(struct intel_fbc *fbc) 736 { 737 trace_intel_fbc_activate(fbc->state.plane); 738 739 fbc->active = true; 740 fbc->activated = true; 741 742 fbc->funcs->activate(fbc); 743 } 744 745 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) 746 { 747 trace_intel_fbc_deactivate(fbc->state.plane); 748 749 fbc->active = false; 750 751 fbc->funcs->deactivate(fbc); 752 } 753 754 static bool intel_fbc_is_compressing(struct intel_fbc *fbc) 755 { 756 return fbc->funcs->is_compressing(fbc); 757 } 758 759 static void intel_fbc_nuke(struct intel_fbc *fbc) 760 { 761 struct intel_display *display = fbc->display; 762 763 lockdep_assert_held(&fbc->lock); 764 drm_WARN_ON(display->drm, fbc->flip_pending); 765 766 trace_intel_fbc_nuke(fbc->state.plane); 767 768 fbc->funcs->nuke(fbc); 769 } 770 771 static void intel_fbc_activate(struct intel_fbc *fbc) 772 { 773 struct intel_display *display = fbc->display; 774 775 lockdep_assert_held(&fbc->lock); 776 777 /* only the fence can change for a flip nuke */ 778 if (fbc->active && !intel_fbc_has_fences(display)) 779 return; 780 /* 781 * In case of FBC dirt rect, any updates to the FBC registers will 782 * trigger the nuke. 783 */ 784 drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display)); 785 786 intel_fbc_hw_activate(fbc); 787 intel_fbc_nuke(fbc); 788 789 fbc->no_fbc_reason = NULL; 790 } 791 792 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) 793 { 794 lockdep_assert_held(&fbc->lock); 795 796 if (fbc->active) 797 intel_fbc_hw_deactivate(fbc); 798 799 fbc->no_fbc_reason = reason; 800 } 801 802 static u64 intel_fbc_cfb_base_max(struct intel_display *display) 803 { 804 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 805 return BIT_ULL(28); 806 else 807 return BIT_ULL(32); 808 } 809 810 static u64 intel_fbc_stolen_end(struct intel_display *display) 811 { 812 u64 end = intel_fbc_cfb_base_max(display); 813 814 /* 815 * The FBC hardware for BDW/SKL doesn't have access to the stolen 816 * reserved range size, so it always assumes the maximum (8mb) is used. 817 * If we enable FBC using a CFB on that memory range we'll get FIFO 818 * underruns, even if that range is not reserved by the BIOS. 819 */ 820 if (display->platform.broadwell || 821 (DISPLAY_VER(display) == 9 && !display->platform.broxton)) { 822 u64 stolen_area_size = intel_parent_stolen_area_size(display); 823 824 /* 825 * If stolen_area_size is less than SZ_8M, use 826 * intel_fbc_cfb_base_max instead. This should not happen, 827 * so warn if it does. 828 */ 829 if (drm_WARN_ON(display->drm, 830 check_sub_overflow(stolen_area_size, 831 SZ_8M, &stolen_area_size))) 832 return end; 833 834 return min(end, stolen_area_size); 835 } 836 837 return end; 838 } 839 840 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) 841 { 842 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; 843 } 844 845 static int intel_fbc_max_limit(struct intel_display *display) 846 { 847 /* WaFbcOnly1to1Ratio:ctg */ 848 if (display->platform.g4x) 849 return 1; 850 851 /* 852 * FBC2 can only do 1:1, 1:2, 1:4, we limit 853 * FBC1 to the same out of convenience. 854 */ 855 return 4; 856 } 857 858 static int find_compression_limit(struct intel_fbc *fbc, 859 unsigned int size, int min_limit) 860 { 861 struct intel_display *display = fbc->display; 862 u64 end = intel_fbc_stolen_end(display); 863 int ret, limit = min_limit; 864 865 size /= limit; 866 867 /* Try to over-allocate to reduce reallocations and fragmentation. */ 868 ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 869 size <<= 1, 4096, 0, end); 870 if (ret == 0) 871 return limit; 872 873 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { 874 ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 875 size >>= 1, 4096, 0, end); 876 if (ret == 0) 877 return limit; 878 } 879 880 return 0; 881 } 882 883 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, 884 unsigned int size, int min_limit) 885 { 886 struct intel_display *display = fbc->display; 887 int ret; 888 889 drm_WARN_ON(display->drm, 890 intel_parent_stolen_node_allocated(display, fbc->compressed_fb)); 891 drm_WARN_ON(display->drm, 892 intel_parent_stolen_node_allocated(display, fbc->compressed_llb)); 893 894 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { 895 ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096); 896 if (ret) 897 goto err; 898 } 899 900 ret = find_compression_limit(fbc, size, min_limit); 901 if (!ret) 902 goto err_llb; 903 else if (ret > min_limit) 904 drm_info_once(display->drm, 905 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 906 907 fbc->limit = ret; 908 909 drm_dbg_kms(display->drm, 910 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 911 intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit); 912 return 0; 913 914 err_llb: 915 if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 916 intel_parent_stolen_remove_node(display, fbc->compressed_llb); 917 err: 918 if (intel_parent_stolen_initialized(display)) 919 drm_info_once(display->drm, 920 "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 921 return -ENOSPC; 922 } 923 924 static void intel_fbc_program_cfb(struct intel_fbc *fbc) 925 { 926 fbc->funcs->program_cfb(fbc); 927 } 928 929 static void intel_fbc_program_workarounds(struct intel_fbc *fbc) 930 { 931 struct intel_display *display = fbc->display; 932 933 if (display->platform.skylake || display->platform.broxton) { 934 /* 935 * WaFbcHighMemBwCorruptionAvoidance:skl,bxt 936 * Display WA #0883: skl,bxt 937 */ 938 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 939 0, DPFC_DISABLE_DUMMY0); 940 } 941 942 if (display->platform.skylake || display->platform.kabylake || 943 display->platform.coffeelake || display->platform.cometlake) { 944 /* 945 * WaFbcNukeOnHostModify:skl,kbl,cfl 946 * Display WA #0873: skl,kbl,cfl 947 */ 948 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 949 0, DPFC_NUKE_ON_ANY_MODIFICATION); 950 } 951 952 /* Wa_1409120013:icl,jsl,tgl,dg1 */ 953 if (IS_DISPLAY_VER(display, 11, 12)) 954 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 955 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL); 956 /* 957 * Wa_22014263786 958 * Fixes: Screen flicker with FBC and Package C state enabled 959 * Workaround: Forced SLB invalidation before start of new frame. 960 */ 961 if (intel_display_wa(display, 22014263786)) 962 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 963 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); 964 965 /* wa_18038517565 Disable DPFC clock gating before FBC enable */ 966 if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 967 fbc_compressor_clkgate_disable_wa(fbc, true); 968 } 969 970 static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg, 971 enum intel_fbc_id id) 972 { 973 if (!HAS_FBC_SYS_CACHE(display)) 974 return; 975 976 lockdep_assert_held(&display->fbc.sys_cache.lock); 977 978 /* 979 * Wa_14025769978: 980 * Fixes: SoC hardware issue in read caching 981 * Workaround: disable cache read setting which is enabled by default. 982 */ 983 if (!intel_display_wa(display, 14025769978)) 984 /* Cache read enable is set by default */ 985 reg |= FBC_SYS_CACHE_READ_ENABLE; 986 987 intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg); 988 989 display->fbc.sys_cache.id = id; 990 } 991 992 static void fbc_sys_cache_disable(const struct intel_fbc *fbc) 993 { 994 struct intel_display *display = fbc->display; 995 struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 996 997 mutex_lock(&sys_cache->lock); 998 /* clear only if "fbc" reserved the cache */ 999 if (sys_cache->id == fbc->id) 1000 fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 1001 mutex_unlock(&sys_cache->lock); 1002 } 1003 1004 static int fbc_sys_cache_limit(struct intel_display *display) 1005 { 1006 if (DISPLAY_VER(display) == 35) 1007 return 2 * 1024 * 1024; 1008 1009 return 0; 1010 } 1011 1012 static void fbc_sys_cache_enable(const struct intel_fbc *fbc) 1013 { 1014 struct intel_display *display = fbc->display; 1015 struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 1016 int range, offset; 1017 u32 cfg; 1018 1019 if (!HAS_FBC_SYS_CACHE(display)) 1020 return; 1021 1022 range = fbc_sys_cache_limit(display) / (64 * 1024); 1023 1024 offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024); 1025 1026 cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) | 1027 FBC_SYS_CACHE_START_BASE(offset); 1028 1029 mutex_lock(&sys_cache->lock); 1030 /* update sys cache config only if sys cache is unassigned */ 1031 if (sys_cache->id == FBC_SYS_CACHE_ID_NONE) 1032 fbc_sys_cache_update_config(display, cfg, fbc->id); 1033 mutex_unlock(&sys_cache->lock); 1034 } 1035 1036 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 1037 { 1038 struct intel_display *display = fbc->display; 1039 1040 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 1041 return; 1042 1043 if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 1044 intel_parent_stolen_remove_node(display, fbc->compressed_llb); 1045 if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb)) 1046 intel_parent_stolen_remove_node(display, fbc->compressed_fb); 1047 } 1048 1049 void intel_fbc_cleanup(struct intel_display *display) 1050 { 1051 struct intel_fbc *fbc; 1052 enum intel_fbc_id fbc_id; 1053 1054 for_each_intel_fbc(display, fbc, fbc_id) { 1055 mutex_lock(&fbc->lock); 1056 __intel_fbc_cleanup_cfb(fbc); 1057 mutex_unlock(&fbc->lock); 1058 1059 intel_parent_stolen_node_free(display, fbc->compressed_fb); 1060 intel_parent_stolen_node_free(display, fbc->compressed_llb); 1061 1062 kfree(fbc); 1063 } 1064 1065 mutex_lock(&display->fbc.sys_cache.lock); 1066 drm_WARN_ON(display->drm, 1067 display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE); 1068 mutex_unlock(&display->fbc.sys_cache.lock); 1069 } 1070 1071 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1072 { 1073 const struct drm_framebuffer *fb = plane_state->hw.fb; 1074 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1075 fb->format->cpp[0]; 1076 1077 return stride == 4096 || stride == 8192; 1078 } 1079 1080 static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1081 { 1082 const struct drm_framebuffer *fb = plane_state->hw.fb; 1083 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1084 fb->format->cpp[0]; 1085 1086 return stride >= 2048 && stride <= 16384; 1087 } 1088 1089 static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1090 { 1091 return true; 1092 } 1093 1094 static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1095 { 1096 const struct drm_framebuffer *fb = plane_state->hw.fb; 1097 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1098 fb->format->cpp[0]; 1099 1100 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ 1101 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) 1102 return false; 1103 1104 return true; 1105 } 1106 1107 static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1108 { 1109 return true; 1110 } 1111 1112 static bool stride_is_valid(const struct intel_plane_state *plane_state) 1113 { 1114 struct intel_display *display = to_intel_display(plane_state); 1115 1116 if (DISPLAY_VER(display) >= 11) 1117 return icl_fbc_stride_is_valid(plane_state); 1118 else if (DISPLAY_VER(display) >= 9) 1119 return skl_fbc_stride_is_valid(plane_state); 1120 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1121 return g4x_fbc_stride_is_valid(plane_state); 1122 else if (DISPLAY_VER(display) == 4) 1123 return i965_fbc_stride_is_valid(plane_state); 1124 else 1125 return i8xx_fbc_stride_is_valid(plane_state); 1126 } 1127 1128 static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1129 { 1130 struct intel_display *display = to_intel_display(plane_state); 1131 const struct drm_framebuffer *fb = plane_state->hw.fb; 1132 1133 switch (fb->format->format) { 1134 case DRM_FORMAT_XRGB8888: 1135 case DRM_FORMAT_XBGR8888: 1136 return true; 1137 case DRM_FORMAT_XRGB1555: 1138 case DRM_FORMAT_RGB565: 1139 /* 16bpp not supported on gen2 */ 1140 if (DISPLAY_VER(display) == 2) 1141 return false; 1142 return true; 1143 default: 1144 return false; 1145 } 1146 } 1147 1148 static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1149 { 1150 struct intel_display *display = to_intel_display(plane_state); 1151 const struct drm_framebuffer *fb = plane_state->hw.fb; 1152 1153 switch (fb->format->format) { 1154 case DRM_FORMAT_XRGB8888: 1155 case DRM_FORMAT_XBGR8888: 1156 return true; 1157 case DRM_FORMAT_RGB565: 1158 /* WaFbcOnly1to1Ratio:ctg */ 1159 if (display->platform.g4x) 1160 return false; 1161 return true; 1162 default: 1163 return false; 1164 } 1165 } 1166 1167 static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1168 { 1169 const struct drm_framebuffer *fb = plane_state->hw.fb; 1170 1171 switch (fb->format->format) { 1172 case DRM_FORMAT_XRGB8888: 1173 case DRM_FORMAT_XBGR8888: 1174 case DRM_FORMAT_ARGB8888: 1175 case DRM_FORMAT_ABGR8888: 1176 case DRM_FORMAT_RGB565: 1177 return true; 1178 default: 1179 return false; 1180 } 1181 } 1182 1183 static bool 1184 xe3p_lpd_fbc_fp16_format_is_valid(const struct intel_plane_state *plane_state) 1185 { 1186 const struct drm_framebuffer *fb = plane_state->hw.fb; 1187 1188 switch (fb->format->format) { 1189 case DRM_FORMAT_ARGB16161616F: 1190 case DRM_FORMAT_ABGR16161616F: 1191 return true; 1192 default: 1193 return false; 1194 } 1195 } 1196 1197 static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1198 { 1199 const struct drm_framebuffer *fb = plane_state->hw.fb; 1200 1201 if (lnl_fbc_pixel_format_is_valid(plane_state)) 1202 return true; 1203 1204 if (xe3p_lpd_fbc_fp16_format_is_valid(plane_state)) 1205 return true; 1206 1207 switch (fb->format->format) { 1208 case DRM_FORMAT_XRGB16161616: 1209 case DRM_FORMAT_XBGR16161616: 1210 case DRM_FORMAT_ARGB16161616: 1211 case DRM_FORMAT_ABGR16161616: 1212 return true; 1213 default: 1214 return false; 1215 } 1216 } 1217 1218 bool 1219 intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state) 1220 { 1221 struct intel_display *display = to_intel_display(plane_state); 1222 1223 return DISPLAY_VER(display) >= 35 && 1224 xe3p_lpd_fbc_fp16_format_is_valid(plane_state); 1225 } 1226 1227 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 1228 { 1229 struct intel_display *display = to_intel_display(plane_state); 1230 1231 if (DISPLAY_VER(display) >= 35) 1232 return xe3p_lpd_fbc_pixel_format_is_valid(plane_state); 1233 else if (DISPLAY_VER(display) >= 20) 1234 return lnl_fbc_pixel_format_is_valid(plane_state); 1235 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1236 return g4x_fbc_pixel_format_is_valid(plane_state); 1237 else 1238 return i8xx_fbc_pixel_format_is_valid(plane_state); 1239 } 1240 1241 static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1242 { 1243 return plane_state->hw.rotation == DRM_MODE_ROTATE_0; 1244 } 1245 1246 static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1247 { 1248 return true; 1249 } 1250 1251 static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1252 { 1253 const struct drm_framebuffer *fb = plane_state->hw.fb; 1254 unsigned int rotation = plane_state->hw.rotation; 1255 1256 if (fb->format->format == DRM_FORMAT_RGB565 && 1257 drm_rotation_90_or_270(rotation)) 1258 return false; 1259 1260 return true; 1261 } 1262 1263 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 1264 { 1265 struct intel_display *display = to_intel_display(plane_state); 1266 1267 if (DISPLAY_VER(display) >= 9) 1268 return skl_fbc_rotation_is_valid(plane_state); 1269 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1270 return g4x_fbc_rotation_is_valid(plane_state); 1271 else 1272 return i8xx_fbc_rotation_is_valid(plane_state); 1273 } 1274 1275 static void intel_fbc_max_surface_size(struct intel_display *display, 1276 unsigned int *w, unsigned int *h) 1277 { 1278 if (DISPLAY_VER(display) >= 11) { 1279 *w = 8192; 1280 *h = 4096; 1281 } else if (DISPLAY_VER(display) >= 10) { 1282 *w = 5120; 1283 *h = 4096; 1284 } else if (DISPLAY_VER(display) >= 7) { 1285 *w = 4096; 1286 *h = 4096; 1287 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1288 *w = 4096; 1289 *h = 2048; 1290 } else { 1291 *w = 2048; 1292 *h = 1536; 1293 } 1294 } 1295 1296 /* 1297 * For some reason, the hardware tracking starts looking at whatever we 1298 * programmed as the display plane base address register. It does not look at 1299 * the X and Y offset registers. That's why we include the src x/y offsets 1300 * instead of just looking at the plane size. 1301 */ 1302 static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state) 1303 { 1304 struct intel_display *display = to_intel_display(plane_state); 1305 unsigned int effective_w, effective_h, max_w, max_h; 1306 1307 intel_fbc_max_surface_size(display, &max_w, &max_h); 1308 1309 effective_w = plane_state->view.color_plane[0].x + 1310 (drm_rect_width(&plane_state->uapi.src) >> 16); 1311 effective_h = plane_state->view.color_plane[0].y + 1312 (drm_rect_height(&plane_state->uapi.src) >> 16); 1313 1314 return effective_w <= max_w && effective_h <= max_h; 1315 } 1316 1317 static void intel_fbc_max_plane_size(struct intel_display *display, 1318 unsigned int *w, unsigned int *h) 1319 { 1320 if (DISPLAY_VER(display) >= 10) { 1321 *w = 5120; 1322 *h = 4096; 1323 } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) { 1324 *w = 4096; 1325 *h = 4096; 1326 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1327 *w = 4096; 1328 *h = 2048; 1329 } else { 1330 *w = 2048; 1331 *h = 1536; 1332 } 1333 } 1334 1335 static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state) 1336 { 1337 struct intel_display *display = to_intel_display(plane_state); 1338 unsigned int w, h, max_w, max_h; 1339 1340 intel_fbc_max_plane_size(display, &max_w, &max_h); 1341 1342 w = drm_rect_width(&plane_state->uapi.src) >> 16; 1343 h = drm_rect_height(&plane_state->uapi.src) >> 16; 1344 1345 return w <= max_w && h <= max_h; 1346 } 1347 1348 static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state) 1349 { 1350 const struct drm_framebuffer *fb = plane_state->hw.fb; 1351 1352 return fb->modifier == I915_FORMAT_MOD_X_TILED; 1353 } 1354 1355 static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state) 1356 { 1357 return true; 1358 } 1359 1360 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 1361 { 1362 struct intel_display *display = to_intel_display(plane_state); 1363 1364 if (DISPLAY_VER(display) >= 9) 1365 return skl_fbc_tiling_valid(plane_state); 1366 else 1367 return i8xx_fbc_tiling_valid(plane_state); 1368 } 1369 1370 static void 1371 intel_fbc_invalidate_dirty_rect(struct intel_fbc *fbc) 1372 { 1373 lockdep_assert_held(&fbc->lock); 1374 1375 fbc->state.dirty_rect = DRM_RECT_INIT(0, 0, 0, 0); 1376 } 1377 1378 static void 1379 intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_fbc *fbc, 1380 const struct drm_rect *fbc_dirty_rect) 1381 { 1382 struct intel_display *display = fbc->display; 1383 1384 drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0); 1385 1386 intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), 1387 FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) | 1388 FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2 - 1)); 1389 } 1390 1391 static void 1392 intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_fbc *fbc) 1393 { 1394 const struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; 1395 1396 lockdep_assert_held(&fbc->lock); 1397 1398 if (!drm_rect_visible(fbc_dirty_rect)) 1399 return; 1400 1401 intel_fbc_program_dirty_rect(dsb, fbc, fbc_dirty_rect); 1402 } 1403 1404 void 1405 intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, 1406 struct intel_plane *plane) 1407 { 1408 struct intel_display *display = to_intel_display(plane); 1409 struct intel_fbc *fbc = plane->fbc; 1410 1411 if (!HAS_FBC_DIRTY_RECT(display)) 1412 return; 1413 1414 mutex_lock(&fbc->lock); 1415 1416 if (fbc->state.plane == plane) 1417 intel_fbc_dirty_rect_update(dsb, fbc); 1418 1419 mutex_unlock(&fbc->lock); 1420 } 1421 1422 static void 1423 intel_fbc_hw_intialize_dirty_rect(struct intel_fbc *fbc, 1424 const struct intel_plane_state *plane_state) 1425 { 1426 struct drm_rect src; 1427 1428 /* 1429 * Initializing the FBC HW with the whole plane area as the dirty rect. 1430 * This is to ensure that we have valid coords be written to the 1431 * HW as dirty rect. 1432 */ 1433 drm_rect_fp_to_int(&src, &plane_state->uapi.src); 1434 1435 intel_fbc_program_dirty_rect(NULL, fbc, &src); 1436 } 1437 1438 static void intel_fbc_update_state(struct intel_atomic_state *state, 1439 struct intel_crtc *crtc, 1440 struct intel_plane *plane) 1441 { 1442 struct intel_display *display = to_intel_display(state); 1443 const struct intel_crtc_state *crtc_state = 1444 intel_atomic_get_new_crtc_state(state, crtc); 1445 const struct intel_plane_state *plane_state = 1446 intel_atomic_get_new_plane_state(state, plane); 1447 struct intel_fbc *fbc = plane->fbc; 1448 struct intel_fbc_state *fbc_state = &fbc->state; 1449 1450 WARN_ON(plane_state->no_fbc_reason); 1451 WARN_ON(fbc_state->plane && fbc_state->plane != plane); 1452 1453 fbc_state->plane = plane; 1454 1455 /* FBC1 compression interval: arbitrary choice of 1 second */ 1456 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); 1457 1458 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); 1459 1460 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && 1461 !intel_fbc_has_fences(display)); 1462 1463 if (plane_state->flags & PLANE_HAS_FENCE) 1464 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma); 1465 else 1466 fbc_state->fence_id = -1; 1467 1468 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); 1469 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); 1470 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); 1471 } 1472 1473 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 1474 { 1475 struct intel_display *display = to_intel_display(plane_state); 1476 1477 /* 1478 * The use of a CPU fence is one of two ways to detect writes by the 1479 * CPU to the scanout and trigger updates to the FBC. 1480 * 1481 * The other method is by software tracking (see 1482 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke 1483 * the current compressed buffer and recompress it. 1484 * 1485 * Note that is possible for a tiled surface to be unmappable (and 1486 * so have no fence associated with it) due to aperture constraints 1487 * at the time of pinning. 1488 */ 1489 return DISPLAY_VER(display) >= 9 || 1490 (plane_state->flags & PLANE_HAS_FENCE && 1491 i915_vma_fence_id(plane_state->ggtt_vma) != -1); 1492 } 1493 1494 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) 1495 { 1496 struct intel_display *display = to_intel_display(plane_state); 1497 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1498 struct intel_fbc *fbc = plane->fbc; 1499 1500 return intel_fbc_min_limit(plane_state) <= fbc->limit && 1501 intel_fbc_cfb_size(plane_state) <= fbc->limit * 1502 intel_parent_stolen_node_size(display, fbc->compressed_fb); 1503 } 1504 1505 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) 1506 { 1507 return !plane_state->no_fbc_reason && 1508 intel_fbc_is_fence_ok(plane_state) && 1509 intel_fbc_is_cfb_ok(plane_state); 1510 } 1511 1512 static void 1513 __intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state, 1514 const struct intel_crtc_state *crtc_state) 1515 { 1516 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1517 struct intel_fbc *fbc = plane->fbc; 1518 struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; 1519 int width = drm_rect_width(&plane_state->uapi.src) >> 16; 1520 const struct drm_rect *damage = &plane_state->damage; 1521 int y_offset = plane_state->view.color_plane[0].y; 1522 1523 lockdep_assert_held(&fbc->lock); 1524 1525 if (intel_crtc_needs_modeset(crtc_state) || 1526 !intel_fbc_is_ok(plane_state)) { 1527 intel_fbc_invalidate_dirty_rect(fbc); 1528 return; 1529 } 1530 1531 if (drm_rect_visible(damage)) 1532 *fbc_dirty_rect = *damage; 1533 else 1534 /* dirty rect must cover at least one line */ 1535 *fbc_dirty_rect = DRM_RECT_INIT(0, y_offset, width, 1); 1536 } 1537 1538 void 1539 intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, 1540 struct intel_crtc *crtc) 1541 { 1542 struct intel_display *display = to_intel_display(state); 1543 const struct intel_crtc_state *crtc_state = 1544 intel_atomic_get_new_crtc_state(state, crtc); 1545 struct intel_plane_state *plane_state; 1546 struct intel_plane *plane; 1547 int i; 1548 1549 if (!HAS_FBC_DIRTY_RECT(display)) 1550 return; 1551 1552 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1553 struct intel_fbc *fbc = plane->fbc; 1554 1555 if (!fbc || plane->pipe != crtc->pipe) 1556 continue; 1557 1558 mutex_lock(&fbc->lock); 1559 1560 if (fbc->state.plane == plane) 1561 __intel_fbc_prepare_dirty_rect(plane_state, 1562 crtc_state); 1563 1564 mutex_unlock(&fbc->lock); 1565 } 1566 } 1567 1568 static int _intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) 1569 { 1570 struct intel_display *display = to_intel_display(crtc_state); 1571 1572 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 1573 if (display->platform.haswell || display->platform.broadwell) 1574 return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95); 1575 1576 /* no FBC specific limits to worry about */ 1577 return 0; 1578 } 1579 1580 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1581 struct intel_plane *plane) 1582 { 1583 struct intel_display *display = to_intel_display(state); 1584 struct intel_plane_state *plane_state = 1585 intel_atomic_get_new_plane_state(state, plane); 1586 const struct drm_framebuffer *fb = plane_state->hw.fb; 1587 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 1588 const struct intel_crtc_state *crtc_state; 1589 struct intel_fbc *fbc = plane->fbc; 1590 1591 if (!fbc) 1592 return 0; 1593 1594 if (!intel_parent_stolen_initialized(display)) { 1595 plane_state->no_fbc_reason = "stolen memory not initialised"; 1596 return 0; 1597 } 1598 1599 if (intel_parent_vgpu_active(display)) { 1600 plane_state->no_fbc_reason = "VGPU active"; 1601 return 0; 1602 } 1603 1604 if (!display->params.enable_fbc) { 1605 plane_state->no_fbc_reason = "disabled per module param or by default"; 1606 return 0; 1607 } 1608 1609 if (!plane_state->uapi.visible) { 1610 plane_state->no_fbc_reason = "plane not visible"; 1611 return 0; 1612 } 1613 1614 if (intel_display_wa(display, 16023588340)) { 1615 plane_state->no_fbc_reason = "Wa_16023588340"; 1616 return 0; 1617 } 1618 1619 /* 1620 * Wa_15018326506: 1621 * Fixes: Underrun during media decode 1622 * Workaround: Do not enable FBC 1623 */ 1624 if (intel_display_wa(display, 15018326506)) { 1625 plane_state->no_fbc_reason = "Wa_15018326506"; 1626 return 0; 1627 } 1628 1629 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1630 if (intel_display_vtd_active(display) && 1631 (display->platform.skylake || display->platform.broxton)) { 1632 plane_state->no_fbc_reason = "VT-d enabled"; 1633 return 0; 1634 } 1635 1636 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1637 1638 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1639 plane_state->no_fbc_reason = "interlaced mode not supported"; 1640 return 0; 1641 } 1642 1643 if (crtc_state->double_wide) { 1644 plane_state->no_fbc_reason = "double wide pipe not supported"; 1645 return 0; 1646 } 1647 1648 /* 1649 * Display 12+ is not supporting FBC with PSR2. 1650 * Recommendation is to keep this combination disabled 1651 * Bspec: 50422 HSD: 14010260002 1652 * 1653 * TODO: Implement a logic to select between PSR2 selective fetch and 1654 * FBC based on Bspec: 68881 in xe2lpd onwards. 1655 * 1656 * As we still see some strange underruns in those platforms while 1657 * disabling PSR2, keep FBC disabled in case of selective update is on 1658 * until the selection logic is implemented. 1659 */ 1660 if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) { 1661 plane_state->no_fbc_reason = "Selective update enabled"; 1662 return 0; 1663 } 1664 1665 /* Wa_14016291713 */ 1666 if ((IS_DISPLAY_VER(display, 12, 13) || 1667 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) && 1668 crtc_state->has_psr && !crtc_state->has_panel_replay) { 1669 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; 1670 return 0; 1671 } 1672 1673 if (!pixel_format_is_valid(plane_state)) { 1674 plane_state->no_fbc_reason = "pixel format not supported"; 1675 return 0; 1676 } 1677 1678 if (!tiling_is_valid(plane_state)) { 1679 plane_state->no_fbc_reason = "tiling not supported"; 1680 return 0; 1681 } 1682 1683 if (!rotation_is_valid(plane_state)) { 1684 plane_state->no_fbc_reason = "rotation not supported"; 1685 return 0; 1686 } 1687 1688 if (!stride_is_valid(plane_state)) { 1689 plane_state->no_fbc_reason = "stride not supported"; 1690 return 0; 1691 } 1692 1693 if (DISPLAY_VER(display) < 20 && 1694 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && 1695 fb->format->has_alpha) { 1696 plane_state->no_fbc_reason = "per-pixel alpha not supported"; 1697 return 0; 1698 } 1699 1700 if (!intel_fbc_plane_size_valid(plane_state)) { 1701 plane_state->no_fbc_reason = "plane size too big"; 1702 return 0; 1703 } 1704 1705 if (!intel_fbc_surface_size_ok(plane_state)) { 1706 plane_state->no_fbc_reason = "surface size too big"; 1707 return 0; 1708 } 1709 1710 /* 1711 * Work around a problem on GEN9+ HW, where enabling FBC on a plane 1712 * having a Y offset that isn't divisible by 4 causes FIFO underrun 1713 * and screen flicker. 1714 */ 1715 if (IS_DISPLAY_VER(display, 9, 12) && 1716 plane_state->view.color_plane[0].y & 3) { 1717 plane_state->no_fbc_reason = "plane start Y offset misaligned"; 1718 return 0; 1719 } 1720 1721 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1722 if (IS_DISPLAY_VER(display, 9, 12) && 1723 (plane_state->view.color_plane[0].y + 1724 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { 1725 plane_state->no_fbc_reason = "plane end Y offset misaligned"; 1726 return 0; 1727 } 1728 1729 if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) { 1730 plane_state->no_fbc_reason = "pixel rate too high"; 1731 return 0; 1732 } 1733 1734 plane_state->no_fbc_reason = NULL; 1735 1736 return 0; 1737 } 1738 1739 int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) 1740 { 1741 struct intel_display *display = to_intel_display(crtc_state); 1742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1743 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1744 int min_cdclk; 1745 1746 if (!plane->fbc) 1747 return 0; 1748 1749 min_cdclk = _intel_fbc_min_cdclk(crtc_state); 1750 1751 /* 1752 * Do not ask for more than the max CDCLK frequency, 1753 * if that is not enough FBC will simply not be used. 1754 */ 1755 if (min_cdclk > display->cdclk.max_cdclk_freq) 1756 return 0; 1757 1758 return min_cdclk; 1759 } 1760 1761 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, 1762 struct intel_crtc *crtc, 1763 struct intel_plane *plane) 1764 { 1765 const struct intel_crtc_state *new_crtc_state = 1766 intel_atomic_get_new_crtc_state(state, crtc); 1767 const struct intel_plane_state *old_plane_state = 1768 intel_atomic_get_old_plane_state(state, plane); 1769 const struct intel_plane_state *new_plane_state = 1770 intel_atomic_get_new_plane_state(state, plane); 1771 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb; 1772 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb; 1773 1774 if (intel_crtc_needs_modeset(new_crtc_state)) 1775 return false; 1776 1777 if (!intel_fbc_is_ok(old_plane_state) || 1778 !intel_fbc_is_ok(new_plane_state)) 1779 return false; 1780 1781 if (old_fb->format->format != new_fb->format->format) 1782 return false; 1783 1784 if (old_fb->modifier != new_fb->modifier) 1785 return false; 1786 1787 if (intel_fbc_plane_stride(old_plane_state) != 1788 intel_fbc_plane_stride(new_plane_state)) 1789 return false; 1790 1791 if (intel_fbc_cfb_stride(old_plane_state) != 1792 intel_fbc_cfb_stride(new_plane_state)) 1793 return false; 1794 1795 if (intel_fbc_cfb_size(old_plane_state) != 1796 intel_fbc_cfb_size(new_plane_state)) 1797 return false; 1798 1799 if (intel_fbc_override_cfb_stride(old_plane_state) != 1800 intel_fbc_override_cfb_stride(new_plane_state)) 1801 return false; 1802 1803 return true; 1804 } 1805 1806 static bool __intel_fbc_pre_update(struct intel_atomic_state *state, 1807 struct intel_crtc *crtc, 1808 struct intel_plane *plane) 1809 { 1810 struct intel_display *display = to_intel_display(state); 1811 struct intel_fbc *fbc = plane->fbc; 1812 bool need_vblank_wait = false; 1813 1814 lockdep_assert_held(&fbc->lock); 1815 1816 fbc->flip_pending = true; 1817 1818 if (intel_fbc_can_flip_nuke(state, crtc, plane)) 1819 return need_vblank_wait; 1820 1821 intel_fbc_deactivate(fbc, "update pending"); 1822 1823 /* 1824 * Display WA #1198: glk+ 1825 * Need an extra vblank wait between FBC disable and most plane 1826 * updates. Bspec says this is only needed for plane disable, but 1827 * that is not true. Touching most plane registers will cause the 1828 * corruption to appear. Also SKL/derivatives do not seem to be 1829 * affected. 1830 * 1831 * TODO: could optimize this a bit by sampling the frame 1832 * counter when we disable FBC (if it was already done earlier) 1833 * and skipping the extra vblank wait before the plane update 1834 * if at least one frame has already passed. 1835 */ 1836 if (fbc->activated && DISPLAY_VER(display) >= 10) 1837 need_vblank_wait = true; 1838 fbc->activated = false; 1839 1840 return need_vblank_wait; 1841 } 1842 1843 bool intel_fbc_pre_update(struct intel_atomic_state *state, 1844 struct intel_crtc *crtc) 1845 { 1846 const struct intel_plane_state __maybe_unused *plane_state; 1847 bool need_vblank_wait = false; 1848 struct intel_plane *plane; 1849 int i; 1850 1851 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1852 struct intel_fbc *fbc = plane->fbc; 1853 1854 if (!fbc || plane->pipe != crtc->pipe) 1855 continue; 1856 1857 mutex_lock(&fbc->lock); 1858 1859 if (fbc->state.plane == plane) 1860 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane); 1861 1862 mutex_unlock(&fbc->lock); 1863 } 1864 1865 return need_vblank_wait; 1866 } 1867 1868 static void __intel_fbc_disable(struct intel_fbc *fbc) 1869 { 1870 struct intel_display *display = fbc->display; 1871 struct intel_plane *plane = fbc->state.plane; 1872 1873 lockdep_assert_held(&fbc->lock); 1874 drm_WARN_ON(display->drm, fbc->active); 1875 1876 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1877 plane->base.base.id, plane->base.name); 1878 1879 intel_fbc_invalidate_dirty_rect(fbc); 1880 1881 __intel_fbc_cleanup_cfb(fbc); 1882 1883 fbc_sys_cache_disable(fbc); 1884 1885 /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 1886 if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 1887 fbc_compressor_clkgate_disable_wa(fbc, false); 1888 1889 fbc->state.plane = NULL; 1890 fbc->flip_pending = false; 1891 fbc->busy_bits = 0; 1892 } 1893 1894 static void __intel_fbc_post_update(struct intel_fbc *fbc) 1895 { 1896 lockdep_assert_held(&fbc->lock); 1897 1898 fbc->flip_pending = false; 1899 fbc->busy_bits = 0; 1900 1901 intel_fbc_activate(fbc); 1902 } 1903 1904 void intel_fbc_post_update(struct intel_atomic_state *state, 1905 struct intel_crtc *crtc) 1906 { 1907 const struct intel_plane_state __maybe_unused *plane_state; 1908 struct intel_plane *plane; 1909 int i; 1910 1911 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1912 struct intel_fbc *fbc = plane->fbc; 1913 1914 if (!fbc || plane->pipe != crtc->pipe) 1915 continue; 1916 1917 mutex_lock(&fbc->lock); 1918 1919 if (fbc->state.plane == plane) 1920 __intel_fbc_post_update(fbc); 1921 1922 mutex_unlock(&fbc->lock); 1923 } 1924 } 1925 1926 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) 1927 { 1928 if (fbc->state.plane) 1929 return fbc->state.plane->frontbuffer_bit; 1930 else 1931 return 0; 1932 } 1933 1934 static void __intel_fbc_invalidate(struct intel_fbc *fbc, 1935 unsigned int frontbuffer_bits, 1936 enum fb_op_origin origin) 1937 { 1938 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1939 return; 1940 1941 mutex_lock(&fbc->lock); 1942 1943 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc); 1944 if (!frontbuffer_bits) 1945 goto out; 1946 1947 fbc->busy_bits |= frontbuffer_bits; 1948 intel_fbc_deactivate(fbc, "frontbuffer write"); 1949 1950 out: 1951 mutex_unlock(&fbc->lock); 1952 } 1953 1954 void intel_fbc_invalidate(struct intel_display *display, 1955 unsigned int frontbuffer_bits, 1956 enum fb_op_origin origin) 1957 { 1958 struct intel_fbc *fbc; 1959 enum intel_fbc_id fbc_id; 1960 1961 for_each_intel_fbc(display, fbc, fbc_id) 1962 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin); 1963 1964 } 1965 1966 static void __intel_fbc_flush(struct intel_fbc *fbc, 1967 unsigned int frontbuffer_bits, 1968 enum fb_op_origin origin) 1969 { 1970 mutex_lock(&fbc->lock); 1971 1972 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc); 1973 if (!frontbuffer_bits) 1974 goto out; 1975 1976 fbc->busy_bits &= ~frontbuffer_bits; 1977 1978 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1979 goto out; 1980 1981 if (fbc->busy_bits || fbc->flip_pending) 1982 goto out; 1983 1984 if (fbc->active) 1985 intel_fbc_nuke(fbc); 1986 else 1987 intel_fbc_activate(fbc); 1988 1989 out: 1990 mutex_unlock(&fbc->lock); 1991 } 1992 1993 void intel_fbc_flush(struct intel_display *display, 1994 unsigned int frontbuffer_bits, 1995 enum fb_op_origin origin) 1996 { 1997 struct intel_fbc *fbc; 1998 enum intel_fbc_id fbc_id; 1999 2000 for_each_intel_fbc(display, fbc, fbc_id) 2001 __intel_fbc_flush(fbc, frontbuffer_bits, origin); 2002 } 2003 2004 int intel_fbc_atomic_check(struct intel_atomic_state *state) 2005 { 2006 struct intel_plane_state __maybe_unused *plane_state; 2007 struct intel_plane *plane; 2008 int i; 2009 2010 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2011 int ret; 2012 2013 ret = intel_fbc_check_plane(state, plane); 2014 if (ret) 2015 return ret; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static void __intel_fbc_enable(struct intel_atomic_state *state, 2022 struct intel_crtc *crtc, 2023 struct intel_plane *plane) 2024 { 2025 struct intel_display *display = to_intel_display(state); 2026 const struct intel_plane_state *plane_state = 2027 intel_atomic_get_new_plane_state(state, plane); 2028 struct intel_fbc *fbc = plane->fbc; 2029 2030 lockdep_assert_held(&fbc->lock); 2031 2032 if (fbc->state.plane) { 2033 if (fbc->state.plane != plane) 2034 return; 2035 2036 if (intel_fbc_is_ok(plane_state)) { 2037 intel_fbc_update_state(state, crtc, plane); 2038 return; 2039 } 2040 2041 __intel_fbc_disable(fbc); 2042 } 2043 2044 drm_WARN_ON(display->drm, fbc->active); 2045 2046 fbc->no_fbc_reason = plane_state->no_fbc_reason; 2047 if (fbc->no_fbc_reason) 2048 return; 2049 2050 if (!intel_fbc_is_fence_ok(plane_state)) { 2051 fbc->no_fbc_reason = "framebuffer not fenced"; 2052 return; 2053 } 2054 2055 if (fbc->underrun_detected) { 2056 fbc->no_fbc_reason = "FIFO underrun"; 2057 return; 2058 } 2059 2060 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), 2061 intel_fbc_min_limit(plane_state))) { 2062 fbc->no_fbc_reason = "not enough stolen memory"; 2063 return; 2064 } 2065 2066 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", 2067 plane->base.base.id, plane->base.name); 2068 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 2069 2070 intel_fbc_update_state(state, crtc, plane); 2071 2072 if (HAS_FBC_DIRTY_RECT(display)) 2073 intel_fbc_hw_intialize_dirty_rect(fbc, plane_state); 2074 2075 intel_fbc_program_workarounds(fbc); 2076 intel_fbc_program_cfb(fbc); 2077 2078 fbc_sys_cache_enable(fbc); 2079 } 2080 2081 /** 2082 * intel_fbc_disable - disable FBC if it's associated with crtc 2083 * @crtc: the CRTC 2084 * 2085 * This function disables FBC if it's associated with the provided CRTC. 2086 */ 2087 void intel_fbc_disable(struct intel_crtc *crtc) 2088 { 2089 struct intel_display *display = to_intel_display(crtc); 2090 struct intel_plane *plane; 2091 2092 for_each_intel_plane(display->drm, plane) { 2093 struct intel_fbc *fbc = plane->fbc; 2094 2095 if (!fbc || plane->pipe != crtc->pipe) 2096 continue; 2097 2098 mutex_lock(&fbc->lock); 2099 if (fbc->state.plane == plane) 2100 __intel_fbc_disable(fbc); 2101 mutex_unlock(&fbc->lock); 2102 } 2103 } 2104 2105 void intel_fbc_update(struct intel_atomic_state *state, 2106 struct intel_crtc *crtc) 2107 { 2108 const struct intel_crtc_state *crtc_state = 2109 intel_atomic_get_new_crtc_state(state, crtc); 2110 const struct intel_plane_state *plane_state; 2111 struct intel_plane *plane; 2112 int i; 2113 2114 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2115 struct intel_fbc *fbc = plane->fbc; 2116 2117 if (!fbc || plane->pipe != crtc->pipe) 2118 continue; 2119 2120 mutex_lock(&fbc->lock); 2121 2122 if (intel_crtc_needs_fastset(crtc_state) && 2123 plane_state->no_fbc_reason) { 2124 if (fbc->state.plane == plane) 2125 __intel_fbc_disable(fbc); 2126 } else { 2127 __intel_fbc_enable(state, crtc, plane); 2128 } 2129 2130 mutex_unlock(&fbc->lock); 2131 } 2132 } 2133 2134 static void intel_fbc_underrun_work_fn(struct work_struct *work) 2135 { 2136 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work); 2137 struct intel_display *display = fbc->display; 2138 2139 mutex_lock(&fbc->lock); 2140 2141 /* Maybe we were scheduled twice. */ 2142 if (fbc->underrun_detected || !fbc->state.plane) 2143 goto out; 2144 2145 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); 2146 fbc->underrun_detected = true; 2147 2148 intel_fbc_deactivate(fbc, "FIFO underrun"); 2149 if (!fbc->flip_pending) 2150 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe)); 2151 __intel_fbc_disable(fbc); 2152 out: 2153 mutex_unlock(&fbc->lock); 2154 } 2155 2156 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc) 2157 { 2158 struct intel_display *display = fbc->display; 2159 2160 cancel_work_sync(&fbc->underrun_work); 2161 2162 mutex_lock(&fbc->lock); 2163 2164 if (fbc->underrun_detected) { 2165 drm_dbg_kms(display->drm, 2166 "Re-allowing FBC after fifo underrun\n"); 2167 fbc->no_fbc_reason = "FIFO underrun cleared"; 2168 } 2169 2170 fbc->underrun_detected = false; 2171 mutex_unlock(&fbc->lock); 2172 } 2173 2174 /* 2175 * intel_fbc_reset_underrun - reset FBC fifo underrun status. 2176 * @display: display 2177 * 2178 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we 2179 * want to re-enable FBC after an underrun to increase test coverage. 2180 */ 2181 void intel_fbc_reset_underrun(struct intel_display *display) 2182 { 2183 struct intel_fbc *fbc; 2184 enum intel_fbc_id fbc_id; 2185 2186 for_each_intel_fbc(display, fbc, fbc_id) 2187 __intel_fbc_reset_underrun(fbc); 2188 } 2189 2190 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc) 2191 { 2192 struct intel_display *display = fbc->display; 2193 2194 /* 2195 * There's no guarantee that underrun_detected won't be set to true 2196 * right after this check and before the work is scheduled, but that's 2197 * not a problem since we'll check it again under the work function 2198 * while FBC is locked. This check here is just to prevent us from 2199 * unnecessarily scheduling the work, and it relies on the fact that we 2200 * never switch underrun_detect back to false after it's true. 2201 */ 2202 if (READ_ONCE(fbc->underrun_detected)) 2203 return; 2204 2205 queue_work(display->wq.unordered, &fbc->underrun_work); 2206 } 2207 2208 /** 2209 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 2210 * @display: display 2211 * 2212 * Without FBC, most underruns are harmless and don't really cause too many 2213 * problems, except for an annoying message on dmesg. With FBC, underruns can 2214 * become black screens or even worse, especially when paired with bad 2215 * watermarks. So in order for us to be on the safe side, completely disable FBC 2216 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe 2217 * already suggests that watermarks may be bad, so try to be as safe as 2218 * possible. 2219 * 2220 * This function is called from the IRQ handler. 2221 */ 2222 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) 2223 { 2224 struct intel_fbc *fbc; 2225 enum intel_fbc_id fbc_id; 2226 2227 for_each_intel_fbc(display, fbc, fbc_id) 2228 __intel_fbc_handle_fifo_underrun_irq(fbc); 2229 } 2230 2231 /** 2232 * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info 2233 * @display: display device instance 2234 * @pipe: the pipe possibly containing the FBC 2235 * @log: log the info? 2236 * 2237 * If @pipe does not contain an FBC instance, this function bails early. 2238 * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log 2239 * is true, printed with error level. 2240 */ 2241 void intel_fbc_read_underrun_dbg_info(struct intel_display *display, 2242 enum pipe pipe, bool log) 2243 { 2244 struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe); 2245 u32 val; 2246 2247 if (!fbc) 2248 return; 2249 2250 val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id)); 2251 if (!(val & FBC_UNDERRUN_DECMPR)) 2252 return; 2253 2254 intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR); 2255 2256 if (log) 2257 drm_err(display->drm, 2258 "Pipe %c FIFO underrun info: FBC decompressing\n", 2259 pipe_name(pipe)); 2260 } 2261 2262 /* 2263 * The DDX driver changes its behavior depending on the value it reads from 2264 * i915.enable_fbc, so sanitize it by translating the default value into either 2265 * 0 or 1 in order to allow it to know what's going on. 2266 * 2267 * Notice that this is done at driver initialization and we still allow user 2268 * space to change the value during runtime without sanitizing it again. IGT 2269 * relies on being able to change i915.enable_fbc at runtime. 2270 */ 2271 static int intel_sanitize_fbc_option(struct intel_display *display) 2272 { 2273 if (display->params.enable_fbc >= 0) 2274 return !!display->params.enable_fbc; 2275 2276 if (!HAS_FBC(display)) 2277 return 0; 2278 2279 if (display->platform.broadwell || DISPLAY_VER(display) >= 9) 2280 return 1; 2281 2282 return 0; 2283 } 2284 2285 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) 2286 { 2287 plane->fbc = fbc; 2288 } 2289 2290 static struct intel_fbc *intel_fbc_create(struct intel_display *display, 2291 enum intel_fbc_id fbc_id) 2292 { 2293 struct intel_fbc *fbc; 2294 2295 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); 2296 if (!fbc) 2297 return NULL; 2298 2299 fbc->compressed_fb = intel_parent_stolen_node_alloc(display); 2300 if (!fbc->compressed_fb) 2301 goto err; 2302 fbc->compressed_llb = intel_parent_stolen_node_alloc(display); 2303 if (!fbc->compressed_llb) 2304 goto err; 2305 2306 fbc->id = fbc_id; 2307 fbc->display = display; 2308 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 2309 mutex_init(&fbc->lock); 2310 2311 if (DISPLAY_VER(display) >= 7) 2312 fbc->funcs = &ivb_fbc_funcs; 2313 else if (DISPLAY_VER(display) == 6) 2314 fbc->funcs = &snb_fbc_funcs; 2315 else if (DISPLAY_VER(display) == 5) 2316 fbc->funcs = &ilk_fbc_funcs; 2317 else if (display->platform.g4x) 2318 fbc->funcs = &g4x_fbc_funcs; 2319 else if (DISPLAY_VER(display) == 4) 2320 fbc->funcs = &i965_fbc_funcs; 2321 else 2322 fbc->funcs = &i8xx_fbc_funcs; 2323 2324 return fbc; 2325 2326 err: 2327 intel_parent_stolen_node_free(display, fbc->compressed_llb); 2328 intel_parent_stolen_node_free(display, fbc->compressed_fb); 2329 kfree(fbc); 2330 2331 return NULL; 2332 } 2333 2334 /** 2335 * intel_fbc_init - Initialize FBC 2336 * @display: display 2337 * 2338 * This function might be called during PM init process. 2339 */ 2340 void intel_fbc_init(struct intel_display *display) 2341 { 2342 enum intel_fbc_id fbc_id; 2343 2344 display->params.enable_fbc = intel_sanitize_fbc_option(display); 2345 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", 2346 display->params.enable_fbc); 2347 2348 for_each_fbc_id(display, fbc_id) 2349 display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id); 2350 2351 mutex_init(&display->fbc.sys_cache.lock); 2352 display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE; 2353 } 2354 2355 /** 2356 * intel_fbc_sanitize - Sanitize FBC 2357 * @display: display 2358 * 2359 * Make sure FBC is initially disabled since we have no 2360 * idea eg. into which parts of stolen it might be scribbling 2361 * into. 2362 */ 2363 void intel_fbc_sanitize(struct intel_display *display) 2364 { 2365 struct intel_fbc *fbc; 2366 enum intel_fbc_id fbc_id; 2367 2368 for_each_intel_fbc(display, fbc, fbc_id) { 2369 if (intel_fbc_hw_is_active(fbc)) 2370 intel_fbc_hw_deactivate(fbc); 2371 } 2372 2373 /* Ensure the sys cache usage config is clear as well */ 2374 mutex_lock(&display->fbc.sys_cache.lock); 2375 fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 2376 mutex_unlock(&display->fbc.sys_cache.lock); 2377 } 2378 2379 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) 2380 { 2381 struct intel_fbc *fbc = m->private; 2382 struct intel_display *display = fbc->display; 2383 struct intel_plane *plane; 2384 struct ref_tracker *wakeref; 2385 2386 drm_modeset_lock_all(display->drm); 2387 2388 wakeref = intel_display_rpm_get(display); 2389 mutex_lock(&fbc->lock); 2390 2391 if (fbc->active) { 2392 seq_puts(m, "FBC enabled\n"); 2393 seq_printf(m, "Compressing: %s\n", 2394 str_yes_no(intel_fbc_is_compressing(fbc))); 2395 2396 mutex_lock(&display->fbc.sys_cache.lock); 2397 seq_printf(m, "Using system cache: %s\n", 2398 str_yes_no(display->fbc.sys_cache.id == fbc->id)); 2399 mutex_unlock(&display->fbc.sys_cache.lock); 2400 } else { 2401 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 2402 } 2403 2404 for_each_intel_plane(display->drm, plane) { 2405 const struct intel_plane_state *plane_state = 2406 to_intel_plane_state(plane->base.state); 2407 2408 if (plane->fbc != fbc) 2409 continue; 2410 2411 seq_printf(m, "%c [PLANE:%d:%s]: %s\n", 2412 fbc->state.plane == plane ? '*' : ' ', 2413 plane->base.base.id, plane->base.name, 2414 plane_state->no_fbc_reason ?: "FBC possible"); 2415 } 2416 2417 mutex_unlock(&fbc->lock); 2418 intel_display_rpm_put(display, wakeref); 2419 2420 drm_modeset_unlock_all(display->drm); 2421 2422 return 0; 2423 } 2424 2425 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status); 2426 2427 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val) 2428 { 2429 struct intel_fbc *fbc = data; 2430 2431 *val = fbc->false_color; 2432 2433 return 0; 2434 } 2435 2436 static int intel_fbc_debugfs_false_color_set(void *data, u64 val) 2437 { 2438 struct intel_fbc *fbc = data; 2439 2440 mutex_lock(&fbc->lock); 2441 2442 fbc->false_color = val; 2443 2444 if (fbc->active) 2445 fbc->funcs->set_false_color(fbc, fbc->false_color); 2446 2447 mutex_unlock(&fbc->lock); 2448 2449 return 0; 2450 } 2451 2452 DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops, 2453 intel_fbc_debugfs_false_color_get, 2454 intel_fbc_debugfs_false_color_set, 2455 "%llu\n"); 2456 2457 static void intel_fbc_debugfs_add(struct intel_fbc *fbc, 2458 struct dentry *parent) 2459 { 2460 debugfs_create_file("i915_fbc_status", 0444, parent, 2461 fbc, &intel_fbc_debugfs_status_fops); 2462 2463 if (fbc->funcs->set_false_color) 2464 debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent, 2465 fbc, &intel_fbc_debugfs_false_color_fops); 2466 } 2467 2468 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc) 2469 { 2470 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2471 2472 if (plane->fbc) 2473 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry); 2474 } 2475 2476 /* FIXME: remove this once igt is on board with per-crtc stuff */ 2477 void intel_fbc_debugfs_register(struct intel_display *display) 2478 { 2479 struct intel_fbc *fbc; 2480 2481 fbc = display->fbc.instances[INTEL_FBC_A]; 2482 if (fbc) 2483 intel_fbc_debugfs_add(fbc, display->drm->debugfs_root); 2484 } 2485