1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Frame Buffer Compression (FBC) 26 * 27 * FBC tries to save memory bandwidth (and so power consumption) by 28 * compressing the amount of memory used by the display. It is total 29 * transparent to user space and completely handled in the kernel. 30 * 31 * The benefits of FBC are mostly visible with solid backgrounds and 32 * variation-less patterns. It comes from keeping the memory footprint small 33 * and having fewer memory pages opened and accessed for refreshing the display. 34 * 35 * i915 is responsible to reserve stolen memory for FBC and configure its 36 * offset on proper registers. The hardware takes care of all 37 * compress/decompress. However there are many known cases where we have to 38 * forcibly disable it to allow proper screen updates. 39 */ 40 41 #include <linux/debugfs.h> 42 #include <linux/string_helpers.h> 43 44 #include <drm/drm_blend.h> 45 #include <drm/drm_fourcc.h> 46 #include <drm/drm_print.h> 47 48 #include "i915_vma.h" 49 #include "i9xx_plane_regs.h" 50 #include "intel_de.h" 51 #include "intel_display_device.h" 52 #include "intel_display_regs.h" 53 #include "intel_display_rpm.h" 54 #include "intel_display_trace.h" 55 #include "intel_display_types.h" 56 #include "intel_display_utils.h" 57 #include "intel_display_wa.h" 58 #include "intel_fbc.h" 59 #include "intel_fbc_regs.h" 60 #include "intel_frontbuffer.h" 61 #include "intel_parent.h" 62 #include "intel_step.h" 63 64 #define for_each_fbc_id(__display, __fbc_id) \ 65 for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \ 66 for_each_if(DISPLAY_RUNTIME_INFO(__display)->fbc_mask & BIT(__fbc_id)) 67 68 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \ 69 for_each_fbc_id((__display), (__fbc_id)) \ 70 for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)]) 71 72 #define FBC_SYS_CACHE_ID_NONE I915_MAX_FBCS 73 74 struct intel_fbc_funcs { 75 void (*activate)(struct intel_fbc *fbc); 76 void (*deactivate)(struct intel_fbc *fbc); 77 bool (*is_active)(struct intel_fbc *fbc); 78 bool (*is_compressing)(struct intel_fbc *fbc); 79 void (*nuke)(struct intel_fbc *fbc); 80 void (*program_cfb)(struct intel_fbc *fbc); 81 void (*set_false_color)(struct intel_fbc *fbc, bool enable); 82 }; 83 84 struct intel_fbc_state { 85 struct intel_plane *plane; 86 unsigned int cfb_stride; 87 unsigned int cfb_size; 88 unsigned int fence_y_offset; 89 u16 override_cfb_stride; 90 u16 interval; 91 s8 fence_id; 92 struct drm_rect dirty_rect; 93 }; 94 95 struct intel_fbc { 96 struct intel_display *display; 97 const struct intel_fbc_funcs *funcs; 98 99 /* This is always the outer lock when overlapping with stolen_lock */ 100 struct mutex lock; 101 unsigned int busy_bits; 102 103 struct intel_stolen_node *compressed_fb; 104 struct intel_stolen_node *compressed_llb; 105 106 enum intel_fbc_id id; 107 108 u8 limit; 109 110 bool false_color; 111 112 bool active; 113 bool activated; 114 bool flip_pending; 115 116 bool underrun_detected; 117 struct work_struct underrun_work; 118 119 /* 120 * This structure contains everything that's relevant to program the 121 * hardware registers. When we want to figure out if we need to disable 122 * and re-enable FBC for a new configuration we just check if there's 123 * something different in the struct. The genx_fbc_activate functions 124 * are supposed to read from it in order to program the registers. 125 */ 126 struct intel_fbc_state state; 127 const char *no_fbc_reason; 128 }; 129 130 static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *display, enum pipe pipe) 131 { 132 struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe); 133 struct intel_plane *primary = NULL; 134 135 primary = to_intel_plane(crtc->base.primary); 136 137 if (drm_WARN_ON(display->drm, !primary)) 138 return NULL; 139 140 return primary->fbc; 141 } 142 143 /* plane stride in pixels */ 144 static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane_state) 145 { 146 const struct drm_framebuffer *fb = plane_state->hw.fb; 147 unsigned int stride; 148 149 stride = plane_state->view.color_plane[0].mapping_stride; 150 if (!drm_rotation_90_or_270(plane_state->hw.rotation)) 151 stride /= fb->format->cpp[0]; 152 153 return stride; 154 } 155 156 static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state) 157 { 158 const struct drm_framebuffer *fb = plane_state->hw.fb; 159 unsigned int cpp = fb->format->cpp[0]; 160 161 return max(cpp, 4); 162 } 163 164 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */ 165 static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state) 166 { 167 unsigned int cpp = intel_fbc_cfb_cpp(plane_state); 168 169 return intel_fbc_plane_stride(plane_state) * cpp; 170 } 171 172 /* minimum acceptable cfb stride in bytes, assuming 1:1 compression limit */ 173 static unsigned int skl_fbc_min_cfb_stride(struct intel_display *display, 174 unsigned int cpp, unsigned int width) 175 { 176 unsigned int limit = 4; /* 1:4 compression limit is the worst case */ 177 unsigned int height = 4; /* FBC segment is 4 lines */ 178 unsigned int stride; 179 180 /* minimum segment stride we can use */ 181 stride = width * cpp * height / limit; 182 183 /* 184 * Wa_16011863758: icl+ 185 * Avoid some hardware segment address miscalculation. 186 */ 187 if (DISPLAY_VER(display) >= 11) 188 stride += 64; 189 190 /* 191 * At least some of the platforms require each 4 line segment to 192 * be 512 byte aligned. Just do it always for simplicity. 193 */ 194 stride = ALIGN(stride, 512); 195 196 /* convert back to single line equivalent with 1:1 compression limit */ 197 return stride * limit / height; 198 } 199 200 /* properly aligned cfb stride in bytes, assuming 1:1 compression limit */ 201 static unsigned int _intel_fbc_cfb_stride(struct intel_display *display, 202 unsigned int cpp, unsigned int width, 203 unsigned int stride) 204 { 205 /* 206 * At least some of the platforms require each 4 line segment to 207 * be 512 byte aligned. Aligning each line to 512 bytes guarantees 208 * that regardless of the compression limit we choose later. 209 */ 210 if (DISPLAY_VER(display) >= 9) 211 return max(ALIGN(stride, 512), skl_fbc_min_cfb_stride(display, cpp, width)); 212 else 213 return stride; 214 } 215 216 static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_state) 217 { 218 struct intel_display *display = to_intel_display(plane_state); 219 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 220 unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16; 221 unsigned int cpp = intel_fbc_cfb_cpp(plane_state); 222 223 return _intel_fbc_cfb_stride(display, cpp, width, stride); 224 } 225 226 /* 227 * Maximum height the hardware will compress, on HSW+ 228 * additional lines (up to the actual plane height) will 229 * remain uncompressed. 230 */ 231 static unsigned int intel_fbc_max_cfb_height(struct intel_display *display) 232 { 233 if (DISPLAY_VER(display) >= 8) 234 return 2560; 235 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 236 return 2048; 237 else 238 return 1536; 239 } 240 241 static unsigned int _intel_fbc_cfb_size(struct intel_display *display, 242 unsigned int height, unsigned int stride) 243 { 244 return min(height, intel_fbc_max_cfb_height(display)) * stride; 245 } 246 247 static unsigned int intel_fbc_cfb_size(const struct intel_plane_state *plane_state) 248 { 249 struct intel_display *display = to_intel_display(plane_state); 250 unsigned int height = drm_rect_height(&plane_state->uapi.src) >> 16; 251 252 return _intel_fbc_cfb_size(display, height, intel_fbc_cfb_stride(plane_state)); 253 } 254 255 static u16 intel_fbc_override_cfb_stride(const struct intel_plane_state *plane_state) 256 { 257 struct intel_display *display = to_intel_display(plane_state); 258 unsigned int stride_aligned = intel_fbc_cfb_stride(plane_state); 259 unsigned int stride = intel_fbc_plane_cfb_stride(plane_state); 260 const struct drm_framebuffer *fb = plane_state->hw.fb; 261 262 /* 263 * Override stride in 64 byte units per 4 line segment. 264 * 265 * Gen9 hw miscalculates cfb stride for linear as 266 * PLANE_STRIDE*512 instead of PLANE_STRIDE*64, so 267 * we always need to use the override there. 268 * 269 * wa_14022269668 For bmg, always program the FBC_STRIDE before fbc enable 270 */ 271 if (stride != stride_aligned || 272 (DISPLAY_VER(display) == 9 && fb->modifier == DRM_FORMAT_MOD_LINEAR) || 273 display->platform.battlemage) 274 return stride_aligned * 4 / 64; 275 276 return 0; 277 } 278 279 static bool intel_fbc_has_fences(struct intel_display *display) 280 { 281 return intel_parent_has_fenced_regions(display); 282 } 283 284 static u32 i8xx_fbc_ctl(struct intel_fbc *fbc) 285 { 286 struct intel_display *display = fbc->display; 287 const struct intel_fbc_state *fbc_state = &fbc->state; 288 unsigned int cfb_stride; 289 u32 fbc_ctl; 290 291 cfb_stride = fbc_state->cfb_stride / fbc->limit; 292 293 /* FBC_CTL wants 32B or 64B units */ 294 if (DISPLAY_VER(display) == 2) 295 cfb_stride = (cfb_stride / 32) - 1; 296 else 297 cfb_stride = (cfb_stride / 64) - 1; 298 299 fbc_ctl = FBC_CTL_PERIODIC | 300 FBC_CTL_INTERVAL(fbc_state->interval) | 301 FBC_CTL_STRIDE(cfb_stride); 302 303 if (display->platform.i945gm) 304 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 305 306 if (fbc_state->fence_id >= 0) 307 fbc_ctl |= FBC_CTL_FENCENO(fbc_state->fence_id); 308 309 return fbc_ctl; 310 } 311 312 static u32 i965_fbc_ctl2(struct intel_fbc *fbc) 313 { 314 const struct intel_fbc_state *fbc_state = &fbc->state; 315 u32 fbc_ctl2; 316 317 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | 318 FBC_CTL_PLANE(fbc_state->plane->i9xx_plane); 319 320 if (fbc_state->fence_id >= 0) 321 fbc_ctl2 |= FBC_CTL_CPU_FENCE_EN; 322 323 return fbc_ctl2; 324 } 325 326 static void i8xx_fbc_deactivate(struct intel_fbc *fbc) 327 { 328 struct intel_display *display = fbc->display; 329 u32 fbc_ctl; 330 331 /* Disable compression */ 332 fbc_ctl = intel_de_read(display, FBC_CONTROL); 333 if ((fbc_ctl & FBC_CTL_EN) == 0) 334 return; 335 336 fbc_ctl &= ~FBC_CTL_EN; 337 intel_de_write(display, FBC_CONTROL, fbc_ctl); 338 339 /* Wait for compressing bit to clear */ 340 if (intel_de_wait_for_clear_ms(display, FBC_STATUS, 341 FBC_STAT_COMPRESSING, 10)) { 342 drm_dbg_kms(display->drm, "FBC idle timed out\n"); 343 return; 344 } 345 } 346 347 static void i8xx_fbc_activate(struct intel_fbc *fbc) 348 { 349 struct intel_display *display = fbc->display; 350 const struct intel_fbc_state *fbc_state = &fbc->state; 351 int i; 352 353 /* Clear old tags */ 354 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 355 intel_de_write(display, FBC_TAG(i), 0); 356 357 if (DISPLAY_VER(display) == 4) { 358 intel_de_write(display, FBC_CONTROL2, 359 i965_fbc_ctl2(fbc)); 360 intel_de_write(display, FBC_FENCE_OFF, 361 fbc_state->fence_y_offset); 362 } 363 364 intel_de_write(display, FBC_CONTROL, 365 FBC_CTL_EN | i8xx_fbc_ctl(fbc)); 366 } 367 368 static bool i8xx_fbc_is_active(struct intel_fbc *fbc) 369 { 370 return intel_de_read(fbc->display, FBC_CONTROL) & FBC_CTL_EN; 371 } 372 373 static bool i8xx_fbc_is_compressing(struct intel_fbc *fbc) 374 { 375 return intel_de_read(fbc->display, FBC_STATUS) & 376 (FBC_STAT_COMPRESSING | FBC_STAT_COMPRESSED); 377 } 378 379 static void i8xx_fbc_nuke(struct intel_fbc *fbc) 380 { 381 struct intel_display *display = fbc->display; 382 struct intel_fbc_state *fbc_state = &fbc->state; 383 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 384 385 intel_de_write_fw(display, DSPADDR(display, i9xx_plane), 386 intel_de_read_fw(display, DSPADDR(display, i9xx_plane))); 387 } 388 389 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) 390 { 391 struct intel_display *display = fbc->display; 392 393 drm_WARN_ON(display->drm, 394 range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 395 intel_parent_stolen_node_offset(display, fbc->compressed_fb), 396 U32_MAX)); 397 drm_WARN_ON(display->drm, 398 range_end_overflows_t(u64, intel_parent_stolen_area_address(display), 399 intel_parent_stolen_node_offset(display, fbc->compressed_llb), 400 U32_MAX)); 401 intel_de_write(display, FBC_CFB_BASE, 402 intel_parent_stolen_node_address(display, fbc->compressed_fb)); 403 intel_de_write(display, FBC_LL_BASE, 404 intel_parent_stolen_node_address(display, fbc->compressed_llb)); 405 } 406 407 static const struct intel_fbc_funcs i8xx_fbc_funcs = { 408 .activate = i8xx_fbc_activate, 409 .deactivate = i8xx_fbc_deactivate, 410 .is_active = i8xx_fbc_is_active, 411 .is_compressing = i8xx_fbc_is_compressing, 412 .nuke = i8xx_fbc_nuke, 413 .program_cfb = i8xx_fbc_program_cfb, 414 }; 415 416 static void i965_fbc_nuke(struct intel_fbc *fbc) 417 { 418 struct intel_display *display = fbc->display; 419 struct intel_fbc_state *fbc_state = &fbc->state; 420 enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; 421 422 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), 423 intel_de_read_fw(display, DSPSURF(display, i9xx_plane))); 424 } 425 426 static const struct intel_fbc_funcs i965_fbc_funcs = { 427 .activate = i8xx_fbc_activate, 428 .deactivate = i8xx_fbc_deactivate, 429 .is_active = i8xx_fbc_is_active, 430 .is_compressing = i8xx_fbc_is_compressing, 431 .nuke = i965_fbc_nuke, 432 .program_cfb = i8xx_fbc_program_cfb, 433 }; 434 435 static u32 g4x_dpfc_ctl_limit(struct intel_fbc *fbc) 436 { 437 switch (fbc->limit) { 438 default: 439 MISSING_CASE(fbc->limit); 440 fallthrough; 441 case 1: 442 return DPFC_CTL_LIMIT_1X; 443 case 2: 444 return DPFC_CTL_LIMIT_2X; 445 case 4: 446 return DPFC_CTL_LIMIT_4X; 447 } 448 } 449 450 static u32 g4x_dpfc_ctl(struct intel_fbc *fbc) 451 { 452 struct intel_display *display = fbc->display; 453 const struct intel_fbc_state *fbc_state = &fbc->state; 454 u32 dpfc_ctl; 455 456 dpfc_ctl = g4x_dpfc_ctl_limit(fbc) | 457 DPFC_CTL_PLANE_G4X(fbc_state->plane->i9xx_plane); 458 459 if (display->platform.g4x) 460 dpfc_ctl |= DPFC_CTL_SR_EN; 461 462 if (fbc_state->fence_id >= 0) { 463 dpfc_ctl |= DPFC_CTL_FENCE_EN_G4X; 464 465 if (DISPLAY_VER(display) < 6) 466 dpfc_ctl |= DPFC_CTL_FENCENO(fbc_state->fence_id); 467 } 468 469 return dpfc_ctl; 470 } 471 472 static void g4x_fbc_activate(struct intel_fbc *fbc) 473 { 474 struct intel_display *display = fbc->display; 475 const struct intel_fbc_state *fbc_state = &fbc->state; 476 477 intel_de_write(display, DPFC_FENCE_YOFF, 478 fbc_state->fence_y_offset); 479 480 intel_de_write(display, DPFC_CONTROL, 481 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 482 } 483 484 static void g4x_fbc_deactivate(struct intel_fbc *fbc) 485 { 486 struct intel_display *display = fbc->display; 487 u32 dpfc_ctl; 488 489 /* Disable compression */ 490 dpfc_ctl = intel_de_read(display, DPFC_CONTROL); 491 if (dpfc_ctl & DPFC_CTL_EN) { 492 dpfc_ctl &= ~DPFC_CTL_EN; 493 intel_de_write(display, DPFC_CONTROL, dpfc_ctl); 494 } 495 } 496 497 static bool g4x_fbc_is_active(struct intel_fbc *fbc) 498 { 499 return intel_de_read(fbc->display, DPFC_CONTROL) & DPFC_CTL_EN; 500 } 501 502 static bool g4x_fbc_is_compressing(struct intel_fbc *fbc) 503 { 504 return intel_de_read(fbc->display, DPFC_STATUS) & DPFC_COMP_SEG_MASK; 505 } 506 507 static void g4x_fbc_program_cfb(struct intel_fbc *fbc) 508 { 509 struct intel_display *display = fbc->display; 510 511 intel_de_write(display, DPFC_CB_BASE, 512 intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 513 } 514 515 static const struct intel_fbc_funcs g4x_fbc_funcs = { 516 .activate = g4x_fbc_activate, 517 .deactivate = g4x_fbc_deactivate, 518 .is_active = g4x_fbc_is_active, 519 .is_compressing = g4x_fbc_is_compressing, 520 .nuke = i965_fbc_nuke, 521 .program_cfb = g4x_fbc_program_cfb, 522 }; 523 524 static void ilk_fbc_activate(struct intel_fbc *fbc) 525 { 526 struct intel_display *display = fbc->display; 527 struct intel_fbc_state *fbc_state = &fbc->state; 528 529 intel_de_write(display, ILK_DPFC_FENCE_YOFF(fbc->id), 530 fbc_state->fence_y_offset); 531 532 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 533 DPFC_CTL_EN | g4x_dpfc_ctl(fbc)); 534 } 535 536 static void fbc_compressor_clkgate_disable_wa(struct intel_fbc *fbc, 537 bool disable) 538 { 539 struct intel_display *display = fbc->display; 540 541 if (display->platform.dg2) 542 intel_de_rmw(display, GEN9_CLKGATE_DIS_4, DG2_DPFC_GATING_DIS, 543 disable ? DG2_DPFC_GATING_DIS : 0); 544 else if (DISPLAY_VER(display) >= 14) 545 intel_de_rmw(display, MTL_PIPE_CLKGATE_DIS2(fbc->id), 546 MTL_DPFC_GATING_DIS, 547 disable ? MTL_DPFC_GATING_DIS : 0); 548 } 549 550 static void ilk_fbc_deactivate(struct intel_fbc *fbc) 551 { 552 struct intel_display *display = fbc->display; 553 u32 dpfc_ctl; 554 555 if (HAS_FBC_DIRTY_RECT(display)) 556 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 0); 557 558 /* Disable compression */ 559 dpfc_ctl = intel_de_read(display, ILK_DPFC_CONTROL(fbc->id)); 560 if (dpfc_ctl & DPFC_CTL_EN) { 561 dpfc_ctl &= ~DPFC_CTL_EN; 562 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 563 } 564 } 565 566 static bool ilk_fbc_is_active(struct intel_fbc *fbc) 567 { 568 return intel_de_read(fbc->display, ILK_DPFC_CONTROL(fbc->id)) & DPFC_CTL_EN; 569 } 570 571 static bool ilk_fbc_is_compressing(struct intel_fbc *fbc) 572 { 573 return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK; 574 } 575 576 static void ilk_fbc_program_cfb(struct intel_fbc *fbc) 577 { 578 struct intel_display *display = fbc->display; 579 580 intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id), 581 intel_parent_stolen_node_offset(display, fbc->compressed_fb)); 582 } 583 584 static const struct intel_fbc_funcs ilk_fbc_funcs = { 585 .activate = ilk_fbc_activate, 586 .deactivate = ilk_fbc_deactivate, 587 .is_active = ilk_fbc_is_active, 588 .is_compressing = ilk_fbc_is_compressing, 589 .nuke = i965_fbc_nuke, 590 .program_cfb = ilk_fbc_program_cfb, 591 }; 592 593 static void snb_fbc_program_fence(struct intel_fbc *fbc) 594 { 595 struct intel_display *display = fbc->display; 596 const struct intel_fbc_state *fbc_state = &fbc->state; 597 u32 ctl = 0; 598 599 if (fbc_state->fence_id >= 0) 600 ctl = SNB_DPFC_FENCE_EN | SNB_DPFC_FENCENO(fbc_state->fence_id); 601 602 intel_de_write(display, SNB_DPFC_CTL_SA, ctl); 603 intel_de_write(display, SNB_DPFC_CPU_FENCE_OFFSET, fbc_state->fence_y_offset); 604 } 605 606 static void snb_fbc_activate(struct intel_fbc *fbc) 607 { 608 snb_fbc_program_fence(fbc); 609 610 ilk_fbc_activate(fbc); 611 } 612 613 static void snb_fbc_nuke(struct intel_fbc *fbc) 614 { 615 struct intel_display *display = fbc->display; 616 617 intel_de_write(display, MSG_FBC_REND_STATE(fbc->id), FBC_REND_NUKE); 618 intel_de_posting_read(display, MSG_FBC_REND_STATE(fbc->id)); 619 } 620 621 static const struct intel_fbc_funcs snb_fbc_funcs = { 622 .activate = snb_fbc_activate, 623 .deactivate = ilk_fbc_deactivate, 624 .is_active = ilk_fbc_is_active, 625 .is_compressing = ilk_fbc_is_compressing, 626 .nuke = snb_fbc_nuke, 627 .program_cfb = ilk_fbc_program_cfb, 628 }; 629 630 static void glk_fbc_program_cfb_stride(struct intel_fbc *fbc) 631 { 632 struct intel_display *display = fbc->display; 633 const struct intel_fbc_state *fbc_state = &fbc->state; 634 u32 val = 0; 635 636 if (fbc_state->override_cfb_stride) 637 val |= FBC_STRIDE_OVERRIDE | 638 FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 639 640 intel_de_write(display, GLK_FBC_STRIDE(fbc->id), val); 641 } 642 643 static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc) 644 { 645 struct intel_display *display = fbc->display; 646 const struct intel_fbc_state *fbc_state = &fbc->state; 647 u32 val = 0; 648 649 /* Display WA #0529: skl, kbl, bxt. */ 650 if (fbc_state->override_cfb_stride) 651 val |= CHICKEN_FBC_STRIDE_OVERRIDE | 652 CHICKEN_FBC_STRIDE(fbc_state->override_cfb_stride / fbc->limit); 653 654 intel_de_rmw(display, CHICKEN_MISC_4, 655 CHICKEN_FBC_STRIDE_OVERRIDE | 656 CHICKEN_FBC_STRIDE_MASK, val); 657 } 658 659 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc) 660 { 661 struct intel_display *display = fbc->display; 662 const struct intel_fbc_state *fbc_state = &fbc->state; 663 u32 dpfc_ctl; 664 665 dpfc_ctl = g4x_dpfc_ctl_limit(fbc); 666 667 if (display->platform.ivybridge) 668 dpfc_ctl |= DPFC_CTL_PLANE_IVB(fbc_state->plane->i9xx_plane); 669 670 if (DISPLAY_VER(display) >= 20) 671 dpfc_ctl |= DPFC_CTL_PLANE_BINDING(fbc_state->plane->id); 672 673 if (fbc_state->fence_id >= 0) 674 dpfc_ctl |= DPFC_CTL_FENCE_EN_IVB; 675 676 if (fbc->false_color) 677 dpfc_ctl |= DPFC_CTL_FALSE_COLOR; 678 679 return dpfc_ctl; 680 } 681 682 static void ivb_fbc_activate(struct intel_fbc *fbc) 683 { 684 struct intel_display *display = fbc->display; 685 u32 dpfc_ctl; 686 687 if (DISPLAY_VER(display) >= 10) 688 glk_fbc_program_cfb_stride(fbc); 689 else if (DISPLAY_VER(display) == 9) 690 skl_fbc_program_cfb_stride(fbc); 691 692 if (intel_fbc_has_fences(display)) 693 snb_fbc_program_fence(fbc); 694 695 /* wa_14019417088 Alternative WA*/ 696 dpfc_ctl = ivb_dpfc_ctl(fbc); 697 if (DISPLAY_VER(display) >= 20) 698 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), dpfc_ctl); 699 700 if (HAS_FBC_DIRTY_RECT(display)) 701 intel_de_write(display, XE3_FBC_DIRTY_CTL(fbc->id), 702 FBC_DIRTY_RECT_EN); 703 704 intel_de_write(display, ILK_DPFC_CONTROL(fbc->id), 705 DPFC_CTL_EN | dpfc_ctl); 706 } 707 708 static bool ivb_fbc_is_compressing(struct intel_fbc *fbc) 709 { 710 return intel_de_read(fbc->display, ILK_DPFC_STATUS2(fbc->id)) & DPFC_COMP_SEG_MASK_IVB; 711 } 712 713 static void ivb_fbc_set_false_color(struct intel_fbc *fbc, 714 bool enable) 715 { 716 intel_de_rmw(fbc->display, ILK_DPFC_CONTROL(fbc->id), 717 DPFC_CTL_FALSE_COLOR, enable ? DPFC_CTL_FALSE_COLOR : 0); 718 } 719 720 static const struct intel_fbc_funcs ivb_fbc_funcs = { 721 .activate = ivb_fbc_activate, 722 .deactivate = ilk_fbc_deactivate, 723 .is_active = ilk_fbc_is_active, 724 .is_compressing = ivb_fbc_is_compressing, 725 .nuke = snb_fbc_nuke, 726 .program_cfb = ilk_fbc_program_cfb, 727 .set_false_color = ivb_fbc_set_false_color, 728 }; 729 730 static bool intel_fbc_hw_is_active(struct intel_fbc *fbc) 731 { 732 return fbc->funcs->is_active(fbc); 733 } 734 735 static void intel_fbc_hw_activate(struct intel_fbc *fbc) 736 { 737 trace_intel_fbc_activate(fbc->state.plane); 738 739 fbc->active = true; 740 fbc->activated = true; 741 742 fbc->funcs->activate(fbc); 743 } 744 745 static void intel_fbc_hw_deactivate(struct intel_fbc *fbc) 746 { 747 trace_intel_fbc_deactivate(fbc->state.plane); 748 749 fbc->active = false; 750 751 fbc->funcs->deactivate(fbc); 752 } 753 754 static bool intel_fbc_is_compressing(struct intel_fbc *fbc) 755 { 756 return fbc->funcs->is_compressing(fbc); 757 } 758 759 static void intel_fbc_nuke(struct intel_fbc *fbc) 760 { 761 struct intel_display *display = fbc->display; 762 763 lockdep_assert_held(&fbc->lock); 764 drm_WARN_ON(display->drm, fbc->flip_pending); 765 766 trace_intel_fbc_nuke(fbc->state.plane); 767 768 fbc->funcs->nuke(fbc); 769 } 770 771 static void intel_fbc_activate(struct intel_fbc *fbc) 772 { 773 struct intel_display *display = fbc->display; 774 775 lockdep_assert_held(&fbc->lock); 776 777 /* only the fence can change for a flip nuke */ 778 if (fbc->active && !intel_fbc_has_fences(display)) 779 return; 780 /* 781 * In case of FBC dirt rect, any updates to the FBC registers will 782 * trigger the nuke. 783 */ 784 drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display)); 785 786 intel_fbc_hw_activate(fbc); 787 intel_fbc_nuke(fbc); 788 789 fbc->no_fbc_reason = NULL; 790 } 791 792 static void intel_fbc_deactivate(struct intel_fbc *fbc, const char *reason) 793 { 794 lockdep_assert_held(&fbc->lock); 795 796 if (fbc->active) 797 intel_fbc_hw_deactivate(fbc); 798 799 fbc->no_fbc_reason = reason; 800 } 801 802 static u64 intel_fbc_cfb_base_max(struct intel_display *display) 803 { 804 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 805 return BIT_ULL(28); 806 else 807 return BIT_ULL(32); 808 } 809 810 static u64 intel_fbc_stolen_end(struct intel_display *display) 811 { 812 u64 end; 813 814 /* The FBC hardware for BDW/SKL doesn't have access to the stolen 815 * reserved range size, so it always assumes the maximum (8mb) is used. 816 * If we enable FBC using a CFB on that memory range we'll get FIFO 817 * underruns, even if that range is not reserved by the BIOS. */ 818 if (display->platform.broadwell || 819 (DISPLAY_VER(display) == 9 && !display->platform.broxton)) 820 end = intel_parent_stolen_area_size(display) - 8 * 1024 * 1024; 821 else 822 end = U64_MAX; 823 824 return min(end, intel_fbc_cfb_base_max(display)); 825 } 826 827 static int intel_fbc_min_limit(const struct intel_plane_state *plane_state) 828 { 829 return plane_state->hw.fb->format->cpp[0] == 2 ? 2 : 1; 830 } 831 832 static int intel_fbc_max_limit(struct intel_display *display) 833 { 834 /* WaFbcOnly1to1Ratio:ctg */ 835 if (display->platform.g4x) 836 return 1; 837 838 /* 839 * FBC2 can only do 1:1, 1:2, 1:4, we limit 840 * FBC1 to the same out of convenience. 841 */ 842 return 4; 843 } 844 845 static int find_compression_limit(struct intel_fbc *fbc, 846 unsigned int size, int min_limit) 847 { 848 struct intel_display *display = fbc->display; 849 u64 end = intel_fbc_stolen_end(display); 850 int ret, limit = min_limit; 851 852 size /= limit; 853 854 /* Try to over-allocate to reduce reallocations and fragmentation. */ 855 ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 856 size <<= 1, 4096, 0, end); 857 if (ret == 0) 858 return limit; 859 860 for (; limit <= intel_fbc_max_limit(display); limit <<= 1) { 861 ret = intel_parent_stolen_insert_node_in_range(display, fbc->compressed_fb, 862 size >>= 1, 4096, 0, end); 863 if (ret == 0) 864 return limit; 865 } 866 867 return 0; 868 } 869 870 static int intel_fbc_alloc_cfb(struct intel_fbc *fbc, 871 unsigned int size, int min_limit) 872 { 873 struct intel_display *display = fbc->display; 874 int ret; 875 876 drm_WARN_ON(display->drm, 877 intel_parent_stolen_node_allocated(display, fbc->compressed_fb)); 878 drm_WARN_ON(display->drm, 879 intel_parent_stolen_node_allocated(display, fbc->compressed_llb)); 880 881 if (DISPLAY_VER(display) < 5 && !display->platform.g4x) { 882 ret = intel_parent_stolen_insert_node(display, fbc->compressed_llb, 4096, 4096); 883 if (ret) 884 goto err; 885 } 886 887 ret = find_compression_limit(fbc, size, min_limit); 888 if (!ret) 889 goto err_llb; 890 else if (ret > min_limit) 891 drm_info_once(display->drm, 892 "Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n"); 893 894 fbc->limit = ret; 895 896 drm_dbg_kms(display->drm, 897 "reserved %llu bytes of contiguous stolen space for FBC, limit: %d\n", 898 intel_parent_stolen_node_size(display, fbc->compressed_fb), fbc->limit); 899 return 0; 900 901 err_llb: 902 if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 903 intel_parent_stolen_remove_node(display, fbc->compressed_llb); 904 err: 905 if (intel_parent_stolen_initialized(display)) 906 drm_info_once(display->drm, 907 "not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size); 908 return -ENOSPC; 909 } 910 911 static void intel_fbc_program_cfb(struct intel_fbc *fbc) 912 { 913 fbc->funcs->program_cfb(fbc); 914 } 915 916 static void intel_fbc_program_workarounds(struct intel_fbc *fbc) 917 { 918 struct intel_display *display = fbc->display; 919 920 if (display->platform.skylake || display->platform.broxton) { 921 /* 922 * WaFbcHighMemBwCorruptionAvoidance:skl,bxt 923 * Display WA #0883: skl,bxt 924 */ 925 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 926 0, DPFC_DISABLE_DUMMY0); 927 } 928 929 if (display->platform.skylake || display->platform.kabylake || 930 display->platform.coffeelake || display->platform.cometlake) { 931 /* 932 * WaFbcNukeOnHostModify:skl,kbl,cfl 933 * Display WA #0873: skl,kbl,cfl 934 */ 935 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 936 0, DPFC_NUKE_ON_ANY_MODIFICATION); 937 } 938 939 /* Wa_1409120013:icl,jsl,tgl,dg1 */ 940 if (IS_DISPLAY_VER(display, 11, 12)) 941 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 942 0, DPFC_CHICKEN_COMP_DUMMY_PIXEL); 943 /* 944 * Wa_22014263786 945 * Fixes: Screen flicker with FBC and Package C state enabled 946 * Workaround: Forced SLB invalidation before start of new frame. 947 */ 948 if (intel_display_wa(display, 22014263786)) 949 intel_de_rmw(display, ILK_DPFC_CHICKEN(fbc->id), 950 0, DPFC_CHICKEN_FORCE_SLB_INVALIDATION); 951 952 /* wa_18038517565 Disable DPFC clock gating before FBC enable */ 953 if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 954 fbc_compressor_clkgate_disable_wa(fbc, true); 955 } 956 957 static void fbc_sys_cache_update_config(struct intel_display *display, u32 reg, 958 enum intel_fbc_id id) 959 { 960 if (!HAS_FBC_SYS_CACHE(display)) 961 return; 962 963 lockdep_assert_held(&display->fbc.sys_cache.lock); 964 965 /* 966 * Wa_14025769978: 967 * Fixes: SoC hardware issue in read caching 968 * Workaround: disable cache read setting which is enabled by default. 969 */ 970 if (!intel_display_wa(display, 14025769978)) 971 /* Cache read enable is set by default */ 972 reg |= FBC_SYS_CACHE_READ_ENABLE; 973 974 intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg); 975 976 display->fbc.sys_cache.id = id; 977 } 978 979 static void fbc_sys_cache_disable(const struct intel_fbc *fbc) 980 { 981 struct intel_display *display = fbc->display; 982 struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 983 984 mutex_lock(&sys_cache->lock); 985 /* clear only if "fbc" reserved the cache */ 986 if (sys_cache->id == fbc->id) 987 fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 988 mutex_unlock(&sys_cache->lock); 989 } 990 991 static int fbc_sys_cache_limit(struct intel_display *display) 992 { 993 if (DISPLAY_VER(display) == 35) 994 return 2 * 1024 * 1024; 995 996 return 0; 997 } 998 999 static void fbc_sys_cache_enable(const struct intel_fbc *fbc) 1000 { 1001 struct intel_display *display = fbc->display; 1002 struct sys_cache_cfg *sys_cache = &display->fbc.sys_cache; 1003 int range, offset; 1004 u32 cfg; 1005 1006 if (!HAS_FBC_SYS_CACHE(display)) 1007 return; 1008 1009 range = fbc_sys_cache_limit(display) / (64 * 1024); 1010 1011 offset = intel_parent_stolen_node_offset(display, fbc->compressed_fb) / (4 * 1024); 1012 1013 cfg = FBC_SYS_CACHE_TAG_USE_RES_SPACE | FBC_SYS_CACHEABLE_RANGE(range) | 1014 FBC_SYS_CACHE_START_BASE(offset); 1015 1016 mutex_lock(&sys_cache->lock); 1017 /* update sys cache config only if sys cache is unassigned */ 1018 if (sys_cache->id == FBC_SYS_CACHE_ID_NONE) 1019 fbc_sys_cache_update_config(display, cfg, fbc->id); 1020 mutex_unlock(&sys_cache->lock); 1021 } 1022 1023 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc) 1024 { 1025 struct intel_display *display = fbc->display; 1026 1027 if (WARN_ON(intel_fbc_hw_is_active(fbc))) 1028 return; 1029 1030 if (intel_parent_stolen_node_allocated(display, fbc->compressed_llb)) 1031 intel_parent_stolen_remove_node(display, fbc->compressed_llb); 1032 if (intel_parent_stolen_node_allocated(display, fbc->compressed_fb)) 1033 intel_parent_stolen_remove_node(display, fbc->compressed_fb); 1034 } 1035 1036 void intel_fbc_cleanup(struct intel_display *display) 1037 { 1038 struct intel_fbc *fbc; 1039 enum intel_fbc_id fbc_id; 1040 1041 for_each_intel_fbc(display, fbc, fbc_id) { 1042 mutex_lock(&fbc->lock); 1043 __intel_fbc_cleanup_cfb(fbc); 1044 mutex_unlock(&fbc->lock); 1045 1046 intel_parent_stolen_node_free(display, fbc->compressed_fb); 1047 intel_parent_stolen_node_free(display, fbc->compressed_llb); 1048 1049 kfree(fbc); 1050 } 1051 1052 mutex_lock(&display->fbc.sys_cache.lock); 1053 drm_WARN_ON(display->drm, 1054 display->fbc.sys_cache.id != FBC_SYS_CACHE_ID_NONE); 1055 mutex_unlock(&display->fbc.sys_cache.lock); 1056 } 1057 1058 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1059 { 1060 const struct drm_framebuffer *fb = plane_state->hw.fb; 1061 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1062 fb->format->cpp[0]; 1063 1064 return stride == 4096 || stride == 8192; 1065 } 1066 1067 static bool i965_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1068 { 1069 const struct drm_framebuffer *fb = plane_state->hw.fb; 1070 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1071 fb->format->cpp[0]; 1072 1073 return stride >= 2048 && stride <= 16384; 1074 } 1075 1076 static bool g4x_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1077 { 1078 return true; 1079 } 1080 1081 static bool skl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1082 { 1083 const struct drm_framebuffer *fb = plane_state->hw.fb; 1084 unsigned int stride = intel_fbc_plane_stride(plane_state) * 1085 fb->format->cpp[0]; 1086 1087 /* Display WA #1105: skl,bxt,kbl,cfl,glk */ 1088 if (fb->modifier == DRM_FORMAT_MOD_LINEAR && stride & 511) 1089 return false; 1090 1091 return true; 1092 } 1093 1094 static bool icl_fbc_stride_is_valid(const struct intel_plane_state *plane_state) 1095 { 1096 return true; 1097 } 1098 1099 static bool stride_is_valid(const struct intel_plane_state *plane_state) 1100 { 1101 struct intel_display *display = to_intel_display(plane_state); 1102 1103 if (DISPLAY_VER(display) >= 11) 1104 return icl_fbc_stride_is_valid(plane_state); 1105 else if (DISPLAY_VER(display) >= 9) 1106 return skl_fbc_stride_is_valid(plane_state); 1107 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1108 return g4x_fbc_stride_is_valid(plane_state); 1109 else if (DISPLAY_VER(display) == 4) 1110 return i965_fbc_stride_is_valid(plane_state); 1111 else 1112 return i8xx_fbc_stride_is_valid(plane_state); 1113 } 1114 1115 static bool i8xx_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1116 { 1117 struct intel_display *display = to_intel_display(plane_state); 1118 const struct drm_framebuffer *fb = plane_state->hw.fb; 1119 1120 switch (fb->format->format) { 1121 case DRM_FORMAT_XRGB8888: 1122 case DRM_FORMAT_XBGR8888: 1123 return true; 1124 case DRM_FORMAT_XRGB1555: 1125 case DRM_FORMAT_RGB565: 1126 /* 16bpp not supported on gen2 */ 1127 if (DISPLAY_VER(display) == 2) 1128 return false; 1129 return true; 1130 default: 1131 return false; 1132 } 1133 } 1134 1135 static bool g4x_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1136 { 1137 struct intel_display *display = to_intel_display(plane_state); 1138 const struct drm_framebuffer *fb = plane_state->hw.fb; 1139 1140 switch (fb->format->format) { 1141 case DRM_FORMAT_XRGB8888: 1142 case DRM_FORMAT_XBGR8888: 1143 return true; 1144 case DRM_FORMAT_RGB565: 1145 /* WaFbcOnly1to1Ratio:ctg */ 1146 if (display->platform.g4x) 1147 return false; 1148 return true; 1149 default: 1150 return false; 1151 } 1152 } 1153 1154 static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1155 { 1156 const struct drm_framebuffer *fb = plane_state->hw.fb; 1157 1158 switch (fb->format->format) { 1159 case DRM_FORMAT_XRGB8888: 1160 case DRM_FORMAT_XBGR8888: 1161 case DRM_FORMAT_ARGB8888: 1162 case DRM_FORMAT_ABGR8888: 1163 case DRM_FORMAT_RGB565: 1164 return true; 1165 default: 1166 return false; 1167 } 1168 } 1169 1170 static bool 1171 xe3p_lpd_fbc_fp16_format_is_valid(const struct intel_plane_state *plane_state) 1172 { 1173 const struct drm_framebuffer *fb = plane_state->hw.fb; 1174 1175 switch (fb->format->format) { 1176 case DRM_FORMAT_ARGB16161616F: 1177 case DRM_FORMAT_ABGR16161616F: 1178 return true; 1179 default: 1180 return false; 1181 } 1182 } 1183 1184 static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state) 1185 { 1186 const struct drm_framebuffer *fb = plane_state->hw.fb; 1187 1188 if (lnl_fbc_pixel_format_is_valid(plane_state)) 1189 return true; 1190 1191 if (xe3p_lpd_fbc_fp16_format_is_valid(plane_state)) 1192 return true; 1193 1194 switch (fb->format->format) { 1195 case DRM_FORMAT_XRGB16161616: 1196 case DRM_FORMAT_XBGR16161616: 1197 case DRM_FORMAT_ARGB16161616: 1198 case DRM_FORMAT_ABGR16161616: 1199 return true; 1200 default: 1201 return false; 1202 } 1203 } 1204 1205 bool 1206 intel_fbc_is_enable_pixel_normalizer(const struct intel_plane_state *plane_state) 1207 { 1208 struct intel_display *display = to_intel_display(plane_state); 1209 1210 return DISPLAY_VER(display) >= 35 && 1211 xe3p_lpd_fbc_fp16_format_is_valid(plane_state); 1212 } 1213 1214 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state) 1215 { 1216 struct intel_display *display = to_intel_display(plane_state); 1217 1218 if (DISPLAY_VER(display) >= 35) 1219 return xe3p_lpd_fbc_pixel_format_is_valid(plane_state); 1220 else if (DISPLAY_VER(display) >= 20) 1221 return lnl_fbc_pixel_format_is_valid(plane_state); 1222 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1223 return g4x_fbc_pixel_format_is_valid(plane_state); 1224 else 1225 return i8xx_fbc_pixel_format_is_valid(plane_state); 1226 } 1227 1228 static bool i8xx_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1229 { 1230 return plane_state->hw.rotation == DRM_MODE_ROTATE_0; 1231 } 1232 1233 static bool g4x_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1234 { 1235 return true; 1236 } 1237 1238 static bool skl_fbc_rotation_is_valid(const struct intel_plane_state *plane_state) 1239 { 1240 const struct drm_framebuffer *fb = plane_state->hw.fb; 1241 unsigned int rotation = plane_state->hw.rotation; 1242 1243 if (fb->format->format == DRM_FORMAT_RGB565 && 1244 drm_rotation_90_or_270(rotation)) 1245 return false; 1246 1247 return true; 1248 } 1249 1250 static bool rotation_is_valid(const struct intel_plane_state *plane_state) 1251 { 1252 struct intel_display *display = to_intel_display(plane_state); 1253 1254 if (DISPLAY_VER(display) >= 9) 1255 return skl_fbc_rotation_is_valid(plane_state); 1256 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) 1257 return g4x_fbc_rotation_is_valid(plane_state); 1258 else 1259 return i8xx_fbc_rotation_is_valid(plane_state); 1260 } 1261 1262 static void intel_fbc_max_surface_size(struct intel_display *display, 1263 unsigned int *w, unsigned int *h) 1264 { 1265 if (DISPLAY_VER(display) >= 11) { 1266 *w = 8192; 1267 *h = 4096; 1268 } else if (DISPLAY_VER(display) >= 10) { 1269 *w = 5120; 1270 *h = 4096; 1271 } else if (DISPLAY_VER(display) >= 7) { 1272 *w = 4096; 1273 *h = 4096; 1274 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1275 *w = 4096; 1276 *h = 2048; 1277 } else { 1278 *w = 2048; 1279 *h = 1536; 1280 } 1281 } 1282 1283 /* 1284 * For some reason, the hardware tracking starts looking at whatever we 1285 * programmed as the display plane base address register. It does not look at 1286 * the X and Y offset registers. That's why we include the src x/y offsets 1287 * instead of just looking at the plane size. 1288 */ 1289 static bool intel_fbc_surface_size_ok(const struct intel_plane_state *plane_state) 1290 { 1291 struct intel_display *display = to_intel_display(plane_state); 1292 unsigned int effective_w, effective_h, max_w, max_h; 1293 1294 intel_fbc_max_surface_size(display, &max_w, &max_h); 1295 1296 effective_w = plane_state->view.color_plane[0].x + 1297 (drm_rect_width(&plane_state->uapi.src) >> 16); 1298 effective_h = plane_state->view.color_plane[0].y + 1299 (drm_rect_height(&plane_state->uapi.src) >> 16); 1300 1301 return effective_w <= max_w && effective_h <= max_h; 1302 } 1303 1304 static void intel_fbc_max_plane_size(struct intel_display *display, 1305 unsigned int *w, unsigned int *h) 1306 { 1307 if (DISPLAY_VER(display) >= 10) { 1308 *w = 5120; 1309 *h = 4096; 1310 } else if (DISPLAY_VER(display) >= 8 || display->platform.haswell) { 1311 *w = 4096; 1312 *h = 4096; 1313 } else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) { 1314 *w = 4096; 1315 *h = 2048; 1316 } else { 1317 *w = 2048; 1318 *h = 1536; 1319 } 1320 } 1321 1322 static bool intel_fbc_plane_size_valid(const struct intel_plane_state *plane_state) 1323 { 1324 struct intel_display *display = to_intel_display(plane_state); 1325 unsigned int w, h, max_w, max_h; 1326 1327 intel_fbc_max_plane_size(display, &max_w, &max_h); 1328 1329 w = drm_rect_width(&plane_state->uapi.src) >> 16; 1330 h = drm_rect_height(&plane_state->uapi.src) >> 16; 1331 1332 return w <= max_w && h <= max_h; 1333 } 1334 1335 static bool i8xx_fbc_tiling_valid(const struct intel_plane_state *plane_state) 1336 { 1337 const struct drm_framebuffer *fb = plane_state->hw.fb; 1338 1339 return fb->modifier == I915_FORMAT_MOD_X_TILED; 1340 } 1341 1342 static bool skl_fbc_tiling_valid(const struct intel_plane_state *plane_state) 1343 { 1344 return true; 1345 } 1346 1347 static bool tiling_is_valid(const struct intel_plane_state *plane_state) 1348 { 1349 struct intel_display *display = to_intel_display(plane_state); 1350 1351 if (DISPLAY_VER(display) >= 9) 1352 return skl_fbc_tiling_valid(plane_state); 1353 else 1354 return i8xx_fbc_tiling_valid(plane_state); 1355 } 1356 1357 static void 1358 intel_fbc_invalidate_dirty_rect(struct intel_fbc *fbc) 1359 { 1360 lockdep_assert_held(&fbc->lock); 1361 1362 fbc->state.dirty_rect = DRM_RECT_INIT(0, 0, 0, 0); 1363 } 1364 1365 static void 1366 intel_fbc_program_dirty_rect(struct intel_dsb *dsb, struct intel_fbc *fbc, 1367 const struct drm_rect *fbc_dirty_rect) 1368 { 1369 struct intel_display *display = fbc->display; 1370 1371 drm_WARN_ON(display->drm, fbc_dirty_rect->y2 == 0); 1372 1373 intel_de_write_dsb(display, dsb, XE3_FBC_DIRTY_RECT(fbc->id), 1374 FBC_DIRTY_RECT_START_LINE(fbc_dirty_rect->y1) | 1375 FBC_DIRTY_RECT_END_LINE(fbc_dirty_rect->y2 - 1)); 1376 } 1377 1378 static void 1379 intel_fbc_dirty_rect_update(struct intel_dsb *dsb, struct intel_fbc *fbc) 1380 { 1381 const struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; 1382 1383 lockdep_assert_held(&fbc->lock); 1384 1385 if (!drm_rect_visible(fbc_dirty_rect)) 1386 return; 1387 1388 intel_fbc_program_dirty_rect(dsb, fbc, fbc_dirty_rect); 1389 } 1390 1391 void 1392 intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb, 1393 struct intel_plane *plane) 1394 { 1395 struct intel_display *display = to_intel_display(plane); 1396 struct intel_fbc *fbc = plane->fbc; 1397 1398 if (!HAS_FBC_DIRTY_RECT(display)) 1399 return; 1400 1401 mutex_lock(&fbc->lock); 1402 1403 if (fbc->state.plane == plane) 1404 intel_fbc_dirty_rect_update(dsb, fbc); 1405 1406 mutex_unlock(&fbc->lock); 1407 } 1408 1409 static void 1410 intel_fbc_hw_intialize_dirty_rect(struct intel_fbc *fbc, 1411 const struct intel_plane_state *plane_state) 1412 { 1413 struct drm_rect src; 1414 1415 /* 1416 * Initializing the FBC HW with the whole plane area as the dirty rect. 1417 * This is to ensure that we have valid coords be written to the 1418 * HW as dirty rect. 1419 */ 1420 drm_rect_fp_to_int(&src, &plane_state->uapi.src); 1421 1422 intel_fbc_program_dirty_rect(NULL, fbc, &src); 1423 } 1424 1425 static void intel_fbc_update_state(struct intel_atomic_state *state, 1426 struct intel_crtc *crtc, 1427 struct intel_plane *plane) 1428 { 1429 struct intel_display *display = to_intel_display(state); 1430 const struct intel_crtc_state *crtc_state = 1431 intel_atomic_get_new_crtc_state(state, crtc); 1432 const struct intel_plane_state *plane_state = 1433 intel_atomic_get_new_plane_state(state, plane); 1434 struct intel_fbc *fbc = plane->fbc; 1435 struct intel_fbc_state *fbc_state = &fbc->state; 1436 1437 WARN_ON(plane_state->no_fbc_reason); 1438 WARN_ON(fbc_state->plane && fbc_state->plane != plane); 1439 1440 fbc_state->plane = plane; 1441 1442 /* FBC1 compression interval: arbitrary choice of 1 second */ 1443 fbc_state->interval = drm_mode_vrefresh(&crtc_state->hw.adjusted_mode); 1444 1445 fbc_state->fence_y_offset = intel_plane_fence_y_offset(plane_state); 1446 1447 drm_WARN_ON(display->drm, plane_state->flags & PLANE_HAS_FENCE && 1448 !intel_fbc_has_fences(display)); 1449 1450 if (plane_state->flags & PLANE_HAS_FENCE) 1451 fbc_state->fence_id = i915_vma_fence_id(plane_state->ggtt_vma); 1452 else 1453 fbc_state->fence_id = -1; 1454 1455 fbc_state->cfb_stride = intel_fbc_cfb_stride(plane_state); 1456 fbc_state->cfb_size = intel_fbc_cfb_size(plane_state); 1457 fbc_state->override_cfb_stride = intel_fbc_override_cfb_stride(plane_state); 1458 } 1459 1460 static bool intel_fbc_is_fence_ok(const struct intel_plane_state *plane_state) 1461 { 1462 struct intel_display *display = to_intel_display(plane_state); 1463 1464 /* 1465 * The use of a CPU fence is one of two ways to detect writes by the 1466 * CPU to the scanout and trigger updates to the FBC. 1467 * 1468 * The other method is by software tracking (see 1469 * intel_fbc_invalidate/flush()), it will manually notify FBC and nuke 1470 * the current compressed buffer and recompress it. 1471 * 1472 * Note that is possible for a tiled surface to be unmappable (and 1473 * so have no fence associated with it) due to aperture constraints 1474 * at the time of pinning. 1475 */ 1476 return DISPLAY_VER(display) >= 9 || 1477 (plane_state->flags & PLANE_HAS_FENCE && 1478 i915_vma_fence_id(plane_state->ggtt_vma) != -1); 1479 } 1480 1481 static bool intel_fbc_is_cfb_ok(const struct intel_plane_state *plane_state) 1482 { 1483 struct intel_display *display = to_intel_display(plane_state); 1484 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1485 struct intel_fbc *fbc = plane->fbc; 1486 1487 return intel_fbc_min_limit(plane_state) <= fbc->limit && 1488 intel_fbc_cfb_size(plane_state) <= fbc->limit * 1489 intel_parent_stolen_node_size(display, fbc->compressed_fb); 1490 } 1491 1492 static bool intel_fbc_is_ok(const struct intel_plane_state *plane_state) 1493 { 1494 return !plane_state->no_fbc_reason && 1495 intel_fbc_is_fence_ok(plane_state) && 1496 intel_fbc_is_cfb_ok(plane_state); 1497 } 1498 1499 static void 1500 __intel_fbc_prepare_dirty_rect(const struct intel_plane_state *plane_state, 1501 const struct intel_crtc_state *crtc_state) 1502 { 1503 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1504 struct intel_fbc *fbc = plane->fbc; 1505 struct drm_rect *fbc_dirty_rect = &fbc->state.dirty_rect; 1506 int width = drm_rect_width(&plane_state->uapi.src) >> 16; 1507 const struct drm_rect *damage = &plane_state->damage; 1508 int y_offset = plane_state->view.color_plane[0].y; 1509 1510 lockdep_assert_held(&fbc->lock); 1511 1512 if (intel_crtc_needs_modeset(crtc_state) || 1513 !intel_fbc_is_ok(plane_state)) { 1514 intel_fbc_invalidate_dirty_rect(fbc); 1515 return; 1516 } 1517 1518 if (drm_rect_visible(damage)) 1519 *fbc_dirty_rect = *damage; 1520 else 1521 /* dirty rect must cover at least one line */ 1522 *fbc_dirty_rect = DRM_RECT_INIT(0, y_offset, width, 1); 1523 } 1524 1525 void 1526 intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state, 1527 struct intel_crtc *crtc) 1528 { 1529 struct intel_display *display = to_intel_display(state); 1530 const struct intel_crtc_state *crtc_state = 1531 intel_atomic_get_new_crtc_state(state, crtc); 1532 struct intel_plane_state *plane_state; 1533 struct intel_plane *plane; 1534 int i; 1535 1536 if (!HAS_FBC_DIRTY_RECT(display)) 1537 return; 1538 1539 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1540 struct intel_fbc *fbc = plane->fbc; 1541 1542 if (!fbc || plane->pipe != crtc->pipe) 1543 continue; 1544 1545 mutex_lock(&fbc->lock); 1546 1547 if (fbc->state.plane == plane) 1548 __intel_fbc_prepare_dirty_rect(plane_state, 1549 crtc_state); 1550 1551 mutex_unlock(&fbc->lock); 1552 } 1553 } 1554 1555 static int _intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) 1556 { 1557 struct intel_display *display = to_intel_display(crtc_state); 1558 1559 /* WaFbcExceedCdClockThreshold:hsw,bdw */ 1560 if (display->platform.haswell || display->platform.broadwell) 1561 return DIV_ROUND_UP(crtc_state->pixel_rate * 100, 95); 1562 1563 /* no FBC specific limits to worry about */ 1564 return 0; 1565 } 1566 1567 static int intel_fbc_check_plane(struct intel_atomic_state *state, 1568 struct intel_plane *plane) 1569 { 1570 struct intel_display *display = to_intel_display(state); 1571 struct intel_plane_state *plane_state = 1572 intel_atomic_get_new_plane_state(state, plane); 1573 const struct drm_framebuffer *fb = plane_state->hw.fb; 1574 struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc); 1575 const struct intel_crtc_state *crtc_state; 1576 struct intel_fbc *fbc = plane->fbc; 1577 1578 if (!fbc) 1579 return 0; 1580 1581 if (!intel_parent_stolen_initialized(display)) { 1582 plane_state->no_fbc_reason = "stolen memory not initialised"; 1583 return 0; 1584 } 1585 1586 if (intel_parent_vgpu_active(display)) { 1587 plane_state->no_fbc_reason = "VGPU active"; 1588 return 0; 1589 } 1590 1591 if (!display->params.enable_fbc) { 1592 plane_state->no_fbc_reason = "disabled per module param or by default"; 1593 return 0; 1594 } 1595 1596 if (!plane_state->uapi.visible) { 1597 plane_state->no_fbc_reason = "plane not visible"; 1598 return 0; 1599 } 1600 1601 if (intel_display_wa(display, 16023588340)) { 1602 plane_state->no_fbc_reason = "Wa_16023588340"; 1603 return 0; 1604 } 1605 1606 /* 1607 * Wa_15018326506: 1608 * Fixes: Underrun during media decode 1609 * Workaround: Do not enable FBC 1610 */ 1611 if (intel_display_wa(display, 15018326506)) { 1612 plane_state->no_fbc_reason = "Wa_15018326506"; 1613 return 0; 1614 } 1615 1616 /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ 1617 if (intel_display_vtd_active(display) && 1618 (display->platform.skylake || display->platform.broxton)) { 1619 plane_state->no_fbc_reason = "VT-d enabled"; 1620 return 0; 1621 } 1622 1623 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 1624 1625 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { 1626 plane_state->no_fbc_reason = "interlaced mode not supported"; 1627 return 0; 1628 } 1629 1630 if (crtc_state->double_wide) { 1631 plane_state->no_fbc_reason = "double wide pipe not supported"; 1632 return 0; 1633 } 1634 1635 /* 1636 * Display 12+ is not supporting FBC with PSR2. 1637 * Recommendation is to keep this combination disabled 1638 * Bspec: 50422 HSD: 14010260002 1639 * 1640 * TODO: Implement a logic to select between PSR2 selective fetch and 1641 * FBC based on Bspec: 68881 in xe2lpd onwards. 1642 * 1643 * As we still see some strange underruns in those platforms while 1644 * disabling PSR2, keep FBC disabled in case of selective update is on 1645 * until the selection logic is implemented. 1646 */ 1647 if (DISPLAY_VER(display) >= 12 && crtc_state->has_sel_update) { 1648 plane_state->no_fbc_reason = "Selective update enabled"; 1649 return 0; 1650 } 1651 1652 /* Wa_14016291713 */ 1653 if ((IS_DISPLAY_VER(display, 12, 13) || 1654 IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, STEP_C0)) && 1655 crtc_state->has_psr && !crtc_state->has_panel_replay) { 1656 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; 1657 return 0; 1658 } 1659 1660 if (!pixel_format_is_valid(plane_state)) { 1661 plane_state->no_fbc_reason = "pixel format not supported"; 1662 return 0; 1663 } 1664 1665 if (!tiling_is_valid(plane_state)) { 1666 plane_state->no_fbc_reason = "tiling not supported"; 1667 return 0; 1668 } 1669 1670 if (!rotation_is_valid(plane_state)) { 1671 plane_state->no_fbc_reason = "rotation not supported"; 1672 return 0; 1673 } 1674 1675 if (!stride_is_valid(plane_state)) { 1676 plane_state->no_fbc_reason = "stride not supported"; 1677 return 0; 1678 } 1679 1680 if (DISPLAY_VER(display) < 20 && 1681 plane_state->hw.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE && 1682 fb->format->has_alpha) { 1683 plane_state->no_fbc_reason = "per-pixel alpha not supported"; 1684 return 0; 1685 } 1686 1687 if (!intel_fbc_plane_size_valid(plane_state)) { 1688 plane_state->no_fbc_reason = "plane size too big"; 1689 return 0; 1690 } 1691 1692 if (!intel_fbc_surface_size_ok(plane_state)) { 1693 plane_state->no_fbc_reason = "surface size too big"; 1694 return 0; 1695 } 1696 1697 /* 1698 * Work around a problem on GEN9+ HW, where enabling FBC on a plane 1699 * having a Y offset that isn't divisible by 4 causes FIFO underrun 1700 * and screen flicker. 1701 */ 1702 if (IS_DISPLAY_VER(display, 9, 12) && 1703 plane_state->view.color_plane[0].y & 3) { 1704 plane_state->no_fbc_reason = "plane start Y offset misaligned"; 1705 return 0; 1706 } 1707 1708 /* Wa_22010751166: icl, ehl, tgl, dg1, rkl */ 1709 if (IS_DISPLAY_VER(display, 9, 12) && 1710 (plane_state->view.color_plane[0].y + 1711 (drm_rect_height(&plane_state->uapi.src) >> 16)) & 3) { 1712 plane_state->no_fbc_reason = "plane end Y offset misaligned"; 1713 return 0; 1714 } 1715 1716 if (_intel_fbc_min_cdclk(crtc_state) > display->cdclk.max_cdclk_freq) { 1717 plane_state->no_fbc_reason = "pixel rate too high"; 1718 return 0; 1719 } 1720 1721 plane_state->no_fbc_reason = NULL; 1722 1723 return 0; 1724 } 1725 1726 int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state) 1727 { 1728 struct intel_display *display = to_intel_display(crtc_state); 1729 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1730 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 1731 int min_cdclk; 1732 1733 if (!plane->fbc) 1734 return 0; 1735 1736 min_cdclk = _intel_fbc_min_cdclk(crtc_state); 1737 1738 /* 1739 * Do not ask for more than the max CDCLK frequency, 1740 * if that is not enough FBC will simply not be used. 1741 */ 1742 if (min_cdclk > display->cdclk.max_cdclk_freq) 1743 return 0; 1744 1745 return min_cdclk; 1746 } 1747 1748 static bool intel_fbc_can_flip_nuke(struct intel_atomic_state *state, 1749 struct intel_crtc *crtc, 1750 struct intel_plane *plane) 1751 { 1752 const struct intel_crtc_state *new_crtc_state = 1753 intel_atomic_get_new_crtc_state(state, crtc); 1754 const struct intel_plane_state *old_plane_state = 1755 intel_atomic_get_old_plane_state(state, plane); 1756 const struct intel_plane_state *new_plane_state = 1757 intel_atomic_get_new_plane_state(state, plane); 1758 const struct drm_framebuffer *old_fb = old_plane_state->hw.fb; 1759 const struct drm_framebuffer *new_fb = new_plane_state->hw.fb; 1760 1761 if (intel_crtc_needs_modeset(new_crtc_state)) 1762 return false; 1763 1764 if (!intel_fbc_is_ok(old_plane_state) || 1765 !intel_fbc_is_ok(new_plane_state)) 1766 return false; 1767 1768 if (old_fb->format->format != new_fb->format->format) 1769 return false; 1770 1771 if (old_fb->modifier != new_fb->modifier) 1772 return false; 1773 1774 if (intel_fbc_plane_stride(old_plane_state) != 1775 intel_fbc_plane_stride(new_plane_state)) 1776 return false; 1777 1778 if (intel_fbc_cfb_stride(old_plane_state) != 1779 intel_fbc_cfb_stride(new_plane_state)) 1780 return false; 1781 1782 if (intel_fbc_cfb_size(old_plane_state) != 1783 intel_fbc_cfb_size(new_plane_state)) 1784 return false; 1785 1786 if (intel_fbc_override_cfb_stride(old_plane_state) != 1787 intel_fbc_override_cfb_stride(new_plane_state)) 1788 return false; 1789 1790 return true; 1791 } 1792 1793 static bool __intel_fbc_pre_update(struct intel_atomic_state *state, 1794 struct intel_crtc *crtc, 1795 struct intel_plane *plane) 1796 { 1797 struct intel_display *display = to_intel_display(state); 1798 struct intel_fbc *fbc = plane->fbc; 1799 bool need_vblank_wait = false; 1800 1801 lockdep_assert_held(&fbc->lock); 1802 1803 fbc->flip_pending = true; 1804 1805 if (intel_fbc_can_flip_nuke(state, crtc, plane)) 1806 return need_vblank_wait; 1807 1808 intel_fbc_deactivate(fbc, "update pending"); 1809 1810 /* 1811 * Display WA #1198: glk+ 1812 * Need an extra vblank wait between FBC disable and most plane 1813 * updates. Bspec says this is only needed for plane disable, but 1814 * that is not true. Touching most plane registers will cause the 1815 * corruption to appear. Also SKL/derivatives do not seem to be 1816 * affected. 1817 * 1818 * TODO: could optimize this a bit by sampling the frame 1819 * counter when we disable FBC (if it was already done earlier) 1820 * and skipping the extra vblank wait before the plane update 1821 * if at least one frame has already passed. 1822 */ 1823 if (fbc->activated && DISPLAY_VER(display) >= 10) 1824 need_vblank_wait = true; 1825 fbc->activated = false; 1826 1827 return need_vblank_wait; 1828 } 1829 1830 bool intel_fbc_pre_update(struct intel_atomic_state *state, 1831 struct intel_crtc *crtc) 1832 { 1833 const struct intel_plane_state __maybe_unused *plane_state; 1834 bool need_vblank_wait = false; 1835 struct intel_plane *plane; 1836 int i; 1837 1838 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1839 struct intel_fbc *fbc = plane->fbc; 1840 1841 if (!fbc || plane->pipe != crtc->pipe) 1842 continue; 1843 1844 mutex_lock(&fbc->lock); 1845 1846 if (fbc->state.plane == plane) 1847 need_vblank_wait |= __intel_fbc_pre_update(state, crtc, plane); 1848 1849 mutex_unlock(&fbc->lock); 1850 } 1851 1852 return need_vblank_wait; 1853 } 1854 1855 static void __intel_fbc_disable(struct intel_fbc *fbc) 1856 { 1857 struct intel_display *display = fbc->display; 1858 struct intel_plane *plane = fbc->state.plane; 1859 1860 lockdep_assert_held(&fbc->lock); 1861 drm_WARN_ON(display->drm, fbc->active); 1862 1863 drm_dbg_kms(display->drm, "Disabling FBC on [PLANE:%d:%s]\n", 1864 plane->base.base.id, plane->base.name); 1865 1866 intel_fbc_invalidate_dirty_rect(fbc); 1867 1868 __intel_fbc_cleanup_cfb(fbc); 1869 1870 fbc_sys_cache_disable(fbc); 1871 1872 /* wa_18038517565 Enable DPFC clock gating after FBC disable */ 1873 if (display->platform.dg2 || DISPLAY_VER(display) >= 14) 1874 fbc_compressor_clkgate_disable_wa(fbc, false); 1875 1876 fbc->state.plane = NULL; 1877 fbc->flip_pending = false; 1878 fbc->busy_bits = 0; 1879 } 1880 1881 static void __intel_fbc_post_update(struct intel_fbc *fbc) 1882 { 1883 lockdep_assert_held(&fbc->lock); 1884 1885 fbc->flip_pending = false; 1886 fbc->busy_bits = 0; 1887 1888 intel_fbc_activate(fbc); 1889 } 1890 1891 void intel_fbc_post_update(struct intel_atomic_state *state, 1892 struct intel_crtc *crtc) 1893 { 1894 const struct intel_plane_state __maybe_unused *plane_state; 1895 struct intel_plane *plane; 1896 int i; 1897 1898 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1899 struct intel_fbc *fbc = plane->fbc; 1900 1901 if (!fbc || plane->pipe != crtc->pipe) 1902 continue; 1903 1904 mutex_lock(&fbc->lock); 1905 1906 if (fbc->state.plane == plane) 1907 __intel_fbc_post_update(fbc); 1908 1909 mutex_unlock(&fbc->lock); 1910 } 1911 } 1912 1913 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc) 1914 { 1915 if (fbc->state.plane) 1916 return fbc->state.plane->frontbuffer_bit; 1917 else 1918 return 0; 1919 } 1920 1921 static void __intel_fbc_invalidate(struct intel_fbc *fbc, 1922 unsigned int frontbuffer_bits, 1923 enum fb_op_origin origin) 1924 { 1925 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1926 return; 1927 1928 mutex_lock(&fbc->lock); 1929 1930 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc); 1931 if (!frontbuffer_bits) 1932 goto out; 1933 1934 fbc->busy_bits |= frontbuffer_bits; 1935 intel_fbc_deactivate(fbc, "frontbuffer write"); 1936 1937 out: 1938 mutex_unlock(&fbc->lock); 1939 } 1940 1941 void intel_fbc_invalidate(struct intel_display *display, 1942 unsigned int frontbuffer_bits, 1943 enum fb_op_origin origin) 1944 { 1945 struct intel_fbc *fbc; 1946 enum intel_fbc_id fbc_id; 1947 1948 for_each_intel_fbc(display, fbc, fbc_id) 1949 __intel_fbc_invalidate(fbc, frontbuffer_bits, origin); 1950 1951 } 1952 1953 static void __intel_fbc_flush(struct intel_fbc *fbc, 1954 unsigned int frontbuffer_bits, 1955 enum fb_op_origin origin) 1956 { 1957 mutex_lock(&fbc->lock); 1958 1959 frontbuffer_bits &= intel_fbc_get_frontbuffer_bit(fbc); 1960 if (!frontbuffer_bits) 1961 goto out; 1962 1963 fbc->busy_bits &= ~frontbuffer_bits; 1964 1965 if (origin == ORIGIN_FLIP || origin == ORIGIN_CURSOR_UPDATE) 1966 goto out; 1967 1968 if (fbc->busy_bits || fbc->flip_pending) 1969 goto out; 1970 1971 if (fbc->active) 1972 intel_fbc_nuke(fbc); 1973 else 1974 intel_fbc_activate(fbc); 1975 1976 out: 1977 mutex_unlock(&fbc->lock); 1978 } 1979 1980 void intel_fbc_flush(struct intel_display *display, 1981 unsigned int frontbuffer_bits, 1982 enum fb_op_origin origin) 1983 { 1984 struct intel_fbc *fbc; 1985 enum intel_fbc_id fbc_id; 1986 1987 for_each_intel_fbc(display, fbc, fbc_id) 1988 __intel_fbc_flush(fbc, frontbuffer_bits, origin); 1989 } 1990 1991 int intel_fbc_atomic_check(struct intel_atomic_state *state) 1992 { 1993 struct intel_plane_state __maybe_unused *plane_state; 1994 struct intel_plane *plane; 1995 int i; 1996 1997 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 1998 int ret; 1999 2000 ret = intel_fbc_check_plane(state, plane); 2001 if (ret) 2002 return ret; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static void __intel_fbc_enable(struct intel_atomic_state *state, 2009 struct intel_crtc *crtc, 2010 struct intel_plane *plane) 2011 { 2012 struct intel_display *display = to_intel_display(state); 2013 const struct intel_plane_state *plane_state = 2014 intel_atomic_get_new_plane_state(state, plane); 2015 struct intel_fbc *fbc = plane->fbc; 2016 2017 lockdep_assert_held(&fbc->lock); 2018 2019 if (fbc->state.plane) { 2020 if (fbc->state.plane != plane) 2021 return; 2022 2023 if (intel_fbc_is_ok(plane_state)) { 2024 intel_fbc_update_state(state, crtc, plane); 2025 return; 2026 } 2027 2028 __intel_fbc_disable(fbc); 2029 } 2030 2031 drm_WARN_ON(display->drm, fbc->active); 2032 2033 fbc->no_fbc_reason = plane_state->no_fbc_reason; 2034 if (fbc->no_fbc_reason) 2035 return; 2036 2037 if (!intel_fbc_is_fence_ok(plane_state)) { 2038 fbc->no_fbc_reason = "framebuffer not fenced"; 2039 return; 2040 } 2041 2042 if (fbc->underrun_detected) { 2043 fbc->no_fbc_reason = "FIFO underrun"; 2044 return; 2045 } 2046 2047 if (intel_fbc_alloc_cfb(fbc, intel_fbc_cfb_size(plane_state), 2048 intel_fbc_min_limit(plane_state))) { 2049 fbc->no_fbc_reason = "not enough stolen memory"; 2050 return; 2051 } 2052 2053 drm_dbg_kms(display->drm, "Enabling FBC on [PLANE:%d:%s]\n", 2054 plane->base.base.id, plane->base.name); 2055 fbc->no_fbc_reason = "FBC enabled but not active yet\n"; 2056 2057 intel_fbc_update_state(state, crtc, plane); 2058 2059 if (HAS_FBC_DIRTY_RECT(display)) 2060 intel_fbc_hw_intialize_dirty_rect(fbc, plane_state); 2061 2062 intel_fbc_program_workarounds(fbc); 2063 intel_fbc_program_cfb(fbc); 2064 2065 fbc_sys_cache_enable(fbc); 2066 } 2067 2068 /** 2069 * intel_fbc_disable - disable FBC if it's associated with crtc 2070 * @crtc: the CRTC 2071 * 2072 * This function disables FBC if it's associated with the provided CRTC. 2073 */ 2074 void intel_fbc_disable(struct intel_crtc *crtc) 2075 { 2076 struct intel_display *display = to_intel_display(crtc); 2077 struct intel_plane *plane; 2078 2079 for_each_intel_plane(display->drm, plane) { 2080 struct intel_fbc *fbc = plane->fbc; 2081 2082 if (!fbc || plane->pipe != crtc->pipe) 2083 continue; 2084 2085 mutex_lock(&fbc->lock); 2086 if (fbc->state.plane == plane) 2087 __intel_fbc_disable(fbc); 2088 mutex_unlock(&fbc->lock); 2089 } 2090 } 2091 2092 void intel_fbc_update(struct intel_atomic_state *state, 2093 struct intel_crtc *crtc) 2094 { 2095 const struct intel_crtc_state *crtc_state = 2096 intel_atomic_get_new_crtc_state(state, crtc); 2097 const struct intel_plane_state *plane_state; 2098 struct intel_plane *plane; 2099 int i; 2100 2101 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { 2102 struct intel_fbc *fbc = plane->fbc; 2103 2104 if (!fbc || plane->pipe != crtc->pipe) 2105 continue; 2106 2107 mutex_lock(&fbc->lock); 2108 2109 if (intel_crtc_needs_fastset(crtc_state) && 2110 plane_state->no_fbc_reason) { 2111 if (fbc->state.plane == plane) 2112 __intel_fbc_disable(fbc); 2113 } else { 2114 __intel_fbc_enable(state, crtc, plane); 2115 } 2116 2117 mutex_unlock(&fbc->lock); 2118 } 2119 } 2120 2121 static void intel_fbc_underrun_work_fn(struct work_struct *work) 2122 { 2123 struct intel_fbc *fbc = container_of(work, typeof(*fbc), underrun_work); 2124 struct intel_display *display = fbc->display; 2125 2126 mutex_lock(&fbc->lock); 2127 2128 /* Maybe we were scheduled twice. */ 2129 if (fbc->underrun_detected || !fbc->state.plane) 2130 goto out; 2131 2132 drm_dbg_kms(display->drm, "Disabling FBC due to FIFO underrun.\n"); 2133 fbc->underrun_detected = true; 2134 2135 intel_fbc_deactivate(fbc, "FIFO underrun"); 2136 if (!fbc->flip_pending) 2137 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, fbc->state.plane->pipe)); 2138 __intel_fbc_disable(fbc); 2139 out: 2140 mutex_unlock(&fbc->lock); 2141 } 2142 2143 static void __intel_fbc_reset_underrun(struct intel_fbc *fbc) 2144 { 2145 struct intel_display *display = fbc->display; 2146 2147 cancel_work_sync(&fbc->underrun_work); 2148 2149 mutex_lock(&fbc->lock); 2150 2151 if (fbc->underrun_detected) { 2152 drm_dbg_kms(display->drm, 2153 "Re-allowing FBC after fifo underrun\n"); 2154 fbc->no_fbc_reason = "FIFO underrun cleared"; 2155 } 2156 2157 fbc->underrun_detected = false; 2158 mutex_unlock(&fbc->lock); 2159 } 2160 2161 /* 2162 * intel_fbc_reset_underrun - reset FBC fifo underrun status. 2163 * @display: display 2164 * 2165 * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we 2166 * want to re-enable FBC after an underrun to increase test coverage. 2167 */ 2168 void intel_fbc_reset_underrun(struct intel_display *display) 2169 { 2170 struct intel_fbc *fbc; 2171 enum intel_fbc_id fbc_id; 2172 2173 for_each_intel_fbc(display, fbc, fbc_id) 2174 __intel_fbc_reset_underrun(fbc); 2175 } 2176 2177 static void __intel_fbc_handle_fifo_underrun_irq(struct intel_fbc *fbc) 2178 { 2179 struct intel_display *display = fbc->display; 2180 2181 /* 2182 * There's no guarantee that underrun_detected won't be set to true 2183 * right after this check and before the work is scheduled, but that's 2184 * not a problem since we'll check it again under the work function 2185 * while FBC is locked. This check here is just to prevent us from 2186 * unnecessarily scheduling the work, and it relies on the fact that we 2187 * never switch underrun_detect back to false after it's true. 2188 */ 2189 if (READ_ONCE(fbc->underrun_detected)) 2190 return; 2191 2192 queue_work(display->wq.unordered, &fbc->underrun_work); 2193 } 2194 2195 /** 2196 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun 2197 * @display: display 2198 * 2199 * Without FBC, most underruns are harmless and don't really cause too many 2200 * problems, except for an annoying message on dmesg. With FBC, underruns can 2201 * become black screens or even worse, especially when paired with bad 2202 * watermarks. So in order for us to be on the safe side, completely disable FBC 2203 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe 2204 * already suggests that watermarks may be bad, so try to be as safe as 2205 * possible. 2206 * 2207 * This function is called from the IRQ handler. 2208 */ 2209 void intel_fbc_handle_fifo_underrun_irq(struct intel_display *display) 2210 { 2211 struct intel_fbc *fbc; 2212 enum intel_fbc_id fbc_id; 2213 2214 for_each_intel_fbc(display, fbc, fbc_id) 2215 __intel_fbc_handle_fifo_underrun_irq(fbc); 2216 } 2217 2218 /** 2219 * intel_fbc_read_underrun_dbg_info - Read and log FBC-related FIFO underrun debug info 2220 * @display: display device instance 2221 * @pipe: the pipe possibly containing the FBC 2222 * @log: log the info? 2223 * 2224 * If @pipe does not contain an FBC instance, this function bails early. 2225 * Otherwise, FBC-related FIFO underrun is read and cleared, and then, if @log 2226 * is true, printed with error level. 2227 */ 2228 void intel_fbc_read_underrun_dbg_info(struct intel_display *display, 2229 enum pipe pipe, bool log) 2230 { 2231 struct intel_fbc *fbc = intel_fbc_for_pipe(display, pipe); 2232 u32 val; 2233 2234 if (!fbc) 2235 return; 2236 2237 val = intel_de_read(display, FBC_DEBUG_STATUS(fbc->id)); 2238 if (!(val & FBC_UNDERRUN_DECMPR)) 2239 return; 2240 2241 intel_de_write(display, FBC_DEBUG_STATUS(fbc->id), FBC_UNDERRUN_DECMPR); 2242 2243 if (log) 2244 drm_err(display->drm, 2245 "Pipe %c FIFO underrun info: FBC decompressing\n", 2246 pipe_name(pipe)); 2247 } 2248 2249 /* 2250 * The DDX driver changes its behavior depending on the value it reads from 2251 * i915.enable_fbc, so sanitize it by translating the default value into either 2252 * 0 or 1 in order to allow it to know what's going on. 2253 * 2254 * Notice that this is done at driver initialization and we still allow user 2255 * space to change the value during runtime without sanitizing it again. IGT 2256 * relies on being able to change i915.enable_fbc at runtime. 2257 */ 2258 static int intel_sanitize_fbc_option(struct intel_display *display) 2259 { 2260 if (display->params.enable_fbc >= 0) 2261 return !!display->params.enable_fbc; 2262 2263 if (!HAS_FBC(display)) 2264 return 0; 2265 2266 if (display->platform.broadwell || DISPLAY_VER(display) >= 9) 2267 return 1; 2268 2269 return 0; 2270 } 2271 2272 void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) 2273 { 2274 plane->fbc = fbc; 2275 } 2276 2277 static struct intel_fbc *intel_fbc_create(struct intel_display *display, 2278 enum intel_fbc_id fbc_id) 2279 { 2280 struct intel_fbc *fbc; 2281 2282 fbc = kzalloc(sizeof(*fbc), GFP_KERNEL); 2283 if (!fbc) 2284 return NULL; 2285 2286 fbc->compressed_fb = intel_parent_stolen_node_alloc(display); 2287 if (!fbc->compressed_fb) 2288 goto err; 2289 fbc->compressed_llb = intel_parent_stolen_node_alloc(display); 2290 if (!fbc->compressed_llb) 2291 goto err; 2292 2293 fbc->id = fbc_id; 2294 fbc->display = display; 2295 INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn); 2296 mutex_init(&fbc->lock); 2297 2298 if (DISPLAY_VER(display) >= 7) 2299 fbc->funcs = &ivb_fbc_funcs; 2300 else if (DISPLAY_VER(display) == 6) 2301 fbc->funcs = &snb_fbc_funcs; 2302 else if (DISPLAY_VER(display) == 5) 2303 fbc->funcs = &ilk_fbc_funcs; 2304 else if (display->platform.g4x) 2305 fbc->funcs = &g4x_fbc_funcs; 2306 else if (DISPLAY_VER(display) == 4) 2307 fbc->funcs = &i965_fbc_funcs; 2308 else 2309 fbc->funcs = &i8xx_fbc_funcs; 2310 2311 return fbc; 2312 2313 err: 2314 intel_parent_stolen_node_free(display, fbc->compressed_llb); 2315 intel_parent_stolen_node_free(display, fbc->compressed_fb); 2316 kfree(fbc); 2317 2318 return NULL; 2319 } 2320 2321 /** 2322 * intel_fbc_init - Initialize FBC 2323 * @display: display 2324 * 2325 * This function might be called during PM init process. 2326 */ 2327 void intel_fbc_init(struct intel_display *display) 2328 { 2329 enum intel_fbc_id fbc_id; 2330 2331 display->params.enable_fbc = intel_sanitize_fbc_option(display); 2332 drm_dbg_kms(display->drm, "Sanitized enable_fbc value: %d\n", 2333 display->params.enable_fbc); 2334 2335 for_each_fbc_id(display, fbc_id) 2336 display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id); 2337 2338 mutex_init(&display->fbc.sys_cache.lock); 2339 display->fbc.sys_cache.id = FBC_SYS_CACHE_ID_NONE; 2340 } 2341 2342 /** 2343 * intel_fbc_sanitize - Sanitize FBC 2344 * @display: display 2345 * 2346 * Make sure FBC is initially disabled since we have no 2347 * idea eg. into which parts of stolen it might be scribbling 2348 * into. 2349 */ 2350 void intel_fbc_sanitize(struct intel_display *display) 2351 { 2352 struct intel_fbc *fbc; 2353 enum intel_fbc_id fbc_id; 2354 2355 for_each_intel_fbc(display, fbc, fbc_id) { 2356 if (intel_fbc_hw_is_active(fbc)) 2357 intel_fbc_hw_deactivate(fbc); 2358 } 2359 2360 /* Ensure the sys cache usage config is clear as well */ 2361 mutex_lock(&display->fbc.sys_cache.lock); 2362 fbc_sys_cache_update_config(display, 0, FBC_SYS_CACHE_ID_NONE); 2363 mutex_unlock(&display->fbc.sys_cache.lock); 2364 } 2365 2366 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused) 2367 { 2368 struct intel_fbc *fbc = m->private; 2369 struct intel_display *display = fbc->display; 2370 struct intel_plane *plane; 2371 struct ref_tracker *wakeref; 2372 2373 drm_modeset_lock_all(display->drm); 2374 2375 wakeref = intel_display_rpm_get(display); 2376 mutex_lock(&fbc->lock); 2377 2378 if (fbc->active) { 2379 seq_puts(m, "FBC enabled\n"); 2380 seq_printf(m, "Compressing: %s\n", 2381 str_yes_no(intel_fbc_is_compressing(fbc))); 2382 2383 mutex_lock(&display->fbc.sys_cache.lock); 2384 seq_printf(m, "Using system cache: %s\n", 2385 str_yes_no(display->fbc.sys_cache.id == fbc->id)); 2386 mutex_unlock(&display->fbc.sys_cache.lock); 2387 } else { 2388 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); 2389 } 2390 2391 for_each_intel_plane(display->drm, plane) { 2392 const struct intel_plane_state *plane_state = 2393 to_intel_plane_state(plane->base.state); 2394 2395 if (plane->fbc != fbc) 2396 continue; 2397 2398 seq_printf(m, "%c [PLANE:%d:%s]: %s\n", 2399 fbc->state.plane == plane ? '*' : ' ', 2400 plane->base.base.id, plane->base.name, 2401 plane_state->no_fbc_reason ?: "FBC possible"); 2402 } 2403 2404 mutex_unlock(&fbc->lock); 2405 intel_display_rpm_put(display, wakeref); 2406 2407 drm_modeset_unlock_all(display->drm); 2408 2409 return 0; 2410 } 2411 2412 DEFINE_SHOW_ATTRIBUTE(intel_fbc_debugfs_status); 2413 2414 static int intel_fbc_debugfs_false_color_get(void *data, u64 *val) 2415 { 2416 struct intel_fbc *fbc = data; 2417 2418 *val = fbc->false_color; 2419 2420 return 0; 2421 } 2422 2423 static int intel_fbc_debugfs_false_color_set(void *data, u64 val) 2424 { 2425 struct intel_fbc *fbc = data; 2426 2427 mutex_lock(&fbc->lock); 2428 2429 fbc->false_color = val; 2430 2431 if (fbc->active) 2432 fbc->funcs->set_false_color(fbc, fbc->false_color); 2433 2434 mutex_unlock(&fbc->lock); 2435 2436 return 0; 2437 } 2438 2439 DEFINE_DEBUGFS_ATTRIBUTE(intel_fbc_debugfs_false_color_fops, 2440 intel_fbc_debugfs_false_color_get, 2441 intel_fbc_debugfs_false_color_set, 2442 "%llu\n"); 2443 2444 static void intel_fbc_debugfs_add(struct intel_fbc *fbc, 2445 struct dentry *parent) 2446 { 2447 debugfs_create_file("i915_fbc_status", 0444, parent, 2448 fbc, &intel_fbc_debugfs_status_fops); 2449 2450 if (fbc->funcs->set_false_color) 2451 debugfs_create_file_unsafe("i915_fbc_false_color", 0644, parent, 2452 fbc, &intel_fbc_debugfs_false_color_fops); 2453 } 2454 2455 void intel_fbc_crtc_debugfs_add(struct intel_crtc *crtc) 2456 { 2457 struct intel_plane *plane = to_intel_plane(crtc->base.primary); 2458 2459 if (plane->fbc) 2460 intel_fbc_debugfs_add(plane->fbc, crtc->base.debugfs_entry); 2461 } 2462 2463 /* FIXME: remove this once igt is on board with per-crtc stuff */ 2464 void intel_fbc_debugfs_register(struct intel_display *display) 2465 { 2466 struct intel_fbc *fbc; 2467 2468 fbc = display->fbc.instances[INTEL_FBC_A]; 2469 if (fbc) 2470 intel_fbc_debugfs_add(fbc, display->drm->debugfs_root); 2471 } 2472