1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "gem/i915_gem_domain.h" 11 #include "gem/i915_gem_object.h" 12 13 #include "i915_drv.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_display_types.h" 16 #include "intel_dpt.h" 17 #include "intel_fb.h" 18 #include "intel_fb_pin.h" 19 20 static struct i915_vma * 21 intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, 22 const struct i915_gtt_view *view, 23 unsigned int alignment, 24 unsigned long *out_flags, 25 struct i915_address_space *vm) 26 { 27 struct drm_device *dev = fb->dev; 28 struct intel_display *display = to_intel_display(dev); 29 struct drm_i915_private *dev_priv = to_i915(dev); 30 struct drm_gem_object *_obj = intel_fb_bo(fb); 31 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 32 struct i915_gem_ww_ctx ww; 33 struct i915_vma *vma; 34 int ret; 35 36 /* 37 * We are not syncing against the binding (and potential migrations) 38 * below, so this vm must never be async. 39 */ 40 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags)) 41 return ERR_PTR(-EINVAL); 42 43 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 44 return ERR_PTR(-EINVAL); 45 46 atomic_inc(&display->restore.pending_fb_pin); 47 48 for_i915_gem_ww(&ww, ret, true) { 49 ret = i915_gem_object_lock(obj, &ww); 50 if (ret) 51 continue; 52 53 if (HAS_LMEM(dev_priv)) { 54 unsigned int flags = obj->flags; 55 56 /* 57 * For this type of buffer we need to able to read from the CPU 58 * the clear color value found in the buffer, hence we need to 59 * ensure it is always in the mappable part of lmem, if this is 60 * a small-bar device. 61 */ 62 if (intel_fb_rc_ccs_cc_plane(fb) >= 0) 63 flags &= ~I915_BO_ALLOC_GPU_ONLY; 64 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, 65 flags); 66 if (ret) 67 continue; 68 } 69 70 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 71 if (ret) 72 continue; 73 74 vma = i915_vma_instance(obj, vm, view); 75 if (IS_ERR(vma)) { 76 ret = PTR_ERR(vma); 77 continue; 78 } 79 80 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 81 ret = i915_vma_unbind(vma); 82 if (ret) 83 continue; 84 } 85 86 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL); 87 if (ret) 88 continue; 89 } 90 if (ret) { 91 vma = ERR_PTR(ret); 92 goto err; 93 } 94 95 vma->display_alignment = max(vma->display_alignment, alignment); 96 97 i915_gem_object_flush_if_display(obj); 98 99 i915_vma_get(vma); 100 err: 101 atomic_dec(&display->restore.pending_fb_pin); 102 103 return vma; 104 } 105 106 struct i915_vma * 107 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, 108 const struct i915_gtt_view *view, 109 unsigned int alignment, 110 unsigned int phys_alignment, 111 unsigned int vtd_guard, 112 bool uses_fence, 113 unsigned long *out_flags) 114 { 115 struct drm_device *dev = fb->dev; 116 struct intel_display *display = to_intel_display(dev); 117 struct drm_i915_private *dev_priv = to_i915(dev); 118 struct drm_gem_object *_obj = intel_fb_bo(fb); 119 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 120 intel_wakeref_t wakeref; 121 struct i915_gem_ww_ctx ww; 122 struct i915_vma *vma; 123 unsigned int pinctl; 124 int ret; 125 126 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 127 return ERR_PTR(-EINVAL); 128 129 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 130 return ERR_PTR(-EINVAL); 131 132 /* 133 * Global gtt pte registers are special registers which actually forward 134 * writes to a chunk of system memory. Which means that there is no risk 135 * that the register values disappear as soon as we call 136 * intel_runtime_pm_put(), so it is correct to wrap only the 137 * pin/unpin/fence and not more. 138 */ 139 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 140 141 atomic_inc(&display->restore.pending_fb_pin); 142 143 /* 144 * Valleyview is definitely limited to scanning out the first 145 * 512MiB. Lets presume this behaviour was inherited from the 146 * g4x display engine and that all earlier gen are similarly 147 * limited. Testing suggests that it is a little more 148 * complicated than this. For example, Cherryview appears quite 149 * happy to scanout from anywhere within its global aperture. 150 */ 151 pinctl = 0; 152 if (HAS_GMCH(dev_priv)) 153 pinctl |= PIN_MAPPABLE; 154 155 i915_gem_ww_ctx_init(&ww, true); 156 retry: 157 ret = i915_gem_object_lock(obj, &ww); 158 if (!ret && phys_alignment) 159 ret = i915_gem_object_attach_phys(obj, phys_alignment); 160 else if (!ret && HAS_LMEM(dev_priv)) 161 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); 162 if (!ret) 163 ret = i915_gem_object_pin_pages(obj); 164 if (ret) 165 goto err; 166 167 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 168 vtd_guard, view, pinctl); 169 if (IS_ERR(vma)) { 170 ret = PTR_ERR(vma); 171 goto err_unpin; 172 } 173 174 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 175 /* 176 * Install a fence for tiled scan-out. Pre-i965 always needs a 177 * fence, whereas 965+ only requires a fence if using 178 * framebuffer compression. For simplicity, we always, when 179 * possible, install a fence as the cost is not that onerous. 180 * 181 * If we fail to fence the tiled scanout, then either the 182 * modeset will reject the change (which is highly unlikely as 183 * the affected systems, all but one, do not have unmappable 184 * space) or we will not be able to enable full powersaving 185 * techniques (also likely not to apply due to various limits 186 * FBC and the like impose on the size of the buffer, which 187 * presumably we violated anyway with this unmappable buffer). 188 * Anyway, it is presumably better to stumble onwards with 189 * something and try to run the system in a "less than optimal" 190 * mode that matches the user configuration. 191 */ 192 ret = i915_vma_pin_fence(vma); 193 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 194 i915_vma_unpin(vma); 195 goto err_unpin; 196 } 197 ret = 0; 198 199 if (vma->fence) 200 *out_flags |= PLANE_HAS_FENCE; 201 } 202 203 i915_vma_get(vma); 204 205 err_unpin: 206 i915_gem_object_unpin_pages(obj); 207 err: 208 if (ret == -EDEADLK) { 209 ret = i915_gem_ww_ctx_backoff(&ww); 210 if (!ret) 211 goto retry; 212 } 213 i915_gem_ww_ctx_fini(&ww); 214 if (ret) 215 vma = ERR_PTR(ret); 216 217 atomic_dec(&display->restore.pending_fb_pin); 218 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 219 return vma; 220 } 221 222 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) 223 { 224 if (flags & PLANE_HAS_FENCE) 225 i915_vma_unpin_fence(vma); 226 i915_vma_unpin(vma); 227 i915_vma_put(vma); 228 } 229 230 static unsigned int 231 intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) 232 { 233 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 234 235 return fb->min_alignment; 236 } 237 238 static unsigned int 239 intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) 240 { 241 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 242 const struct drm_framebuffer *fb = plane_state->hw.fb; 243 244 if (!intel_plane_needs_physical(plane)) 245 return 0; 246 247 return plane->min_alignment(plane, fb, 0); 248 } 249 250 static unsigned int 251 intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) 252 { 253 return intel_fb_view_vtd_guard(plane_state->hw.fb, 254 &plane_state->view, 255 plane_state->hw.rotation); 256 } 257 258 int intel_plane_pin_fb(struct intel_plane_state *plane_state, 259 const struct intel_plane_state *old_plane_state) 260 { 261 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 262 const struct intel_framebuffer *fb = 263 to_intel_framebuffer(plane_state->hw.fb); 264 struct i915_vma *vma; 265 266 if (!intel_fb_uses_dpt(&fb->base)) { 267 vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, 268 intel_plane_fb_min_alignment(plane_state), 269 intel_plane_fb_min_phys_alignment(plane_state), 270 intel_plane_fb_vtd_guard(plane_state), 271 intel_plane_uses_fence(plane_state), 272 &plane_state->flags); 273 if (IS_ERR(vma)) 274 return PTR_ERR(vma); 275 276 plane_state->ggtt_vma = vma; 277 278 /* 279 * Pre-populate the dma address before we enter the vblank 280 * evade critical section as i915_gem_object_get_dma_address() 281 * will trigger might_sleep() even if it won't actually sleep, 282 * which is the case when the fb has already been pinned. 283 */ 284 if (intel_plane_needs_physical(plane)) { 285 struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); 286 287 plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0); 288 } 289 } else { 290 unsigned int alignment = intel_plane_fb_min_alignment(plane_state); 291 292 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); 293 if (IS_ERR(vma)) 294 return PTR_ERR(vma); 295 296 plane_state->ggtt_vma = vma; 297 298 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, 299 alignment, &plane_state->flags, 300 fb->dpt_vm); 301 if (IS_ERR(vma)) { 302 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 303 plane_state->ggtt_vma = NULL; 304 return PTR_ERR(vma); 305 } 306 307 plane_state->dpt_vma = vma; 308 309 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 310 } 311 312 return 0; 313 } 314 315 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 316 { 317 const struct intel_framebuffer *fb = 318 to_intel_framebuffer(old_plane_state->hw.fb); 319 struct i915_vma *vma; 320 321 if (!intel_fb_uses_dpt(&fb->base)) { 322 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 323 if (vma) 324 intel_fb_unpin_vma(vma, old_plane_state->flags); 325 } else { 326 vma = fetch_and_zero(&old_plane_state->dpt_vma); 327 if (vma) 328 intel_fb_unpin_vma(vma, old_plane_state->flags); 329 330 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 331 if (vma) 332 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 333 } 334 } 335