1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "gem/i915_gem_domain.h" 11 #include "gem/i915_gem_object.h" 12 13 #include "i915_drv.h" 14 #include "intel_atomic_plane.h" 15 #include "intel_display_types.h" 16 #include "intel_dpt.h" 17 #include "intel_fb.h" 18 #include "intel_fb_pin.h" 19 20 static struct i915_vma * 21 intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, 22 const struct i915_gtt_view *view, 23 unsigned int alignment, 24 unsigned long *out_flags, 25 struct i915_address_space *vm) 26 { 27 struct drm_device *dev = fb->dev; 28 struct drm_i915_private *dev_priv = to_i915(dev); 29 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 30 struct i915_gem_ww_ctx ww; 31 struct i915_vma *vma; 32 int ret; 33 34 /* 35 * We are not syncing against the binding (and potential migrations) 36 * below, so this vm must never be async. 37 */ 38 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags)) 39 return ERR_PTR(-EINVAL); 40 41 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 42 return ERR_PTR(-EINVAL); 43 44 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 45 46 for_i915_gem_ww(&ww, ret, true) { 47 ret = i915_gem_object_lock(obj, &ww); 48 if (ret) 49 continue; 50 51 if (HAS_LMEM(dev_priv)) { 52 unsigned int flags = obj->flags; 53 54 /* 55 * For this type of buffer we need to able to read from the CPU 56 * the clear color value found in the buffer, hence we need to 57 * ensure it is always in the mappable part of lmem, if this is 58 * a small-bar device. 59 */ 60 if (intel_fb_rc_ccs_cc_plane(fb) >= 0) 61 flags &= ~I915_BO_ALLOC_GPU_ONLY; 62 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, 63 flags); 64 if (ret) 65 continue; 66 } 67 68 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 69 if (ret) 70 continue; 71 72 vma = i915_vma_instance(obj, vm, view); 73 if (IS_ERR(vma)) { 74 ret = PTR_ERR(vma); 75 continue; 76 } 77 78 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 79 ret = i915_vma_unbind(vma); 80 if (ret) 81 continue; 82 } 83 84 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL); 85 if (ret) 86 continue; 87 } 88 if (ret) { 89 vma = ERR_PTR(ret); 90 goto err; 91 } 92 93 vma->display_alignment = max(vma->display_alignment, alignment); 94 95 i915_gem_object_flush_if_display(obj); 96 97 i915_vma_get(vma); 98 err: 99 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 100 101 return vma; 102 } 103 104 struct i915_vma * 105 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, 106 bool phys_cursor, 107 const struct i915_gtt_view *view, 108 bool uses_fence, 109 unsigned long *out_flags) 110 { 111 struct drm_device *dev = fb->dev; 112 struct drm_i915_private *dev_priv = to_i915(dev); 113 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 114 intel_wakeref_t wakeref; 115 struct i915_gem_ww_ctx ww; 116 unsigned int alignment; 117 struct i915_vma *vma; 118 unsigned int pinctl; 119 int ret; 120 121 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 122 return ERR_PTR(-EINVAL); 123 124 if (phys_cursor) 125 alignment = intel_cursor_alignment(dev_priv); 126 else 127 alignment = intel_surf_alignment(fb, 0); 128 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 129 return ERR_PTR(-EINVAL); 130 131 /* Note that the w/a also requires 64 PTE of padding following the 132 * bo. We currently fill all unused PTE with the shadow page and so 133 * we should always have valid PTE following the scanout preventing 134 * the VT-d warning. 135 */ 136 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) 137 alignment = 256 * 1024; 138 139 /* 140 * Global gtt pte registers are special registers which actually forward 141 * writes to a chunk of system memory. Which means that there is no risk 142 * that the register values disappear as soon as we call 143 * intel_runtime_pm_put(), so it is correct to wrap only the 144 * pin/unpin/fence and not more. 145 */ 146 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 147 148 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 149 150 /* 151 * Valleyview is definitely limited to scanning out the first 152 * 512MiB. Lets presume this behaviour was inherited from the 153 * g4x display engine and that all earlier gen are similarly 154 * limited. Testing suggests that it is a little more 155 * complicated than this. For example, Cherryview appears quite 156 * happy to scanout from anywhere within its global aperture. 157 */ 158 pinctl = 0; 159 if (HAS_GMCH(dev_priv)) 160 pinctl |= PIN_MAPPABLE; 161 162 i915_gem_ww_ctx_init(&ww, true); 163 retry: 164 ret = i915_gem_object_lock(obj, &ww); 165 if (!ret && phys_cursor) 166 ret = i915_gem_object_attach_phys(obj, alignment); 167 else if (!ret && HAS_LMEM(dev_priv)) 168 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); 169 if (!ret) 170 ret = i915_gem_object_pin_pages(obj); 171 if (ret) 172 goto err; 173 174 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 175 view, pinctl); 176 if (IS_ERR(vma)) { 177 ret = PTR_ERR(vma); 178 goto err_unpin; 179 } 180 181 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 182 /* 183 * Install a fence for tiled scan-out. Pre-i965 always needs a 184 * fence, whereas 965+ only requires a fence if using 185 * framebuffer compression. For simplicity, we always, when 186 * possible, install a fence as the cost is not that onerous. 187 * 188 * If we fail to fence the tiled scanout, then either the 189 * modeset will reject the change (which is highly unlikely as 190 * the affected systems, all but one, do not have unmappable 191 * space) or we will not be able to enable full powersaving 192 * techniques (also likely not to apply due to various limits 193 * FBC and the like impose on the size of the buffer, which 194 * presumably we violated anyway with this unmappable buffer). 195 * Anyway, it is presumably better to stumble onwards with 196 * something and try to run the system in a "less than optimal" 197 * mode that matches the user configuration. 198 */ 199 ret = i915_vma_pin_fence(vma); 200 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 201 i915_vma_unpin(vma); 202 goto err_unpin; 203 } 204 ret = 0; 205 206 if (vma->fence) 207 *out_flags |= PLANE_HAS_FENCE; 208 } 209 210 i915_vma_get(vma); 211 212 err_unpin: 213 i915_gem_object_unpin_pages(obj); 214 err: 215 if (ret == -EDEADLK) { 216 ret = i915_gem_ww_ctx_backoff(&ww); 217 if (!ret) 218 goto retry; 219 } 220 i915_gem_ww_ctx_fini(&ww); 221 if (ret) 222 vma = ERR_PTR(ret); 223 224 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 225 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 226 return vma; 227 } 228 229 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) 230 { 231 if (flags & PLANE_HAS_FENCE) 232 i915_vma_unpin_fence(vma); 233 i915_vma_unpin(vma); 234 i915_vma_put(vma); 235 } 236 237 int intel_plane_pin_fb(struct intel_plane_state *plane_state) 238 { 239 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 240 const struct intel_framebuffer *fb = 241 to_intel_framebuffer(plane_state->hw.fb); 242 struct i915_vma *vma; 243 244 if (!intel_fb_uses_dpt(&fb->base)) { 245 vma = intel_fb_pin_to_ggtt(&fb->base, intel_plane_needs_physical(plane), 246 &plane_state->view.gtt, 247 intel_plane_uses_fence(plane_state), 248 &plane_state->flags); 249 if (IS_ERR(vma)) 250 return PTR_ERR(vma); 251 252 plane_state->ggtt_vma = vma; 253 254 /* 255 * Pre-populate the dma address before we enter the vblank 256 * evade critical section as i915_gem_object_get_dma_address() 257 * will trigger might_sleep() even if it won't actually sleep, 258 * which is the case when the fb has already been pinned. 259 */ 260 if (intel_plane_needs_physical(plane)) 261 plane_state->phys_dma_addr = 262 i915_gem_object_get_dma_address(intel_fb_obj(&fb->base), 0); 263 } else { 264 unsigned int alignment = intel_surf_alignment(&fb->base, 0); 265 266 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); 267 if (IS_ERR(vma)) 268 return PTR_ERR(vma); 269 270 plane_state->ggtt_vma = vma; 271 272 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, 273 alignment, &plane_state->flags, 274 fb->dpt_vm); 275 if (IS_ERR(vma)) { 276 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 277 plane_state->ggtt_vma = NULL; 278 return PTR_ERR(vma); 279 } 280 281 plane_state->dpt_vma = vma; 282 283 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 284 } 285 286 return 0; 287 } 288 289 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 290 { 291 const struct intel_framebuffer *fb = 292 to_intel_framebuffer(old_plane_state->hw.fb); 293 struct i915_vma *vma; 294 295 if (!intel_fb_uses_dpt(&fb->base)) { 296 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 297 if (vma) 298 intel_fb_unpin_vma(vma, old_plane_state->flags); 299 } else { 300 vma = fetch_and_zero(&old_plane_state->dpt_vma); 301 if (vma) 302 intel_fb_unpin_vma(vma, old_plane_state->flags); 303 304 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 305 if (vma) 306 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 307 } 308 } 309