1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "gem/i915_gem_domain.h" 11 #include "gem/i915_gem_object.h" 12 13 #include "i915_drv.h" 14 #include "intel_display_types.h" 15 #include "intel_dpt.h" 16 #include "intel_fb.h" 17 #include "intel_fb_pin.h" 18 19 static struct i915_vma * 20 intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, 21 const struct i915_ggtt_view *view, 22 bool uses_fence, 23 unsigned long *out_flags, 24 struct i915_address_space *vm) 25 { 26 struct drm_device *dev = fb->dev; 27 struct drm_i915_private *dev_priv = to_i915(dev); 28 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 29 struct i915_vma *vma; 30 u32 alignment; 31 int ret; 32 33 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 34 return ERR_PTR(-EINVAL); 35 36 alignment = 4096 * 512; 37 38 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 39 40 ret = i915_gem_object_lock_interruptible(obj, NULL); 41 if (!ret) { 42 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 43 i915_gem_object_unlock(obj); 44 } 45 if (ret) { 46 vma = ERR_PTR(ret); 47 goto err; 48 } 49 50 vma = i915_vma_instance(obj, vm, view); 51 if (IS_ERR(vma)) 52 goto err; 53 54 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 55 ret = i915_vma_unbind_unlocked(vma); 56 if (ret) { 57 vma = ERR_PTR(ret); 58 goto err; 59 } 60 } 61 62 ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL); 63 if (ret) { 64 vma = ERR_PTR(ret); 65 goto err; 66 } 67 68 vma->display_alignment = max_t(u64, vma->display_alignment, alignment); 69 70 i915_gem_object_flush_if_display(obj); 71 72 i915_vma_get(vma); 73 err: 74 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 75 76 return vma; 77 } 78 79 struct i915_vma * 80 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, 81 bool phys_cursor, 82 const struct i915_ggtt_view *view, 83 bool uses_fence, 84 unsigned long *out_flags) 85 { 86 struct drm_device *dev = fb->dev; 87 struct drm_i915_private *dev_priv = to_i915(dev); 88 struct drm_i915_gem_object *obj = intel_fb_obj(fb); 89 intel_wakeref_t wakeref; 90 struct i915_gem_ww_ctx ww; 91 struct i915_vma *vma; 92 unsigned int pinctl; 93 u32 alignment; 94 int ret; 95 96 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 97 return ERR_PTR(-EINVAL); 98 99 if (phys_cursor) 100 alignment = intel_cursor_alignment(dev_priv); 101 else 102 alignment = intel_surf_alignment(fb, 0); 103 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 104 return ERR_PTR(-EINVAL); 105 106 /* Note that the w/a also requires 64 PTE of padding following the 107 * bo. We currently fill all unused PTE with the shadow page and so 108 * we should always have valid PTE following the scanout preventing 109 * the VT-d warning. 110 */ 111 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) 112 alignment = 256 * 1024; 113 114 /* 115 * Global gtt pte registers are special registers which actually forward 116 * writes to a chunk of system memory. Which means that there is no risk 117 * that the register values disappear as soon as we call 118 * intel_runtime_pm_put(), so it is correct to wrap only the 119 * pin/unpin/fence and not more. 120 */ 121 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); 122 123 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 124 125 /* 126 * Valleyview is definitely limited to scanning out the first 127 * 512MiB. Lets presume this behaviour was inherited from the 128 * g4x display engine and that all earlier gen are similarly 129 * limited. Testing suggests that it is a little more 130 * complicated than this. For example, Cherryview appears quite 131 * happy to scanout from anywhere within its global aperture. 132 */ 133 pinctl = 0; 134 if (HAS_GMCH(dev_priv)) 135 pinctl |= PIN_MAPPABLE; 136 137 i915_gem_ww_ctx_init(&ww, true); 138 retry: 139 ret = i915_gem_object_lock(obj, &ww); 140 if (!ret && phys_cursor) 141 ret = i915_gem_object_attach_phys(obj, alignment); 142 else if (!ret && HAS_LMEM(dev_priv)) 143 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); 144 /* TODO: Do we need to sync when migration becomes async? */ 145 if (!ret) 146 ret = i915_gem_object_pin_pages(obj); 147 if (ret) 148 goto err; 149 150 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 151 view, pinctl); 152 if (IS_ERR(vma)) { 153 ret = PTR_ERR(vma); 154 goto err_unpin; 155 } 156 157 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 158 /* 159 * Install a fence for tiled scan-out. Pre-i965 always needs a 160 * fence, whereas 965+ only requires a fence if using 161 * framebuffer compression. For simplicity, we always, when 162 * possible, install a fence as the cost is not that onerous. 163 * 164 * If we fail to fence the tiled scanout, then either the 165 * modeset will reject the change (which is highly unlikely as 166 * the affected systems, all but one, do not have unmappable 167 * space) or we will not be able to enable full powersaving 168 * techniques (also likely not to apply due to various limits 169 * FBC and the like impose on the size of the buffer, which 170 * presumably we violated anyway with this unmappable buffer). 171 * Anyway, it is presumably better to stumble onwards with 172 * something and try to run the system in a "less than optimal" 173 * mode that matches the user configuration. 174 */ 175 ret = i915_vma_pin_fence(vma); 176 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 177 i915_vma_unpin(vma); 178 goto err_unpin; 179 } 180 ret = 0; 181 182 if (vma->fence) 183 *out_flags |= PLANE_HAS_FENCE; 184 } 185 186 i915_vma_get(vma); 187 188 err_unpin: 189 i915_gem_object_unpin_pages(obj); 190 err: 191 if (ret == -EDEADLK) { 192 ret = i915_gem_ww_ctx_backoff(&ww); 193 if (!ret) 194 goto retry; 195 } 196 i915_gem_ww_ctx_fini(&ww); 197 if (ret) 198 vma = ERR_PTR(ret); 199 200 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 201 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); 202 return vma; 203 } 204 205 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) 206 { 207 if (flags & PLANE_HAS_FENCE) 208 i915_vma_unpin_fence(vma); 209 i915_vma_unpin(vma); 210 i915_vma_put(vma); 211 } 212 213 int intel_plane_pin_fb(struct intel_plane_state *plane_state) 214 { 215 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 216 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 217 struct drm_framebuffer *fb = plane_state->hw.fb; 218 struct i915_vma *vma; 219 bool phys_cursor = 220 plane->id == PLANE_CURSOR && 221 INTEL_INFO(dev_priv)->display.cursor_needs_physical; 222 223 if (!intel_fb_uses_dpt(fb)) { 224 vma = intel_pin_and_fence_fb_obj(fb, phys_cursor, 225 &plane_state->view.gtt, 226 intel_plane_uses_fence(plane_state), 227 &plane_state->flags); 228 if (IS_ERR(vma)) 229 return PTR_ERR(vma); 230 231 plane_state->ggtt_vma = vma; 232 } else { 233 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 234 235 vma = intel_dpt_pin(intel_fb->dpt_vm); 236 if (IS_ERR(vma)) 237 return PTR_ERR(vma); 238 239 plane_state->ggtt_vma = vma; 240 241 vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false, 242 &plane_state->flags, intel_fb->dpt_vm); 243 if (IS_ERR(vma)) { 244 intel_dpt_unpin(intel_fb->dpt_vm); 245 plane_state->ggtt_vma = NULL; 246 return PTR_ERR(vma); 247 } 248 249 plane_state->dpt_vma = vma; 250 251 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 252 } 253 254 return 0; 255 } 256 257 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 258 { 259 struct drm_framebuffer *fb = old_plane_state->hw.fb; 260 struct i915_vma *vma; 261 262 if (!intel_fb_uses_dpt(fb)) { 263 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 264 if (vma) 265 intel_unpin_fb_vma(vma, old_plane_state->flags); 266 } else { 267 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 268 269 vma = fetch_and_zero(&old_plane_state->dpt_vma); 270 if (vma) 271 intel_unpin_fb_vma(vma, old_plane_state->flags); 272 273 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 274 if (vma) 275 intel_dpt_unpin(intel_fb->dpt_vm); 276 } 277 } 278