1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /** 7 * DOC: display pinning helpers 8 */ 9 10 #include "gem/i915_gem_domain.h" 11 #include "gem/i915_gem_object.h" 12 13 #include "i915_drv.h" 14 #include "intel_display_core.h" 15 #include "intel_display_rpm.h" 16 #include "intel_display_types.h" 17 #include "intel_dpt.h" 18 #include "intel_fb.h" 19 #include "intel_fb_pin.h" 20 #include "intel_plane.h" 21 22 static struct i915_vma * 23 intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, 24 const struct i915_gtt_view *view, 25 unsigned int alignment, 26 unsigned long *out_flags, 27 struct i915_address_space *vm) 28 { 29 struct drm_device *dev = fb->dev; 30 struct intel_display *display = to_intel_display(dev); 31 struct drm_i915_private *dev_priv = to_i915(dev); 32 struct drm_gem_object *_obj = intel_fb_bo(fb); 33 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 34 struct i915_gem_ww_ctx ww; 35 struct i915_vma *vma; 36 int ret; 37 38 /* 39 * We are not syncing against the binding (and potential migrations) 40 * below, so this vm must never be async. 41 */ 42 if (drm_WARN_ON(&dev_priv->drm, vm->bind_async_flags)) 43 return ERR_PTR(-EINVAL); 44 45 if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) 46 return ERR_PTR(-EINVAL); 47 48 atomic_inc(&display->restore.pending_fb_pin); 49 50 for_i915_gem_ww(&ww, ret, true) { 51 ret = i915_gem_object_lock(obj, &ww); 52 if (ret) 53 continue; 54 55 if (HAS_LMEM(dev_priv)) { 56 unsigned int flags = obj->flags; 57 58 /* 59 * For this type of buffer we need to able to read from the CPU 60 * the clear color value found in the buffer, hence we need to 61 * ensure it is always in the mappable part of lmem, if this is 62 * a small-bar device. 63 */ 64 if (intel_fb_rc_ccs_cc_plane(fb) >= 0) 65 flags &= ~I915_BO_ALLOC_GPU_ONLY; 66 ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, 67 flags); 68 if (ret) 69 continue; 70 } 71 72 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); 73 if (ret) 74 continue; 75 76 vma = i915_vma_instance(obj, vm, view); 77 if (IS_ERR(vma)) { 78 ret = PTR_ERR(vma); 79 continue; 80 } 81 82 if (i915_vma_misplaced(vma, 0, alignment, 0)) { 83 ret = i915_vma_unbind(vma); 84 if (ret) 85 continue; 86 } 87 88 ret = i915_vma_pin_ww(vma, &ww, 0, alignment, PIN_GLOBAL); 89 if (ret) 90 continue; 91 } 92 if (ret) { 93 vma = ERR_PTR(ret); 94 goto err; 95 } 96 97 vma->display_alignment = max(vma->display_alignment, alignment); 98 99 i915_gem_object_flush_if_display(obj); 100 101 i915_vma_get(vma); 102 err: 103 atomic_dec(&display->restore.pending_fb_pin); 104 105 return vma; 106 } 107 108 struct i915_vma * 109 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, 110 const struct i915_gtt_view *view, 111 unsigned int alignment, 112 unsigned int phys_alignment, 113 unsigned int vtd_guard, 114 bool uses_fence, 115 unsigned long *out_flags) 116 { 117 struct drm_device *dev = fb->dev; 118 struct intel_display *display = to_intel_display(dev); 119 struct drm_i915_private *dev_priv = to_i915(dev); 120 struct drm_gem_object *_obj = intel_fb_bo(fb); 121 struct drm_i915_gem_object *obj = to_intel_bo(_obj); 122 struct ref_tracker *wakeref; 123 struct i915_gem_ww_ctx ww; 124 struct i915_vma *vma; 125 unsigned int pinctl; 126 int ret; 127 128 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) 129 return ERR_PTR(-EINVAL); 130 131 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))) 132 return ERR_PTR(-EINVAL); 133 134 /* 135 * Global gtt pte registers are special registers which actually forward 136 * writes to a chunk of system memory. Which means that there is no risk 137 * that the register values disappear as soon as we call 138 * intel_runtime_pm_put(), so it is correct to wrap only the 139 * pin/unpin/fence and not more. 140 */ 141 wakeref = intel_display_rpm_get(display); 142 143 atomic_inc(&display->restore.pending_fb_pin); 144 145 /* 146 * Valleyview is definitely limited to scanning out the first 147 * 512MiB. Lets presume this behaviour was inherited from the 148 * g4x display engine and that all earlier gen are similarly 149 * limited. Testing suggests that it is a little more 150 * complicated than this. For example, Cherryview appears quite 151 * happy to scanout from anywhere within its global aperture. 152 */ 153 pinctl = 0; 154 if (HAS_GMCH(dev_priv)) 155 pinctl |= PIN_MAPPABLE; 156 157 i915_gem_ww_ctx_init(&ww, true); 158 retry: 159 ret = i915_gem_object_lock(obj, &ww); 160 if (!ret && phys_alignment) 161 ret = i915_gem_object_attach_phys(obj, phys_alignment); 162 else if (!ret && HAS_LMEM(dev_priv)) 163 ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); 164 if (!ret) 165 ret = i915_gem_object_pin_pages(obj); 166 if (ret) 167 goto err; 168 169 vma = i915_gem_object_pin_to_display_plane(obj, &ww, alignment, 170 vtd_guard, view, pinctl); 171 if (IS_ERR(vma)) { 172 ret = PTR_ERR(vma); 173 goto err_unpin; 174 } 175 176 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { 177 /* 178 * Install a fence for tiled scan-out. Pre-i965 always needs a 179 * fence, whereas 965+ only requires a fence if using 180 * framebuffer compression. For simplicity, we always, when 181 * possible, install a fence as the cost is not that onerous. 182 * 183 * If we fail to fence the tiled scanout, then either the 184 * modeset will reject the change (which is highly unlikely as 185 * the affected systems, all but one, do not have unmappable 186 * space) or we will not be able to enable full powersaving 187 * techniques (also likely not to apply due to various limits 188 * FBC and the like impose on the size of the buffer, which 189 * presumably we violated anyway with this unmappable buffer). 190 * Anyway, it is presumably better to stumble onwards with 191 * something and try to run the system in a "less than optimal" 192 * mode that matches the user configuration. 193 */ 194 ret = i915_vma_pin_fence(vma); 195 if (ret != 0 && DISPLAY_VER(dev_priv) < 4) { 196 i915_vma_unpin(vma); 197 goto err_unpin; 198 } 199 ret = 0; 200 201 if (vma->fence) 202 *out_flags |= PLANE_HAS_FENCE; 203 } 204 205 i915_vma_get(vma); 206 207 err_unpin: 208 i915_gem_object_unpin_pages(obj); 209 err: 210 if (ret == -EDEADLK) { 211 ret = i915_gem_ww_ctx_backoff(&ww); 212 if (!ret) 213 goto retry; 214 } 215 i915_gem_ww_ctx_fini(&ww); 216 if (ret) 217 vma = ERR_PTR(ret); 218 219 atomic_dec(&display->restore.pending_fb_pin); 220 intel_display_rpm_put(display, wakeref); 221 return vma; 222 } 223 224 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) 225 { 226 if (flags & PLANE_HAS_FENCE) 227 i915_vma_unpin_fence(vma); 228 i915_vma_unpin(vma); 229 i915_vma_put(vma); 230 } 231 232 static unsigned int 233 intel_plane_fb_min_alignment(const struct intel_plane_state *plane_state) 234 { 235 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 236 237 return fb->min_alignment; 238 } 239 240 static unsigned int 241 intel_plane_fb_min_phys_alignment(const struct intel_plane_state *plane_state) 242 { 243 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 244 const struct drm_framebuffer *fb = plane_state->hw.fb; 245 246 if (!intel_plane_needs_physical(plane)) 247 return 0; 248 249 return plane->min_alignment(plane, fb, 0); 250 } 251 252 static unsigned int 253 intel_plane_fb_vtd_guard(const struct intel_plane_state *plane_state) 254 { 255 return intel_fb_view_vtd_guard(plane_state->hw.fb, 256 &plane_state->view, 257 plane_state->hw.rotation); 258 } 259 260 int intel_plane_pin_fb(struct intel_plane_state *plane_state, 261 const struct intel_plane_state *old_plane_state) 262 { 263 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 264 const struct intel_framebuffer *fb = 265 to_intel_framebuffer(plane_state->hw.fb); 266 struct i915_vma *vma; 267 268 if (!intel_fb_uses_dpt(&fb->base)) { 269 vma = intel_fb_pin_to_ggtt(&fb->base, &plane_state->view.gtt, 270 intel_plane_fb_min_alignment(plane_state), 271 intel_plane_fb_min_phys_alignment(plane_state), 272 intel_plane_fb_vtd_guard(plane_state), 273 intel_plane_uses_fence(plane_state), 274 &plane_state->flags); 275 if (IS_ERR(vma)) 276 return PTR_ERR(vma); 277 278 plane_state->ggtt_vma = vma; 279 280 /* 281 * Pre-populate the dma address before we enter the vblank 282 * evade critical section as i915_gem_object_get_dma_address() 283 * will trigger might_sleep() even if it won't actually sleep, 284 * which is the case when the fb has already been pinned. 285 */ 286 if (intel_plane_needs_physical(plane)) { 287 struct drm_i915_gem_object *obj = to_intel_bo(intel_fb_bo(&fb->base)); 288 289 plane_state->phys_dma_addr = i915_gem_object_get_dma_address(obj, 0); 290 } 291 } else { 292 unsigned int alignment = intel_plane_fb_min_alignment(plane_state); 293 294 vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); 295 if (IS_ERR(vma)) 296 return PTR_ERR(vma); 297 298 plane_state->ggtt_vma = vma; 299 300 vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, 301 alignment, &plane_state->flags, 302 fb->dpt_vm); 303 if (IS_ERR(vma)) { 304 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 305 plane_state->ggtt_vma = NULL; 306 return PTR_ERR(vma); 307 } 308 309 plane_state->dpt_vma = vma; 310 311 WARN_ON(plane_state->ggtt_vma == plane_state->dpt_vma); 312 } 313 314 return 0; 315 } 316 317 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 318 { 319 const struct intel_framebuffer *fb = 320 to_intel_framebuffer(old_plane_state->hw.fb); 321 struct i915_vma *vma; 322 323 if (!intel_fb_uses_dpt(&fb->base)) { 324 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 325 if (vma) 326 intel_fb_unpin_vma(vma, old_plane_state->flags); 327 } else { 328 vma = fetch_and_zero(&old_plane_state->dpt_vma); 329 if (vma) 330 intel_fb_unpin_vma(vma, old_plane_state->flags); 331 332 vma = fetch_and_zero(&old_plane_state->ggtt_vma); 333 if (vma) 334 intel_dpt_unpin_from_ggtt(fb->dpt_vm); 335 } 336 } 337 338 void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) 339 { 340 iosys_map_set_vaddr_iomem(map, i915_vma_get_iomap(vma)); 341 } 342