xref: /linux/drivers/gpu/drm/i915/display/intel_fb.c (revision 5ce42b5de461c3154f61a023b191dd6b77ee66c0)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include <drm/drm_blend.h>
7 #include <drm/drm_modeset_helper.h>
8 
9 #include <linux/dma-fence.h>
10 #include <linux/dma-resv.h>
11 
12 #include "gem/i915_gem_object.h"
13 #include "i915_drv.h"
14 #include "intel_atomic_plane.h"
15 #include "intel_display.h"
16 #include "intel_display_types.h"
17 #include "intel_dpt.h"
18 #include "intel_fb.h"
19 #include "intel_fb_bo.h"
20 #include "intel_frontbuffer.h"
21 
22 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
23 
24 /*
25  * From the Sky Lake PRM:
26  * "The Color Control Surface (CCS) contains the compression status of
27  *  the cache-line pairs. The compression state of the cache-line pair
28  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
29  *  an area on the main surface of 16 x16 sets of 128 byte Y-tiled
30  *  cache-line-pairs. CCS is always Y tiled."
31  *
32  * Since cache line pairs refers to horizontally adjacent cache lines,
33  * each cache line in the CCS corresponds to an area of 32x16 cache
34  * lines on the main surface. Since each pixel is 4 bytes, this gives
35  * us a ratio of one byte in the CCS for each 8x16 pixels in the
36  * main surface.
37  */
38 static const struct drm_format_info skl_ccs_formats[] = {
39 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
40 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
41 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
42 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
43 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
44 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
45 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
46 	  .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, },
47 };
48 
49 /*
50  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
51  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
52  * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
53  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
54  * the main surface.
55  */
56 static const struct drm_format_info gen12_ccs_formats[] = {
57 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
58 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
59 	  .hsub = 1, .vsub = 1, },
60 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
61 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
62 	  .hsub = 1, .vsub = 1, },
63 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
64 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
65 	  .hsub = 1, .vsub = 1, .has_alpha = true },
66 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
67 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
68 	  .hsub = 1, .vsub = 1, .has_alpha = true },
69 	{ .format = DRM_FORMAT_YUYV, .num_planes = 2,
70 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
71 	  .hsub = 2, .vsub = 1, .is_yuv = true },
72 	{ .format = DRM_FORMAT_YVYU, .num_planes = 2,
73 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
74 	  .hsub = 2, .vsub = 1, .is_yuv = true },
75 	{ .format = DRM_FORMAT_UYVY, .num_planes = 2,
76 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
77 	  .hsub = 2, .vsub = 1, .is_yuv = true },
78 	{ .format = DRM_FORMAT_VYUY, .num_planes = 2,
79 	  .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
80 	  .hsub = 2, .vsub = 1, .is_yuv = true },
81 	{ .format = DRM_FORMAT_XYUV8888, .num_planes = 2,
82 	  .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
83 	  .hsub = 1, .vsub = 1, .is_yuv = true },
84 	{ .format = DRM_FORMAT_NV12, .num_planes = 4,
85 	  .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
86 	  .hsub = 2, .vsub = 2, .is_yuv = true },
87 	{ .format = DRM_FORMAT_P010, .num_planes = 4,
88 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
89 	  .hsub = 2, .vsub = 2, .is_yuv = true },
90 	{ .format = DRM_FORMAT_P012, .num_planes = 4,
91 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
92 	  .hsub = 2, .vsub = 2, .is_yuv = true },
93 	{ .format = DRM_FORMAT_P016, .num_planes = 4,
94 	  .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
95 	  .hsub = 2, .vsub = 2, .is_yuv = true },
96 };
97 
98 /*
99  * Same as gen12_ccs_formats[] above, but with additional surface used
100  * to pass Clear Color information in plane 2 with 64 bits of data.
101  */
102 static const struct drm_format_info gen12_ccs_cc_formats[] = {
103 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3,
104 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
105 	  .hsub = 1, .vsub = 1, },
106 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3,
107 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
108 	  .hsub = 1, .vsub = 1, },
109 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3,
110 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
111 	  .hsub = 1, .vsub = 1, .has_alpha = true },
112 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3,
113 	  .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 },
114 	  .hsub = 1, .vsub = 1, .has_alpha = true },
115 };
116 
117 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
118 	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
119 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
120 	  .hsub = 1, .vsub = 1, },
121 	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
122 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
123 	  .hsub = 1, .vsub = 1, },
124 	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
125 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
126 	  .hsub = 1, .vsub = 1, .has_alpha = true },
127 	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
128 	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
129 	  .hsub = 1, .vsub = 1, .has_alpha = true },
130 };
131 
132 struct intel_modifier_desc {
133 	u64 modifier;
134 	struct {
135 		u8 from;
136 		u8 until;
137 	} display_ver;
138 #define DISPLAY_VER_ALL		{ 0, -1 }
139 
140 	const struct drm_format_info *formats;
141 	int format_count;
142 #define FORMAT_OVERRIDE(format_list) \
143 	.formats = format_list, \
144 	.format_count = ARRAY_SIZE(format_list)
145 
146 	u8 plane_caps;
147 
148 	struct {
149 		u8 cc_planes:3;
150 		u8 packed_aux_planes:4;
151 		u8 planar_aux_planes:4;
152 	} ccs;
153 };
154 
155 #define INTEL_PLANE_CAP_CCS_MASK	(INTEL_PLANE_CAP_CCS_RC | \
156 					 INTEL_PLANE_CAP_CCS_RC_CC | \
157 					 INTEL_PLANE_CAP_CCS_MC)
158 #define INTEL_PLANE_CAP_TILING_MASK	(INTEL_PLANE_CAP_TILING_X | \
159 					 INTEL_PLANE_CAP_TILING_Y | \
160 					 INTEL_PLANE_CAP_TILING_Yf | \
161 					 INTEL_PLANE_CAP_TILING_4)
162 #define INTEL_PLANE_CAP_TILING_NONE	0
163 
164 static const struct intel_modifier_desc intel_modifiers[] = {
165 	{
166 		.modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS,
167 		.display_ver = { 20, -1 },
168 		.plane_caps = INTEL_PLANE_CAP_TILING_4,
169 	}, {
170 		.modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS,
171 		.display_ver = { 14, -1 },
172 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS,
173 	}, {
174 		.modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS,
175 		.display_ver = { 14, 14 },
176 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
177 
178 		.ccs.packed_aux_planes = BIT(1),
179 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
180 
181 		FORMAT_OVERRIDE(gen12_ccs_formats),
182 	}, {
183 		.modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS,
184 		.display_ver = { 14, 14 },
185 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
186 
187 		.ccs.packed_aux_planes = BIT(1),
188 
189 		FORMAT_OVERRIDE(gen12_ccs_formats),
190 	}, {
191 		.modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC,
192 		.display_ver = { 14, 14 },
193 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
194 
195 		.ccs.cc_planes = BIT(2),
196 		.ccs.packed_aux_planes = BIT(1),
197 
198 		FORMAT_OVERRIDE(gen12_ccs_cc_formats),
199 	}, {
200 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
201 		.display_ver = { 13, 13 },
202 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
203 	}, {
204 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
205 		.display_ver = { 13, 13 },
206 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
207 
208 		.ccs.cc_planes = BIT(1),
209 
210 		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
211 	}, {
212 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
213 		.display_ver = { 13, 13 },
214 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
215 	}, {
216 		.modifier = I915_FORMAT_MOD_4_TILED,
217 		.display_ver = { 13, -1 },
218 		.plane_caps = INTEL_PLANE_CAP_TILING_4,
219 	}, {
220 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
221 		.display_ver = { 12, 13 },
222 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
223 
224 		.ccs.packed_aux_planes = BIT(1),
225 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
226 
227 		FORMAT_OVERRIDE(gen12_ccs_formats),
228 	}, {
229 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS,
230 		.display_ver = { 12, 13 },
231 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
232 
233 		.ccs.packed_aux_planes = BIT(1),
234 
235 		FORMAT_OVERRIDE(gen12_ccs_formats),
236 	}, {
237 		.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC,
238 		.display_ver = { 12, 13 },
239 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC,
240 
241 		.ccs.cc_planes = BIT(2),
242 		.ccs.packed_aux_planes = BIT(1),
243 
244 		FORMAT_OVERRIDE(gen12_ccs_cc_formats),
245 	}, {
246 		.modifier = I915_FORMAT_MOD_Yf_TILED_CCS,
247 		.display_ver = { 9, 11 },
248 		.plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC,
249 
250 		.ccs.packed_aux_planes = BIT(1),
251 
252 		FORMAT_OVERRIDE(skl_ccs_formats),
253 	}, {
254 		.modifier = I915_FORMAT_MOD_Y_TILED_CCS,
255 		.display_ver = { 9, 11 },
256 		.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC,
257 
258 		.ccs.packed_aux_planes = BIT(1),
259 
260 		FORMAT_OVERRIDE(skl_ccs_formats),
261 	}, {
262 		.modifier = I915_FORMAT_MOD_Yf_TILED,
263 		.display_ver = { 9, 11 },
264 		.plane_caps = INTEL_PLANE_CAP_TILING_Yf,
265 	}, {
266 		.modifier = I915_FORMAT_MOD_Y_TILED,
267 		.display_ver = { 9, 13 },
268 		.plane_caps = INTEL_PLANE_CAP_TILING_Y,
269 	}, {
270 		.modifier = I915_FORMAT_MOD_X_TILED,
271 		.display_ver = DISPLAY_VER_ALL,
272 		.plane_caps = INTEL_PLANE_CAP_TILING_X,
273 	}, {
274 		.modifier = DRM_FORMAT_MOD_LINEAR,
275 		.display_ver = DISPLAY_VER_ALL,
276 	},
277 };
278 
279 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier)
280 {
281 	int i;
282 
283 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++)
284 		if (intel_modifiers[i].modifier == modifier)
285 			return &intel_modifiers[i];
286 
287 	return NULL;
288 }
289 
290 static const struct intel_modifier_desc *lookup_modifier(u64 modifier)
291 {
292 	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
293 
294 	if (WARN_ON(!md))
295 		return &intel_modifiers[0];
296 
297 	return md;
298 }
299 
300 static const struct drm_format_info *
301 lookup_format_info(const struct drm_format_info formats[],
302 		   int num_formats, u32 format)
303 {
304 	int i;
305 
306 	for (i = 0; i < num_formats; i++) {
307 		if (formats[i].format == format)
308 			return &formats[i];
309 	}
310 
311 	return NULL;
312 }
313 
314 unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
315 {
316 	const struct intel_modifier_desc *md;
317 	u8 tiling_caps;
318 
319 	md = lookup_modifier_or_null(fb_modifier);
320 	if (!md)
321 		return I915_TILING_NONE;
322 
323 	tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps &
324 			 INTEL_PLANE_CAP_TILING_MASK;
325 
326 	switch (tiling_caps) {
327 	case INTEL_PLANE_CAP_TILING_Y:
328 		return I915_TILING_Y;
329 	case INTEL_PLANE_CAP_TILING_X:
330 		return I915_TILING_X;
331 	case INTEL_PLANE_CAP_TILING_4:
332 	case INTEL_PLANE_CAP_TILING_Yf:
333 	case INTEL_PLANE_CAP_TILING_NONE:
334 		return I915_TILING_NONE;
335 	default:
336 		MISSING_CASE(tiling_caps);
337 		return I915_TILING_NONE;
338 	}
339 }
340 
341 /**
342  * intel_fb_get_format_info: Get a modifier specific format information
343  * @cmd: FB add command structure
344  *
345  * Returns:
346  * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0],
347  * or %NULL if the modifier doesn't override the format.
348  */
349 const struct drm_format_info *
350 intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
351 {
352 	const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]);
353 
354 	if (!md || !md->formats)
355 		return NULL;
356 
357 	return lookup_format_info(md->formats, md->format_count, cmd->pixel_format);
358 }
359 
360 static bool plane_caps_contain_any(u8 caps, u8 mask)
361 {
362 	return caps & mask;
363 }
364 
365 static bool plane_caps_contain_all(u8 caps, u8 mask)
366 {
367 	return (caps & mask) == mask;
368 }
369 
370 /**
371  * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type
372  * @modifier: Modifier to check
373  *
374  * Returns:
375  * Returns %true if @modifier is a tiled modifier.
376  */
377 bool intel_fb_is_tiled_modifier(u64 modifier)
378 {
379 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
380 				      INTEL_PLANE_CAP_TILING_MASK);
381 }
382 
383 /**
384  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
385  * @modifier: Modifier to check
386  *
387  * Returns:
388  * Returns %true if @modifier is a render, render with color clear or
389  * media compression modifier.
390  */
391 bool intel_fb_is_ccs_modifier(u64 modifier)
392 {
393 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
394 				      INTEL_PLANE_CAP_CCS_MASK);
395 }
396 
397 /**
398  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
399  * @modifier: Modifier to check
400  *
401  * Returns:
402  * Returns %true if @modifier is a render with color clear modifier.
403  */
404 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier)
405 {
406 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
407 				      INTEL_PLANE_CAP_CCS_RC_CC);
408 }
409 
410 /**
411  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
412  * @modifier: Modifier to check
413  *
414  * Returns:
415  * Returns %true if @modifier is a media compression modifier.
416  */
417 bool intel_fb_is_mc_ccs_modifier(u64 modifier)
418 {
419 	return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps,
420 				      INTEL_PLANE_CAP_CCS_MC);
421 }
422 
423 /**
424  * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement.
425  * @modifier: Modifier to check
426  *
427  * Returns:
428  * Returns %true if @modifier requires 64k aligned physical pages.
429  */
430 bool intel_fb_needs_64k_phys(u64 modifier)
431 {
432 	const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier);
433 
434 	if (!md)
435 		return false;
436 
437 	return plane_caps_contain_any(md->plane_caps,
438 				      INTEL_PLANE_CAP_NEED64K_PHYS);
439 }
440 
441 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md,
442 					     u8 display_ver_from, u8 display_ver_until)
443 {
444 	return md->display_ver.from <= display_ver_until &&
445 		display_ver_from <= md->display_ver.until;
446 }
447 
448 static bool plane_has_modifier(struct drm_i915_private *i915,
449 			       u8 plane_caps,
450 			       const struct intel_modifier_desc *md)
451 {
452 	if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until))
453 		return false;
454 
455 	if (!plane_caps_contain_all(plane_caps, md->plane_caps))
456 		return false;
457 
458 	/*
459 	 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms
460 	 * where supported.
461 	 */
462 	if (intel_fb_is_ccs_modifier(md->modifier) &&
463 	    HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)
464 		return false;
465 
466 	if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS &&
467 	    (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915)))
468 		return false;
469 
470 	if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS &&
471 	    (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915)))
472 		return false;
473 
474 	return true;
475 }
476 
477 /**
478  * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities
479  * @i915: i915 device instance
480  * @plane_caps: capabilities for the plane the modifiers are queried for
481  *
482  * Returns:
483  * Returns the list of modifiers allowed by the @i915 platform and @plane_caps.
484  * The caller must free the returned buffer.
485  */
486 u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915,
487 				  u8 plane_caps)
488 {
489 	u64 *list, *p;
490 	int count = 1;		/* +1 for invalid modifier terminator */
491 	int i;
492 
493 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
494 		if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
495 			count++;
496 	}
497 
498 	list = kmalloc_array(count, sizeof(*list), GFP_KERNEL);
499 	if (drm_WARN_ON(&i915->drm, !list))
500 		return NULL;
501 
502 	p = list;
503 	for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) {
504 		if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i]))
505 			*p++ = intel_modifiers[i].modifier;
506 	}
507 	*p++ = DRM_FORMAT_MOD_INVALID;
508 
509 	return list;
510 }
511 
512 /**
513  * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane
514  * @plane: Plane to check the modifier support for
515  * @modifier: The modifier to check the support for
516  *
517  * Returns:
518  * %true if the @modifier is supported on @plane.
519  */
520 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
521 {
522 	int i;
523 
524 	for (i = 0; i < plane->base.modifier_count; i++)
525 		if (plane->base.modifiers[i] == modifier)
526 			return true;
527 
528 	return false;
529 }
530 
531 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
532 				     const struct drm_format_info *info)
533 {
534 	if (!info->is_yuv)
535 		return false;
536 
537 	if (hweight8(md->ccs.planar_aux_planes) == 2)
538 		return info->num_planes == 4;
539 	else
540 		return info->num_planes == 2;
541 }
542 
543 /**
544  * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar
545  * @info: format to check
546  * @modifier: modifier used with the format
547  *
548  * Returns:
549  * %true if @info / @modifier is YUV semiplanar.
550  */
551 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
552 					 u64 modifier)
553 {
554 	return format_is_yuv_semiplanar(lookup_modifier(modifier), info);
555 }
556 
557 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md,
558 			     const struct drm_format_info *format)
559 {
560 	if (format_is_yuv_semiplanar(md, format))
561 		return md->ccs.planar_aux_planes;
562 	else
563 		return md->ccs.packed_aux_planes;
564 }
565 
566 /**
567  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
568  * @fb: Framebuffer
569  * @color_plane: color plane index to check
570  *
571  * Returns:
572  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
573  */
574 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
575 {
576 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
577 
578 	return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
579 }
580 
581 /**
582  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
583  * @fb: Framebuffer
584  * @color_plane: color plane index to check
585  *
586  * Returns:
587  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
588  */
589 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane)
590 {
591 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
592 
593 	return check_modifier_display_ver_range(md, 12, 14) &&
594 	       ccs_aux_plane_mask(md, fb->format) & BIT(color_plane);
595 }
596 
597 /**
598  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
599  * @fb: Framebuffer
600  *
601  * Returns:
602  * Returns the index of the color clear plane for @fb, or -1 if @fb is not a
603  * framebuffer using a render compression/color clear modifier.
604  */
605 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb)
606 {
607 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
608 
609 	if (!md->ccs.cc_planes)
610 		return -1;
611 
612 	drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);
613 
614 	return ilog2((int)md->ccs.cc_planes);
615 }
616 
617 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane)
618 {
619 	return intel_fb_rc_ccs_cc_plane(fb) == color_plane;
620 }
621 
622 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
623 {
624 	return fb->modifier == DRM_FORMAT_MOD_LINEAR ||
625 	       intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) ||
626 	       is_gen12_ccs_cc_plane(fb, color_plane);
627 }
628 
629 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
630 {
631 	drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
632 		    (main_plane && main_plane >= fb->format->num_planes / 2));
633 
634 	return fb->format->num_planes / 2 + main_plane;
635 }
636 
637 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
638 {
639 	drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) ||
640 		    ccs_plane < fb->format->num_planes / 2);
641 
642 	if (is_gen12_ccs_cc_plane(fb, ccs_plane))
643 		return 0;
644 
645 	return ccs_plane - fb->format->num_planes / 2;
646 }
647 
648 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane)
649 {
650 	int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane);
651 	unsigned int main_stride = fb->base.pitches[main_plane];
652 	unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane);
653 
654 	return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64;
655 }
656 
657 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
658 {
659 	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
660 	struct drm_i915_private *i915 = to_i915(fb->dev);
661 
662 	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
663 		return main_to_ccs_plane(fb, main_plane);
664 	else if (DISPLAY_VER(i915) < 11 &&
665 		 format_is_yuv_semiplanar(md, fb->format))
666 		return 1;
667 	else
668 		return 0;
669 }
670 
671 unsigned int intel_tile_size(const struct drm_i915_private *i915)
672 {
673 	return DISPLAY_VER(i915) == 2 ? 2048 : 4096;
674 }
675 
676 unsigned int
677 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
678 {
679 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
680 	unsigned int cpp = fb->format->cpp[color_plane];
681 
682 	switch (fb->modifier) {
683 	case DRM_FORMAT_MOD_LINEAR:
684 		return intel_tile_size(dev_priv);
685 	case I915_FORMAT_MOD_X_TILED:
686 		if (DISPLAY_VER(dev_priv) == 2)
687 			return 128;
688 		else
689 			return 512;
690 	case I915_FORMAT_MOD_4_TILED_BMG_CCS:
691 	case I915_FORMAT_MOD_4_TILED_LNL_CCS:
692 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
693 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
694 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
695 	case I915_FORMAT_MOD_4_TILED:
696 		/*
697 		 * Each 4K tile consists of 64B(8*8) subtiles, with
698 		 * same shape as Y Tile(i.e 4*16B OWords)
699 		 */
700 		return 128;
701 	case I915_FORMAT_MOD_Y_TILED_CCS:
702 		if (intel_fb_is_ccs_aux_plane(fb, color_plane))
703 			return 128;
704 		fallthrough;
705 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
706 	case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
707 	case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
708 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
709 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
710 	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
711 		if (intel_fb_is_ccs_aux_plane(fb, color_plane) ||
712 		    is_gen12_ccs_cc_plane(fb, color_plane))
713 			return 64;
714 		fallthrough;
715 	case I915_FORMAT_MOD_Y_TILED:
716 		if (DISPLAY_VER(dev_priv) == 2 || HAS_128_BYTE_Y_TILING(dev_priv))
717 			return 128;
718 		else
719 			return 512;
720 	case I915_FORMAT_MOD_Yf_TILED_CCS:
721 		if (intel_fb_is_ccs_aux_plane(fb, color_plane))
722 			return 128;
723 		fallthrough;
724 	case I915_FORMAT_MOD_Yf_TILED:
725 		switch (cpp) {
726 		case 1:
727 			return 64;
728 		case 2:
729 		case 4:
730 			return 128;
731 		case 8:
732 		case 16:
733 			return 256;
734 		default:
735 			MISSING_CASE(cpp);
736 			return cpp;
737 		}
738 		break;
739 	default:
740 		MISSING_CASE(fb->modifier);
741 		return cpp;
742 	}
743 }
744 
745 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
746 {
747 	return intel_tile_size(to_i915(fb->dev)) /
748 		intel_tile_width_bytes(fb, color_plane);
749 }
750 
751 /*
752  * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT
753  * page tile size.
754  */
755 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
756 			    unsigned int *tile_width,
757 			    unsigned int *tile_height)
758 {
759 	unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
760 	unsigned int cpp = fb->format->cpp[color_plane];
761 
762 	*tile_width = tile_width_bytes / cpp;
763 	*tile_height = intel_tile_height(fb, color_plane);
764 }
765 
766 /*
767  * Return the tile dimensions in pixel units, based on the tile block size.
768  * The block covers the full GTT page sized tile on all tiled surfaces and
769  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
770  */
771 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane,
772 				  unsigned int *tile_width,
773 				  unsigned int *tile_height)
774 {
775 	intel_tile_dims(fb, color_plane, tile_width, tile_height);
776 
777 	if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane))
778 		*tile_height = 1;
779 }
780 
781 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane)
782 {
783 	unsigned int tile_width, tile_height;
784 
785 	intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
786 
787 	return fb->pitches[color_plane] * tile_height;
788 }
789 
790 unsigned int
791 intel_fb_align_height(const struct drm_framebuffer *fb,
792 		      int color_plane, unsigned int height)
793 {
794 	unsigned int tile_height = intel_tile_height(fb, color_plane);
795 
796 	return ALIGN(height, tile_height);
797 }
798 
799 bool intel_fb_modifier_uses_dpt(struct drm_i915_private *i915, u64 modifier)
800 {
801 	return HAS_DPT(i915) && modifier != DRM_FORMAT_MOD_LINEAR;
802 }
803 
804 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb)
805 {
806 	return to_i915(fb->dev)->display.params.enable_dpt &&
807 		intel_fb_modifier_uses_dpt(to_i915(fb->dev), fb->modifier);
808 }
809 
810 void intel_fb_plane_get_subsampling(int *hsub, int *vsub,
811 				    const struct drm_framebuffer *fb,
812 				    int color_plane)
813 {
814 	int main_plane;
815 
816 	if (color_plane == 0) {
817 		*hsub = 1;
818 		*vsub = 1;
819 
820 		return;
821 	}
822 
823 	/*
824 	 * TODO: Deduct the subsampling from the char block for all CCS
825 	 * formats and planes.
826 	 */
827 	if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) {
828 		*hsub = fb->format->hsub;
829 		*vsub = fb->format->vsub;
830 
831 		return;
832 	}
833 
834 	main_plane = skl_ccs_to_main_plane(fb, color_plane);
835 	*hsub = drm_format_info_block_width(fb->format, color_plane) /
836 		drm_format_info_block_width(fb->format, main_plane);
837 
838 	/*
839 	 * The min stride check in the core framebuffer_check() function
840 	 * assumes that format->hsub applies to every plane except for the
841 	 * first plane. That's incorrect for the CCS AUX plane of the first
842 	 * plane, but for the above check to pass we must define the block
843 	 * width with that subsampling applied to it. Adjust the width here
844 	 * accordingly, so we can calculate the actual subsampling factor.
845 	 */
846 	if (main_plane == 0)
847 		*hsub *= fb->format->hsub;
848 
849 	*vsub = 32;
850 }
851 
852 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h)
853 {
854 	int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ?
855 			 skl_ccs_to_main_plane(&fb->base, color_plane) : 0;
856 	unsigned int main_width = fb->base.width;
857 	unsigned int main_height = fb->base.height;
858 	int main_hsub, main_vsub;
859 	int hsub, vsub;
860 
861 	intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane);
862 	intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane);
863 
864 	*w = DIV_ROUND_UP(main_width, main_hsub * hsub);
865 	*h = DIV_ROUND_UP(main_height, main_vsub * vsub);
866 }
867 
868 static u32 intel_adjust_tile_offset(int *x, int *y,
869 				    unsigned int tile_width,
870 				    unsigned int tile_height,
871 				    unsigned int tile_size,
872 				    unsigned int pitch_tiles,
873 				    u32 old_offset,
874 				    u32 new_offset)
875 {
876 	unsigned int pitch_pixels = pitch_tiles * tile_width;
877 	unsigned int tiles;
878 
879 	WARN_ON(old_offset & (tile_size - 1));
880 	WARN_ON(new_offset & (tile_size - 1));
881 	WARN_ON(new_offset > old_offset);
882 
883 	tiles = (old_offset - new_offset) / tile_size;
884 
885 	*y += tiles / pitch_tiles * tile_height;
886 	*x += tiles % pitch_tiles * tile_width;
887 
888 	/* minimize x in case it got needlessly big */
889 	*y += *x / pitch_pixels * tile_height;
890 	*x %= pitch_pixels;
891 
892 	return new_offset;
893 }
894 
895 static u32 intel_adjust_linear_offset(int *x, int *y,
896 				      unsigned int cpp,
897 				      unsigned int pitch,
898 				      u32 old_offset,
899 				      u32 new_offset)
900 {
901 	old_offset += *y * pitch + *x * cpp;
902 
903 	*y = (old_offset - new_offset) / pitch;
904 	*x = ((old_offset - new_offset) - *y * pitch) / cpp;
905 
906 	return new_offset;
907 }
908 
909 static u32 intel_adjust_aligned_offset(int *x, int *y,
910 				       const struct drm_framebuffer *fb,
911 				       int color_plane,
912 				       unsigned int rotation,
913 				       unsigned int pitch,
914 				       u32 old_offset, u32 new_offset)
915 {
916 	struct drm_i915_private *i915 = to_i915(fb->dev);
917 	unsigned int cpp = fb->format->cpp[color_plane];
918 
919 	drm_WARN_ON(&i915->drm, new_offset > old_offset);
920 
921 	if (!is_surface_linear(fb, color_plane)) {
922 		unsigned int tile_size, tile_width, tile_height;
923 		unsigned int pitch_tiles;
924 
925 		tile_size = intel_tile_size(i915);
926 		intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
927 
928 		if (drm_rotation_90_or_270(rotation)) {
929 			pitch_tiles = pitch / tile_height;
930 			swap(tile_width, tile_height);
931 		} else {
932 			pitch_tiles = pitch / (tile_width * cpp);
933 		}
934 
935 		intel_adjust_tile_offset(x, y, tile_width, tile_height,
936 					 tile_size, pitch_tiles,
937 					 old_offset, new_offset);
938 	} else {
939 		intel_adjust_linear_offset(x, y, cpp, pitch,
940 					   old_offset, new_offset);
941 	}
942 
943 	return new_offset;
944 }
945 
946 /*
947  * Adjust the tile offset by moving the difference into
948  * the x/y offsets.
949  */
950 u32 intel_plane_adjust_aligned_offset(int *x, int *y,
951 				      const struct intel_plane_state *state,
952 				      int color_plane,
953 				      u32 old_offset, u32 new_offset)
954 {
955 	return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
956 					   state->hw.rotation,
957 					   state->view.color_plane[color_plane].mapping_stride,
958 					   old_offset, new_offset);
959 }
960 
961 /*
962  * Computes the aligned offset to the base tile and adjusts
963  * x, y. bytes per pixel is assumed to be a power-of-two.
964  *
965  * In the 90/270 rotated case, x and y are assumed
966  * to be already rotated to match the rotated GTT view, and
967  * pitch is the tile_height aligned framebuffer height.
968  *
969  * This function is used when computing the derived information
970  * under intel_framebuffer, so using any of that information
971  * here is not allowed. Anything under drm_framebuffer can be
972  * used. This is why the user has to pass in the pitch since it
973  * is specified in the rotated orientation.
974  */
975 static u32 intel_compute_aligned_offset(struct drm_i915_private *i915,
976 					int *x, int *y,
977 					const struct drm_framebuffer *fb,
978 					int color_plane,
979 					unsigned int pitch,
980 					unsigned int rotation,
981 					unsigned int alignment)
982 {
983 	unsigned int cpp = fb->format->cpp[color_plane];
984 	u32 offset, offset_aligned;
985 
986 	if (!is_surface_linear(fb, color_plane)) {
987 		unsigned int tile_size, tile_width, tile_height;
988 		unsigned int tile_rows, tiles, pitch_tiles;
989 
990 		tile_size = intel_tile_size(i915);
991 		intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
992 
993 		if (drm_rotation_90_or_270(rotation)) {
994 			pitch_tiles = pitch / tile_height;
995 			swap(tile_width, tile_height);
996 		} else {
997 			pitch_tiles = pitch / (tile_width * cpp);
998 		}
999 
1000 		tile_rows = *y / tile_height;
1001 		*y %= tile_height;
1002 
1003 		tiles = *x / tile_width;
1004 		*x %= tile_width;
1005 
1006 		offset = (tile_rows * pitch_tiles + tiles) * tile_size;
1007 
1008 		offset_aligned = offset;
1009 		if (alignment)
1010 			offset_aligned = rounddown(offset_aligned, alignment);
1011 
1012 		intel_adjust_tile_offset(x, y, tile_width, tile_height,
1013 					 tile_size, pitch_tiles,
1014 					 offset, offset_aligned);
1015 	} else {
1016 		offset = *y * pitch + *x * cpp;
1017 		offset_aligned = offset;
1018 		if (alignment) {
1019 			offset_aligned = rounddown(offset_aligned, alignment);
1020 			*y = (offset % alignment) / pitch;
1021 			*x = ((offset % alignment) - *y * pitch) / cpp;
1022 		} else {
1023 			*y = *x = 0;
1024 		}
1025 	}
1026 
1027 	return offset_aligned;
1028 }
1029 
1030 u32 intel_plane_compute_aligned_offset(int *x, int *y,
1031 				       const struct intel_plane_state *state,
1032 				       int color_plane)
1033 {
1034 	struct intel_plane *plane = to_intel_plane(state->uapi.plane);
1035 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
1036 	const struct drm_framebuffer *fb = state->hw.fb;
1037 	unsigned int rotation = state->hw.rotation;
1038 	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
1039 	unsigned int alignment = plane->min_alignment(plane, fb, color_plane);
1040 
1041 	return intel_compute_aligned_offset(i915, x, y, fb, color_plane,
1042 					    pitch, rotation, alignment);
1043 }
1044 
1045 /* Convert the fb->offset[] into x/y offsets */
1046 static int intel_fb_offset_to_xy(int *x, int *y,
1047 				 const struct drm_framebuffer *fb,
1048 				 int color_plane)
1049 {
1050 	struct drm_i915_private *i915 = to_i915(fb->dev);
1051 	unsigned int height, alignment, unused;
1052 
1053 	if (fb->modifier != DRM_FORMAT_MOD_LINEAR)
1054 		alignment = intel_tile_size(i915);
1055 	else
1056 		alignment = 0;
1057 
1058 	if (alignment != 0 && fb->offsets[color_plane] % alignment) {
1059 		drm_dbg_kms(&i915->drm,
1060 			    "Misaligned offset 0x%08x for color plane %d\n",
1061 			    fb->offsets[color_plane], color_plane);
1062 		return -EINVAL;
1063 	}
1064 
1065 	height = drm_format_info_plane_height(fb->format, fb->height, color_plane);
1066 	height = ALIGN(height, intel_tile_height(fb, color_plane));
1067 
1068 	/* Catch potential overflows early */
1069 	if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]),
1070 			       fb->offsets[color_plane], &unused)) {
1071 		drm_dbg_kms(&i915->drm,
1072 			    "Bad offset 0x%08x or pitch %d for color plane %d\n",
1073 			    fb->offsets[color_plane], fb->pitches[color_plane],
1074 			    color_plane);
1075 		return -ERANGE;
1076 	}
1077 
1078 	*x = 0;
1079 	*y = 0;
1080 
1081 	intel_adjust_aligned_offset(x, y,
1082 				    fb, color_plane, DRM_MODE_ROTATE_0,
1083 				    fb->pitches[color_plane],
1084 				    fb->offsets[color_plane], 0);
1085 
1086 	return 0;
1087 }
1088 
1089 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y)
1090 {
1091 	struct drm_i915_private *i915 = to_i915(fb->dev);
1092 	const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1093 	int main_plane;
1094 	int hsub, vsub;
1095 	int tile_width, tile_height;
1096 	int ccs_x, ccs_y;
1097 	int main_x, main_y;
1098 
1099 	if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1100 		return 0;
1101 
1102 	/*
1103 	 * While all the tile dimensions are based on a 2k or 4k GTT page size
1104 	 * here the main and CCS coordinates must match only within a (64 byte
1105 	 * on TGL+) block inside the tile.
1106 	 */
1107 	intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height);
1108 	intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1109 
1110 	tile_width *= hsub;
1111 	tile_height *= vsub;
1112 
1113 	ccs_x = (x * hsub) % tile_width;
1114 	ccs_y = (y * vsub) % tile_height;
1115 
1116 	main_plane = skl_ccs_to_main_plane(fb, ccs_plane);
1117 	main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width;
1118 	main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height;
1119 
1120 	/*
1121 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile
1122 	 * x/y offsets must match between CCS and the main surface.
1123 	 */
1124 	if (main_x != ccs_x || main_y != ccs_y) {
1125 		drm_dbg_kms(&i915->drm,
1126 			      "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",
1127 			      main_x, main_y,
1128 			      ccs_x, ccs_y,
1129 			      intel_fb->normal_view.color_plane[main_plane].x,
1130 			      intel_fb->normal_view.color_plane[main_plane].y,
1131 			      x, y);
1132 		return -EINVAL;
1133 	}
1134 
1135 	return 0;
1136 }
1137 
1138 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
1139 {
1140 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1141 	struct drm_i915_private *i915 = to_i915(plane->base.dev);
1142 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1143 	int i;
1144 
1145 	/* We don't want to deal with remapping with cursors */
1146 	if (plane->id == PLANE_CURSOR)
1147 		return false;
1148 
1149 	/*
1150 	 * The display engine limits already match/exceed the
1151 	 * render engine limits, so not much point in remapping.
1152 	 * Would also need to deal with the fence POT alignment
1153 	 * and gen2 2KiB GTT tile size.
1154 	 */
1155 	if (DISPLAY_VER(i915) < 4)
1156 		return false;
1157 
1158 	/*
1159 	 * The new CCS hash mode isn't compatible with remapping as
1160 	 * the virtual address of the pages affects the compressed data.
1161 	 */
1162 	if (intel_fb_is_ccs_modifier(fb->modifier))
1163 		return false;
1164 
1165 	/* Linear needs a page aligned stride for remapping */
1166 	if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1167 		unsigned int alignment = intel_tile_size(i915) - 1;
1168 
1169 		for (i = 0; i < fb->format->num_planes; i++) {
1170 			if (fb->pitches[i] & alignment)
1171 				return false;
1172 		}
1173 	}
1174 
1175 	return true;
1176 }
1177 
1178 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb)
1179 {
1180 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1181 
1182 	return (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1183 		intel_fb_uses_dpt(&fb->base);
1184 }
1185 
1186 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation)
1187 {
1188 	if (drm_rotation_90_or_270(rotation))
1189 		return fb->rotated_view.color_plane[color_plane].mapping_stride;
1190 	else if (intel_fb_needs_pot_stride_remap(fb))
1191 		return fb->remapped_view.color_plane[color_plane].mapping_stride;
1192 	else
1193 		return fb->normal_view.color_plane[color_plane].mapping_stride;
1194 }
1195 
1196 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
1197 {
1198 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1199 	const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb);
1200 	unsigned int rotation = plane_state->hw.rotation;
1201 	u32 stride, max_stride;
1202 
1203 	/*
1204 	 * No remapping for invisible planes since we don't have
1205 	 * an actual source viewport to remap.
1206 	 */
1207 	if (!plane_state->uapi.visible)
1208 		return false;
1209 
1210 	if (!intel_plane_can_remap(plane_state))
1211 		return false;
1212 
1213 	/*
1214 	 * FIXME: aux plane limits on gen9+ are
1215 	 * unclear in Bspec, for now no checking.
1216 	 */
1217 	stride = intel_fb_pitch(fb, 0, rotation);
1218 	max_stride = plane->max_stride(plane, fb->base.format->format,
1219 				       fb->base.modifier, rotation);
1220 
1221 	return stride > max_stride;
1222 }
1223 
1224 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane,
1225 				      int plane_width, int *x, int *y)
1226 {
1227 	struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1228 	int ret;
1229 
1230 	ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane);
1231 	if (ret) {
1232 		drm_dbg_kms(fb->base.dev,
1233 			    "bad fb plane %d offset: 0x%x\n",
1234 			    color_plane, fb->base.offsets[color_plane]);
1235 		return ret;
1236 	}
1237 
1238 	ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y);
1239 	if (ret)
1240 		return ret;
1241 
1242 	/*
1243 	 * The fence (if used) is aligned to the start of the object
1244 	 * so having the framebuffer wrap around across the edge of the
1245 	 * fenced region doesn't really work. We have no API to configure
1246 	 * the fence start offset within the object (nor could we probably
1247 	 * on gen2/3). So it's just easier if we just require that the
1248 	 * fb layout agrees with the fence layout. We already check that the
1249 	 * fb stride matches the fence stride elsewhere.
1250 	 */
1251 	if (color_plane == 0 && i915_gem_object_is_tiled(obj) &&
1252 	    (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) {
1253 		drm_dbg_kms(fb->base.dev,
1254 			    "bad fb plane %d offset: 0x%x\n",
1255 			    color_plane, fb->base.offsets[color_plane]);
1256 		return -EINVAL;
1257 	}
1258 
1259 	return 0;
1260 }
1261 
1262 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y)
1263 {
1264 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1265 	unsigned int tile_size = intel_tile_size(i915);
1266 	u32 offset;
1267 
1268 	offset = intel_compute_aligned_offset(i915, x, y, &fb->base, color_plane,
1269 					      fb->base.pitches[color_plane],
1270 					      DRM_MODE_ROTATE_0,
1271 					      tile_size);
1272 
1273 	return offset / tile_size;
1274 }
1275 
1276 struct fb_plane_view_dims {
1277 	unsigned int width, height;
1278 	unsigned int tile_width, tile_height;
1279 };
1280 
1281 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane,
1282 				 unsigned int width, unsigned int height,
1283 				 struct fb_plane_view_dims *dims)
1284 {
1285 	dims->width = width;
1286 	dims->height = height;
1287 
1288 	intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height);
1289 }
1290 
1291 static unsigned int
1292 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1293 			    const struct fb_plane_view_dims *dims)
1294 {
1295 	return DIV_ROUND_UP(fb->base.pitches[color_plane],
1296 			    dims->tile_width * fb->base.format->cpp[color_plane]);
1297 }
1298 
1299 static unsigned int
1300 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane,
1301 			    unsigned int pitch_tiles)
1302 {
1303 	if (intel_fb_needs_pot_stride_remap(fb)) {
1304 		/*
1305 		 * ADL_P, the only platform needing a POT stride has a minimum
1306 		 * of 8 main surface tiles.
1307 		 */
1308 		return roundup_pow_of_two(max(pitch_tiles, 8u));
1309 	} else {
1310 		return pitch_tiles;
1311 	}
1312 }
1313 
1314 static unsigned int
1315 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane,
1316 			  unsigned int tile_width,
1317 			  unsigned int src_stride_tiles, unsigned int dst_stride_tiles)
1318 {
1319 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1320 	unsigned int stride_tiles;
1321 
1322 	if ((IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) &&
1323 	    src_stride_tiles < dst_stride_tiles)
1324 		stride_tiles = src_stride_tiles;
1325 	else
1326 		stride_tiles = dst_stride_tiles;
1327 
1328 	return stride_tiles * tile_width * fb->base.format->cpp[color_plane];
1329 }
1330 
1331 static unsigned int
1332 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane,
1333 		       const struct fb_plane_view_dims *dims,
1334 		       int x)
1335 {
1336 	return DIV_ROUND_UP(x + dims->width, dims->tile_width);
1337 }
1338 
1339 static unsigned int
1340 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane,
1341 			const struct fb_plane_view_dims *dims,
1342 			int y)
1343 {
1344 	return DIV_ROUND_UP(y + dims->height, dims->tile_height);
1345 }
1346 
1347 static unsigned int
1348 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane,
1349 			const struct fb_plane_view_dims *dims,
1350 			int x, int y)
1351 {
1352 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1353 	unsigned int size;
1354 
1355 	size = (y + dims->height) * fb->base.pitches[color_plane] +
1356 		x * fb->base.format->cpp[color_plane];
1357 
1358 	return DIV_ROUND_UP(size, intel_tile_size(i915));
1359 }
1360 
1361 #define assign_chk_ovf(i915, var, val) ({ \
1362 	drm_WARN_ON(&(i915)->drm, overflows_type(val, var)); \
1363 	(var) = (val); \
1364 })
1365 
1366 #define assign_bfld_chk_ovf(i915, var, val) ({ \
1367 	(var) = (val); \
1368 	drm_WARN_ON(&(i915)->drm, (var) != (val)); \
1369 	(var); \
1370 })
1371 
1372 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane,
1373 				 const struct fb_plane_view_dims *dims,
1374 				 u32 obj_offset, u32 gtt_offset, int x, int y,
1375 				 struct intel_fb_view *view)
1376 {
1377 	struct drm_i915_private *i915 = to_i915(fb->base.dev);
1378 	struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane];
1379 	struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane];
1380 	unsigned int tile_width = dims->tile_width;
1381 	unsigned int tile_height = dims->tile_height;
1382 	unsigned int tile_size = intel_tile_size(i915);
1383 	struct drm_rect r;
1384 	u32 size = 0;
1385 
1386 	assign_bfld_chk_ovf(i915, remap_info->offset, obj_offset);
1387 
1388 	if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) {
1389 		remap_info->linear = 1;
1390 
1391 		assign_chk_ovf(i915, remap_info->size,
1392 			       plane_view_linear_tiles(fb, color_plane, dims, x, y));
1393 	} else {
1394 		remap_info->linear = 0;
1395 
1396 		assign_chk_ovf(i915, remap_info->src_stride,
1397 			       plane_view_src_stride_tiles(fb, color_plane, dims));
1398 		assign_chk_ovf(i915, remap_info->width,
1399 			       plane_view_width_tiles(fb, color_plane, dims, x));
1400 		assign_chk_ovf(i915, remap_info->height,
1401 			       plane_view_height_tiles(fb, color_plane, dims, y));
1402 	}
1403 
1404 	if (view->gtt.type == I915_GTT_VIEW_ROTATED) {
1405 		drm_WARN_ON(&i915->drm, remap_info->linear);
1406 		check_array_bounds(i915, view->gtt.rotated.plane, color_plane);
1407 
1408 		assign_chk_ovf(i915, remap_info->dst_stride,
1409 			       plane_view_dst_stride_tiles(fb, color_plane, remap_info->height));
1410 
1411 		/* rotate the x/y offsets to match the GTT view */
1412 		drm_rect_init(&r, x, y, dims->width, dims->height);
1413 		drm_rect_rotate(&r,
1414 				remap_info->width * tile_width,
1415 				remap_info->height * tile_height,
1416 				DRM_MODE_ROTATE_270);
1417 
1418 		color_plane_info->x = r.x1;
1419 		color_plane_info->y = r.y1;
1420 
1421 		color_plane_info->mapping_stride = remap_info->dst_stride * tile_height;
1422 		color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1423 
1424 		size += remap_info->dst_stride * remap_info->width;
1425 
1426 		/* rotate the tile dimensions to match the GTT view */
1427 		swap(tile_width, tile_height);
1428 	} else {
1429 		drm_WARN_ON(&i915->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED);
1430 
1431 		check_array_bounds(i915, view->gtt.remapped.plane, color_plane);
1432 
1433 		if (view->gtt.remapped.plane_alignment) {
1434 			u32 aligned_offset = ALIGN(gtt_offset,
1435 						   view->gtt.remapped.plane_alignment);
1436 
1437 			size += aligned_offset - gtt_offset;
1438 			gtt_offset = aligned_offset;
1439 		}
1440 
1441 		color_plane_info->x = x;
1442 		color_plane_info->y = y;
1443 
1444 		if (remap_info->linear) {
1445 			color_plane_info->mapping_stride = fb->base.pitches[color_plane];
1446 			color_plane_info->scanout_stride = color_plane_info->mapping_stride;
1447 
1448 			size += remap_info->size;
1449 		} else {
1450 			unsigned int dst_stride;
1451 
1452 			/*
1453 			 * The hardware automagically calculates the CCS AUX surface
1454 			 * stride from the main surface stride so can't really remap a
1455 			 * smaller subset (unless we'd remap in whole AUX page units).
1456 			 */
1457 			if (intel_fb_needs_pot_stride_remap(fb) &&
1458 			    intel_fb_is_ccs_modifier(fb->base.modifier))
1459 				dst_stride = remap_info->src_stride;
1460 			else
1461 				dst_stride = remap_info->width;
1462 
1463 			dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride);
1464 
1465 			assign_chk_ovf(i915, remap_info->dst_stride, dst_stride);
1466 			color_plane_info->mapping_stride = dst_stride *
1467 							   tile_width *
1468 							   fb->base.format->cpp[color_plane];
1469 			color_plane_info->scanout_stride =
1470 				plane_view_scanout_stride(fb, color_plane, tile_width,
1471 							  remap_info->src_stride,
1472 							  dst_stride);
1473 
1474 			size += dst_stride * remap_info->height;
1475 		}
1476 	}
1477 
1478 	/*
1479 	 * We only keep the x/y offsets, so push all of the gtt offset into
1480 	 * the x/y offsets.  x,y will hold the first pixel of the framebuffer
1481 	 * plane from the start of the remapped/rotated gtt mapping.
1482 	 */
1483 	if (remap_info->linear)
1484 		intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y,
1485 					   fb->base.format->cpp[color_plane],
1486 					   color_plane_info->mapping_stride,
1487 					   gtt_offset * tile_size, 0);
1488 	else
1489 		intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y,
1490 					 tile_width, tile_height,
1491 					 tile_size, remap_info->dst_stride,
1492 					 gtt_offset * tile_size, 0);
1493 
1494 	return size;
1495 }
1496 
1497 #undef assign_chk_ovf
1498 
1499 /* Return number of tiles @color_plane needs. */
1500 static unsigned int
1501 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane,
1502 		       const struct fb_plane_view_dims *dims,
1503 		       int x, int y)
1504 {
1505 	unsigned int tiles;
1506 
1507 	if (is_surface_linear(&fb->base, color_plane)) {
1508 		tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y);
1509 	} else {
1510 		tiles = plane_view_src_stride_tiles(fb, color_plane, dims) *
1511 			plane_view_height_tiles(fb, color_plane, dims, y);
1512 		/*
1513 		 * If the plane isn't horizontally tile aligned,
1514 		 * we need one more tile.
1515 		 */
1516 		if (x != 0)
1517 			tiles++;
1518 	}
1519 
1520 	return tiles;
1521 }
1522 
1523 static void intel_fb_view_init(struct drm_i915_private *i915, struct intel_fb_view *view,
1524 			       enum i915_gtt_view_type view_type)
1525 {
1526 	memset(view, 0, sizeof(*view));
1527 	view->gtt.type = view_type;
1528 
1529 	if (view_type == I915_GTT_VIEW_REMAPPED &&
1530 	    (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14))
1531 		view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE;
1532 }
1533 
1534 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb)
1535 {
1536 	if (DISPLAY_VER(to_i915(fb->base.dev)) >= 13)
1537 		return false;
1538 
1539 	return fb->base.modifier == I915_FORMAT_MOD_Y_TILED ||
1540 	       fb->base.modifier == I915_FORMAT_MOD_Yf_TILED;
1541 }
1542 
1543 static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb)
1544 {
1545 	struct drm_i915_private *i915 = to_i915(fb->dev);
1546 	struct intel_plane *plane;
1547 	unsigned int min_alignment = 0;
1548 
1549 	for_each_intel_plane(&i915->drm, plane) {
1550 		unsigned int plane_min_alignment;
1551 
1552 		if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier))
1553 			continue;
1554 
1555 		plane_min_alignment = plane->min_alignment(plane, fb, 0);
1556 
1557 		drm_WARN_ON(&i915->drm, plane_min_alignment &&
1558 			    !is_power_of_2(plane_min_alignment));
1559 
1560 		if (intel_plane_needs_physical(plane))
1561 			continue;
1562 
1563 		min_alignment = max(min_alignment, plane_min_alignment);
1564 	}
1565 
1566 	return min_alignment;
1567 }
1568 
1569 int intel_fill_fb_info(struct drm_i915_private *i915, struct intel_framebuffer *fb)
1570 {
1571 	struct drm_i915_gem_object *obj = intel_fb_obj(&fb->base);
1572 	u32 gtt_offset_rotated = 0;
1573 	u32 gtt_offset_remapped = 0;
1574 	unsigned int max_size = 0;
1575 	int i, num_planes = fb->base.format->num_planes;
1576 	unsigned int tile_size = intel_tile_size(i915);
1577 
1578 	intel_fb_view_init(i915, &fb->normal_view, I915_GTT_VIEW_NORMAL);
1579 
1580 	drm_WARN_ON(&i915->drm,
1581 		    intel_fb_supports_90_270_rotation(fb) &&
1582 		    intel_fb_needs_pot_stride_remap(fb));
1583 
1584 	if (intel_fb_supports_90_270_rotation(fb))
1585 		intel_fb_view_init(i915, &fb->rotated_view, I915_GTT_VIEW_ROTATED);
1586 	if (intel_fb_needs_pot_stride_remap(fb))
1587 		intel_fb_view_init(i915, &fb->remapped_view, I915_GTT_VIEW_REMAPPED);
1588 
1589 	for (i = 0; i < num_planes; i++) {
1590 		struct fb_plane_view_dims view_dims;
1591 		unsigned int width, height;
1592 		unsigned int size;
1593 		u32 offset;
1594 		int x, y;
1595 		int ret;
1596 
1597 		/*
1598 		 * Plane 2 of Render Compression with Clear Color fb modifier
1599 		 * is consumed by the driver and not passed to DE. Skip the
1600 		 * arithmetic related to alignment and offset calculation.
1601 		 */
1602 		if (is_gen12_ccs_cc_plane(&fb->base, i)) {
1603 			if (IS_ALIGNED(fb->base.offsets[i], PAGE_SIZE))
1604 				continue;
1605 			else
1606 				return -EINVAL;
1607 		}
1608 
1609 		intel_fb_plane_dims(fb, i, &width, &height);
1610 
1611 		ret = convert_plane_offset_to_xy(fb, i, width, &x, &y);
1612 		if (ret)
1613 			return ret;
1614 
1615 		init_plane_view_dims(fb, i, width, height, &view_dims);
1616 
1617 		/*
1618 		 * First pixel of the framebuffer from
1619 		 * the start of the normal gtt mapping.
1620 		 */
1621 		fb->normal_view.color_plane[i].x = x;
1622 		fb->normal_view.color_plane[i].y = y;
1623 		fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i];
1624 		fb->normal_view.color_plane[i].scanout_stride =
1625 			fb->normal_view.color_plane[i].mapping_stride;
1626 
1627 		offset = calc_plane_aligned_offset(fb, i, &x, &y);
1628 
1629 		if (intel_fb_supports_90_270_rotation(fb))
1630 			gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims,
1631 								    offset, gtt_offset_rotated, x, y,
1632 								    &fb->rotated_view);
1633 
1634 		if (intel_fb_needs_pot_stride_remap(fb))
1635 			gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims,
1636 								     offset, gtt_offset_remapped, x, y,
1637 								     &fb->remapped_view);
1638 
1639 		size = calc_plane_normal_size(fb, i, &view_dims, x, y);
1640 		/* how many tiles in total needed in the bo */
1641 		max_size = max(max_size, offset + size);
1642 	}
1643 
1644 	if (mul_u32_u32(max_size, tile_size) > intel_bo_to_drm_bo(obj)->size) {
1645 		drm_dbg_kms(&i915->drm,
1646 			    "fb too big for bo (need %llu bytes, have %zu bytes)\n",
1647 			    mul_u32_u32(max_size, tile_size), intel_bo_to_drm_bo(obj)->size);
1648 		return -EINVAL;
1649 	}
1650 
1651 	fb->min_alignment = intel_fb_min_alignment(&fb->base);
1652 
1653 	return 0;
1654 }
1655 
1656 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state)
1657 {
1658 	struct drm_i915_private *i915 =
1659 		to_i915(plane_state->uapi.plane->dev);
1660 	struct drm_framebuffer *fb = plane_state->hw.fb;
1661 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1662 	unsigned int rotation = plane_state->hw.rotation;
1663 	int i, num_planes = fb->format->num_planes;
1664 	unsigned int src_x, src_y;
1665 	unsigned int src_w, src_h;
1666 	u32 gtt_offset = 0;
1667 
1668 	intel_fb_view_init(i915, &plane_state->view,
1669 			   drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED :
1670 							      I915_GTT_VIEW_REMAPPED);
1671 
1672 	src_x = plane_state->uapi.src.x1 >> 16;
1673 	src_y = plane_state->uapi.src.y1 >> 16;
1674 	src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1675 	src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1676 
1677 	drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier));
1678 
1679 	/* Make src coordinates relative to the viewport */
1680 	drm_rect_translate(&plane_state->uapi.src,
1681 			   -(src_x << 16), -(src_y << 16));
1682 
1683 	/* Rotate src coordinates to match rotated GTT view */
1684 	if (drm_rotation_90_or_270(rotation))
1685 		drm_rect_rotate(&plane_state->uapi.src,
1686 				src_w << 16, src_h << 16,
1687 				DRM_MODE_ROTATE_270);
1688 
1689 	for (i = 0; i < num_planes; i++) {
1690 		unsigned int hsub = i ? fb->format->hsub : 1;
1691 		unsigned int vsub = i ? fb->format->vsub : 1;
1692 		struct fb_plane_view_dims view_dims;
1693 		unsigned int width, height;
1694 		unsigned int x, y;
1695 		u32 offset;
1696 
1697 		x = src_x / hsub;
1698 		y = src_y / vsub;
1699 		width = src_w / hsub;
1700 		height = src_h / vsub;
1701 
1702 		init_plane_view_dims(intel_fb, i, width, height, &view_dims);
1703 
1704 		/*
1705 		 * First pixel of the src viewport from the
1706 		 * start of the normal gtt mapping.
1707 		 */
1708 		x += intel_fb->normal_view.color_plane[i].x;
1709 		y += intel_fb->normal_view.color_plane[i].y;
1710 
1711 		offset = calc_plane_aligned_offset(intel_fb, i, &x, &y);
1712 
1713 		gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims,
1714 						    offset, gtt_offset, x, y,
1715 						    &plane_state->view);
1716 	}
1717 }
1718 
1719 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation,
1720 			struct intel_fb_view *view)
1721 {
1722 	if (drm_rotation_90_or_270(rotation))
1723 		*view = fb->rotated_view;
1724 	else if (intel_fb_needs_pot_stride_remap(fb))
1725 		*view = fb->remapped_view;
1726 	else
1727 		*view = fb->normal_view;
1728 }
1729 
1730 static
1731 u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
1732 			u32 pixel_format, u64 modifier)
1733 {
1734 	/*
1735 	 * Arbitrary limit for gen4+ chosen to match the
1736 	 * render engine max stride.
1737 	 *
1738 	 * The new CCS hash mode makes remapping impossible
1739 	 */
1740 	if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) ||
1741 	    intel_fb_modifier_uses_dpt(dev_priv, modifier))
1742 		return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
1743 	else if (DISPLAY_VER(dev_priv) >= 7)
1744 		return 256 * 1024;
1745 	else
1746 		return 128 * 1024;
1747 }
1748 
1749 static unsigned int
1750 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
1751 {
1752 	struct drm_i915_private *dev_priv = to_i915(fb->dev);
1753 	unsigned int tile_width;
1754 
1755 	if (is_surface_linear(fb, color_plane)) {
1756 		unsigned int max_stride = intel_plane_fb_max_stride(dev_priv,
1757 								    fb->format->format,
1758 								    fb->modifier);
1759 
1760 		/*
1761 		 * To make remapping with linear generally feasible
1762 		 * we need the stride to be page aligned.
1763 		 */
1764 		if (fb->pitches[color_plane] > max_stride &&
1765 		    !intel_fb_is_ccs_modifier(fb->modifier))
1766 			return intel_tile_size(dev_priv);
1767 		else
1768 			return 64;
1769 	}
1770 
1771 	tile_width = intel_tile_width_bytes(fb, color_plane);
1772 	if (intel_fb_is_ccs_modifier(fb->modifier)) {
1773 		/*
1774 		 * On TGL the surface stride must be 4 tile aligned, mapped by
1775 		 * one 64 byte cacheline on the CCS AUX surface.
1776 		 */
1777 		if (DISPLAY_VER(dev_priv) >= 12)
1778 			tile_width *= 4;
1779 		/*
1780 		 * Display WA #0531: skl,bxt,kbl,glk
1781 		 *
1782 		 * Render decompression and plane width > 3840
1783 		 * combined with horizontal panning requires the
1784 		 * plane stride to be a multiple of 4. We'll just
1785 		 * require the entire fb to accommodate that to avoid
1786 		 * potential runtime errors at plane configuration time.
1787 		 */
1788 		else if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) &&
1789 			 color_plane == 0 && fb->width > 3840)
1790 			tile_width *= 4;
1791 	}
1792 	return tile_width;
1793 }
1794 
1795 static int intel_plane_check_stride(const struct intel_plane_state *plane_state)
1796 {
1797 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1798 	const struct drm_framebuffer *fb = plane_state->hw.fb;
1799 	unsigned int rotation = plane_state->hw.rotation;
1800 	u32 stride, max_stride;
1801 
1802 	/*
1803 	 * We ignore stride for all invisible planes that
1804 	 * can be remapped. Otherwise we could end up
1805 	 * with a false positive when the remapping didn't
1806 	 * kick in due the plane being invisible.
1807 	 */
1808 	if (intel_plane_can_remap(plane_state) &&
1809 	    !plane_state->uapi.visible)
1810 		return 0;
1811 
1812 	/* FIXME other color planes? */
1813 	stride = plane_state->view.color_plane[0].mapping_stride;
1814 	max_stride = plane->max_stride(plane, fb->format->format,
1815 				       fb->modifier, rotation);
1816 
1817 	if (stride > max_stride) {
1818 		drm_dbg_kms(plane->base.dev,
1819 			    "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
1820 			    fb->base.id, stride,
1821 			    plane->base.base.id, plane->base.name, max_stride);
1822 		return -EINVAL;
1823 	}
1824 
1825 	return 0;
1826 }
1827 
1828 int intel_plane_compute_gtt(struct intel_plane_state *plane_state)
1829 {
1830 	const struct intel_framebuffer *fb =
1831 		to_intel_framebuffer(plane_state->hw.fb);
1832 	unsigned int rotation = plane_state->hw.rotation;
1833 
1834 	if (!fb)
1835 		return 0;
1836 
1837 	if (intel_plane_needs_remap(plane_state)) {
1838 		intel_plane_remap_gtt(plane_state);
1839 
1840 		/*
1841 		 * Sometimes even remapping can't overcome
1842 		 * the stride limitations :( Can happen with
1843 		 * big plane sizes and suitably misaligned
1844 		 * offsets.
1845 		 */
1846 		return intel_plane_check_stride(plane_state);
1847 	}
1848 
1849 	intel_fb_fill_view(fb, rotation, &plane_state->view);
1850 
1851 	/* Rotate src coordinates to match rotated GTT view */
1852 	if (drm_rotation_90_or_270(rotation))
1853 		drm_rect_rotate(&plane_state->uapi.src,
1854 				fb->base.width << 16, fb->base.height << 16,
1855 				DRM_MODE_ROTATE_270);
1856 
1857 	return intel_plane_check_stride(plane_state);
1858 }
1859 
1860 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
1861 {
1862 	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1863 
1864 	drm_framebuffer_cleanup(fb);
1865 
1866 	if (intel_fb_uses_dpt(fb))
1867 		intel_dpt_destroy(intel_fb->dpt_vm);
1868 
1869 	intel_frontbuffer_put(intel_fb->frontbuffer);
1870 
1871 	intel_fb_bo_framebuffer_fini(intel_fb_obj(fb));
1872 
1873 	kfree(intel_fb);
1874 }
1875 
1876 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1877 						struct drm_file *file,
1878 						unsigned int *handle)
1879 {
1880 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1881 	struct drm_i915_private *i915 = to_i915(intel_bo_to_drm_bo(obj)->dev);
1882 
1883 	if (i915_gem_object_is_userptr(obj)) {
1884 		drm_dbg(&i915->drm,
1885 			"attempting to use a userptr for a framebuffer, denied\n");
1886 		return -EINVAL;
1887 	}
1888 
1889 	return drm_gem_handle_create(file, intel_bo_to_drm_bo(obj), handle);
1890 }
1891 
1892 struct frontbuffer_fence_cb {
1893 	struct dma_fence_cb base;
1894 	struct intel_frontbuffer *front;
1895 };
1896 
1897 static void intel_user_framebuffer_fence_wake(struct dma_fence *dma,
1898 					      struct dma_fence_cb *data)
1899 {
1900 	struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base);
1901 
1902 	intel_frontbuffer_queue_flush(cb->front);
1903 	kfree(cb);
1904 	dma_fence_put(dma);
1905 }
1906 
1907 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
1908 					struct drm_file *file,
1909 					unsigned int flags, unsigned int color,
1910 					struct drm_clip_rect *clips,
1911 					unsigned int num_clips)
1912 {
1913 	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1914 	struct intel_frontbuffer *front = to_intel_frontbuffer(fb);
1915 	struct dma_fence *fence;
1916 	struct frontbuffer_fence_cb *cb;
1917 	int ret = 0;
1918 
1919 	if (!atomic_read(&front->bits))
1920 		return 0;
1921 
1922 	if (dma_resv_test_signaled(intel_bo_to_drm_bo(obj)->resv, dma_resv_usage_rw(false)))
1923 		goto flush;
1924 
1925 	ret = dma_resv_get_singleton(intel_bo_to_drm_bo(obj)->resv, dma_resv_usage_rw(false),
1926 				     &fence);
1927 	if (ret || !fence)
1928 		goto flush;
1929 
1930 	cb = kmalloc(sizeof(*cb), GFP_KERNEL);
1931 	if (!cb) {
1932 		dma_fence_put(fence);
1933 		ret = -ENOMEM;
1934 		goto flush;
1935 	}
1936 
1937 	cb->front = front;
1938 
1939 	intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB);
1940 
1941 	ret = dma_fence_add_callback(fence, &cb->base,
1942 				     intel_user_framebuffer_fence_wake);
1943 	if (ret) {
1944 		intel_user_framebuffer_fence_wake(fence, &cb->base);
1945 		if (ret == -ENOENT)
1946 			ret = 0;
1947 	}
1948 
1949 	return ret;
1950 
1951 flush:
1952 	i915_gem_object_flush_if_display(obj);
1953 	intel_frontbuffer_flush(front, ORIGIN_DIRTYFB);
1954 	return ret;
1955 }
1956 
1957 static const struct drm_framebuffer_funcs intel_fb_funcs = {
1958 	.destroy = intel_user_framebuffer_destroy,
1959 	.create_handle = intel_user_framebuffer_create_handle,
1960 	.dirty = intel_user_framebuffer_dirty,
1961 };
1962 
1963 int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
1964 			   struct drm_i915_gem_object *obj,
1965 			   struct drm_mode_fb_cmd2 *mode_cmd)
1966 {
1967 	struct drm_i915_private *dev_priv = to_i915(intel_bo_to_drm_bo(obj)->dev);
1968 	struct drm_framebuffer *fb = &intel_fb->base;
1969 	u32 max_stride;
1970 	int ret = -EINVAL;
1971 	int i;
1972 
1973 	ret = intel_fb_bo_framebuffer_init(intel_fb, obj, mode_cmd);
1974 	if (ret)
1975 		return ret;
1976 
1977 	intel_fb->frontbuffer = intel_frontbuffer_get(obj);
1978 	if (!intel_fb->frontbuffer) {
1979 		ret = -ENOMEM;
1980 		goto err;
1981 	}
1982 
1983 	ret = -EINVAL;
1984 	if (!drm_any_plane_has_format(&dev_priv->drm,
1985 				      mode_cmd->pixel_format,
1986 				      mode_cmd->modifier[0])) {
1987 		drm_dbg_kms(&dev_priv->drm,
1988 			    "unsupported pixel format %p4cc / modifier 0x%llx\n",
1989 			    &mode_cmd->pixel_format, mode_cmd->modifier[0]);
1990 		goto err_frontbuffer_put;
1991 	}
1992 
1993 	max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format,
1994 					 mode_cmd->modifier[0]);
1995 	if (mode_cmd->pitches[0] > max_stride) {
1996 		drm_dbg_kms(&dev_priv->drm,
1997 			    "%s pitch (%u) must be at most %d\n",
1998 			    mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
1999 			    "tiled" : "linear",
2000 			    mode_cmd->pitches[0], max_stride);
2001 		goto err_frontbuffer_put;
2002 	}
2003 
2004 	/* FIXME need to adjust LINOFF/TILEOFF accordingly. */
2005 	if (mode_cmd->offsets[0] != 0) {
2006 		drm_dbg_kms(&dev_priv->drm,
2007 			    "plane 0 offset (0x%08x) must be 0\n",
2008 			    mode_cmd->offsets[0]);
2009 		goto err_frontbuffer_put;
2010 	}
2011 
2012 	drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd);
2013 
2014 	for (i = 0; i < fb->format->num_planes; i++) {
2015 		unsigned int stride_alignment;
2016 
2017 		if (mode_cmd->handles[i] != mode_cmd->handles[0]) {
2018 			drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",
2019 				    i);
2020 			goto err_frontbuffer_put;
2021 		}
2022 
2023 		stride_alignment = intel_fb_stride_alignment(fb, i);
2024 		if (fb->pitches[i] & (stride_alignment - 1)) {
2025 			drm_dbg_kms(&dev_priv->drm,
2026 				    "plane %d pitch (%d) must be at least %u byte aligned\n",
2027 				    i, fb->pitches[i], stride_alignment);
2028 			goto err_frontbuffer_put;
2029 		}
2030 
2031 		if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) {
2032 			unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i);
2033 
2034 			if (fb->pitches[i] != ccs_aux_stride) {
2035 				drm_dbg_kms(&dev_priv->drm,
2036 					    "ccs aux plane %d pitch (%d) must be %d\n",
2037 					    i,
2038 					    fb->pitches[i], ccs_aux_stride);
2039 				goto err_frontbuffer_put;
2040 			}
2041 		}
2042 
2043 		fb->obj[i] = intel_bo_to_drm_bo(obj);
2044 	}
2045 
2046 	ret = intel_fill_fb_info(dev_priv, intel_fb);
2047 	if (ret)
2048 		goto err_frontbuffer_put;
2049 
2050 	if (intel_fb_uses_dpt(fb)) {
2051 		struct i915_address_space *vm;
2052 
2053 		vm = intel_dpt_create(intel_fb);
2054 		if (IS_ERR(vm)) {
2055 			drm_dbg_kms(&dev_priv->drm, "failed to create DPT\n");
2056 			ret = PTR_ERR(vm);
2057 			goto err_frontbuffer_put;
2058 		}
2059 
2060 		intel_fb->dpt_vm = vm;
2061 	}
2062 
2063 	ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs);
2064 	if (ret) {
2065 		drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret);
2066 		goto err_free_dpt;
2067 	}
2068 
2069 	return 0;
2070 
2071 err_free_dpt:
2072 	if (intel_fb_uses_dpt(fb))
2073 		intel_dpt_destroy(intel_fb->dpt_vm);
2074 err_frontbuffer_put:
2075 	intel_frontbuffer_put(intel_fb->frontbuffer);
2076 err:
2077 	intel_fb_bo_framebuffer_fini(obj);
2078 	return ret;
2079 }
2080 
2081 struct drm_framebuffer *
2082 intel_user_framebuffer_create(struct drm_device *dev,
2083 			      struct drm_file *filp,
2084 			      const struct drm_mode_fb_cmd2 *user_mode_cmd)
2085 {
2086 	struct drm_framebuffer *fb;
2087 	struct drm_i915_gem_object *obj;
2088 	struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
2089 	struct drm_i915_private *i915 = to_i915(dev);
2090 
2091 	obj = intel_fb_bo_lookup_valid_bo(i915, filp, &mode_cmd);
2092 	if (IS_ERR(obj))
2093 		return ERR_CAST(obj);
2094 
2095 	fb = intel_framebuffer_create(obj, &mode_cmd);
2096 	drm_gem_object_put(intel_bo_to_drm_bo(obj));
2097 
2098 	return fb;
2099 }
2100 
2101 struct drm_framebuffer *
2102 intel_framebuffer_create(struct drm_i915_gem_object *obj,
2103 			 struct drm_mode_fb_cmd2 *mode_cmd)
2104 {
2105 	struct intel_framebuffer *intel_fb;
2106 	int ret;
2107 
2108 	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2109 	if (!intel_fb)
2110 		return ERR_PTR(-ENOMEM);
2111 
2112 	ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
2113 	if (ret)
2114 		goto err;
2115 
2116 	return &intel_fb->base;
2117 
2118 err:
2119 	kfree(intel_fb);
2120 	return ERR_PTR(ret);
2121 }
2122