1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include <linux/dma-fence.h> 7 #include <linux/dma-resv.h> 8 9 #include <drm/drm_blend.h> 10 #include <drm/drm_gem.h> 11 #include <drm/drm_modeset_helper.h> 12 13 #include "i915_drv.h" 14 #include "intel_bo.h" 15 #include "intel_display.h" 16 #include "intel_display_core.h" 17 #include "intel_display_types.h" 18 #include "intel_dpt.h" 19 #include "intel_fb.h" 20 #include "intel_fb_bo.h" 21 #include "intel_frontbuffer.h" 22 #include "intel_plane.h" 23 24 #define check_array_bounds(display, a, i) drm_WARN_ON((display)->drm, (i) >= ARRAY_SIZE(a)) 25 26 /* 27 * From the Sky Lake PRM: 28 * "The Color Control Surface (CCS) contains the compression status of 29 * the cache-line pairs. The compression state of the cache-line pair 30 * is specified by 2 bits in the CCS. Each CCS cache-line represents 31 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled 32 * cache-line-pairs. CCS is always Y tiled." 33 * 34 * Since cache line pairs refers to horizontally adjacent cache lines, 35 * each cache line in the CCS corresponds to an area of 32x16 cache 36 * lines on the main surface. Since each pixel is 4 bytes, this gives 37 * us a ratio of one byte in the CCS for each 8x16 pixels in the 38 * main surface. 39 */ 40 static const struct drm_format_info skl_ccs_formats[] = { 41 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 42 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 43 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 44 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 45 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 46 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 47 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 48 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 49 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 50 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 51 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 52 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, 53 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 54 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 55 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 56 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, 57 }; 58 59 /* 60 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the 61 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles 62 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of 63 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in 64 * the main surface. 65 */ 66 static const struct drm_format_info gen12_ccs_formats[] = { 67 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 68 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 69 .hsub = 1, .vsub = 1, }, 70 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 71 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 72 .hsub = 1, .vsub = 1, }, 73 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 74 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 75 .hsub = 1, .vsub = 1, .has_alpha = true }, 76 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 77 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 78 .hsub = 1, .vsub = 1, .has_alpha = true }, 79 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 80 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 81 .hsub = 1, .vsub = 1, }, 82 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 83 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 84 .hsub = 1, .vsub = 1, }, 85 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 86 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 87 .hsub = 1, .vsub = 1, .has_alpha = true }, 88 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 89 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 90 .hsub = 1, .vsub = 1, .has_alpha = true }, 91 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 92 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 93 .hsub = 1, .vsub = 1, }, 94 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 95 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 96 .hsub = 1, .vsub = 1, }, 97 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 98 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 99 .hsub = 1, .vsub = 1, .has_alpha = true }, 100 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 101 .char_per_block = { 8, 1 }, .block_w = { 1, 1 }, .block_h = { 1, 1 }, 102 .hsub = 1, .vsub = 1, .has_alpha = true }, 103 { .format = DRM_FORMAT_YUYV, .num_planes = 2, 104 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 105 .hsub = 2, .vsub = 1, .is_yuv = true }, 106 { .format = DRM_FORMAT_YVYU, .num_planes = 2, 107 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 108 .hsub = 2, .vsub = 1, .is_yuv = true }, 109 { .format = DRM_FORMAT_UYVY, .num_planes = 2, 110 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 111 .hsub = 2, .vsub = 1, .is_yuv = true }, 112 { .format = DRM_FORMAT_VYUY, .num_planes = 2, 113 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 114 .hsub = 2, .vsub = 1, .is_yuv = true }, 115 { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, 116 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, 117 .hsub = 1, .vsub = 1, .is_yuv = true }, 118 { .format = DRM_FORMAT_NV12, .num_planes = 4, 119 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, 120 .hsub = 2, .vsub = 2, .is_yuv = true }, 121 { .format = DRM_FORMAT_P010, .num_planes = 4, 122 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 123 .hsub = 2, .vsub = 2, .is_yuv = true }, 124 { .format = DRM_FORMAT_P012, .num_planes = 4, 125 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 126 .hsub = 2, .vsub = 2, .is_yuv = true }, 127 { .format = DRM_FORMAT_P016, .num_planes = 4, 128 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, 129 .hsub = 2, .vsub = 2, .is_yuv = true }, 130 }; 131 132 /* 133 * Same as gen12_ccs_formats[] above, but with additional surface used 134 * to pass Clear Color information in plane 2 with 64 bits of data. 135 */ 136 static const struct drm_format_info gen12_ccs_cc_formats[] = { 137 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, 138 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 139 .hsub = 1, .vsub = 1, }, 140 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, 141 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 142 .hsub = 1, .vsub = 1, }, 143 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, 144 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 145 .hsub = 1, .vsub = 1, .has_alpha = true }, 146 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, 147 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 148 .hsub = 1, .vsub = 1, .has_alpha = true }, 149 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 3, 150 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 151 .hsub = 1, .vsub = 1, }, 152 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 3, 153 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 154 .hsub = 1, .vsub = 1, }, 155 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 3, 156 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 157 .hsub = 1, .vsub = 1, .has_alpha = true }, 158 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 3, 159 .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 0 }, .block_h = { 1, 1, 0 }, 160 .hsub = 1, .vsub = 1, .has_alpha = true }, 161 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 3, 162 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 163 .hsub = 1, .vsub = 1, }, 164 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 3, 165 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 166 .hsub = 1, .vsub = 1, }, 167 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 3, 168 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 169 .hsub = 1, .vsub = 1, .has_alpha = true }, 170 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 3, 171 .char_per_block = { 8, 1, 0 }, .block_w = { 1, 1, 0 }, .block_h = { 1, 1, 0 }, 172 .hsub = 1, .vsub = 1, .has_alpha = true }, 173 }; 174 175 static const struct drm_format_info gen12_flat_ccs_cc_formats[] = { 176 { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, 177 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 178 .hsub = 1, .vsub = 1, }, 179 { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, 180 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 181 .hsub = 1, .vsub = 1, }, 182 { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, 183 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 184 .hsub = 1, .vsub = 1, .has_alpha = true }, 185 { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, 186 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 187 .hsub = 1, .vsub = 1, .has_alpha = true }, 188 { .format = DRM_FORMAT_XRGB2101010, .depth = 30, .num_planes = 2, 189 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 190 .hsub = 1, .vsub = 1, }, 191 { .format = DRM_FORMAT_XBGR2101010, .depth = 30, .num_planes = 2, 192 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 193 .hsub = 1, .vsub = 1, }, 194 { .format = DRM_FORMAT_ARGB2101010, .depth = 30, .num_planes = 2, 195 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 196 .hsub = 1, .vsub = 1, .has_alpha = true }, 197 { .format = DRM_FORMAT_ABGR2101010, .depth = 30, .num_planes = 2, 198 .char_per_block = { 4, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 199 .hsub = 1, .vsub = 1, .has_alpha = true }, 200 { .format = DRM_FORMAT_XRGB16161616F, .depth = 0, .num_planes = 2, 201 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 202 .hsub = 1, .vsub = 1, }, 203 { .format = DRM_FORMAT_XBGR16161616F, .depth = 0, .num_planes = 2, 204 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 205 .hsub = 1, .vsub = 1, }, 206 { .format = DRM_FORMAT_ARGB16161616F, .depth = 0, .num_planes = 2, 207 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 208 .hsub = 1, .vsub = 1, .has_alpha = true }, 209 { .format = DRM_FORMAT_ABGR16161616F, .depth = 0, .num_planes = 2, 210 .char_per_block = { 8, 0 }, .block_w = { 1, 0 }, .block_h = { 1, 0 }, 211 .hsub = 1, .vsub = 1, .has_alpha = true }, 212 }; 213 214 struct intel_modifier_desc { 215 u64 modifier; 216 struct { 217 u8 from; 218 u8 until; 219 } display_ver; 220 #define DISPLAY_VER_ALL { 0, -1 } 221 222 const struct drm_format_info *formats; 223 int format_count; 224 #define FORMAT_OVERRIDE(format_list) \ 225 .formats = format_list, \ 226 .format_count = ARRAY_SIZE(format_list) 227 228 u8 plane_caps; 229 230 struct { 231 u8 cc_planes:3; 232 u8 packed_aux_planes:4; 233 u8 planar_aux_planes:4; 234 } ccs; 235 }; 236 237 #define INTEL_PLANE_CAP_CCS_MASK (INTEL_PLANE_CAP_CCS_RC | \ 238 INTEL_PLANE_CAP_CCS_RC_CC | \ 239 INTEL_PLANE_CAP_CCS_MC) 240 #define INTEL_PLANE_CAP_TILING_MASK (INTEL_PLANE_CAP_TILING_X | \ 241 INTEL_PLANE_CAP_TILING_Y | \ 242 INTEL_PLANE_CAP_TILING_Yf | \ 243 INTEL_PLANE_CAP_TILING_4) 244 #define INTEL_PLANE_CAP_TILING_NONE 0 245 246 static const struct intel_modifier_desc intel_modifiers[] = { 247 { 248 .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS, 249 .display_ver = { 20, -1 }, 250 .plane_caps = INTEL_PLANE_CAP_TILING_4, 251 }, { 252 .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS, 253 .display_ver = { 14, -1 }, 254 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS, 255 }, { 256 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, 257 .display_ver = { 14, 14 }, 258 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 259 260 .ccs.packed_aux_planes = BIT(1), 261 .ccs.planar_aux_planes = BIT(2) | BIT(3), 262 263 FORMAT_OVERRIDE(gen12_ccs_formats), 264 }, { 265 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, 266 .display_ver = { 14, 14 }, 267 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 268 269 .ccs.packed_aux_planes = BIT(1), 270 271 FORMAT_OVERRIDE(gen12_ccs_formats), 272 }, { 273 .modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC, 274 .display_ver = { 14, 14 }, 275 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 276 277 .ccs.cc_planes = BIT(2), 278 .ccs.packed_aux_planes = BIT(1), 279 280 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 281 }, { 282 .modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS, 283 .display_ver = { 13, 13 }, 284 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, 285 }, { 286 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC, 287 .display_ver = { 13, 13 }, 288 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC, 289 290 .ccs.cc_planes = BIT(1), 291 292 FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats), 293 }, { 294 .modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS, 295 .display_ver = { 13, 13 }, 296 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC, 297 }, { 298 .modifier = I915_FORMAT_MOD_4_TILED, 299 .display_ver = { 13, -1 }, 300 .plane_caps = INTEL_PLANE_CAP_TILING_4, 301 }, { 302 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 303 .display_ver = { 12, 13 }, 304 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC, 305 306 .ccs.packed_aux_planes = BIT(1), 307 .ccs.planar_aux_planes = BIT(2) | BIT(3), 308 309 FORMAT_OVERRIDE(gen12_ccs_formats), 310 }, { 311 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 312 .display_ver = { 12, 13 }, 313 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 314 315 .ccs.packed_aux_planes = BIT(1), 316 317 FORMAT_OVERRIDE(gen12_ccs_formats), 318 }, { 319 .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, 320 .display_ver = { 12, 13 }, 321 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC_CC, 322 323 .ccs.cc_planes = BIT(2), 324 .ccs.packed_aux_planes = BIT(1), 325 326 FORMAT_OVERRIDE(gen12_ccs_cc_formats), 327 }, { 328 .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, 329 .display_ver = { 9, 11 }, 330 .plane_caps = INTEL_PLANE_CAP_TILING_Yf | INTEL_PLANE_CAP_CCS_RC, 331 332 .ccs.packed_aux_planes = BIT(1), 333 334 FORMAT_OVERRIDE(skl_ccs_formats), 335 }, { 336 .modifier = I915_FORMAT_MOD_Y_TILED_CCS, 337 .display_ver = { 9, 11 }, 338 .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_RC, 339 340 .ccs.packed_aux_planes = BIT(1), 341 342 FORMAT_OVERRIDE(skl_ccs_formats), 343 }, { 344 .modifier = I915_FORMAT_MOD_Yf_TILED, 345 .display_ver = { 9, 11 }, 346 .plane_caps = INTEL_PLANE_CAP_TILING_Yf, 347 }, { 348 .modifier = I915_FORMAT_MOD_Y_TILED, 349 .display_ver = { 9, 13 }, 350 .plane_caps = INTEL_PLANE_CAP_TILING_Y, 351 }, { 352 .modifier = I915_FORMAT_MOD_X_TILED, 353 .display_ver = { 0, 29 }, 354 .plane_caps = INTEL_PLANE_CAP_TILING_X, 355 }, { 356 .modifier = DRM_FORMAT_MOD_LINEAR, 357 .display_ver = DISPLAY_VER_ALL, 358 }, 359 }; 360 361 static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) 362 { 363 int i; 364 365 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) 366 if (intel_modifiers[i].modifier == modifier) 367 return &intel_modifiers[i]; 368 369 return NULL; 370 } 371 372 static const struct intel_modifier_desc *lookup_modifier(u64 modifier) 373 { 374 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 375 376 if (WARN_ON(!md)) 377 return &intel_modifiers[0]; 378 379 return md; 380 } 381 382 static const struct drm_format_info * 383 lookup_format_info(const struct drm_format_info formats[], 384 int num_formats, u32 format) 385 { 386 int i; 387 388 for (i = 0; i < num_formats; i++) { 389 if (formats[i].format == format) 390 return &formats[i]; 391 } 392 393 return NULL; 394 } 395 396 unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) 397 { 398 const struct intel_modifier_desc *md; 399 u8 tiling_caps; 400 401 md = lookup_modifier_or_null(fb_modifier); 402 if (!md) 403 return I915_TILING_NONE; 404 405 tiling_caps = lookup_modifier_or_null(fb_modifier)->plane_caps & 406 INTEL_PLANE_CAP_TILING_MASK; 407 408 switch (tiling_caps) { 409 case INTEL_PLANE_CAP_TILING_Y: 410 return I915_TILING_Y; 411 case INTEL_PLANE_CAP_TILING_X: 412 return I915_TILING_X; 413 case INTEL_PLANE_CAP_TILING_4: 414 case INTEL_PLANE_CAP_TILING_Yf: 415 case INTEL_PLANE_CAP_TILING_NONE: 416 return I915_TILING_NONE; 417 default: 418 MISSING_CASE(tiling_caps); 419 return I915_TILING_NONE; 420 } 421 } 422 423 /** 424 * intel_fb_get_format_info: Get a modifier specific format information 425 * @pixel_format: pixel format 426 * @modifier: modifier 427 * 428 * Returns: 429 * Returns the format information for @pixel_format specific to @modifier, 430 * or %NULL if the modifier doesn't override the format. 431 */ 432 const struct drm_format_info * 433 intel_fb_get_format_info(u32 pixel_format, u64 modifier) 434 { 435 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 436 437 if (!md || !md->formats) 438 return NULL; 439 440 return lookup_format_info(md->formats, md->format_count, pixel_format); 441 } 442 443 static bool plane_caps_contain_any(u8 caps, u8 mask) 444 { 445 return caps & mask; 446 } 447 448 static bool plane_caps_contain_all(u8 caps, u8 mask) 449 { 450 return (caps & mask) == mask; 451 } 452 453 /** 454 * intel_fb_is_tiled_modifier: Check if a modifier is a tiled modifier type 455 * @modifier: Modifier to check 456 * 457 * Returns: 458 * Returns %true if @modifier is a tiled modifier. 459 */ 460 bool intel_fb_is_tiled_modifier(u64 modifier) 461 { 462 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 463 INTEL_PLANE_CAP_TILING_MASK); 464 } 465 466 /** 467 * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type 468 * @modifier: Modifier to check 469 * 470 * Returns: 471 * Returns %true if @modifier is a render, render with color clear or 472 * media compression modifier. 473 */ 474 bool intel_fb_is_ccs_modifier(u64 modifier) 475 { 476 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 477 INTEL_PLANE_CAP_CCS_MASK); 478 } 479 480 /** 481 * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type 482 * @modifier: Modifier to check 483 * 484 * Returns: 485 * Returns %true if @modifier is a render with color clear modifier. 486 */ 487 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) 488 { 489 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 490 INTEL_PLANE_CAP_CCS_RC_CC); 491 } 492 493 /** 494 * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type 495 * @modifier: Modifier to check 496 * 497 * Returns: 498 * Returns %true if @modifier is a media compression modifier. 499 */ 500 bool intel_fb_is_mc_ccs_modifier(u64 modifier) 501 { 502 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 503 INTEL_PLANE_CAP_CCS_MC); 504 } 505 506 /** 507 * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement. 508 * @modifier: Modifier to check 509 * 510 * Returns: 511 * Returns %true if @modifier requires 64k aligned physical pages. 512 */ 513 bool intel_fb_needs_64k_phys(u64 modifier) 514 { 515 const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 516 517 if (!md) 518 return false; 519 520 return plane_caps_contain_any(md->plane_caps, 521 INTEL_PLANE_CAP_NEED64K_PHYS); 522 } 523 524 /** 525 * intel_fb_is_tile4_modifier: Check if a modifier is a tile4 modifier type 526 * @modifier: Modifier to check 527 * 528 * Returns: 529 * Returns %true if @modifier is a tile4 modifier. 530 */ 531 bool intel_fb_is_tile4_modifier(u64 modifier) 532 { 533 return plane_caps_contain_any(lookup_modifier(modifier)->plane_caps, 534 INTEL_PLANE_CAP_TILING_4); 535 } 536 537 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, 538 u8 display_ver_from, u8 display_ver_until) 539 { 540 return md->display_ver.from <= display_ver_until && 541 display_ver_from <= md->display_ver.until; 542 } 543 544 static bool plane_has_modifier(struct intel_display *display, 545 u8 plane_caps, 546 const struct intel_modifier_desc *md) 547 { 548 struct drm_i915_private *i915 = to_i915(display->drm); 549 550 if (!IS_DISPLAY_VER(display, md->display_ver.from, md->display_ver.until)) 551 return false; 552 553 if (!plane_caps_contain_all(plane_caps, md->plane_caps)) 554 return false; 555 556 /* 557 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms 558 * where supported. 559 */ 560 if (intel_fb_is_ccs_modifier(md->modifier) && 561 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) 562 return false; 563 564 if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && 565 (GRAPHICS_VER(i915) < 20 || !display->platform.dgfx)) 566 return false; 567 568 if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS && 569 (GRAPHICS_VER(i915) < 20 || display->platform.dgfx)) 570 return false; 571 572 return true; 573 } 574 575 /** 576 * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities 577 * @display: display instance 578 * @plane_caps: capabilities for the plane the modifiers are queried for 579 * 580 * Returns: 581 * Returns the list of modifiers allowed by the @display platform and @plane_caps. 582 * The caller must free the returned buffer. 583 */ 584 u64 *intel_fb_plane_get_modifiers(struct intel_display *display, 585 u8 plane_caps) 586 { 587 u64 *list, *p; 588 int count = 1; /* +1 for invalid modifier terminator */ 589 int i; 590 591 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 592 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 593 count++; 594 } 595 596 list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); 597 if (drm_WARN_ON(display->drm, !list)) 598 return NULL; 599 600 p = list; 601 for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { 602 if (plane_has_modifier(display, plane_caps, &intel_modifiers[i])) 603 *p++ = intel_modifiers[i].modifier; 604 } 605 *p++ = DRM_FORMAT_MOD_INVALID; 606 607 return list; 608 } 609 610 /** 611 * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane 612 * @plane: Plane to check the modifier support for 613 * @modifier: The modifier to check the support for 614 * 615 * Returns: 616 * %true if the @modifier is supported on @plane. 617 */ 618 bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) 619 { 620 int i; 621 622 for (i = 0; i < plane->base.modifier_count; i++) 623 if (plane->base.modifiers[i] == modifier) 624 return true; 625 626 return false; 627 } 628 629 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, 630 const struct drm_format_info *info) 631 { 632 if (!info->is_yuv) 633 return false; 634 635 if (hweight8(md->ccs.planar_aux_planes) == 2) 636 return info->num_planes == 4; 637 else 638 return info->num_planes == 2; 639 } 640 641 /** 642 * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar 643 * @info: format to check 644 * @modifier: modifier used with the format 645 * 646 * Returns: 647 * %true if @info / @modifier is YUV semiplanar. 648 */ 649 bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, 650 u64 modifier) 651 { 652 return format_is_yuv_semiplanar(lookup_modifier(modifier), info); 653 } 654 655 static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, 656 const struct drm_format_info *format) 657 { 658 if (format_is_yuv_semiplanar(md, format)) 659 return md->ccs.planar_aux_planes; 660 else 661 return md->ccs.packed_aux_planes; 662 } 663 664 /** 665 * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane 666 * @fb: Framebuffer 667 * @color_plane: color plane index to check 668 * 669 * Returns: 670 * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. 671 */ 672 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 673 { 674 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 675 676 return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 677 } 678 679 /** 680 * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane 681 * @fb: Framebuffer 682 * @color_plane: color plane index to check 683 * 684 * Returns: 685 * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. 686 */ 687 static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) 688 { 689 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 690 691 return check_modifier_display_ver_range(md, 12, 14) && 692 ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); 693 } 694 695 /** 696 * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer 697 * @fb: Framebuffer 698 * 699 * Returns: 700 * Returns the index of the color clear plane for @fb, or -1 if @fb is not a 701 * framebuffer using a render compression/color clear modifier. 702 */ 703 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) 704 { 705 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 706 707 if (!md->ccs.cc_planes) 708 return -1; 709 710 drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1); 711 712 return ilog2((int)md->ccs.cc_planes); 713 } 714 715 static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) 716 { 717 return intel_fb_rc_ccs_cc_plane(fb) == color_plane; 718 } 719 720 bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) 721 { 722 return fb->modifier == DRM_FORMAT_MOD_LINEAR || 723 intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || 724 is_gen12_ccs_cc_plane(fb, color_plane); 725 } 726 727 int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) 728 { 729 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 730 (main_plane && main_plane >= fb->format->num_planes / 2)); 731 732 return fb->format->num_planes / 2 + main_plane; 733 } 734 735 int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) 736 { 737 drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || 738 ccs_plane < fb->format->num_planes / 2); 739 740 if (is_gen12_ccs_cc_plane(fb, ccs_plane)) 741 return 0; 742 743 return ccs_plane - fb->format->num_planes / 2; 744 } 745 746 static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_plane) 747 { 748 int main_plane = skl_ccs_to_main_plane(&fb->base, ccs_plane); 749 unsigned int main_stride = fb->base.pitches[main_plane]; 750 unsigned int main_tile_width = intel_tile_width_bytes(&fb->base, main_plane); 751 752 return DIV_ROUND_UP(main_stride, 4 * main_tile_width) * 64; 753 } 754 755 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) 756 { 757 const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); 758 struct intel_display *display = to_intel_display(fb->dev); 759 760 if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes) 761 return main_to_ccs_plane(fb, main_plane); 762 else if (DISPLAY_VER(display) < 11 && 763 format_is_yuv_semiplanar(md, fb->format)) 764 return 1; 765 else 766 return 0; 767 } 768 769 unsigned int intel_tile_size(struct intel_display *display) 770 { 771 return DISPLAY_VER(display) == 2 ? 2048 : 4096; 772 } 773 774 unsigned int 775 intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) 776 { 777 struct intel_display *display = to_intel_display(fb->dev); 778 struct drm_i915_private *i915 = to_i915(display->drm); 779 unsigned int cpp = fb->format->cpp[color_plane]; 780 781 switch (fb->modifier) { 782 case DRM_FORMAT_MOD_LINEAR: 783 return intel_tile_size(display); 784 case I915_FORMAT_MOD_X_TILED: 785 if (DISPLAY_VER(display) == 2) 786 return 128; 787 else 788 return 512; 789 case I915_FORMAT_MOD_4_TILED_BMG_CCS: 790 case I915_FORMAT_MOD_4_TILED_LNL_CCS: 791 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 792 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 793 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 794 case I915_FORMAT_MOD_4_TILED: 795 /* 796 * Each 4K tile consists of 64B(8*8) subtiles, with 797 * same shape as Y Tile(i.e 4*16B OWords) 798 */ 799 return 128; 800 case I915_FORMAT_MOD_Y_TILED_CCS: 801 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 802 return 128; 803 fallthrough; 804 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS: 805 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC: 806 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 807 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 808 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 809 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 810 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 811 is_gen12_ccs_cc_plane(fb, color_plane)) 812 return 64; 813 fallthrough; 814 case I915_FORMAT_MOD_Y_TILED: 815 if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) 816 return 128; 817 else 818 return 512; 819 case I915_FORMAT_MOD_Yf_TILED_CCS: 820 if (intel_fb_is_ccs_aux_plane(fb, color_plane)) 821 return 128; 822 fallthrough; 823 case I915_FORMAT_MOD_Yf_TILED: 824 switch (cpp) { 825 case 1: 826 return 64; 827 case 2: 828 case 4: 829 return 128; 830 case 8: 831 case 16: 832 return 256; 833 default: 834 MISSING_CASE(cpp); 835 return cpp; 836 } 837 break; 838 default: 839 MISSING_CASE(fb->modifier); 840 return cpp; 841 } 842 } 843 844 unsigned int intel_tile_height(const struct drm_framebuffer *fb, int color_plane) 845 { 846 struct intel_display *display = to_intel_display(fb->dev); 847 848 return intel_tile_size(display) / 849 intel_tile_width_bytes(fb, color_plane); 850 } 851 852 /* 853 * Return the tile dimensions in pixel units, based on the (2 or 4 kbyte) GTT 854 * page tile size. 855 */ 856 static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, 857 unsigned int *tile_width, 858 unsigned int *tile_height) 859 { 860 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); 861 unsigned int cpp = fb->format->cpp[color_plane]; 862 863 *tile_width = tile_width_bytes / cpp; 864 *tile_height = intel_tile_height(fb, color_plane); 865 } 866 867 /* 868 * Return the tile dimensions in pixel units, based on the tile block size. 869 * The block covers the full GTT page sized tile on all tiled surfaces and 870 * it's a 64 byte portion of the tile on TGL+ CCS surfaces. 871 */ 872 static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_plane, 873 unsigned int *tile_width, 874 unsigned int *tile_height) 875 { 876 intel_tile_dims(fb, color_plane, tile_width, tile_height); 877 878 if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) 879 *tile_height = 1; 880 } 881 882 unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, int color_plane) 883 { 884 unsigned int tile_width, tile_height; 885 886 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 887 888 return fb->pitches[color_plane] * tile_height; 889 } 890 891 unsigned int 892 intel_fb_align_height(const struct drm_framebuffer *fb, 893 int color_plane, unsigned int height) 894 { 895 unsigned int tile_height = intel_tile_height(fb, color_plane); 896 897 return ALIGN(height, tile_height); 898 } 899 900 bool intel_fb_modifier_uses_dpt(struct intel_display *display, u64 modifier) 901 { 902 return HAS_DPT(display) && modifier != DRM_FORMAT_MOD_LINEAR; 903 } 904 905 bool intel_fb_uses_dpt(const struct drm_framebuffer *fb) 906 { 907 struct intel_display *display = to_intel_display(fb->dev); 908 909 return display->params.enable_dpt && 910 intel_fb_modifier_uses_dpt(display, fb->modifier); 911 } 912 913 void intel_fb_plane_get_subsampling(int *hsub, int *vsub, 914 const struct drm_framebuffer *fb, 915 int color_plane) 916 { 917 int main_plane; 918 919 if (color_plane == 0) { 920 *hsub = 1; 921 *vsub = 1; 922 923 return; 924 } 925 926 /* 927 * TODO: Deduct the subsampling from the char block for all CCS 928 * formats and planes. 929 */ 930 if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { 931 *hsub = fb->format->hsub; 932 *vsub = fb->format->vsub; 933 934 return; 935 } 936 937 main_plane = skl_ccs_to_main_plane(fb, color_plane); 938 *hsub = drm_format_info_block_width(fb->format, color_plane) / 939 drm_format_info_block_width(fb->format, main_plane); 940 941 /* 942 * The min stride check in the core framebuffer_check() function 943 * assumes that format->hsub applies to every plane except for the 944 * first plane. That's incorrect for the CCS AUX plane of the first 945 * plane, but for the above check to pass we must define the block 946 * width with that subsampling applied to it. Adjust the width here 947 * accordingly, so we can calculate the actual subsampling factor. 948 */ 949 if (main_plane == 0) 950 *hsub *= fb->format->hsub; 951 952 *vsub = 32; 953 } 954 955 static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) 956 { 957 int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? 958 skl_ccs_to_main_plane(&fb->base, color_plane) : 0; 959 unsigned int main_width = fb->base.width; 960 unsigned int main_height = fb->base.height; 961 int main_hsub, main_vsub; 962 int hsub, vsub; 963 964 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, &fb->base, main_plane); 965 intel_fb_plane_get_subsampling(&hsub, &vsub, &fb->base, color_plane); 966 967 *w = DIV_ROUND_UP(main_width, main_hsub * hsub); 968 *h = DIV_ROUND_UP(main_height, main_vsub * vsub); 969 } 970 971 static u32 intel_adjust_tile_offset(int *x, int *y, 972 unsigned int tile_width, 973 unsigned int tile_height, 974 unsigned int tile_size, 975 unsigned int pitch_tiles, 976 u32 old_offset, 977 u32 new_offset) 978 { 979 unsigned int pitch_pixels = pitch_tiles * tile_width; 980 unsigned int tiles; 981 982 WARN_ON(old_offset & (tile_size - 1)); 983 WARN_ON(new_offset & (tile_size - 1)); 984 WARN_ON(new_offset > old_offset); 985 986 tiles = (old_offset - new_offset) / tile_size; 987 988 *y += tiles / pitch_tiles * tile_height; 989 *x += tiles % pitch_tiles * tile_width; 990 991 /* minimize x in case it got needlessly big */ 992 *y += *x / pitch_pixels * tile_height; 993 *x %= pitch_pixels; 994 995 return new_offset; 996 } 997 998 static u32 intel_adjust_linear_offset(int *x, int *y, 999 unsigned int cpp, 1000 unsigned int pitch, 1001 u32 old_offset, 1002 u32 new_offset) 1003 { 1004 old_offset += *y * pitch + *x * cpp; 1005 1006 *y = (old_offset - new_offset) / pitch; 1007 *x = ((old_offset - new_offset) - *y * pitch) / cpp; 1008 1009 return new_offset; 1010 } 1011 1012 static u32 intel_adjust_aligned_offset(int *x, int *y, 1013 const struct drm_framebuffer *fb, 1014 int color_plane, 1015 unsigned int rotation, 1016 unsigned int pitch, 1017 u32 old_offset, u32 new_offset) 1018 { 1019 struct intel_display *display = to_intel_display(fb->dev); 1020 unsigned int cpp = fb->format->cpp[color_plane]; 1021 1022 drm_WARN_ON(display->drm, new_offset > old_offset); 1023 1024 if (!is_surface_linear(fb, color_plane)) { 1025 unsigned int tile_size, tile_width, tile_height; 1026 unsigned int pitch_tiles; 1027 1028 tile_size = intel_tile_size(display); 1029 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1030 1031 if (drm_rotation_90_or_270(rotation)) { 1032 pitch_tiles = pitch / tile_height; 1033 swap(tile_width, tile_height); 1034 } else { 1035 pitch_tiles = pitch / (tile_width * cpp); 1036 } 1037 1038 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1039 tile_size, pitch_tiles, 1040 old_offset, new_offset); 1041 } else { 1042 intel_adjust_linear_offset(x, y, cpp, pitch, 1043 old_offset, new_offset); 1044 } 1045 1046 return new_offset; 1047 } 1048 1049 /* 1050 * Adjust the tile offset by moving the difference into 1051 * the x/y offsets. 1052 */ 1053 u32 intel_plane_adjust_aligned_offset(int *x, int *y, 1054 const struct intel_plane_state *plane_state, 1055 int color_plane, 1056 u32 old_offset, u32 new_offset) 1057 { 1058 return intel_adjust_aligned_offset(x, y, plane_state->hw.fb, color_plane, 1059 plane_state->hw.rotation, 1060 plane_state->view.color_plane[color_plane].mapping_stride, 1061 old_offset, new_offset); 1062 } 1063 1064 /* 1065 * Computes the aligned offset to the base tile and adjusts 1066 * x, y. bytes per pixel is assumed to be a power-of-two. 1067 * 1068 * In the 90/270 rotated case, x and y are assumed 1069 * to be already rotated to match the rotated GTT view, and 1070 * pitch is the tile_height aligned framebuffer height. 1071 * 1072 * This function is used when computing the derived information 1073 * under intel_framebuffer, so using any of that information 1074 * here is not allowed. Anything under drm_framebuffer can be 1075 * used. This is why the user has to pass in the pitch since it 1076 * is specified in the rotated orientation. 1077 */ 1078 static u32 intel_compute_aligned_offset(struct intel_display *display, 1079 int *x, int *y, 1080 const struct drm_framebuffer *fb, 1081 int color_plane, 1082 unsigned int pitch, 1083 unsigned int rotation, 1084 unsigned int alignment) 1085 { 1086 unsigned int cpp = fb->format->cpp[color_plane]; 1087 u32 offset, offset_aligned; 1088 1089 if (!is_surface_linear(fb, color_plane)) { 1090 unsigned int tile_size, tile_width, tile_height; 1091 unsigned int tile_rows, tiles, pitch_tiles; 1092 1093 tile_size = intel_tile_size(display); 1094 intel_tile_dims(fb, color_plane, &tile_width, &tile_height); 1095 1096 if (drm_rotation_90_or_270(rotation)) { 1097 pitch_tiles = pitch / tile_height; 1098 swap(tile_width, tile_height); 1099 } else { 1100 pitch_tiles = pitch / (tile_width * cpp); 1101 } 1102 1103 tile_rows = *y / tile_height; 1104 *y %= tile_height; 1105 1106 tiles = *x / tile_width; 1107 *x %= tile_width; 1108 1109 offset = (tile_rows * pitch_tiles + tiles) * tile_size; 1110 1111 offset_aligned = offset; 1112 if (alignment) 1113 offset_aligned = rounddown(offset_aligned, alignment); 1114 1115 intel_adjust_tile_offset(x, y, tile_width, tile_height, 1116 tile_size, pitch_tiles, 1117 offset, offset_aligned); 1118 } else { 1119 offset = *y * pitch + *x * cpp; 1120 offset_aligned = offset; 1121 if (alignment) { 1122 offset_aligned = rounddown(offset_aligned, alignment); 1123 *y = (offset % alignment) / pitch; 1124 *x = ((offset % alignment) - *y * pitch) / cpp; 1125 } else { 1126 *y = *x = 0; 1127 } 1128 } 1129 1130 return offset_aligned; 1131 } 1132 1133 u32 intel_plane_compute_aligned_offset(int *x, int *y, 1134 const struct intel_plane_state *plane_state, 1135 int color_plane) 1136 { 1137 struct intel_display *display = to_intel_display(plane_state); 1138 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1139 const struct drm_framebuffer *fb = plane_state->hw.fb; 1140 unsigned int rotation = plane_state->hw.rotation; 1141 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1142 unsigned int alignment = plane->min_alignment(plane, fb, color_plane); 1143 1144 return intel_compute_aligned_offset(display, x, y, fb, color_plane, 1145 pitch, rotation, alignment); 1146 } 1147 1148 /* Convert the fb->offset[] into x/y offsets */ 1149 static int intel_fb_offset_to_xy(int *x, int *y, 1150 const struct drm_framebuffer *fb, 1151 int color_plane) 1152 { 1153 struct intel_display *display = to_intel_display(fb->dev); 1154 unsigned int height, alignment, unused; 1155 1156 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) 1157 alignment = intel_tile_size(display); 1158 else 1159 alignment = 0; 1160 1161 if (alignment != 0 && fb->offsets[color_plane] % alignment) { 1162 drm_dbg_kms(display->drm, 1163 "Misaligned offset 0x%08x for color plane %d\n", 1164 fb->offsets[color_plane], color_plane); 1165 return -EINVAL; 1166 } 1167 1168 height = drm_format_info_plane_height(fb->format, fb->height, color_plane); 1169 height = ALIGN(height, intel_tile_height(fb, color_plane)); 1170 1171 /* Catch potential overflows early */ 1172 if (check_add_overflow(mul_u32_u32(height, fb->pitches[color_plane]), 1173 fb->offsets[color_plane], &unused)) { 1174 drm_dbg_kms(display->drm, 1175 "Bad offset 0x%08x or pitch %d for color plane %d\n", 1176 fb->offsets[color_plane], fb->pitches[color_plane], 1177 color_plane); 1178 return -ERANGE; 1179 } 1180 1181 *x = 0; 1182 *y = 0; 1183 1184 intel_adjust_aligned_offset(x, y, 1185 fb, color_plane, DRM_MODE_ROTATE_0, 1186 fb->pitches[color_plane], 1187 fb->offsets[color_plane], 0); 1188 1189 return 0; 1190 } 1191 1192 static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane, int x, int y) 1193 { 1194 struct intel_display *display = to_intel_display(fb->dev); 1195 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1196 int main_plane; 1197 int hsub, vsub; 1198 int tile_width, tile_height; 1199 int ccs_x, ccs_y; 1200 int main_x, main_y; 1201 1202 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) 1203 return 0; 1204 1205 /* 1206 * While all the tile dimensions are based on a 2k or 4k GTT page size 1207 * here the main and CCS coordinates must match only within a (64 byte 1208 * on TGL+) block inside the tile. 1209 */ 1210 intel_tile_block_dims(fb, ccs_plane, &tile_width, &tile_height); 1211 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); 1212 1213 tile_width *= hsub; 1214 tile_height *= vsub; 1215 1216 ccs_x = (x * hsub) % tile_width; 1217 ccs_y = (y * vsub) % tile_height; 1218 1219 main_plane = skl_ccs_to_main_plane(fb, ccs_plane); 1220 main_x = intel_fb->normal_view.color_plane[main_plane].x % tile_width; 1221 main_y = intel_fb->normal_view.color_plane[main_plane].y % tile_height; 1222 1223 /* 1224 * CCS doesn't have its own x/y offset register, so the intra CCS tile 1225 * x/y offsets must match between CCS and the main surface. 1226 */ 1227 if (main_x != ccs_x || main_y != ccs_y) { 1228 drm_dbg_kms(display->drm, 1229 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", 1230 main_x, main_y, ccs_x, ccs_y, 1231 intel_fb->normal_view.color_plane[main_plane].x, 1232 intel_fb->normal_view.color_plane[main_plane].y, 1233 x, y); 1234 return -EINVAL; 1235 } 1236 1237 return 0; 1238 } 1239 1240 static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) 1241 { 1242 struct intel_display *display = to_intel_display(plane_state); 1243 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1244 const struct drm_framebuffer *fb = plane_state->hw.fb; 1245 int i; 1246 1247 /* We don't want to deal with remapping with cursors */ 1248 if (plane->id == PLANE_CURSOR) 1249 return false; 1250 1251 /* 1252 * The display engine limits already match/exceed the 1253 * render engine limits, so not much point in remapping. 1254 * Would also need to deal with the fence POT alignment 1255 * and gen2 2KiB GTT tile size. 1256 */ 1257 if (DISPLAY_VER(display) < 4) 1258 return false; 1259 1260 /* 1261 * The new CCS hash mode isn't compatible with remapping as 1262 * the virtual address of the pages affects the compressed data. 1263 */ 1264 if (intel_fb_is_ccs_modifier(fb->modifier)) 1265 return false; 1266 1267 /* Linear needs a page aligned stride for remapping */ 1268 if (fb->modifier == DRM_FORMAT_MOD_LINEAR) { 1269 unsigned int alignment = intel_tile_size(display) - 1; 1270 1271 for (i = 0; i < fb->format->num_planes; i++) { 1272 if (fb->pitches[i] & alignment) 1273 return false; 1274 } 1275 } 1276 1277 return true; 1278 } 1279 1280 bool intel_fb_needs_pot_stride_remap(const struct intel_framebuffer *fb) 1281 { 1282 struct intel_display *display = to_intel_display(fb->base.dev); 1283 1284 return (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1285 intel_fb_uses_dpt(&fb->base); 1286 } 1287 1288 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) 1289 { 1290 struct intel_display *display = to_intel_display(plane_state); 1291 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1292 1293 return DISPLAY_VER(display) < 4 || 1294 (plane->fbc && !plane_state->no_fbc_reason && 1295 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL); 1296 } 1297 1298 static int intel_fb_pitch(const struct intel_framebuffer *fb, int color_plane, unsigned int rotation) 1299 { 1300 if (drm_rotation_90_or_270(rotation)) 1301 return fb->rotated_view.color_plane[color_plane].mapping_stride; 1302 else if (intel_fb_needs_pot_stride_remap(fb)) 1303 return fb->remapped_view.color_plane[color_plane].mapping_stride; 1304 else 1305 return fb->normal_view.color_plane[color_plane].mapping_stride; 1306 } 1307 1308 static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) 1309 { 1310 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1311 const struct intel_framebuffer *fb = to_intel_framebuffer(plane_state->hw.fb); 1312 unsigned int rotation = plane_state->hw.rotation; 1313 u32 stride, max_stride; 1314 1315 /* 1316 * No remapping for invisible planes since we don't have 1317 * an actual source viewport to remap. 1318 */ 1319 if (!plane_state->uapi.visible) 1320 return false; 1321 1322 if (!intel_plane_can_remap(plane_state)) 1323 return false; 1324 1325 /* 1326 * FIXME: aux plane limits on gen9+ are 1327 * unclear in Bspec, for now no checking. 1328 */ 1329 stride = intel_fb_pitch(fb, 0, rotation); 1330 max_stride = plane->max_stride(plane, fb->base.format->format, 1331 fb->base.modifier, rotation); 1332 1333 return stride > max_stride; 1334 } 1335 1336 static int convert_plane_offset_to_xy(const struct intel_framebuffer *fb, int color_plane, 1337 int plane_width, int *x, int *y) 1338 { 1339 struct intel_display *display = to_intel_display(fb->base.dev); 1340 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1341 int ret; 1342 1343 ret = intel_fb_offset_to_xy(x, y, &fb->base, color_plane); 1344 if (ret) { 1345 drm_dbg_kms(display->drm, 1346 "bad fb plane %d offset: 0x%x\n", 1347 color_plane, fb->base.offsets[color_plane]); 1348 return ret; 1349 } 1350 1351 ret = intel_fb_check_ccs_xy(&fb->base, color_plane, *x, *y); 1352 if (ret) 1353 return ret; 1354 1355 /* 1356 * The fence (if used) is aligned to the start of the object 1357 * so having the framebuffer wrap around across the edge of the 1358 * fenced region doesn't really work. We have no API to configure 1359 * the fence start offset within the object (nor could we probably 1360 * on gen2/3). So it's just easier if we just require that the 1361 * fb layout agrees with the fence layout. We already check that the 1362 * fb stride matches the fence stride elsewhere. 1363 */ 1364 if (color_plane == 0 && intel_bo_is_tiled(obj) && 1365 (*x + plane_width) * fb->base.format->cpp[color_plane] > fb->base.pitches[color_plane]) { 1366 drm_dbg_kms(display->drm, 1367 "bad fb plane %d offset: 0x%x\n", 1368 color_plane, fb->base.offsets[color_plane]); 1369 return -EINVAL; 1370 } 1371 1372 return 0; 1373 } 1374 1375 static u32 calc_plane_aligned_offset(const struct intel_framebuffer *fb, int color_plane, int *x, int *y) 1376 { 1377 struct intel_display *display = to_intel_display(fb->base.dev); 1378 unsigned int tile_size = intel_tile_size(display); 1379 u32 offset; 1380 1381 offset = intel_compute_aligned_offset(display, x, y, &fb->base, color_plane, 1382 fb->base.pitches[color_plane], 1383 DRM_MODE_ROTATE_0, 1384 tile_size); 1385 1386 return offset / tile_size; 1387 } 1388 1389 struct fb_plane_view_dims { 1390 unsigned int width, height; 1391 unsigned int tile_width, tile_height; 1392 }; 1393 1394 static void init_plane_view_dims(const struct intel_framebuffer *fb, int color_plane, 1395 unsigned int width, unsigned int height, 1396 struct fb_plane_view_dims *dims) 1397 { 1398 dims->width = width; 1399 dims->height = height; 1400 1401 intel_tile_dims(&fb->base, color_plane, &dims->tile_width, &dims->tile_height); 1402 } 1403 1404 static unsigned int 1405 plane_view_src_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1406 const struct fb_plane_view_dims *dims) 1407 { 1408 return DIV_ROUND_UP(fb->base.pitches[color_plane], 1409 dims->tile_width * fb->base.format->cpp[color_plane]); 1410 } 1411 1412 static unsigned int 1413 plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, 1414 unsigned int pitch_tiles) 1415 { 1416 if (intel_fb_needs_pot_stride_remap(fb)) { 1417 /* 1418 * ADL_P, the only platform needing a POT stride has a minimum 1419 * of 8 main surface tiles. 1420 */ 1421 return roundup_pow_of_two(max(pitch_tiles, 8u)); 1422 } else { 1423 return pitch_tiles; 1424 } 1425 } 1426 1427 static unsigned int 1428 plane_view_scanout_stride(const struct intel_framebuffer *fb, int color_plane, 1429 unsigned int tile_width, 1430 unsigned int src_stride_tiles, unsigned int dst_stride_tiles) 1431 { 1432 struct intel_display *display = to_intel_display(fb->base.dev); 1433 unsigned int stride_tiles; 1434 1435 if ((display->platform.alderlake_p || DISPLAY_VER(display) >= 14) && 1436 src_stride_tiles < dst_stride_tiles) 1437 stride_tiles = src_stride_tiles; 1438 else 1439 stride_tiles = dst_stride_tiles; 1440 1441 return stride_tiles * tile_width * fb->base.format->cpp[color_plane]; 1442 } 1443 1444 static unsigned int 1445 plane_view_width_tiles(const struct intel_framebuffer *fb, int color_plane, 1446 const struct fb_plane_view_dims *dims, 1447 int x) 1448 { 1449 return DIV_ROUND_UP(x + dims->width, dims->tile_width); 1450 } 1451 1452 static unsigned int 1453 plane_view_height_tiles(const struct intel_framebuffer *fb, int color_plane, 1454 const struct fb_plane_view_dims *dims, 1455 int y) 1456 { 1457 return DIV_ROUND_UP(y + dims->height, dims->tile_height); 1458 } 1459 1460 static unsigned int 1461 plane_view_linear_tiles(const struct intel_framebuffer *fb, int color_plane, 1462 const struct fb_plane_view_dims *dims, 1463 int x, int y) 1464 { 1465 struct intel_display *display = to_intel_display(fb->base.dev); 1466 unsigned int size; 1467 1468 size = (y + dims->height) * fb->base.pitches[color_plane] + 1469 x * fb->base.format->cpp[color_plane]; 1470 1471 return DIV_ROUND_UP(size, intel_tile_size(display)); 1472 } 1473 1474 #define assign_chk_ovf(display, var, val) ({ \ 1475 drm_WARN_ON((display)->drm, overflows_type(val, var)); \ 1476 (var) = (val); \ 1477 }) 1478 1479 #define assign_bfld_chk_ovf(display, var, val) ({ \ 1480 (var) = (val); \ 1481 drm_WARN_ON((display)->drm, (var) != (val)); \ 1482 (var); \ 1483 }) 1484 1485 static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_plane, 1486 const struct fb_plane_view_dims *dims, 1487 u32 obj_offset, u32 gtt_offset, int x, int y, 1488 struct intel_fb_view *view) 1489 { 1490 struct intel_display *display = to_intel_display(fb->base.dev); 1491 struct intel_remapped_plane_info *remap_info = &view->gtt.remapped.plane[color_plane]; 1492 struct i915_color_plane_view *color_plane_info = &view->color_plane[color_plane]; 1493 unsigned int tile_width = dims->tile_width; 1494 unsigned int tile_height = dims->tile_height; 1495 unsigned int tile_size = intel_tile_size(display); 1496 struct drm_rect r; 1497 u32 size = 0; 1498 1499 assign_bfld_chk_ovf(display, remap_info->offset, obj_offset); 1500 1501 if (intel_fb_is_gen12_ccs_aux_plane(&fb->base, color_plane)) { 1502 remap_info->linear = 1; 1503 1504 assign_chk_ovf(display, remap_info->size, 1505 plane_view_linear_tiles(fb, color_plane, dims, x, y)); 1506 } else { 1507 remap_info->linear = 0; 1508 1509 assign_chk_ovf(display, remap_info->src_stride, 1510 plane_view_src_stride_tiles(fb, color_plane, dims)); 1511 assign_chk_ovf(display, remap_info->width, 1512 plane_view_width_tiles(fb, color_plane, dims, x)); 1513 assign_chk_ovf(display, remap_info->height, 1514 plane_view_height_tiles(fb, color_plane, dims, y)); 1515 } 1516 1517 if (view->gtt.type == I915_GTT_VIEW_ROTATED) { 1518 drm_WARN_ON(display->drm, remap_info->linear); 1519 check_array_bounds(display, view->gtt.rotated.plane, color_plane); 1520 1521 assign_chk_ovf(display, remap_info->dst_stride, 1522 plane_view_dst_stride_tiles(fb, color_plane, remap_info->height)); 1523 1524 /* rotate the x/y offsets to match the GTT view */ 1525 drm_rect_init(&r, x, y, dims->width, dims->height); 1526 drm_rect_rotate(&r, 1527 remap_info->width * tile_width, 1528 remap_info->height * tile_height, 1529 DRM_MODE_ROTATE_270); 1530 1531 color_plane_info->x = r.x1; 1532 color_plane_info->y = r.y1; 1533 1534 color_plane_info->mapping_stride = remap_info->dst_stride * tile_height; 1535 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1536 1537 size += remap_info->dst_stride * remap_info->width; 1538 1539 /* rotate the tile dimensions to match the GTT view */ 1540 swap(tile_width, tile_height); 1541 } else { 1542 drm_WARN_ON(display->drm, view->gtt.type != I915_GTT_VIEW_REMAPPED); 1543 1544 check_array_bounds(display, view->gtt.remapped.plane, color_plane); 1545 1546 if (view->gtt.remapped.plane_alignment) { 1547 u32 aligned_offset = ALIGN(gtt_offset, 1548 view->gtt.remapped.plane_alignment); 1549 1550 size += aligned_offset - gtt_offset; 1551 gtt_offset = aligned_offset; 1552 } 1553 1554 color_plane_info->x = x; 1555 color_plane_info->y = y; 1556 1557 if (remap_info->linear) { 1558 color_plane_info->mapping_stride = fb->base.pitches[color_plane]; 1559 color_plane_info->scanout_stride = color_plane_info->mapping_stride; 1560 1561 size += remap_info->size; 1562 } else { 1563 unsigned int dst_stride; 1564 1565 /* 1566 * The hardware automagically calculates the CCS AUX surface 1567 * stride from the main surface stride so can't really remap a 1568 * smaller subset (unless we'd remap in whole AUX page units). 1569 */ 1570 if (intel_fb_needs_pot_stride_remap(fb) && 1571 intel_fb_is_ccs_modifier(fb->base.modifier)) 1572 dst_stride = remap_info->src_stride; 1573 else 1574 dst_stride = remap_info->width; 1575 1576 dst_stride = plane_view_dst_stride_tiles(fb, color_plane, dst_stride); 1577 1578 assign_chk_ovf(display, remap_info->dst_stride, dst_stride); 1579 color_plane_info->mapping_stride = dst_stride * 1580 tile_width * 1581 fb->base.format->cpp[color_plane]; 1582 color_plane_info->scanout_stride = 1583 plane_view_scanout_stride(fb, color_plane, tile_width, 1584 remap_info->src_stride, 1585 dst_stride); 1586 1587 size += dst_stride * remap_info->height; 1588 } 1589 } 1590 1591 /* 1592 * We only keep the x/y offsets, so push all of the gtt offset into 1593 * the x/y offsets. x,y will hold the first pixel of the framebuffer 1594 * plane from the start of the remapped/rotated gtt mapping. 1595 */ 1596 if (remap_info->linear) 1597 intel_adjust_linear_offset(&color_plane_info->x, &color_plane_info->y, 1598 fb->base.format->cpp[color_plane], 1599 color_plane_info->mapping_stride, 1600 gtt_offset * tile_size, 0); 1601 else 1602 intel_adjust_tile_offset(&color_plane_info->x, &color_plane_info->y, 1603 tile_width, tile_height, 1604 tile_size, remap_info->dst_stride, 1605 gtt_offset * tile_size, 0); 1606 1607 return size; 1608 } 1609 1610 #undef assign_chk_ovf 1611 1612 /* Return number of tiles @color_plane needs. */ 1613 static unsigned int 1614 calc_plane_normal_size(const struct intel_framebuffer *fb, int color_plane, 1615 const struct fb_plane_view_dims *dims, 1616 int x, int y) 1617 { 1618 unsigned int tiles; 1619 1620 if (is_surface_linear(&fb->base, color_plane)) { 1621 tiles = plane_view_linear_tiles(fb, color_plane, dims, x, y); 1622 } else { 1623 tiles = plane_view_src_stride_tiles(fb, color_plane, dims) * 1624 plane_view_height_tiles(fb, color_plane, dims, y); 1625 /* 1626 * If the plane isn't horizontally tile aligned, 1627 * we need one more tile. 1628 */ 1629 if (x != 0) 1630 tiles++; 1631 } 1632 1633 return tiles; 1634 } 1635 1636 static void intel_fb_view_init(struct intel_display *display, 1637 struct intel_fb_view *view, 1638 enum i915_gtt_view_type view_type) 1639 { 1640 memset(view, 0, sizeof(*view)); 1641 view->gtt.type = view_type; 1642 1643 if (view_type == I915_GTT_VIEW_REMAPPED && 1644 (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)) 1645 view->gtt.remapped.plane_alignment = SZ_2M / PAGE_SIZE; 1646 } 1647 1648 bool intel_fb_supports_90_270_rotation(const struct intel_framebuffer *fb) 1649 { 1650 struct intel_display *display = to_intel_display(fb->base.dev); 1651 1652 if (DISPLAY_VER(display) >= 13) 1653 return false; 1654 1655 return fb->base.modifier == I915_FORMAT_MOD_Y_TILED || 1656 fb->base.modifier == I915_FORMAT_MOD_Yf_TILED; 1657 } 1658 1659 static unsigned int intel_fb_min_alignment(const struct drm_framebuffer *fb) 1660 { 1661 struct intel_display *display = to_intel_display(fb->dev); 1662 struct intel_plane *plane; 1663 unsigned int min_alignment = 0; 1664 1665 for_each_intel_plane(display->drm, plane) { 1666 unsigned int plane_min_alignment; 1667 1668 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1669 continue; 1670 1671 plane_min_alignment = plane->min_alignment(plane, fb, 0); 1672 1673 drm_WARN_ON(display->drm, plane_min_alignment && 1674 !is_power_of_2(plane_min_alignment)); 1675 1676 if (intel_plane_needs_physical(plane)) 1677 continue; 1678 1679 min_alignment = max(min_alignment, plane_min_alignment); 1680 } 1681 1682 return min_alignment; 1683 } 1684 1685 static unsigned int intel_fb_vtd_guard(const struct drm_framebuffer *fb) 1686 { 1687 struct intel_display *display = to_intel_display(fb->dev); 1688 struct intel_plane *plane; 1689 unsigned int vtd_guard = 0; 1690 1691 for_each_intel_plane(display->drm, plane) { 1692 if (!drm_plane_has_format(&plane->base, fb->format->format, fb->modifier)) 1693 continue; 1694 1695 vtd_guard = max_t(unsigned int, vtd_guard, plane->vtd_guard); 1696 } 1697 1698 return vtd_guard; 1699 } 1700 1701 int intel_fill_fb_info(struct intel_display *display, struct intel_framebuffer *fb) 1702 { 1703 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 1704 u32 gtt_offset_rotated = 0; 1705 u32 gtt_offset_remapped = 0; 1706 unsigned int max_size = 0; 1707 int i, num_planes = fb->base.format->num_planes; 1708 unsigned int tile_size = intel_tile_size(display); 1709 1710 intel_fb_view_init(display, &fb->normal_view, I915_GTT_VIEW_NORMAL); 1711 1712 drm_WARN_ON(display->drm, 1713 intel_fb_supports_90_270_rotation(fb) && 1714 intel_fb_needs_pot_stride_remap(fb)); 1715 1716 if (intel_fb_supports_90_270_rotation(fb)) 1717 intel_fb_view_init(display, &fb->rotated_view, I915_GTT_VIEW_ROTATED); 1718 if (intel_fb_needs_pot_stride_remap(fb)) 1719 intel_fb_view_init(display, &fb->remapped_view, I915_GTT_VIEW_REMAPPED); 1720 1721 for (i = 0; i < num_planes; i++) { 1722 struct fb_plane_view_dims view_dims; 1723 unsigned int width, height; 1724 unsigned int size; 1725 u32 offset; 1726 int x, y; 1727 int ret; 1728 1729 /* 1730 * Plane 2 of Render Compression with Clear Color fb modifier 1731 * is consumed by the driver and not passed to DE. Skip the 1732 * arithmetic related to alignment and offset calculation. 1733 */ 1734 if (is_gen12_ccs_cc_plane(&fb->base, i)) { 1735 unsigned int end; 1736 1737 if (!IS_ALIGNED(fb->base.offsets[i], 64)) { 1738 drm_dbg_kms(display->drm, 1739 "fb misaligned clear color plane %d offset (0x%x)\n", 1740 i, fb->base.offsets[i]); 1741 return -EINVAL; 1742 } 1743 1744 if (check_add_overflow(fb->base.offsets[i], 64, &end)) { 1745 drm_dbg_kms(display->drm, 1746 "fb bad clear color plane %d offset (0x%x)\n", 1747 i, fb->base.offsets[i]); 1748 return -EINVAL; 1749 } 1750 1751 max_size = max(max_size, DIV_ROUND_UP(end, tile_size)); 1752 continue; 1753 } 1754 1755 intel_fb_plane_dims(fb, i, &width, &height); 1756 1757 ret = convert_plane_offset_to_xy(fb, i, width, &x, &y); 1758 if (ret) 1759 return ret; 1760 1761 init_plane_view_dims(fb, i, width, height, &view_dims); 1762 1763 /* 1764 * First pixel of the framebuffer from 1765 * the start of the normal gtt mapping. 1766 */ 1767 fb->normal_view.color_plane[i].x = x; 1768 fb->normal_view.color_plane[i].y = y; 1769 fb->normal_view.color_plane[i].mapping_stride = fb->base.pitches[i]; 1770 fb->normal_view.color_plane[i].scanout_stride = 1771 fb->normal_view.color_plane[i].mapping_stride; 1772 1773 offset = calc_plane_aligned_offset(fb, i, &x, &y); 1774 1775 if (intel_fb_supports_90_270_rotation(fb)) 1776 gtt_offset_rotated += calc_plane_remap_info(fb, i, &view_dims, 1777 offset, gtt_offset_rotated, x, y, 1778 &fb->rotated_view); 1779 1780 if (intel_fb_needs_pot_stride_remap(fb)) 1781 gtt_offset_remapped += calc_plane_remap_info(fb, i, &view_dims, 1782 offset, gtt_offset_remapped, x, y, 1783 &fb->remapped_view); 1784 1785 size = calc_plane_normal_size(fb, i, &view_dims, x, y); 1786 /* how many tiles in total needed in the bo */ 1787 max_size = max(max_size, offset + size); 1788 } 1789 1790 if (mul_u32_u32(max_size, tile_size) > obj->size) { 1791 drm_dbg_kms(display->drm, 1792 "fb too big for bo (need %llu bytes, have %zu bytes)\n", 1793 mul_u32_u32(max_size, tile_size), obj->size); 1794 return -EINVAL; 1795 } 1796 1797 fb->min_alignment = intel_fb_min_alignment(&fb->base); 1798 fb->vtd_guard = intel_fb_vtd_guard(&fb->base); 1799 1800 return 0; 1801 } 1802 1803 unsigned int intel_fb_view_vtd_guard(const struct drm_framebuffer *fb, 1804 const struct intel_fb_view *view, 1805 unsigned int rotation) 1806 { 1807 unsigned int vtd_guard; 1808 int color_plane; 1809 1810 vtd_guard = to_intel_framebuffer(fb)->vtd_guard; 1811 if (!vtd_guard) 1812 return 0; 1813 1814 for (color_plane = 0; color_plane < fb->format->num_planes; color_plane++) { 1815 unsigned int stride, tile; 1816 1817 if (intel_fb_is_ccs_aux_plane(fb, color_plane) || 1818 is_gen12_ccs_cc_plane(fb, color_plane)) 1819 continue; 1820 1821 stride = view->color_plane[color_plane].mapping_stride; 1822 1823 if (drm_rotation_90_or_270(rotation)) 1824 tile = intel_tile_height(fb, color_plane); 1825 else 1826 tile = intel_tile_width_bytes(fb, color_plane); 1827 1828 vtd_guard = max(vtd_guard, DIV_ROUND_UP(stride, tile)); 1829 } 1830 1831 return vtd_guard; 1832 } 1833 1834 static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) 1835 { 1836 struct intel_display *display = to_intel_display(plane_state); 1837 struct drm_framebuffer *fb = plane_state->hw.fb; 1838 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 1839 unsigned int rotation = plane_state->hw.rotation; 1840 int i, num_planes = fb->format->num_planes; 1841 unsigned int src_x, src_y; 1842 unsigned int src_w, src_h; 1843 u32 gtt_offset = 0; 1844 1845 intel_fb_view_init(display, &plane_state->view, 1846 drm_rotation_90_or_270(rotation) ? I915_GTT_VIEW_ROTATED : 1847 I915_GTT_VIEW_REMAPPED); 1848 1849 src_x = plane_state->uapi.src.x1 >> 16; 1850 src_y = plane_state->uapi.src.y1 >> 16; 1851 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1852 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1853 1854 drm_WARN_ON(display->drm, intel_fb_is_ccs_modifier(fb->modifier)); 1855 1856 /* Make src coordinates relative to the viewport */ 1857 drm_rect_translate(&plane_state->uapi.src, 1858 -(src_x << 16), -(src_y << 16)); 1859 1860 /* Rotate src coordinates to match rotated GTT view */ 1861 if (drm_rotation_90_or_270(rotation)) 1862 drm_rect_rotate(&plane_state->uapi.src, 1863 src_w << 16, src_h << 16, 1864 DRM_MODE_ROTATE_270); 1865 1866 for (i = 0; i < num_planes; i++) { 1867 unsigned int hsub = i ? fb->format->hsub : 1; 1868 unsigned int vsub = i ? fb->format->vsub : 1; 1869 struct fb_plane_view_dims view_dims; 1870 unsigned int width, height; 1871 unsigned int x, y; 1872 u32 offset; 1873 1874 x = src_x / hsub; 1875 y = src_y / vsub; 1876 width = src_w / hsub; 1877 height = src_h / vsub; 1878 1879 init_plane_view_dims(intel_fb, i, width, height, &view_dims); 1880 1881 /* 1882 * First pixel of the src viewport from the 1883 * start of the normal gtt mapping. 1884 */ 1885 x += intel_fb->normal_view.color_plane[i].x; 1886 y += intel_fb->normal_view.color_plane[i].y; 1887 1888 offset = calc_plane_aligned_offset(intel_fb, i, &x, &y); 1889 1890 gtt_offset += calc_plane_remap_info(intel_fb, i, &view_dims, 1891 offset, gtt_offset, x, y, 1892 &plane_state->view); 1893 } 1894 } 1895 1896 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) 1897 { 1898 unsigned int size = 0; 1899 int i; 1900 1901 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) 1902 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width; 1903 1904 return size; 1905 } 1906 1907 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) 1908 { 1909 unsigned int size = 0; 1910 int i; 1911 1912 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) { 1913 unsigned int plane_size; 1914 1915 if (rem_info->plane[i].linear) 1916 plane_size = rem_info->plane[i].size; 1917 else 1918 plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height; 1919 1920 if (plane_size == 0) 1921 continue; 1922 1923 if (rem_info->plane_alignment) 1924 size = ALIGN(size, rem_info->plane_alignment); 1925 1926 size += plane_size; 1927 } 1928 1929 return size; 1930 } 1931 1932 void intel_fb_fill_view(const struct intel_framebuffer *fb, unsigned int rotation, 1933 struct intel_fb_view *view) 1934 { 1935 if (drm_rotation_90_or_270(rotation)) 1936 *view = fb->rotated_view; 1937 else if (intel_fb_needs_pot_stride_remap(fb)) 1938 *view = fb->remapped_view; 1939 else 1940 *view = fb->normal_view; 1941 } 1942 1943 /* 1944 * Convert the x/y offsets into a linear offset. 1945 * Only valid with 0/180 degree rotation, which is fine since linear 1946 * offset is only used with linear buffers on pre-hsw and tiled buffers 1947 * with gen2/3, and 90/270 degree rotations isn't supported on any of them. 1948 */ 1949 u32 intel_fb_xy_to_linear(int x, int y, 1950 const struct intel_plane_state *plane_state, 1951 int color_plane) 1952 { 1953 const struct drm_framebuffer *fb = plane_state->hw.fb; 1954 unsigned int cpp = fb->format->cpp[color_plane]; 1955 unsigned int pitch = plane_state->view.color_plane[color_plane].mapping_stride; 1956 1957 return y * pitch + x * cpp; 1958 } 1959 1960 /* 1961 * Add the x/y offsets derived from fb->offsets[] to the user 1962 * specified plane src x/y offsets. The resulting x/y offsets 1963 * specify the start of scanout from the beginning of the gtt mapping. 1964 */ 1965 void intel_add_fb_offsets(int *x, int *y, 1966 const struct intel_plane_state *plane_state, 1967 int color_plane) 1968 1969 { 1970 *x += plane_state->view.color_plane[color_plane].x; 1971 *y += plane_state->view.color_plane[color_plane].y; 1972 } 1973 1974 static 1975 u32 intel_fb_max_stride(struct intel_display *display, 1976 u32 pixel_format, u64 modifier) 1977 { 1978 /* 1979 * Arbitrary limit for gen4+ chosen to match the 1980 * render engine max stride. 1981 * 1982 * The new CCS hash mode makes remapping impossible 1983 */ 1984 if (DISPLAY_VER(display) < 4 || intel_fb_is_ccs_modifier(modifier) || 1985 intel_fb_modifier_uses_dpt(display, modifier)) 1986 return intel_plane_fb_max_stride(display->drm, pixel_format, modifier); 1987 else if (DISPLAY_VER(display) >= 7) 1988 return 256 * 1024; 1989 else 1990 return 128 * 1024; 1991 } 1992 1993 static unsigned int 1994 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) 1995 { 1996 struct intel_display *display = to_intel_display(fb->dev); 1997 unsigned int tile_width; 1998 1999 if (is_surface_linear(fb, color_plane)) { 2000 unsigned int max_stride = intel_plane_fb_max_stride(display->drm, 2001 fb->format->format, 2002 fb->modifier); 2003 2004 /* 2005 * To make remapping with linear generally feasible 2006 * we need the stride to be page aligned. 2007 */ 2008 if (fb->pitches[color_plane] > max_stride && 2009 !intel_fb_is_ccs_modifier(fb->modifier)) 2010 return intel_tile_size(display); 2011 else 2012 return 64; 2013 } 2014 2015 tile_width = intel_tile_width_bytes(fb, color_plane); 2016 if (intel_fb_is_ccs_modifier(fb->modifier)) { 2017 /* 2018 * On TGL the surface stride must be 4 tile aligned, mapped by 2019 * one 64 byte cacheline on the CCS AUX surface. 2020 */ 2021 if (DISPLAY_VER(display) >= 12) 2022 tile_width *= 4; 2023 /* 2024 * Display WA #0531: skl,bxt,kbl,glk 2025 * 2026 * Render decompression and plane width > 3840 2027 * combined with horizontal panning requires the 2028 * plane stride to be a multiple of 4. We'll just 2029 * require the entire fb to accommodate that to avoid 2030 * potential runtime errors at plane configuration time. 2031 */ 2032 else if ((DISPLAY_VER(display) == 9 || display->platform.geminilake) && 2033 color_plane == 0 && fb->width > 3840) 2034 tile_width *= 4; 2035 } 2036 return tile_width; 2037 } 2038 2039 static int intel_plane_check_stride(const struct intel_plane_state *plane_state) 2040 { 2041 struct intel_display *display = to_intel_display(plane_state); 2042 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2043 const struct drm_framebuffer *fb = plane_state->hw.fb; 2044 unsigned int rotation = plane_state->hw.rotation; 2045 u32 stride, max_stride; 2046 2047 /* 2048 * We ignore stride for all invisible planes that 2049 * can be remapped. Otherwise we could end up 2050 * with a false positive when the remapping didn't 2051 * kick in due the plane being invisible. 2052 */ 2053 if (intel_plane_can_remap(plane_state) && 2054 !plane_state->uapi.visible) 2055 return 0; 2056 2057 /* FIXME other color planes? */ 2058 stride = plane_state->view.color_plane[0].mapping_stride; 2059 max_stride = plane->max_stride(plane, fb->format->format, 2060 fb->modifier, rotation); 2061 2062 if (stride > max_stride) { 2063 drm_dbg_kms(display->drm, 2064 "[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 2065 fb->base.id, stride, 2066 plane->base.base.id, plane->base.name, max_stride); 2067 return -EINVAL; 2068 } 2069 2070 return 0; 2071 } 2072 2073 int intel_plane_compute_gtt(struct intel_plane_state *plane_state) 2074 { 2075 const struct intel_framebuffer *fb = 2076 to_intel_framebuffer(plane_state->hw.fb); 2077 unsigned int rotation = plane_state->hw.rotation; 2078 2079 if (!fb) 2080 return 0; 2081 2082 if (intel_plane_needs_remap(plane_state)) { 2083 intel_plane_remap_gtt(plane_state); 2084 2085 /* 2086 * Sometimes even remapping can't overcome 2087 * the stride limitations :( Can happen with 2088 * big plane sizes and suitably misaligned 2089 * offsets. 2090 */ 2091 return intel_plane_check_stride(plane_state); 2092 } 2093 2094 intel_fb_fill_view(fb, rotation, &plane_state->view); 2095 2096 /* Rotate src coordinates to match rotated GTT view */ 2097 if (drm_rotation_90_or_270(rotation)) 2098 drm_rect_rotate(&plane_state->uapi.src, 2099 fb->base.width << 16, fb->base.height << 16, 2100 DRM_MODE_ROTATE_270); 2101 2102 return intel_plane_check_stride(plane_state); 2103 } 2104 2105 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 2106 { 2107 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 2108 2109 drm_framebuffer_cleanup(fb); 2110 2111 if (intel_fb_uses_dpt(fb)) 2112 intel_dpt_destroy(intel_fb->dpt_vm); 2113 2114 intel_frontbuffer_put(intel_fb->frontbuffer); 2115 2116 intel_fb_bo_framebuffer_fini(intel_fb_bo(fb)); 2117 2118 kfree(intel_fb); 2119 } 2120 2121 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 2122 struct drm_file *file, 2123 unsigned int *handle) 2124 { 2125 struct drm_gem_object *obj = intel_fb_bo(fb); 2126 struct intel_display *display = to_intel_display(obj->dev); 2127 2128 if (intel_bo_is_userptr(obj)) { 2129 drm_dbg(display->drm, 2130 "attempting to use a userptr for a framebuffer, denied\n"); 2131 return -EINVAL; 2132 } 2133 2134 return drm_gem_handle_create(file, obj, handle); 2135 } 2136 2137 struct frontbuffer_fence_cb { 2138 struct dma_fence_cb base; 2139 struct intel_frontbuffer *front; 2140 }; 2141 2142 static void intel_user_framebuffer_fence_wake(struct dma_fence *dma, 2143 struct dma_fence_cb *data) 2144 { 2145 struct frontbuffer_fence_cb *cb = container_of(data, typeof(*cb), base); 2146 2147 intel_frontbuffer_queue_flush(cb->front); 2148 kfree(cb); 2149 dma_fence_put(dma); 2150 } 2151 2152 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, 2153 struct drm_file *file, 2154 unsigned int flags, unsigned int color, 2155 struct drm_clip_rect *clips, 2156 unsigned int num_clips) 2157 { 2158 struct drm_gem_object *obj = intel_fb_bo(fb); 2159 struct intel_frontbuffer *front = to_intel_frontbuffer(fb); 2160 struct dma_fence *fence; 2161 struct frontbuffer_fence_cb *cb; 2162 int ret = 0; 2163 2164 if (!atomic_read(&front->bits)) 2165 return 0; 2166 2167 if (dma_resv_test_signaled(obj->resv, dma_resv_usage_rw(false))) 2168 goto flush; 2169 2170 ret = dma_resv_get_singleton(obj->resv, dma_resv_usage_rw(false), 2171 &fence); 2172 if (ret || !fence) 2173 goto flush; 2174 2175 cb = kmalloc(sizeof(*cb), GFP_KERNEL); 2176 if (!cb) { 2177 dma_fence_put(fence); 2178 ret = -ENOMEM; 2179 goto flush; 2180 } 2181 2182 cb->front = front; 2183 2184 intel_frontbuffer_invalidate(front, ORIGIN_DIRTYFB); 2185 2186 ret = dma_fence_add_callback(fence, &cb->base, 2187 intel_user_framebuffer_fence_wake); 2188 if (ret) { 2189 intel_user_framebuffer_fence_wake(fence, &cb->base); 2190 if (ret == -ENOENT) 2191 ret = 0; 2192 } 2193 2194 return ret; 2195 2196 flush: 2197 intel_bo_flush_if_display(obj); 2198 intel_frontbuffer_flush(front, ORIGIN_DIRTYFB); 2199 return ret; 2200 } 2201 2202 static const struct drm_framebuffer_funcs intel_fb_funcs = { 2203 .destroy = intel_user_framebuffer_destroy, 2204 .create_handle = intel_user_framebuffer_create_handle, 2205 .dirty = intel_user_framebuffer_dirty, 2206 }; 2207 2208 int intel_framebuffer_init(struct intel_framebuffer *intel_fb, 2209 struct drm_gem_object *obj, 2210 const struct drm_format_info *info, 2211 struct drm_mode_fb_cmd2 *mode_cmd) 2212 { 2213 struct intel_display *display = to_intel_display(obj->dev); 2214 struct drm_framebuffer *fb = &intel_fb->base; 2215 u32 max_stride; 2216 int ret = -EINVAL; 2217 int i; 2218 2219 ret = intel_fb_bo_framebuffer_init(fb, obj, mode_cmd); 2220 if (ret) 2221 return ret; 2222 2223 intel_fb->frontbuffer = intel_frontbuffer_get(obj); 2224 if (!intel_fb->frontbuffer) { 2225 ret = -ENOMEM; 2226 goto err; 2227 } 2228 2229 ret = -EINVAL; 2230 if (!drm_any_plane_has_format(display->drm, 2231 mode_cmd->pixel_format, 2232 mode_cmd->modifier[0])) { 2233 drm_dbg_kms(display->drm, 2234 "unsupported pixel format %p4cc / modifier 0x%llx\n", 2235 &mode_cmd->pixel_format, mode_cmd->modifier[0]); 2236 goto err_frontbuffer_put; 2237 } 2238 2239 max_stride = intel_fb_max_stride(display, mode_cmd->pixel_format, 2240 mode_cmd->modifier[0]); 2241 if (mode_cmd->pitches[0] > max_stride) { 2242 drm_dbg_kms(display->drm, 2243 "%s pitch (%u) must be at most %d\n", 2244 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? 2245 "tiled" : "linear", 2246 mode_cmd->pitches[0], max_stride); 2247 goto err_frontbuffer_put; 2248 } 2249 2250 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 2251 if (mode_cmd->offsets[0] != 0) { 2252 drm_dbg_kms(display->drm, 2253 "plane 0 offset (0x%08x) must be 0\n", 2254 mode_cmd->offsets[0]); 2255 goto err_frontbuffer_put; 2256 } 2257 2258 drm_helper_mode_fill_fb_struct(display->drm, fb, info, mode_cmd); 2259 2260 for (i = 0; i < fb->format->num_planes; i++) { 2261 unsigned int stride_alignment; 2262 2263 if (mode_cmd->handles[i] != mode_cmd->handles[0]) { 2264 drm_dbg_kms(display->drm, "bad plane %d handle\n", i); 2265 goto err_frontbuffer_put; 2266 } 2267 2268 stride_alignment = intel_fb_stride_alignment(fb, i); 2269 if (fb->pitches[i] & (stride_alignment - 1)) { 2270 drm_dbg_kms(display->drm, 2271 "plane %d pitch (%d) must be at least %u byte aligned\n", 2272 i, fb->pitches[i], stride_alignment); 2273 goto err_frontbuffer_put; 2274 } 2275 2276 if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { 2277 unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); 2278 2279 if (fb->pitches[i] != ccs_aux_stride) { 2280 drm_dbg_kms(display->drm, 2281 "ccs aux plane %d pitch (%d) must be %d\n", 2282 i, fb->pitches[i], ccs_aux_stride); 2283 goto err_frontbuffer_put; 2284 } 2285 } 2286 2287 fb->obj[i] = obj; 2288 } 2289 2290 ret = intel_fill_fb_info(display, intel_fb); 2291 if (ret) 2292 goto err_frontbuffer_put; 2293 2294 if (intel_fb_uses_dpt(fb)) { 2295 struct i915_address_space *vm; 2296 2297 vm = intel_dpt_create(intel_fb); 2298 if (IS_ERR(vm)) { 2299 drm_dbg_kms(display->drm, "failed to create DPT\n"); 2300 ret = PTR_ERR(vm); 2301 goto err_frontbuffer_put; 2302 } 2303 2304 intel_fb->dpt_vm = vm; 2305 } 2306 2307 ret = drm_framebuffer_init(display->drm, fb, &intel_fb_funcs); 2308 if (ret) { 2309 drm_err(display->drm, "framebuffer init failed %d\n", ret); 2310 goto err_free_dpt; 2311 } 2312 2313 return 0; 2314 2315 err_free_dpt: 2316 if (intel_fb_uses_dpt(fb)) 2317 intel_dpt_destroy(intel_fb->dpt_vm); 2318 err_frontbuffer_put: 2319 intel_frontbuffer_put(intel_fb->frontbuffer); 2320 err: 2321 intel_fb_bo_framebuffer_fini(obj); 2322 return ret; 2323 } 2324 2325 struct drm_framebuffer * 2326 intel_user_framebuffer_create(struct drm_device *dev, 2327 struct drm_file *filp, 2328 const struct drm_format_info *info, 2329 const struct drm_mode_fb_cmd2 *user_mode_cmd) 2330 { 2331 struct drm_framebuffer *fb; 2332 struct drm_gem_object *obj; 2333 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; 2334 2335 obj = intel_fb_bo_lookup_valid_bo(dev, filp, &mode_cmd); 2336 if (IS_ERR(obj)) 2337 return ERR_CAST(obj); 2338 2339 fb = intel_framebuffer_create(obj, info, &mode_cmd); 2340 drm_gem_object_put(obj); 2341 2342 return fb; 2343 } 2344 2345 struct drm_framebuffer * 2346 intel_framebuffer_create(struct drm_gem_object *obj, 2347 const struct drm_format_info *info, 2348 struct drm_mode_fb_cmd2 *mode_cmd) 2349 { 2350 struct intel_framebuffer *intel_fb; 2351 int ret; 2352 2353 intel_fb = intel_bo_alloc_framebuffer(); 2354 if (!intel_fb) 2355 return ERR_PTR(-ENOMEM); 2356 2357 ret = intel_framebuffer_init(intel_fb, obj, info, mode_cmd); 2358 if (ret) 2359 goto err; 2360 2361 return &intel_fb->base; 2362 2363 err: 2364 kfree(intel_fb); 2365 return ERR_PTR(ret); 2366 } 2367 2368 struct drm_gem_object *intel_fb_bo(const struct drm_framebuffer *fb) 2369 { 2370 return fb ? fb->obj[0] : NULL; 2371 } 2372