1 /* SPDX-License-Identifier: MIT */ 2 /* Copyright © 2025 Intel Corporation */ 3 4 #ifndef __INTEL_DSI_VBT_DEFS_H__ 5 #define __INTEL_DSI_VBT_DEFS_H__ 6 7 #include <linux/types.h> 8 9 /* 10 * MIPI Sequence Block definitions 11 * 12 * Note the VBT spec has AssertReset / DeassertReset swapped from their 13 * usual naming, we use the proper names here to avoid confusion when 14 * reading the code. 15 */ 16 enum mipi_seq { 17 MIPI_SEQ_END = 0, 18 MIPI_SEQ_DEASSERT_RESET, /* Spec says MipiAssertResetPin */ 19 MIPI_SEQ_INIT_OTP, 20 MIPI_SEQ_DISPLAY_ON, 21 MIPI_SEQ_DISPLAY_OFF, 22 MIPI_SEQ_ASSERT_RESET, /* Spec says MipiDeassertResetPin */ 23 MIPI_SEQ_BACKLIGHT_ON, /* sequence block v2+ */ 24 MIPI_SEQ_BACKLIGHT_OFF, /* sequence block v2+ */ 25 MIPI_SEQ_TEAR_ON, /* sequence block v2+ */ 26 MIPI_SEQ_TEAR_OFF, /* sequence block v3+ */ 27 MIPI_SEQ_POWER_ON, /* sequence block v3+ */ 28 MIPI_SEQ_POWER_OFF, /* sequence block v3+ */ 29 MIPI_SEQ_MAX 30 }; 31 32 enum mipi_seq_element { 33 MIPI_SEQ_ELEM_END = 0, 34 MIPI_SEQ_ELEM_SEND_PKT, 35 MIPI_SEQ_ELEM_DELAY, 36 MIPI_SEQ_ELEM_GPIO, 37 MIPI_SEQ_ELEM_I2C, /* sequence block v2+ */ 38 MIPI_SEQ_ELEM_SPI, /* sequence block v3+ */ 39 MIPI_SEQ_ELEM_PMIC, /* sequence block v3+ */ 40 MIPI_SEQ_ELEM_MAX 41 }; 42 43 #define MIPI_DSI_UNDEFINED_PANEL_ID 0 44 #define MIPI_DSI_GENERIC_PANEL_ID 1 45 46 struct mipi_config { 47 u16 panel_id; 48 49 /* General Params */ 50 struct { 51 u32 enable_dithering:1; 52 u32 rsvd1:1; 53 u32 is_bridge:1; 54 55 u32 panel_arch_type:2; 56 u32 is_cmd_mode:1; 57 58 #define NON_BURST_SYNC_PULSE 0x1 59 #define NON_BURST_SYNC_EVENTS 0x2 60 #define BURST_MODE 0x3 61 u32 video_transfer_mode:2; 62 63 u32 cabc_supported:1; 64 #define PPS_BLC_PMIC 0 65 #define PPS_BLC_SOC 1 66 u32 pwm_blc:1; 67 68 #define PIXEL_FORMAT_RGB565 0x1 69 #define PIXEL_FORMAT_RGB666 0x2 70 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED 0x3 71 #define PIXEL_FORMAT_RGB888 0x4 72 u32 videomode_color_format:4; 73 74 #define ENABLE_ROTATION_0 0x0 75 #define ENABLE_ROTATION_90 0x1 76 #define ENABLE_ROTATION_180 0x2 77 #define ENABLE_ROTATION_270 0x3 78 u32 rotation:2; 79 u32 bta_disable:1; 80 u32 rsvd2:15; 81 } __packed; 82 83 /* Port Desc */ 84 struct { 85 #define DUAL_LINK_NOT_SUPPORTED 0 86 #define DUAL_LINK_FRONT_BACK 1 87 #define DUAL_LINK_PIXEL_ALT 2 88 u16 dual_link:2; 89 u16 lane_cnt:2; 90 u16 pixel_overlap:3; 91 u16 rgb_flip:1; 92 #define DL_DCS_PORT_A 0x00 93 #define DL_DCS_PORT_C 0x01 94 #define DL_DCS_PORT_A_AND_C 0x02 95 u16 dl_dcs_cabc_ports:2; 96 u16 dl_dcs_backlight_ports:2; 97 u16 port_sync:1; /* 219-230 */ 98 u16 rsvd3:3; 99 } __packed; 100 101 /* DSI Controller Parameters */ 102 struct { 103 u16 dsi_usage:1; 104 u16 rsvd4:15; 105 } __packed; 106 107 u8 rsvd5; 108 u32 target_burst_mode_freq; 109 u32 dsi_ddr_clk; 110 u32 bridge_ref_clk; 111 112 /* LP Byte Clock */ 113 struct { 114 #define BYTE_CLK_SEL_20MHZ 0 115 #define BYTE_CLK_SEL_10MHZ 1 116 #define BYTE_CLK_SEL_5MHZ 2 117 u8 byte_clk_sel:2; 118 u8 rsvd6:6; 119 } __packed; 120 121 /* DPhy Flags */ 122 struct { 123 u16 dphy_param_valid:1; 124 u16 eot_pkt_disabled:1; 125 u16 enable_clk_stop:1; 126 u16 blanking_packets_during_bllp:1; /* 219+ */ 127 u16 lp_clock_during_lpm:1; /* 219+ */ 128 u16 rsvd7:11; 129 } __packed; 130 131 u32 hs_tx_timeout; 132 u32 lp_rx_timeout; 133 u32 turn_around_timeout; 134 u32 device_reset_timer; 135 u32 master_init_timer; 136 u32 dbi_bw_timer; 137 u32 lp_byte_clk_val; 138 139 /* DPhy Params */ 140 struct { 141 u32 prepare_cnt:6; 142 u32 rsvd8:2; 143 u32 clk_zero_cnt:8; 144 u32 trail_cnt:5; 145 u32 rsvd9:3; 146 u32 exit_zero_cnt:6; 147 u32 rsvd10:2; 148 } __packed; 149 150 u32 clk_lane_switch_cnt; 151 u32 hl_switch_cnt; 152 153 u32 rsvd11[6]; 154 155 /* timings based on dphy spec */ 156 u8 tclk_miss; 157 u8 tclk_post; 158 u8 rsvd12; 159 u8 tclk_pre; 160 u8 tclk_prepare; 161 u8 tclk_settle; 162 u8 tclk_term_enable; 163 u8 tclk_trail; 164 u16 tclk_prepare_clkzero; 165 u8 rsvd13; 166 u8 td_term_enable; 167 u8 teot; 168 u8 ths_exit; 169 u8 ths_prepare; 170 u16 ths_prepare_hszero; 171 u8 rsvd14; 172 u8 ths_settle; 173 u8 ths_skip; 174 u8 ths_trail; 175 u8 tinit; 176 u8 tlpx; 177 u8 rsvd15[3]; 178 179 /* GPIOs */ 180 u8 panel_enable; 181 u8 bl_enable; 182 u8 pwm_enable; 183 u8 reset_r_n; 184 u8 pwr_down_r; 185 u8 stdby_r_n; 186 } __packed; 187 188 /* all delays have a unit of 100us */ 189 struct mipi_pps_data { 190 u16 panel_on_delay; 191 u16 bl_enable_delay; 192 u16 bl_disable_delay; 193 u16 panel_off_delay; 194 u16 panel_power_cycle_delay; 195 } __packed; 196 197 #endif /* __INTEL_DSI_VBT_DEFS_H__ */ 198