1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <asm/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 40 #include <video/mipi_display.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_display_types.h" 45 #include "intel_dsi.h" 46 #include "intel_dsi_vbt.h" 47 #include "vlv_dsi.h" 48 #include "vlv_dsi_regs.h" 49 #include "vlv_sideband.h" 50 51 #define MIPI_TRANSFER_MODE_SHIFT 0 52 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 53 #define MIPI_PORT_SHIFT 3 54 55 /* base offsets for gpio pads */ 56 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 57 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 58 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 59 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 60 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 61 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 62 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 63 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 64 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 65 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 66 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 67 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 68 69 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 70 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 71 72 struct gpio_map { 73 u16 base_offset; 74 bool init; 75 }; 76 77 static struct gpio_map vlv_gpio_table[] = { 78 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 79 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 80 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 81 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 82 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 83 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 84 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 85 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 86 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 87 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 88 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 89 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 90 }; 91 92 struct i2c_adapter_lookup { 93 u16 slave_addr; 94 struct intel_dsi *intel_dsi; 95 acpi_handle dev_handle; 96 }; 97 98 #define CHV_GPIO_IDX_START_N 0 99 #define CHV_GPIO_IDX_START_E 73 100 #define CHV_GPIO_IDX_START_SW 100 101 #define CHV_GPIO_IDX_START_SE 198 102 103 #define CHV_VBT_MAX_PINS_PER_FMLY 15 104 105 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 106 #define CHV_GPIO_GPIOEN (1 << 15) 107 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 108 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 109 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 110 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 111 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 112 113 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 114 #define CHV_GPIO_CFGLOCK (1 << 31) 115 116 /* ICL DSI Display GPIO Pins */ 117 #define ICL_GPIO_DDSP_HPD_A 0 118 #define ICL_GPIO_L_VDDEN_1 1 119 #define ICL_GPIO_L_BKLTEN_1 2 120 #define ICL_GPIO_DDPA_CTRLCLK_1 3 121 #define ICL_GPIO_DDPA_CTRLDATA_1 4 122 #define ICL_GPIO_DDSP_HPD_B 5 123 #define ICL_GPIO_L_VDDEN_2 6 124 #define ICL_GPIO_L_BKLTEN_2 7 125 #define ICL_GPIO_DDPA_CTRLCLK_2 8 126 #define ICL_GPIO_DDPA_CTRLDATA_2 9 127 128 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 129 u8 seq_port) 130 { 131 /* 132 * If single link DSI is being used on any port, the VBT sequence block 133 * send packet apparently always has 0 for the port. Just use the port 134 * we have configured, and ignore the sequence block port. 135 */ 136 if (hweight8(intel_dsi->ports) == 1) 137 return ffs(intel_dsi->ports) - 1; 138 139 if (seq_port) { 140 if (intel_dsi->ports & PORT_B) 141 return PORT_B; 142 else if (intel_dsi->ports & PORT_C) 143 return PORT_C; 144 } 145 146 return PORT_A; 147 } 148 149 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 150 const u8 *data) 151 { 152 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 153 struct mipi_dsi_device *dsi_device; 154 u8 type, flags, seq_port; 155 u16 len; 156 enum port port; 157 158 drm_dbg_kms(&dev_priv->drm, "\n"); 159 160 flags = *data++; 161 type = *data++; 162 163 len = *((u16 *) data); 164 data += 2; 165 166 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 167 168 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 169 170 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) 171 goto out; 172 173 dsi_device = intel_dsi->dsi_hosts[port]->device; 174 if (!dsi_device) { 175 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 176 port_name(port)); 177 goto out; 178 } 179 180 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 181 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 182 else 183 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 184 185 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 186 187 switch (type) { 188 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 189 mipi_dsi_generic_write(dsi_device, NULL, 0); 190 break; 191 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 192 mipi_dsi_generic_write(dsi_device, data, 1); 193 break; 194 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 195 mipi_dsi_generic_write(dsi_device, data, 2); 196 break; 197 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 198 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 199 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 200 drm_dbg(&dev_priv->drm, 201 "Generic Read not yet implemented or used\n"); 202 break; 203 case MIPI_DSI_GENERIC_LONG_WRITE: 204 mipi_dsi_generic_write(dsi_device, data, len); 205 break; 206 case MIPI_DSI_DCS_SHORT_WRITE: 207 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 208 break; 209 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 210 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 211 break; 212 case MIPI_DSI_DCS_READ: 213 drm_dbg(&dev_priv->drm, 214 "DCS Read not yet implemented or used\n"); 215 break; 216 case MIPI_DSI_DCS_LONG_WRITE: 217 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 218 break; 219 } 220 221 if (DISPLAY_VER(dev_priv) < 11) 222 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 223 224 out: 225 data += len; 226 227 return data; 228 } 229 230 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 231 { 232 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 233 u32 delay = *((const u32 *) data); 234 235 drm_dbg_kms(&i915->drm, "\n"); 236 237 usleep_range(delay, delay + 10); 238 data += 4; 239 240 return data; 241 } 242 243 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 244 u8 gpio_source, u8 gpio_index, bool value) 245 { 246 struct gpio_map *map; 247 u16 pconf0, padval; 248 u32 tmp; 249 u8 port; 250 251 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 252 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 253 gpio_index); 254 return; 255 } 256 257 map = &vlv_gpio_table[gpio_index]; 258 259 if (dev_priv->vbt.dsi.seq_version >= 3) { 260 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 261 port = IOSF_PORT_GPIO_NC; 262 } else { 263 if (gpio_source == 0) { 264 port = IOSF_PORT_GPIO_NC; 265 } else if (gpio_source == 1) { 266 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 267 return; 268 } else { 269 drm_dbg_kms(&dev_priv->drm, 270 "unknown gpio source %u\n", gpio_source); 271 return; 272 } 273 } 274 275 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 276 padval = VLV_GPIO_PAD_VAL(map->base_offset); 277 278 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 279 if (!map->init) { 280 /* FIXME: remove constant below */ 281 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 282 map->init = true; 283 } 284 285 tmp = 0x4 | value; 286 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 287 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 288 } 289 290 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 291 u8 gpio_source, u8 gpio_index, bool value) 292 { 293 u16 cfg0, cfg1; 294 u16 family_num; 295 u8 port; 296 297 if (dev_priv->vbt.dsi.seq_version >= 3) { 298 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 299 /* XXX: it's unclear whether 255->57 is part of SE. */ 300 gpio_index -= CHV_GPIO_IDX_START_SE; 301 port = CHV_IOSF_PORT_GPIO_SE; 302 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 303 gpio_index -= CHV_GPIO_IDX_START_SW; 304 port = CHV_IOSF_PORT_GPIO_SW; 305 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 306 gpio_index -= CHV_GPIO_IDX_START_E; 307 port = CHV_IOSF_PORT_GPIO_E; 308 } else { 309 port = CHV_IOSF_PORT_GPIO_N; 310 } 311 } else { 312 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 313 if (gpio_source != 0) { 314 drm_dbg_kms(&dev_priv->drm, 315 "unknown gpio source %u\n", gpio_source); 316 return; 317 } 318 319 if (gpio_index >= CHV_GPIO_IDX_START_E) { 320 drm_dbg_kms(&dev_priv->drm, 321 "invalid gpio index %u for GPIO N\n", 322 gpio_index); 323 return; 324 } 325 326 port = CHV_IOSF_PORT_GPIO_N; 327 } 328 329 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 330 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 331 332 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 333 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 334 335 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 336 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 337 vlv_iosf_sb_write(dev_priv, port, cfg0, 338 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 339 CHV_GPIO_GPIOTXSTATE(value)); 340 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 341 } 342 343 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 344 u8 gpio_source, u8 gpio_index, bool value) 345 { 346 /* XXX: this table is a quick ugly hack. */ 347 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 348 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 349 350 if (!gpio_desc) { 351 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 352 NULL, gpio_index, 353 value ? GPIOD_OUT_LOW : 354 GPIOD_OUT_HIGH); 355 356 if (IS_ERR_OR_NULL(gpio_desc)) { 357 drm_err(&dev_priv->drm, 358 "GPIO index %u request failed (%ld)\n", 359 gpio_index, PTR_ERR(gpio_desc)); 360 return; 361 } 362 363 bxt_gpio_table[gpio_index] = gpio_desc; 364 } 365 366 gpiod_set_value(gpio_desc, value); 367 } 368 369 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 370 u8 gpio_source, u8 gpio_index, bool value) 371 { 372 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 373 } 374 375 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 376 { 377 struct drm_device *dev = intel_dsi->base.base.dev; 378 struct drm_i915_private *dev_priv = to_i915(dev); 379 u8 gpio_source, gpio_index = 0, gpio_number; 380 bool value; 381 382 drm_dbg_kms(&dev_priv->drm, "\n"); 383 384 if (dev_priv->vbt.dsi.seq_version >= 3) 385 gpio_index = *data++; 386 387 gpio_number = *data++; 388 389 /* gpio source in sequence v2 only */ 390 if (dev_priv->vbt.dsi.seq_version == 2) 391 gpio_source = (*data >> 1) & 3; 392 else 393 gpio_source = 0; 394 395 /* pull up/down */ 396 value = *data++ & 1; 397 398 if (DISPLAY_VER(dev_priv) >= 11) 399 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 400 else if (IS_VALLEYVIEW(dev_priv)) 401 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 402 else if (IS_CHERRYVIEW(dev_priv)) 403 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 404 else 405 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 406 407 return data; 408 } 409 410 #ifdef CONFIG_ACPI 411 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 412 { 413 struct i2c_adapter_lookup *lookup = data; 414 struct intel_dsi *intel_dsi = lookup->intel_dsi; 415 struct acpi_resource_i2c_serialbus *sb; 416 struct i2c_adapter *adapter; 417 acpi_handle adapter_handle; 418 acpi_status status; 419 420 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 421 return 1; 422 423 if (lookup->slave_addr != sb->slave_address) 424 return 1; 425 426 status = acpi_get_handle(lookup->dev_handle, 427 sb->resource_source.string_ptr, 428 &adapter_handle); 429 if (ACPI_FAILURE(status)) 430 return 1; 431 432 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 433 if (adapter) 434 intel_dsi->i2c_bus_num = adapter->nr; 435 436 return 1; 437 } 438 439 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 440 const u16 slave_addr) 441 { 442 struct drm_device *drm_dev = intel_dsi->base.base.dev; 443 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 444 struct i2c_adapter_lookup lookup = { 445 .slave_addr = slave_addr, 446 .intel_dsi = intel_dsi, 447 .dev_handle = acpi_device_handle(adev), 448 }; 449 LIST_HEAD(resource_list); 450 451 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 452 acpi_dev_free_resource_list(&resource_list); 453 } 454 #else 455 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 456 const u16 slave_addr) 457 { 458 } 459 #endif 460 461 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 462 { 463 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 464 struct i2c_adapter *adapter; 465 struct i2c_msg msg; 466 int ret; 467 u8 vbt_i2c_bus_num = *(data + 2); 468 u16 slave_addr = *(u16 *)(data + 3); 469 u8 reg_offset = *(data + 5); 470 u8 payload_size = *(data + 6); 471 u8 *payload_data; 472 473 if (intel_dsi->i2c_bus_num < 0) { 474 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 475 i2c_acpi_find_adapter(intel_dsi, slave_addr); 476 } 477 478 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 479 if (!adapter) { 480 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 481 goto err_bus; 482 } 483 484 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 485 if (!payload_data) 486 goto err_alloc; 487 488 payload_data[0] = reg_offset; 489 memcpy(&payload_data[1], (data + 7), payload_size); 490 491 msg.addr = slave_addr; 492 msg.flags = 0; 493 msg.len = payload_size + 1; 494 msg.buf = payload_data; 495 496 ret = i2c_transfer(adapter, &msg, 1); 497 if (ret < 0) 498 drm_err(&i915->drm, 499 "Failed to xfer payload of size (%u) to reg (%u)\n", 500 payload_size, reg_offset); 501 502 kfree(payload_data); 503 err_alloc: 504 i2c_put_adapter(adapter); 505 err_bus: 506 return data + payload_size + 7; 507 } 508 509 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 510 { 511 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 512 513 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 514 515 return data + *(data + 5) + 6; 516 } 517 518 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 519 { 520 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 521 #ifdef CONFIG_PMIC_OPREGION 522 u32 value, mask, reg_address; 523 u16 i2c_address; 524 int ret; 525 526 /* byte 0 aka PMIC Flag is reserved */ 527 i2c_address = get_unaligned_le16(data + 1); 528 reg_address = get_unaligned_le32(data + 3); 529 value = get_unaligned_le32(data + 7); 530 mask = get_unaligned_le32(data + 11); 531 532 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 533 reg_address, 534 value, mask); 535 if (ret) 536 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 537 #else 538 drm_err(&i915->drm, 539 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 540 #endif 541 542 return data + 15; 543 } 544 545 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 546 const u8 *data); 547 static const fn_mipi_elem_exec exec_elem[] = { 548 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 549 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 550 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 551 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 552 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 553 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 554 }; 555 556 /* 557 * MIPI Sequence from VBT #53 parsing logic 558 * We have already separated each seqence during bios parsing 559 * Following is generic execution function for any sequence 560 */ 561 562 static const char * const seq_name[] = { 563 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 564 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 565 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 566 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 567 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 568 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 569 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 570 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 571 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 572 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 573 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 574 }; 575 576 static const char *sequence_name(enum mipi_seq seq_id) 577 { 578 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 579 return seq_name[seq_id]; 580 else 581 return "(unknown)"; 582 } 583 584 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 585 enum mipi_seq seq_id) 586 { 587 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 588 const u8 *data; 589 fn_mipi_elem_exec mipi_elem_exec; 590 591 if (drm_WARN_ON(&dev_priv->drm, 592 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 593 return; 594 595 data = dev_priv->vbt.dsi.sequence[seq_id]; 596 if (!data) 597 return; 598 599 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 600 601 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 602 seq_id, sequence_name(seq_id)); 603 604 /* Skip Sequence Byte. */ 605 data++; 606 607 /* Skip Size of Sequence. */ 608 if (dev_priv->vbt.dsi.seq_version >= 3) 609 data += 4; 610 611 while (1) { 612 u8 operation_byte = *data++; 613 u8 operation_size = 0; 614 615 if (operation_byte == MIPI_SEQ_ELEM_END) 616 break; 617 618 if (operation_byte < ARRAY_SIZE(exec_elem)) 619 mipi_elem_exec = exec_elem[operation_byte]; 620 else 621 mipi_elem_exec = NULL; 622 623 /* Size of Operation. */ 624 if (dev_priv->vbt.dsi.seq_version >= 3) 625 operation_size = *data++; 626 627 if (mipi_elem_exec) { 628 const u8 *next = data + operation_size; 629 630 data = mipi_elem_exec(intel_dsi, data); 631 632 /* Consistency check if we have size. */ 633 if (operation_size && data != next) { 634 drm_err(&dev_priv->drm, 635 "Inconsistent operation size\n"); 636 return; 637 } 638 } else if (operation_size) { 639 /* We have size, skip. */ 640 drm_dbg_kms(&dev_priv->drm, 641 "Unsupported MIPI operation byte %u\n", 642 operation_byte); 643 data += operation_size; 644 } else { 645 /* No size, can't skip without parsing. */ 646 drm_err(&dev_priv->drm, 647 "Unsupported MIPI operation byte %u\n", 648 operation_byte); 649 return; 650 } 651 } 652 } 653 654 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 655 enum mipi_seq seq_id) 656 { 657 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 658 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 659 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 660 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 661 662 intel_dsi_vbt_exec(intel_dsi, seq_id); 663 664 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 665 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 666 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 667 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 668 } 669 670 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 671 { 672 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 673 674 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 675 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 676 return; 677 678 msleep(msec); 679 } 680 681 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 682 { 683 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 684 685 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 686 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 687 intel_dsi->pixel_overlap); 688 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 689 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 690 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 691 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 692 "non-burst with sync pulse" : 693 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 694 "non-burst with sync events" : 695 intel_dsi->video_mode == BURST_MODE ? 696 "burst" : "<unknown>"); 697 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 698 intel_dsi->burst_mode_ratio); 699 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 700 drm_dbg_kms(&i915->drm, "Eot %s\n", 701 str_enabled_disabled(intel_dsi->eotp_pkt)); 702 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 703 str_enabled_disabled(!intel_dsi->clock_stop)); 704 drm_dbg_kms(&i915->drm, "Mode %s\n", 705 intel_dsi->operation_mode ? "command" : "video"); 706 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 707 drm_dbg_kms(&i915->drm, 708 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 709 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 710 drm_dbg_kms(&i915->drm, 711 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 712 else 713 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 714 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 715 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 716 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 717 intel_dsi->lp_rx_timeout); 718 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 719 intel_dsi->turn_arnd_val); 720 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 721 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 722 intel_dsi->hs_to_lp_count); 723 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 724 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 725 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 726 intel_dsi->clk_lp_to_hs_count); 727 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 728 intel_dsi->clk_hs_to_lp_count); 729 drm_dbg_kms(&i915->drm, "BTA %s\n", 730 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 731 } 732 733 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 734 { 735 struct drm_device *dev = intel_dsi->base.base.dev; 736 struct drm_i915_private *dev_priv = to_i915(dev); 737 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 738 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 739 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 740 u16 burst_mode_ratio; 741 enum port port; 742 743 drm_dbg_kms(&dev_priv->drm, "\n"); 744 745 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 746 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 747 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 748 intel_dsi->pixel_format = 749 pixel_format_from_register_bits( 750 mipi_config->videomode_color_format << 7); 751 752 intel_dsi->dual_link = mipi_config->dual_link; 753 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 754 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 755 intel_dsi->video_mode = mipi_config->video_transfer_mode; 756 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 757 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 758 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 759 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 760 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 761 intel_dsi->init_count = mipi_config->master_init_timer; 762 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 763 intel_dsi->video_frmt_cfg_bits = 764 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 765 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 766 767 /* Starting point, adjusted depending on dual link and burst mode */ 768 intel_dsi->pclk = mode->clock; 769 770 /* In dual link mode each port needs half of pixel clock */ 771 if (intel_dsi->dual_link) { 772 intel_dsi->pclk /= 2; 773 774 /* we can enable pixel_overlap if needed by panel. In this 775 * case we need to increase the pixelclock for extra pixels 776 */ 777 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 778 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 779 } 780 } 781 782 /* Burst Mode Ratio 783 * Target ddr frequency from VBT / non burst ddr freq 784 * multiply by 100 to preserve remainder 785 */ 786 if (intel_dsi->video_mode == BURST_MODE) { 787 if (mipi_config->target_burst_mode_freq) { 788 u32 bitrate = intel_dsi_bitrate(intel_dsi); 789 790 /* 791 * Sometimes the VBT contains a slightly lower clock, 792 * then the bitrate we have calculated, in this case 793 * just replace it with the calculated bitrate. 794 */ 795 if (mipi_config->target_burst_mode_freq < bitrate && 796 intel_fuzzy_clock_check( 797 mipi_config->target_burst_mode_freq, 798 bitrate)) 799 mipi_config->target_burst_mode_freq = bitrate; 800 801 if (mipi_config->target_burst_mode_freq < bitrate) { 802 drm_err(&dev_priv->drm, 803 "Burst mode freq is less than computed\n"); 804 return false; 805 } 806 807 burst_mode_ratio = DIV_ROUND_UP( 808 mipi_config->target_burst_mode_freq * 100, 809 bitrate); 810 811 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 812 } else { 813 drm_err(&dev_priv->drm, 814 "Burst mode target is not set\n"); 815 return false; 816 } 817 } else 818 burst_mode_ratio = 100; 819 820 intel_dsi->burst_mode_ratio = burst_mode_ratio; 821 822 /* delays in VBT are in unit of 100us, so need to convert 823 * here in ms 824 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 825 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 826 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 827 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 828 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 829 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 830 831 intel_dsi->i2c_bus_num = -1; 832 833 /* a regular driver would get the device in probe */ 834 for_each_dsi_port(port, intel_dsi->ports) { 835 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 836 } 837 838 return true; 839 } 840 841 /* 842 * On some BYT/CHT devs some sequences are incomplete and we need to manually 843 * control some GPIOs. We need to add a GPIO lookup table before we get these. 844 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 845 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 846 */ 847 static struct gpiod_lookup_table pmic_panel_gpio_table = { 848 /* Intel GFX is consumer */ 849 .dev_id = "0000:00:02.0", 850 .table = { 851 /* Panel EN/DISABLE */ 852 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 853 { } 854 }, 855 }; 856 857 static struct gpiod_lookup_table soc_panel_gpio_table = { 858 .dev_id = "0000:00:02.0", 859 .table = { 860 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 861 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 862 { } 863 }, 864 }; 865 866 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 867 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 868 "pwm0_grp", "pwm"), 869 }; 870 871 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 872 { 873 struct drm_device *dev = intel_dsi->base.base.dev; 874 struct drm_i915_private *dev_priv = to_i915(dev); 875 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 876 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 877 bool want_backlight_gpio = false; 878 bool want_panel_gpio = false; 879 struct pinctrl *pinctrl; 880 int ret; 881 882 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 883 mipi_config->pwm_blc == PPS_BLC_PMIC) { 884 gpiod_add_lookup_table(&pmic_panel_gpio_table); 885 want_panel_gpio = true; 886 } 887 888 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 889 gpiod_add_lookup_table(&soc_panel_gpio_table); 890 want_panel_gpio = true; 891 want_backlight_gpio = true; 892 893 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 894 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 895 ARRAY_SIZE(soc_pwm_pinctrl_map)); 896 if (ret) 897 drm_err(&dev_priv->drm, 898 "Failed to register pwm0 pinmux mapping\n"); 899 900 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 901 if (IS_ERR(pinctrl)) 902 drm_err(&dev_priv->drm, 903 "Failed to set pinmux to PWM\n"); 904 } 905 906 if (want_panel_gpio) { 907 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 908 if (IS_ERR(intel_dsi->gpio_panel)) { 909 drm_err(&dev_priv->drm, 910 "Failed to own gpio for panel control\n"); 911 intel_dsi->gpio_panel = NULL; 912 } 913 } 914 915 if (want_backlight_gpio) { 916 intel_dsi->gpio_backlight = 917 gpiod_get(dev->dev, "backlight", flags); 918 if (IS_ERR(intel_dsi->gpio_backlight)) { 919 drm_err(&dev_priv->drm, 920 "Failed to own gpio for backlight control\n"); 921 intel_dsi->gpio_backlight = NULL; 922 } 923 } 924 } 925 926 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 927 { 928 struct drm_device *dev = intel_dsi->base.base.dev; 929 struct drm_i915_private *dev_priv = to_i915(dev); 930 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 931 932 if (intel_dsi->gpio_panel) { 933 gpiod_put(intel_dsi->gpio_panel); 934 intel_dsi->gpio_panel = NULL; 935 } 936 937 if (intel_dsi->gpio_backlight) { 938 gpiod_put(intel_dsi->gpio_backlight); 939 intel_dsi->gpio_backlight = NULL; 940 } 941 942 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 943 mipi_config->pwm_blc == PPS_BLC_PMIC) 944 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 945 946 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 947 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 948 gpiod_remove_lookup_table(&soc_panel_gpio_table); 949 } 950 } 951