1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <linux/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 40 #include <video/mipi_display.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_dsi.h" 47 #include "intel_dsi_vbt.h" 48 #include "intel_gmbus_regs.h" 49 #include "intel_pps_regs.h" 50 #include "vlv_dsi.h" 51 #include "vlv_dsi_regs.h" 52 #include "vlv_sideband.h" 53 54 #define MIPI_TRANSFER_MODE_SHIFT 0 55 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 56 #define MIPI_PORT_SHIFT 3 57 58 struct i2c_adapter_lookup { 59 u16 target_addr; 60 struct intel_dsi *intel_dsi; 61 acpi_handle dev_handle; 62 }; 63 64 #define CHV_GPIO_IDX_START_N 0 65 #define CHV_GPIO_IDX_START_E 73 66 #define CHV_GPIO_IDX_START_SW 100 67 #define CHV_GPIO_IDX_START_SE 198 68 69 /* ICL DSI Display GPIO Pins */ 70 #define ICL_GPIO_DDSP_HPD_A 0 71 #define ICL_GPIO_L_VDDEN_1 1 72 #define ICL_GPIO_L_BKLTEN_1 2 73 #define ICL_GPIO_DDPA_CTRLCLK_1 3 74 #define ICL_GPIO_DDPA_CTRLDATA_1 4 75 #define ICL_GPIO_DDSP_HPD_B 5 76 #define ICL_GPIO_L_VDDEN_2 6 77 #define ICL_GPIO_L_BKLTEN_2 7 78 #define ICL_GPIO_DDPA_CTRLCLK_2 8 79 #define ICL_GPIO_DDPA_CTRLDATA_2 9 80 81 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 82 u8 seq_port) 83 { 84 /* 85 * If single link DSI is being used on any port, the VBT sequence block 86 * send packet apparently always has 0 for the port. Just use the port 87 * we have configured, and ignore the sequence block port. 88 */ 89 if (hweight8(intel_dsi->ports) == 1) 90 return ffs(intel_dsi->ports) - 1; 91 92 if (seq_port) { 93 if (intel_dsi->ports & BIT(PORT_B)) 94 return PORT_B; 95 if (intel_dsi->ports & BIT(PORT_C)) 96 return PORT_C; 97 } 98 99 return PORT_A; 100 } 101 102 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 103 const u8 *data) 104 { 105 struct intel_display *display = to_intel_display(&intel_dsi->base); 106 struct mipi_dsi_device *dsi_device; 107 u8 type, flags, seq_port; 108 u16 len; 109 enum port port; 110 111 drm_dbg_kms(display->drm, "\n"); 112 113 flags = *data++; 114 type = *data++; 115 116 len = *((u16 *) data); 117 data += 2; 118 119 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 120 121 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 122 123 if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port])) 124 goto out; 125 126 dsi_device = intel_dsi->dsi_hosts[port]->device; 127 if (!dsi_device) { 128 drm_dbg_kms(display->drm, "no dsi device for port %c\n", 129 port_name(port)); 130 goto out; 131 } 132 133 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 134 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 135 else 136 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 137 138 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 139 140 switch (type) { 141 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 142 mipi_dsi_generic_write(dsi_device, NULL, 0); 143 break; 144 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 145 mipi_dsi_generic_write(dsi_device, data, 1); 146 break; 147 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 148 mipi_dsi_generic_write(dsi_device, data, 2); 149 break; 150 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 151 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 152 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 153 drm_dbg_kms(display->drm, "Generic Read not yet implemented or used\n"); 154 break; 155 case MIPI_DSI_GENERIC_LONG_WRITE: 156 mipi_dsi_generic_write(dsi_device, data, len); 157 break; 158 case MIPI_DSI_DCS_SHORT_WRITE: 159 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 160 break; 161 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 162 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 163 break; 164 case MIPI_DSI_DCS_READ: 165 drm_dbg_kms(display->drm, "DCS Read not yet implemented or used\n"); 166 break; 167 case MIPI_DSI_DCS_LONG_WRITE: 168 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 169 break; 170 } 171 172 if (DISPLAY_VER(display) < 11) 173 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 174 175 out: 176 data += len; 177 178 return data; 179 } 180 181 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 182 { 183 struct intel_display *display = to_intel_display(&intel_dsi->base); 184 u32 delay = *((const u32 *) data); 185 186 drm_dbg_kms(display->drm, "%d usecs\n", delay); 187 188 usleep_range(delay, delay + 10); 189 data += 4; 190 191 return data; 192 } 193 194 static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index, 195 const char *con_id, u8 idx, bool value) 196 { 197 struct intel_display *display = to_intel_display(connector); 198 /* XXX: this table is a quick ugly hack. */ 199 static struct gpio_desc *soc_gpio_table[U8_MAX + 1]; 200 struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index]; 201 202 if (gpio_desc) { 203 gpiod_set_value(gpio_desc, value); 204 } else { 205 gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx, 206 value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW); 207 if (IS_ERR(gpio_desc)) { 208 drm_err(display->drm, 209 "GPIO index %u request failed (%pe)\n", 210 gpio_index, gpio_desc); 211 return; 212 } 213 214 soc_gpio_table[gpio_index] = gpio_desc; 215 } 216 } 217 218 static void soc_opaque_gpio_set_value(struct intel_connector *connector, 219 u8 gpio_index, const char *chip, 220 const char *con_id, u8 idx, bool value) 221 { 222 struct gpiod_lookup_table *lookup; 223 224 lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL); 225 if (!lookup) 226 return; 227 228 lookup->dev_id = "0000:00:02.0"; 229 lookup->table[0] = 230 GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH); 231 232 gpiod_add_lookup_table(lookup); 233 234 soc_gpio_set_value(connector, gpio_index, con_id, idx, value); 235 236 gpiod_remove_lookup_table(lookup); 237 kfree(lookup); 238 } 239 240 static void vlv_gpio_set_value(struct intel_connector *connector, 241 u8 gpio_source, u8 gpio_index, bool value) 242 { 243 struct intel_display *display = to_intel_display(connector); 244 245 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 246 if (connector->panel.vbt.dsi.seq_version < 3) { 247 if (gpio_source == 1) { 248 drm_dbg_kms(display->drm, "SC gpio not supported\n"); 249 return; 250 } 251 if (gpio_source > 1) { 252 drm_dbg_kms(display->drm, 253 "unknown gpio source %u\n", gpio_source); 254 return; 255 } 256 } 257 258 soc_opaque_gpio_set_value(connector, gpio_index, 259 "INT33FC:01", "Panel N", gpio_index, value); 260 } 261 262 static void chv_gpio_set_value(struct intel_connector *connector, 263 u8 gpio_source, u8 gpio_index, bool value) 264 { 265 struct intel_display *display = to_intel_display(connector); 266 267 if (connector->panel.vbt.dsi.seq_version >= 3) { 268 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 269 /* XXX: it's unclear whether 255->57 is part of SE. */ 270 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:03", "Panel SE", 271 gpio_index - CHV_GPIO_IDX_START_SE, value); 272 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 273 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:00", "Panel SW", 274 gpio_index - CHV_GPIO_IDX_START_SW, value); 275 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 276 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:02", "Panel E", 277 gpio_index - CHV_GPIO_IDX_START_E, value); 278 } else { 279 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 280 gpio_index - CHV_GPIO_IDX_START_N, value); 281 } 282 } else { 283 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 284 if (gpio_source != 0) { 285 drm_dbg_kms(display->drm, 286 "unknown gpio source %u\n", gpio_source); 287 return; 288 } 289 290 if (gpio_index >= CHV_GPIO_IDX_START_E) { 291 drm_dbg_kms(display->drm, 292 "invalid gpio index %u for GPIO N\n", 293 gpio_index); 294 return; 295 } 296 297 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 298 gpio_index - CHV_GPIO_IDX_START_N, value); 299 } 300 } 301 302 static void bxt_gpio_set_value(struct intel_connector *connector, 303 u8 gpio_index, bool value) 304 { 305 soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value); 306 } 307 308 enum { 309 MIPI_RESET_1 = 0, 310 MIPI_AVDD_EN_1, 311 MIPI_BKLT_EN_1, 312 MIPI_AVEE_EN_1, 313 MIPI_VIO_EN_1, 314 MIPI_RESET_2, 315 MIPI_AVDD_EN_2, 316 MIPI_BKLT_EN_2, 317 MIPI_AVEE_EN_2, 318 MIPI_VIO_EN_2, 319 }; 320 321 static void icl_native_gpio_set_value(struct intel_display *display, 322 int gpio, bool value) 323 { 324 struct drm_i915_private *dev_priv = to_i915(display->drm); 325 int index; 326 327 if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2)) 328 return; 329 330 switch (gpio) { 331 case MIPI_RESET_1: 332 case MIPI_RESET_2: 333 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B; 334 335 /* 336 * Disable HPD to set the pin to output, and set output 337 * value. The HPD pin should not be enabled for DSI anyway, 338 * assuming the board design and VBT are sane, and the pin isn't 339 * used by a non-DSI encoder. 340 * 341 * The locking protects against concurrent SHOTPLUG_CTL_DDI 342 * modifications in irq setup and handling. 343 */ 344 spin_lock_irq(&dev_priv->irq_lock); 345 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 346 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | 347 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), 348 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); 349 spin_unlock_irq(&dev_priv->irq_lock); 350 break; 351 case MIPI_AVDD_EN_1: 352 case MIPI_AVDD_EN_2: 353 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; 354 355 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, 356 value ? PANEL_POWER_ON : 0); 357 break; 358 case MIPI_BKLT_EN_1: 359 case MIPI_BKLT_EN_2: 360 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; 361 362 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, 363 value ? EDP_BLC_ENABLE : 0); 364 break; 365 case MIPI_AVEE_EN_1: 366 case MIPI_AVEE_EN_2: 367 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2; 368 369 intel_de_rmw(display, GPIO(display, index), 370 GPIO_CLOCK_VAL_OUT, 371 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | 372 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0)); 373 break; 374 case MIPI_VIO_EN_1: 375 case MIPI_VIO_EN_2: 376 index = gpio == MIPI_VIO_EN_1 ? 1 : 2; 377 378 intel_de_rmw(display, GPIO(display, index), 379 GPIO_DATA_VAL_OUT, 380 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | 381 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0)); 382 break; 383 default: 384 MISSING_CASE(gpio); 385 } 386 } 387 388 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 389 { 390 struct intel_display *display = to_intel_display(&intel_dsi->base); 391 struct intel_connector *connector = intel_dsi->attached_connector; 392 u8 gpio_source = 0, gpio_index = 0, gpio_number; 393 bool value; 394 int size; 395 bool native = DISPLAY_VER(display) >= 11; 396 397 if (connector->panel.vbt.dsi.seq_version >= 3) { 398 size = 3; 399 400 gpio_index = data[0]; 401 gpio_number = data[1]; 402 value = data[2] & BIT(0); 403 404 if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1)) 405 native = false; 406 } else { 407 size = 2; 408 409 gpio_number = data[0]; 410 value = data[1] & BIT(0); 411 412 if (connector->panel.vbt.dsi.seq_version == 2) 413 gpio_source = (data[1] >> 1) & 3; 414 } 415 416 drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n", 417 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value)); 418 419 if (native) 420 icl_native_gpio_set_value(display, gpio_number, value); 421 else if (DISPLAY_VER(display) >= 9) 422 bxt_gpio_set_value(connector, gpio_index, value); 423 else if (display->platform.valleyview) 424 vlv_gpio_set_value(connector, gpio_source, gpio_number, value); 425 else if (display->platform.cherryview) 426 chv_gpio_set_value(connector, gpio_source, gpio_number, value); 427 428 return data + size; 429 } 430 431 #ifdef CONFIG_ACPI 432 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 433 { 434 struct i2c_adapter_lookup *lookup = data; 435 struct intel_dsi *intel_dsi = lookup->intel_dsi; 436 struct acpi_resource_i2c_serialbus *sb; 437 struct i2c_adapter *adapter; 438 acpi_handle adapter_handle; 439 acpi_status status; 440 441 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 442 return 1; 443 444 if (lookup->target_addr != sb->slave_address) 445 return 1; 446 447 status = acpi_get_handle(lookup->dev_handle, 448 sb->resource_source.string_ptr, 449 &adapter_handle); 450 if (ACPI_FAILURE(status)) 451 return 1; 452 453 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 454 if (adapter) 455 intel_dsi->i2c_bus_num = adapter->nr; 456 457 return 1; 458 } 459 460 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 461 const u16 target_addr) 462 { 463 struct intel_display *display = to_intel_display(&intel_dsi->base); 464 struct acpi_device *adev = ACPI_COMPANION(display->drm->dev); 465 struct i2c_adapter_lookup lookup = { 466 .target_addr = target_addr, 467 .intel_dsi = intel_dsi, 468 .dev_handle = acpi_device_handle(adev), 469 }; 470 LIST_HEAD(resource_list); 471 472 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 473 acpi_dev_free_resource_list(&resource_list); 474 } 475 #else 476 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 477 const u16 target_addr) 478 { 479 } 480 #endif 481 482 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 483 { 484 struct intel_display *display = to_intel_display(&intel_dsi->base); 485 struct i2c_adapter *adapter; 486 struct i2c_msg msg; 487 int ret; 488 u8 vbt_i2c_bus_num = *(data + 2); 489 u16 target_addr = *(u16 *)(data + 3); 490 u8 reg_offset = *(data + 5); 491 u8 payload_size = *(data + 6); 492 u8 *payload_data; 493 494 drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n", 495 vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7); 496 497 if (intel_dsi->i2c_bus_num < 0) { 498 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 499 i2c_acpi_find_adapter(intel_dsi, target_addr); 500 } 501 502 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 503 if (!adapter) { 504 drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n"); 505 goto err_bus; 506 } 507 508 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 509 if (!payload_data) 510 goto err_alloc; 511 512 payload_data[0] = reg_offset; 513 memcpy(&payload_data[1], (data + 7), payload_size); 514 515 msg.addr = target_addr; 516 msg.flags = 0; 517 msg.len = payload_size + 1; 518 msg.buf = payload_data; 519 520 ret = i2c_transfer(adapter, &msg, 1); 521 if (ret < 0) 522 drm_err(display->drm, 523 "Failed to xfer payload of size (%u) to reg (%u)\n", 524 payload_size, reg_offset); 525 526 kfree(payload_data); 527 err_alloc: 528 i2c_put_adapter(adapter); 529 err_bus: 530 return data + payload_size + 7; 531 } 532 533 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 534 { 535 struct intel_display *display = to_intel_display(&intel_dsi->base); 536 537 drm_dbg_kms(display->drm, "Skipping SPI element execution\n"); 538 539 return data + *(data + 5) + 6; 540 } 541 542 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 543 { 544 struct intel_display *display = to_intel_display(&intel_dsi->base); 545 #ifdef CONFIG_PMIC_OPREGION 546 u32 value, mask, reg_address; 547 u16 i2c_address; 548 int ret; 549 550 /* byte 0 aka PMIC Flag is reserved */ 551 i2c_address = get_unaligned_le16(data + 1); 552 reg_address = get_unaligned_le32(data + 3); 553 value = get_unaligned_le32(data + 7); 554 mask = get_unaligned_le32(data + 11); 555 556 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 557 reg_address, 558 value, mask); 559 if (ret) 560 drm_err(display->drm, "%s failed, error: %d\n", __func__, ret); 561 #else 562 drm_err(display->drm, 563 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 564 #endif 565 566 return data + 15; 567 } 568 569 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 570 const u8 *data); 571 static const fn_mipi_elem_exec exec_elem[] = { 572 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 573 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 574 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 575 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 576 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 577 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 578 }; 579 580 /* 581 * MIPI Sequence from VBT #53 parsing logic 582 * We have already separated each sequence during bios parsing 583 * Following is generic execution function for any sequence 584 */ 585 586 static const char * const seq_name[] = { 587 [MIPI_SEQ_END] = "MIPI_SEQ_END", 588 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 589 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 590 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 591 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 592 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 593 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 594 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 595 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 596 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 597 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 598 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 599 }; 600 601 static const char *sequence_name(enum mipi_seq seq_id) 602 { 603 if (seq_id < ARRAY_SIZE(seq_name)) 604 return seq_name[seq_id]; 605 606 return "(unknown)"; 607 } 608 609 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 610 enum mipi_seq seq_id) 611 { 612 struct intel_display *display = to_intel_display(&intel_dsi->base); 613 struct intel_connector *connector = intel_dsi->attached_connector; 614 const u8 *data; 615 fn_mipi_elem_exec mipi_elem_exec; 616 617 if (drm_WARN_ON(display->drm, 618 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))) 619 return; 620 621 data = connector->panel.vbt.dsi.sequence[seq_id]; 622 if (!data) 623 return; 624 625 drm_WARN_ON(display->drm, *data != seq_id); 626 627 drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n", 628 seq_id, sequence_name(seq_id)); 629 630 /* Skip Sequence Byte. */ 631 data++; 632 633 /* Skip Size of Sequence. */ 634 if (connector->panel.vbt.dsi.seq_version >= 3) 635 data += 4; 636 637 while (*data != MIPI_SEQ_ELEM_END) { 638 u8 operation_byte = *data++; 639 u8 operation_size = 0; 640 641 if (operation_byte < ARRAY_SIZE(exec_elem)) 642 mipi_elem_exec = exec_elem[operation_byte]; 643 else 644 mipi_elem_exec = NULL; 645 646 /* Size of Operation. */ 647 if (connector->panel.vbt.dsi.seq_version >= 3) 648 operation_size = *data++; 649 650 if (mipi_elem_exec) { 651 const u8 *next = data + operation_size; 652 653 data = mipi_elem_exec(intel_dsi, data); 654 655 /* Consistency check if we have size. */ 656 if (operation_size && data != next) { 657 drm_err(display->drm, 658 "Inconsistent operation size\n"); 659 return; 660 } 661 } else if (operation_size) { 662 /* We have size, skip. */ 663 drm_dbg_kms(display->drm, 664 "Unsupported MIPI operation byte %u\n", 665 operation_byte); 666 data += operation_size; 667 } else { 668 /* No size, can't skip without parsing. */ 669 drm_err(display->drm, 670 "Unsupported MIPI operation byte %u\n", 671 operation_byte); 672 return; 673 } 674 } 675 } 676 677 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 678 enum mipi_seq seq_id) 679 { 680 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 681 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 682 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 683 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 684 685 intel_dsi_vbt_exec(intel_dsi, seq_id); 686 687 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 688 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 689 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 690 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 691 } 692 693 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 694 { 695 struct intel_display *display = to_intel_display(&intel_dsi->base); 696 struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, 697 "DSI parameters:"); 698 699 drm_printf(&p, "Pclk %d\n", intel_dsi->pclk); 700 drm_printf(&p, "Pixel overlap %d\n", intel_dsi->pixel_overlap); 701 drm_printf(&p, "Lane count %d\n", intel_dsi->lane_count); 702 drm_printf(&p, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 703 drm_printf(&p, "Video mode format %s\n", 704 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 705 "non-burst with sync pulse" : 706 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 707 "non-burst with sync events" : 708 intel_dsi->video_mode == BURST_MODE ? 709 "burst" : "<unknown>"); 710 drm_printf(&p, "Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); 711 drm_printf(&p, "Reset timer %d\n", intel_dsi->rst_timer_val); 712 drm_printf(&p, "Eot %s\n", str_enabled_disabled(intel_dsi->eotp_pkt)); 713 drm_printf(&p, "Clockstop %s\n", str_enabled_disabled(!intel_dsi->clock_stop)); 714 drm_printf(&p, "Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); 715 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 716 drm_printf(&p, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 717 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 718 drm_printf(&p, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 719 else 720 drm_printf(&p, "Dual link: NONE\n"); 721 drm_printf(&p, "Pixel Format %d\n", intel_dsi->pixel_format); 722 drm_printf(&p, "TLPX %d\n", intel_dsi->escape_clk_div); 723 drm_printf(&p, "LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); 724 drm_printf(&p, "Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); 725 drm_printf(&p, "Init Count 0x%x\n", intel_dsi->init_count); 726 drm_printf(&p, "HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); 727 drm_printf(&p, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 728 drm_printf(&p, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 729 drm_printf(&p, "LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); 730 drm_printf(&p, "HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); 731 drm_printf(&p, "BTA %s\n", 732 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 733 } 734 735 static enum mipi_dsi_pixel_format vbt_to_dsi_pixel_format(unsigned int format) 736 { 737 switch (format) { 738 case PIXEL_FORMAT_RGB888: 739 return MIPI_DSI_FMT_RGB888; 740 case PIXEL_FORMAT_RGB666_LOOSELY_PACKED: 741 return MIPI_DSI_FMT_RGB666; 742 case PIXEL_FORMAT_RGB666: 743 return MIPI_DSI_FMT_RGB666_PACKED; 744 case PIXEL_FORMAT_RGB565: 745 return MIPI_DSI_FMT_RGB565; 746 default: 747 MISSING_CASE(format); 748 return MIPI_DSI_FMT_RGB666; 749 } 750 } 751 752 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 753 { 754 struct intel_display *display = to_intel_display(&intel_dsi->base); 755 struct intel_connector *connector = intel_dsi->attached_connector; 756 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 757 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; 758 struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode; 759 u16 burst_mode_ratio; 760 enum port port; 761 762 drm_dbg_kms(display->drm, "\n"); 763 764 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 765 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 766 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 767 intel_dsi->pixel_format = 768 vbt_to_dsi_pixel_format(mipi_config->videomode_color_format); 769 770 intel_dsi->dual_link = mipi_config->dual_link; 771 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 772 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 773 intel_dsi->video_mode = mipi_config->video_transfer_mode; 774 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 775 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 776 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 777 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 778 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 779 intel_dsi->init_count = mipi_config->master_init_timer; 780 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 781 intel_dsi->video_frmt_cfg_bits = 782 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 783 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 784 785 /* Starting point, adjusted depending on dual link and burst mode */ 786 intel_dsi->pclk = mode->clock; 787 788 /* In dual link mode each port needs half of pixel clock */ 789 if (intel_dsi->dual_link) { 790 intel_dsi->pclk /= 2; 791 792 /* we can enable pixel_overlap if needed by panel. In this 793 * case we need to increase the pixelclock for extra pixels 794 */ 795 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 796 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 797 } 798 } 799 800 /* Burst Mode Ratio 801 * Target ddr frequency from VBT / non burst ddr freq 802 * multiply by 100 to preserve remainder 803 */ 804 if (intel_dsi->video_mode == BURST_MODE) { 805 u32 bitrate; 806 807 if (mipi_config->target_burst_mode_freq == 0) { 808 drm_err(display->drm, "Burst mode target is not set\n"); 809 return false; 810 } 811 812 bitrate = intel_dsi_bitrate(intel_dsi); 813 814 /* 815 * Sometimes the VBT contains a slightly lower clock, then 816 * the bitrate we have calculated, in this case just replace it 817 * with the calculated bitrate. 818 */ 819 if (mipi_config->target_burst_mode_freq < bitrate && 820 intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq, 821 bitrate)) 822 mipi_config->target_burst_mode_freq = bitrate; 823 824 if (mipi_config->target_burst_mode_freq < bitrate) { 825 drm_err(display->drm, "Burst mode freq is less than computed\n"); 826 return false; 827 } 828 829 burst_mode_ratio = 830 DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate); 831 832 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 833 } else 834 burst_mode_ratio = 100; 835 836 intel_dsi->burst_mode_ratio = burst_mode_ratio; 837 838 /* delays in VBT are in unit of 100us, so need to convert 839 * here in ms 840 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 841 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 842 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 843 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 844 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 845 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 846 847 intel_dsi->i2c_bus_num = -1; 848 849 /* a regular driver would get the device in probe */ 850 for_each_dsi_port(port, intel_dsi->ports) { 851 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 852 } 853 854 return true; 855 } 856 857 /* 858 * On some BYT/CHT devs some sequences are incomplete and we need to manually 859 * control some GPIOs. We need to add a GPIO lookup table before we get these. 860 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 861 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 862 */ 863 static struct gpiod_lookup_table pmic_panel_gpio_table = { 864 /* Intel GFX is consumer */ 865 .dev_id = "0000:00:02.0", 866 .table = { 867 /* Panel EN/DISABLE */ 868 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 869 { } 870 }, 871 }; 872 873 static struct gpiod_lookup_table soc_panel_gpio_table = { 874 .dev_id = "0000:00:02.0", 875 .table = { 876 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 877 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 878 { } 879 }, 880 }; 881 882 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 883 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 884 "pwm0_grp", "pwm"), 885 }; 886 887 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 888 { 889 struct intel_display *display = to_intel_display(&intel_dsi->base); 890 struct intel_connector *connector = intel_dsi->attached_connector; 891 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 892 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 893 struct gpiod_lookup_table *gpiod_lookup_table = NULL; 894 bool want_backlight_gpio = false; 895 bool want_panel_gpio = false; 896 struct pinctrl *pinctrl; 897 int ret; 898 899 if ((display->platform.valleyview || display->platform.cherryview) && 900 mipi_config->pwm_blc == PPS_BLC_PMIC) { 901 gpiod_lookup_table = &pmic_panel_gpio_table; 902 want_panel_gpio = true; 903 } 904 905 if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) { 906 gpiod_lookup_table = &soc_panel_gpio_table; 907 want_panel_gpio = true; 908 want_backlight_gpio = true; 909 910 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 911 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 912 ARRAY_SIZE(soc_pwm_pinctrl_map)); 913 if (ret) 914 drm_err(display->drm, 915 "Failed to register pwm0 pinmux mapping\n"); 916 917 pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0"); 918 if (IS_ERR(pinctrl)) 919 drm_err(display->drm, 920 "Failed to set pinmux to PWM\n"); 921 } 922 923 if (gpiod_lookup_table) 924 gpiod_add_lookup_table(gpiod_lookup_table); 925 926 if (want_panel_gpio) { 927 intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags); 928 if (IS_ERR(intel_dsi->gpio_panel)) { 929 drm_err(display->drm, 930 "Failed to own gpio for panel control\n"); 931 intel_dsi->gpio_panel = NULL; 932 } 933 } 934 935 if (want_backlight_gpio) { 936 intel_dsi->gpio_backlight = 937 devm_gpiod_get(display->drm->dev, "backlight", flags); 938 if (IS_ERR(intel_dsi->gpio_backlight)) { 939 drm_err(display->drm, 940 "Failed to own gpio for backlight control\n"); 941 intel_dsi->gpio_backlight = NULL; 942 } 943 } 944 945 if (gpiod_lookup_table) 946 gpiod_remove_lookup_table(gpiod_lookup_table); 947 } 948