1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 #include <linux/unaligned.h> 35 36 #include <drm/drm_crtc.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_print.h> 39 #include <video/mipi_display.h> 40 41 #include "intel_de.h" 42 #include "intel_display_regs.h" 43 #include "intel_display_types.h" 44 #include "intel_display_utils.h" 45 #include "intel_dsi.h" 46 #include "intel_dsi_vbt.h" 47 #include "intel_gmbus_regs.h" 48 #include "intel_pps_regs.h" 49 #include "vlv_dsi.h" 50 #include "vlv_dsi_regs.h" 51 #include "vlv_sideband.h" 52 53 #define MIPI_TRANSFER_MODE_SHIFT 0 54 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 55 #define MIPI_PORT_SHIFT 3 56 57 struct i2c_adapter_lookup { 58 u16 target_addr; 59 struct intel_dsi *intel_dsi; 60 acpi_handle dev_handle; 61 }; 62 63 #define CHV_GPIO_IDX_START_N 0 64 #define CHV_GPIO_IDX_START_E 73 65 #define CHV_GPIO_IDX_START_SW 100 66 #define CHV_GPIO_IDX_START_SE 198 67 68 /* ICL DSI Display GPIO Pins */ 69 #define ICL_GPIO_DDSP_HPD_A 0 70 #define ICL_GPIO_L_VDDEN_1 1 71 #define ICL_GPIO_L_BKLTEN_1 2 72 #define ICL_GPIO_DDPA_CTRLCLK_1 3 73 #define ICL_GPIO_DDPA_CTRLDATA_1 4 74 #define ICL_GPIO_DDSP_HPD_B 5 75 #define ICL_GPIO_L_VDDEN_2 6 76 #define ICL_GPIO_L_BKLTEN_2 7 77 #define ICL_GPIO_DDPA_CTRLCLK_2 8 78 #define ICL_GPIO_DDPA_CTRLDATA_2 9 79 80 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 81 u8 seq_port) 82 { 83 /* 84 * If single link DSI is being used on any port, the VBT sequence block 85 * send packet apparently always has 0 for the port. Just use the port 86 * we have configured, and ignore the sequence block port. 87 */ 88 if (hweight8(intel_dsi->ports) == 1) 89 return ffs(intel_dsi->ports) - 1; 90 91 if (seq_port) { 92 if (intel_dsi->ports & BIT(PORT_B)) 93 return PORT_B; 94 if (intel_dsi->ports & BIT(PORT_C)) 95 return PORT_C; 96 } 97 98 return PORT_A; 99 } 100 101 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 102 const u8 *data) 103 { 104 struct intel_display *display = to_intel_display(&intel_dsi->base); 105 struct mipi_dsi_device *dsi_device; 106 u8 type, flags, seq_port; 107 u16 len; 108 enum port port; 109 ssize_t ret; 110 bool hs_mode; 111 112 flags = *data++; 113 type = *data++; 114 115 len = *((u16 *) data); 116 data += 2; 117 118 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 119 120 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 121 122 if (drm_WARN_ON(display->drm, !intel_dsi->dsi_hosts[port])) 123 goto out; 124 125 dsi_device = intel_dsi->dsi_hosts[port]->device; 126 if (!dsi_device) { 127 drm_dbg_kms(display->drm, "no dsi device for port %c\n", 128 port_name(port)); 129 goto out; 130 } 131 132 hs_mode = (flags >> MIPI_TRANSFER_MODE_SHIFT) & 1; 133 if (hs_mode) 134 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 135 else 136 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 137 138 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 139 140 drm_dbg_kms(display->drm, "DSI packet: Port %c (seq %u), Flags 0x%02x, VC %u, %s, Type 0x%02x, Length %u, Data %*ph\n", 141 port_name(port), seq_port, flags, dsi_device->channel, 142 hs_mode ? "HS" : "LP", type, len, (int)len, data); 143 144 switch (type) { 145 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 146 ret = mipi_dsi_generic_write(dsi_device, NULL, 0); 147 break; 148 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 149 ret = mipi_dsi_generic_write(dsi_device, data, 1); 150 break; 151 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 152 ret = mipi_dsi_generic_write(dsi_device, data, 2); 153 break; 154 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 155 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 156 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 157 ret = -EOPNOTSUPP; 158 break; 159 case MIPI_DSI_GENERIC_LONG_WRITE: 160 ret = mipi_dsi_generic_write(dsi_device, data, len); 161 break; 162 case MIPI_DSI_DCS_SHORT_WRITE: 163 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 164 break; 165 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 166 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 167 break; 168 case MIPI_DSI_DCS_READ: 169 ret = -EOPNOTSUPP; 170 break; 171 case MIPI_DSI_DCS_LONG_WRITE: 172 ret = mipi_dsi_dcs_write_buffer(dsi_device, data, len); 173 break; 174 } 175 176 if (ret < 0) 177 drm_err(display->drm, "DSI send packet failed with %pe\n", ERR_PTR(ret)); 178 179 if (DISPLAY_VER(display) < 11) 180 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 181 182 out: 183 data += len; 184 185 return data; 186 } 187 188 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 189 { 190 struct intel_display *display = to_intel_display(&intel_dsi->base); 191 u32 delay = *((const u32 *) data); 192 193 drm_dbg_kms(display->drm, "%d usecs\n", delay); 194 195 usleep_range(delay, delay + 10); 196 data += 4; 197 198 return data; 199 } 200 201 static void soc_gpio_set_value(struct intel_connector *connector, u8 gpio_index, 202 const char *con_id, u8 idx, bool value) 203 { 204 struct intel_display *display = to_intel_display(connector); 205 /* XXX: this table is a quick ugly hack. */ 206 static struct gpio_desc *soc_gpio_table[U8_MAX + 1]; 207 struct gpio_desc *gpio_desc = soc_gpio_table[gpio_index]; 208 209 if (gpio_desc) { 210 gpiod_set_value(gpio_desc, value); 211 } else { 212 gpio_desc = devm_gpiod_get_index(display->drm->dev, con_id, idx, 213 value ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW); 214 if (IS_ERR(gpio_desc)) { 215 drm_err(display->drm, 216 "GPIO index %u request failed (%pe)\n", 217 gpio_index, gpio_desc); 218 return; 219 } 220 221 soc_gpio_table[gpio_index] = gpio_desc; 222 } 223 } 224 225 static void soc_opaque_gpio_set_value(struct intel_connector *connector, 226 u8 gpio_index, const char *chip, 227 const char *con_id, u8 idx, bool value) 228 { 229 struct gpiod_lookup_table *lookup; 230 231 lookup = kzalloc(struct_size(lookup, table, 2), GFP_KERNEL); 232 if (!lookup) 233 return; 234 235 lookup->dev_id = "0000:00:02.0"; 236 lookup->table[0] = 237 GPIO_LOOKUP_IDX(chip, idx, con_id, idx, GPIO_ACTIVE_HIGH); 238 239 gpiod_add_lookup_table(lookup); 240 241 soc_gpio_set_value(connector, gpio_index, con_id, idx, value); 242 243 gpiod_remove_lookup_table(lookup); 244 kfree(lookup); 245 } 246 247 static void vlv_gpio_set_value(struct intel_connector *connector, 248 u8 gpio_source, u8 gpio_index, bool value) 249 { 250 struct intel_display *display = to_intel_display(connector); 251 252 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 253 if (connector->panel.vbt.dsi.seq_version < 3) { 254 if (gpio_source == 1) { 255 drm_dbg_kms(display->drm, "SC gpio not supported\n"); 256 return; 257 } 258 if (gpio_source > 1) { 259 drm_dbg_kms(display->drm, 260 "unknown gpio source %u\n", gpio_source); 261 return; 262 } 263 } 264 265 soc_opaque_gpio_set_value(connector, gpio_index, 266 "INT33FC:01", "Panel N", gpio_index, value); 267 } 268 269 static void chv_gpio_set_value(struct intel_connector *connector, 270 u8 gpio_source, u8 gpio_index, bool value) 271 { 272 struct intel_display *display = to_intel_display(connector); 273 274 if (connector->panel.vbt.dsi.seq_version >= 3) { 275 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 276 /* XXX: it's unclear whether 255->57 is part of SE. */ 277 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:03", "Panel SE", 278 gpio_index - CHV_GPIO_IDX_START_SE, value); 279 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 280 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:00", "Panel SW", 281 gpio_index - CHV_GPIO_IDX_START_SW, value); 282 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 283 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:02", "Panel E", 284 gpio_index - CHV_GPIO_IDX_START_E, value); 285 } else { 286 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 287 gpio_index - CHV_GPIO_IDX_START_N, value); 288 } 289 } else { 290 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 291 if (gpio_source != 0) { 292 drm_dbg_kms(display->drm, 293 "unknown gpio source %u\n", gpio_source); 294 return; 295 } 296 297 if (gpio_index >= CHV_GPIO_IDX_START_E) { 298 drm_dbg_kms(display->drm, 299 "invalid gpio index %u for GPIO N\n", 300 gpio_index); 301 return; 302 } 303 304 soc_opaque_gpio_set_value(connector, gpio_index, "INT33FF:01", "Panel N", 305 gpio_index - CHV_GPIO_IDX_START_N, value); 306 } 307 } 308 309 static void bxt_gpio_set_value(struct intel_connector *connector, 310 u8 gpio_index, bool value) 311 { 312 soc_gpio_set_value(connector, gpio_index, NULL, gpio_index, value); 313 } 314 315 enum { 316 MIPI_RESET_1 = 0, 317 MIPI_AVDD_EN_1, 318 MIPI_BKLT_EN_1, 319 MIPI_AVEE_EN_1, 320 MIPI_VIO_EN_1, 321 MIPI_RESET_2, 322 MIPI_AVDD_EN_2, 323 MIPI_BKLT_EN_2, 324 MIPI_AVEE_EN_2, 325 MIPI_VIO_EN_2, 326 }; 327 328 static void icl_native_gpio_set_value(struct intel_display *display, 329 int gpio, bool value) 330 { 331 int index; 332 333 if (drm_WARN_ON(display->drm, DISPLAY_VER(display) == 11 && gpio >= MIPI_RESET_2)) 334 return; 335 336 switch (gpio) { 337 case MIPI_RESET_1: 338 case MIPI_RESET_2: 339 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B; 340 341 /* 342 * Disable HPD to set the pin to output, and set output 343 * value. The HPD pin should not be enabled for DSI anyway, 344 * assuming the board design and VBT are sane, and the pin isn't 345 * used by a non-DSI encoder. 346 * 347 * The locking protects against concurrent SHOTPLUG_CTL_DDI 348 * modifications in irq setup and handling. 349 */ 350 spin_lock_irq(&display->irq.lock); 351 intel_de_rmw(display, SHOTPLUG_CTL_DDI, 352 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | 353 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), 354 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); 355 spin_unlock_irq(&display->irq.lock); 356 break; 357 case MIPI_AVDD_EN_1: 358 case MIPI_AVDD_EN_2: 359 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; 360 361 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, 362 value ? PANEL_POWER_ON : 0); 363 break; 364 case MIPI_BKLT_EN_1: 365 case MIPI_BKLT_EN_2: 366 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; 367 368 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, 369 value ? EDP_BLC_ENABLE : 0); 370 break; 371 case MIPI_AVEE_EN_1: 372 case MIPI_AVEE_EN_2: 373 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2; 374 375 intel_de_rmw(display, GPIO(display, index), 376 GPIO_CLOCK_VAL_OUT, 377 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | 378 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0)); 379 break; 380 case MIPI_VIO_EN_1: 381 case MIPI_VIO_EN_2: 382 index = gpio == MIPI_VIO_EN_1 ? 1 : 2; 383 384 intel_de_rmw(display, GPIO(display, index), 385 GPIO_DATA_VAL_OUT, 386 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | 387 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0)); 388 break; 389 default: 390 MISSING_CASE(gpio); 391 } 392 } 393 394 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 395 { 396 struct intel_display *display = to_intel_display(&intel_dsi->base); 397 struct intel_connector *connector = intel_dsi->attached_connector; 398 u8 gpio_source = 0, gpio_index = 0, gpio_number; 399 bool value; 400 int size; 401 bool native = DISPLAY_VER(display) >= 11; 402 403 if (connector->panel.vbt.dsi.seq_version >= 3) { 404 size = 3; 405 406 gpio_index = data[0]; 407 gpio_number = data[1]; 408 value = data[2] & BIT(0); 409 410 if (connector->panel.vbt.dsi.seq_version >= 4 && data[2] & BIT(1)) 411 native = false; 412 } else { 413 size = 2; 414 415 gpio_number = data[0]; 416 value = data[1] & BIT(0); 417 418 if (connector->panel.vbt.dsi.seq_version == 2) 419 gpio_source = (data[1] >> 1) & 3; 420 } 421 422 drm_dbg_kms(display->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n", 423 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value)); 424 425 if (native) 426 icl_native_gpio_set_value(display, gpio_number, value); 427 else if (DISPLAY_VER(display) >= 9) 428 bxt_gpio_set_value(connector, gpio_index, value); 429 else if (display->platform.valleyview) 430 vlv_gpio_set_value(connector, gpio_source, gpio_number, value); 431 else if (display->platform.cherryview) 432 chv_gpio_set_value(connector, gpio_source, gpio_number, value); 433 434 return data + size; 435 } 436 437 #ifdef CONFIG_ACPI 438 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 439 { 440 struct i2c_adapter_lookup *lookup = data; 441 struct intel_dsi *intel_dsi = lookup->intel_dsi; 442 struct acpi_resource_i2c_serialbus *sb; 443 struct i2c_adapter *adapter; 444 acpi_handle adapter_handle; 445 acpi_status status; 446 447 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 448 return 1; 449 450 if (lookup->target_addr != sb->slave_address) 451 return 1; 452 453 status = acpi_get_handle(lookup->dev_handle, 454 sb->resource_source.string_ptr, 455 &adapter_handle); 456 if (ACPI_FAILURE(status)) 457 return 1; 458 459 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 460 if (adapter) 461 intel_dsi->i2c_bus_num = adapter->nr; 462 463 return 1; 464 } 465 466 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 467 const u16 target_addr) 468 { 469 struct intel_display *display = to_intel_display(&intel_dsi->base); 470 struct acpi_device *adev = ACPI_COMPANION(display->drm->dev); 471 struct i2c_adapter_lookup lookup = { 472 .target_addr = target_addr, 473 .intel_dsi = intel_dsi, 474 .dev_handle = acpi_device_handle(adev), 475 }; 476 LIST_HEAD(resource_list); 477 478 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 479 acpi_dev_free_resource_list(&resource_list); 480 } 481 #else 482 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 483 const u16 target_addr) 484 { 485 } 486 #endif 487 488 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 489 { 490 struct intel_display *display = to_intel_display(&intel_dsi->base); 491 struct i2c_adapter *adapter; 492 struct i2c_msg msg; 493 int ret; 494 u8 vbt_i2c_bus_num = *(data + 2); 495 u16 target_addr = *(u16 *)(data + 3); 496 u8 reg_offset = *(data + 5); 497 u8 payload_size = *(data + 6); 498 u8 *payload_data; 499 500 drm_dbg_kms(display->drm, "bus %d target-addr 0x%02x reg 0x%02x data %*ph\n", 501 vbt_i2c_bus_num, target_addr, reg_offset, payload_size, data + 7); 502 503 if (intel_dsi->i2c_bus_num < 0) { 504 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 505 i2c_acpi_find_adapter(intel_dsi, target_addr); 506 } 507 508 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 509 if (!adapter) { 510 drm_err(display->drm, "Cannot find a valid i2c bus for xfer\n"); 511 goto err_bus; 512 } 513 514 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 515 if (!payload_data) 516 goto err_alloc; 517 518 payload_data[0] = reg_offset; 519 memcpy(&payload_data[1], (data + 7), payload_size); 520 521 msg.addr = target_addr; 522 msg.flags = 0; 523 msg.len = payload_size + 1; 524 msg.buf = payload_data; 525 526 ret = i2c_transfer(adapter, &msg, 1); 527 if (ret < 0) 528 drm_err(display->drm, 529 "Failed to xfer payload of size (%u) to reg (%u)\n", 530 payload_size, reg_offset); 531 532 kfree(payload_data); 533 err_alloc: 534 i2c_put_adapter(adapter); 535 err_bus: 536 return data + payload_size + 7; 537 } 538 539 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 540 { 541 struct intel_display *display = to_intel_display(&intel_dsi->base); 542 543 drm_dbg_kms(display->drm, "Skipping SPI element execution\n"); 544 545 return data + *(data + 5) + 6; 546 } 547 548 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 549 { 550 struct intel_display *display = to_intel_display(&intel_dsi->base); 551 #ifdef CONFIG_PMIC_OPREGION 552 u32 value, mask, reg_address; 553 u16 i2c_address; 554 int ret; 555 556 /* byte 0 aka PMIC Flag is reserved */ 557 i2c_address = get_unaligned_le16(data + 1); 558 reg_address = get_unaligned_le32(data + 3); 559 value = get_unaligned_le32(data + 7); 560 mask = get_unaligned_le32(data + 11); 561 562 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 563 reg_address, 564 value, mask); 565 if (ret) 566 drm_err(display->drm, "%s failed, error: %d\n", __func__, ret); 567 #else 568 drm_err(display->drm, 569 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 570 #endif 571 572 return data + 15; 573 } 574 575 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 576 const u8 *data); 577 static const fn_mipi_elem_exec exec_elem[] = { 578 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 579 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 580 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 581 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 582 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 583 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 584 }; 585 586 /* 587 * MIPI Sequence from VBT #53 parsing logic 588 * We have already separated each sequence during bios parsing 589 * Following is generic execution function for any sequence 590 */ 591 592 static const char * const seq_name[] = { 593 [MIPI_SEQ_END] = "MIPI_SEQ_END", 594 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 595 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 596 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 597 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 598 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 599 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 600 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 601 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 602 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 603 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 604 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 605 }; 606 607 static const char *sequence_name(enum mipi_seq seq_id) 608 { 609 if (seq_id < ARRAY_SIZE(seq_name)) 610 return seq_name[seq_id]; 611 612 return "(unknown)"; 613 } 614 615 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 616 enum mipi_seq seq_id) 617 { 618 struct intel_display *display = to_intel_display(&intel_dsi->base); 619 struct intel_connector *connector = intel_dsi->attached_connector; 620 const u8 *data; 621 fn_mipi_elem_exec mipi_elem_exec; 622 623 if (drm_WARN_ON(display->drm, 624 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))) 625 return; 626 627 data = connector->panel.vbt.dsi.sequence[seq_id]; 628 if (!data) 629 return; 630 631 drm_WARN_ON(display->drm, *data != seq_id); 632 633 drm_dbg_kms(display->drm, "Starting MIPI sequence %d - %s\n", 634 seq_id, sequence_name(seq_id)); 635 636 /* Skip Sequence Byte. */ 637 data++; 638 639 /* Skip Size of Sequence. */ 640 if (connector->panel.vbt.dsi.seq_version >= 3) 641 data += 4; 642 643 while (*data != MIPI_SEQ_ELEM_END) { 644 u8 operation_byte = *data++; 645 u8 operation_size = 0; 646 647 if (operation_byte < ARRAY_SIZE(exec_elem)) 648 mipi_elem_exec = exec_elem[operation_byte]; 649 else 650 mipi_elem_exec = NULL; 651 652 /* Size of Operation. */ 653 if (connector->panel.vbt.dsi.seq_version >= 3) 654 operation_size = *data++; 655 656 if (mipi_elem_exec) { 657 const u8 *next = data + operation_size; 658 659 data = mipi_elem_exec(intel_dsi, data); 660 661 /* Consistency check if we have size. */ 662 if (operation_size && data != next) { 663 drm_err(display->drm, 664 "Inconsistent operation size\n"); 665 return; 666 } 667 } else if (operation_size) { 668 /* We have size, skip. */ 669 drm_dbg_kms(display->drm, 670 "Unsupported MIPI operation byte %u\n", 671 operation_byte); 672 data += operation_size; 673 } else { 674 /* No size, can't skip without parsing. */ 675 drm_err(display->drm, 676 "Unsupported MIPI operation byte %u\n", 677 operation_byte); 678 return; 679 } 680 } 681 } 682 683 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 684 enum mipi_seq seq_id) 685 { 686 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 687 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 688 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 689 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 690 691 intel_dsi_vbt_exec(intel_dsi, seq_id); 692 693 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 694 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 695 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 696 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 697 } 698 699 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 700 { 701 struct intel_display *display = to_intel_display(&intel_dsi->base); 702 struct drm_printer p = drm_dbg_printer(display->drm, DRM_UT_KMS, 703 "DSI parameters:"); 704 705 drm_printf(&p, "Pclk %d\n", intel_dsi->pclk); 706 drm_printf(&p, "Pixel overlap %d\n", intel_dsi->pixel_overlap); 707 drm_printf(&p, "Lane count %d\n", intel_dsi->lane_count); 708 drm_printf(&p, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 709 drm_printf(&p, "Video mode format %s\n", 710 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 711 "non-burst with sync pulse" : 712 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 713 "non-burst with sync events" : 714 intel_dsi->video_mode == BURST_MODE ? 715 "burst" : "<unknown>"); 716 drm_printf(&p, "Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); 717 drm_printf(&p, "Reset timer %d\n", intel_dsi->rst_timer_val); 718 drm_printf(&p, "Eot %s\n", str_enabled_disabled(intel_dsi->eotp_pkt)); 719 drm_printf(&p, "Clockstop %s\n", str_enabled_disabled(!intel_dsi->clock_stop)); 720 drm_printf(&p, "Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); 721 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 722 drm_printf(&p, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 723 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 724 drm_printf(&p, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 725 else 726 drm_printf(&p, "Dual link: NONE\n"); 727 drm_printf(&p, "Pixel Format %d\n", intel_dsi->pixel_format); 728 drm_printf(&p, "TLPX %d\n", intel_dsi->escape_clk_div); 729 drm_printf(&p, "LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); 730 drm_printf(&p, "Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); 731 drm_printf(&p, "Init Count 0x%x\n", intel_dsi->init_count); 732 drm_printf(&p, "HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); 733 drm_printf(&p, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 734 drm_printf(&p, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 735 drm_printf(&p, "LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); 736 drm_printf(&p, "HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); 737 drm_printf(&p, "BTA %s\n", 738 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 739 } 740 741 static enum mipi_dsi_pixel_format vbt_to_dsi_pixel_format(unsigned int format) 742 { 743 switch (format) { 744 case PIXEL_FORMAT_RGB888: 745 return MIPI_DSI_FMT_RGB888; 746 case PIXEL_FORMAT_RGB666_LOOSELY_PACKED: 747 return MIPI_DSI_FMT_RGB666; 748 case PIXEL_FORMAT_RGB666: 749 return MIPI_DSI_FMT_RGB666_PACKED; 750 case PIXEL_FORMAT_RGB565: 751 return MIPI_DSI_FMT_RGB565; 752 default: 753 MISSING_CASE(format); 754 return MIPI_DSI_FMT_RGB666; 755 } 756 } 757 758 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 759 { 760 struct intel_display *display = to_intel_display(&intel_dsi->base); 761 struct intel_connector *connector = intel_dsi->attached_connector; 762 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 763 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; 764 struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode; 765 u16 burst_mode_ratio; 766 enum port port; 767 768 drm_dbg_kms(display->drm, "\n"); 769 770 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 771 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 772 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 773 intel_dsi->pixel_format = 774 vbt_to_dsi_pixel_format(mipi_config->videomode_color_format); 775 776 intel_dsi->dual_link = mipi_config->dual_link; 777 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 778 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 779 intel_dsi->video_mode = mipi_config->video_transfer_mode; 780 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 781 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 782 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 783 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 784 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 785 intel_dsi->init_count = mipi_config->master_init_timer; 786 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 787 intel_dsi->video_frmt_cfg_bits = 788 mipi_config->bta_disable ? DISABLE_VIDEO_BTA : 0; 789 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 790 791 /* Starting point, adjusted depending on dual link and burst mode */ 792 intel_dsi->pclk = mode->clock; 793 794 /* In dual link mode each port needs half of pixel clock */ 795 if (intel_dsi->dual_link) { 796 intel_dsi->pclk /= 2; 797 798 /* we can enable pixel_overlap if needed by panel. In this 799 * case we need to increase the pixelclock for extra pixels 800 */ 801 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 802 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 803 } 804 } 805 806 /* Burst Mode Ratio 807 * Target ddr frequency from VBT / non burst ddr freq 808 * multiply by 100 to preserve remainder 809 */ 810 if (intel_dsi->video_mode == BURST_MODE) { 811 u32 bitrate; 812 813 if (mipi_config->target_burst_mode_freq == 0) { 814 drm_err(display->drm, "Burst mode target is not set\n"); 815 return false; 816 } 817 818 bitrate = intel_dsi_bitrate(intel_dsi); 819 820 /* 821 * Sometimes the VBT contains a slightly lower clock, then 822 * the bitrate we have calculated, in this case just replace it 823 * with the calculated bitrate. 824 */ 825 if (mipi_config->target_burst_mode_freq < bitrate && 826 intel_fuzzy_clock_check(mipi_config->target_burst_mode_freq, 827 bitrate)) 828 mipi_config->target_burst_mode_freq = bitrate; 829 830 if (mipi_config->target_burst_mode_freq < bitrate) { 831 drm_err(display->drm, "Burst mode freq is less than computed\n"); 832 return false; 833 } 834 835 burst_mode_ratio = 836 DIV_ROUND_UP(mipi_config->target_burst_mode_freq * 100, bitrate); 837 838 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 839 } else 840 burst_mode_ratio = 100; 841 842 intel_dsi->burst_mode_ratio = burst_mode_ratio; 843 844 /* delays in VBT are in unit of 100us, so need to convert 845 * here in ms 846 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 847 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 848 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 849 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 850 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 851 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 852 853 intel_dsi->i2c_bus_num = -1; 854 855 /* a regular driver would get the device in probe */ 856 for_each_dsi_port(port, intel_dsi->ports) { 857 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 858 } 859 860 return true; 861 } 862 863 /* 864 * On some BYT/CHT devs some sequences are incomplete and we need to manually 865 * control some GPIOs. We need to add a GPIO lookup table before we get these. 866 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 867 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 868 */ 869 static struct gpiod_lookup_table pmic_panel_gpio_table = { 870 /* Intel GFX is consumer */ 871 .dev_id = "0000:00:02.0", 872 .table = { 873 /* Panel EN/DISABLE */ 874 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 875 { } 876 }, 877 }; 878 879 static struct gpiod_lookup_table soc_panel_gpio_table = { 880 .dev_id = "0000:00:02.0", 881 .table = { 882 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 883 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 884 { } 885 }, 886 }; 887 888 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 889 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 890 "pwm0_grp", "pwm"), 891 }; 892 893 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 894 { 895 struct intel_display *display = to_intel_display(&intel_dsi->base); 896 struct intel_connector *connector = intel_dsi->attached_connector; 897 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 898 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 899 struct gpiod_lookup_table *gpiod_lookup_table = NULL; 900 bool want_backlight_gpio = false; 901 bool want_panel_gpio = false; 902 struct pinctrl *pinctrl; 903 int ret; 904 905 if ((display->platform.valleyview || display->platform.cherryview) && 906 mipi_config->pwm_blc == PPS_BLC_PMIC) { 907 gpiod_lookup_table = &pmic_panel_gpio_table; 908 want_panel_gpio = true; 909 } 910 911 if (display->platform.valleyview && mipi_config->pwm_blc == PPS_BLC_SOC) { 912 gpiod_lookup_table = &soc_panel_gpio_table; 913 want_panel_gpio = true; 914 want_backlight_gpio = true; 915 916 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 917 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 918 ARRAY_SIZE(soc_pwm_pinctrl_map)); 919 if (ret) 920 drm_err(display->drm, 921 "Failed to register pwm0 pinmux mapping\n"); 922 923 pinctrl = devm_pinctrl_get_select(display->drm->dev, "soc_pwm0"); 924 if (IS_ERR(pinctrl)) 925 drm_err(display->drm, 926 "Failed to set pinmux to PWM\n"); 927 } 928 929 if (gpiod_lookup_table) 930 gpiod_add_lookup_table(gpiod_lookup_table); 931 932 if (want_panel_gpio) { 933 intel_dsi->gpio_panel = devm_gpiod_get(display->drm->dev, "panel", flags); 934 if (IS_ERR(intel_dsi->gpio_panel)) { 935 drm_err(display->drm, 936 "Failed to own gpio for panel control\n"); 937 intel_dsi->gpio_panel = NULL; 938 } 939 } 940 941 if (want_backlight_gpio) { 942 intel_dsi->gpio_backlight = 943 devm_gpiod_get(display->drm->dev, "backlight", flags); 944 if (IS_ERR(intel_dsi->gpio_backlight)) { 945 drm_err(display->drm, 946 "Failed to own gpio for backlight control\n"); 947 intel_dsi->gpio_backlight = NULL; 948 } 949 } 950 951 if (gpiod_lookup_table) 952 gpiod_remove_lookup_table(gpiod_lookup_table); 953 } 954