1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 #include <linux/string_helpers.h> 34 35 #include <asm/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 40 #include <video/mipi_display.h> 41 42 #include "i915_drv.h" 43 #include "i915_reg.h" 44 #include "intel_de.h" 45 #include "intel_display_types.h" 46 #include "intel_dsi.h" 47 #include "intel_dsi_vbt.h" 48 #include "intel_gmbus_regs.h" 49 #include "intel_pps_regs.h" 50 #include "vlv_dsi.h" 51 #include "vlv_dsi_regs.h" 52 #include "vlv_sideband.h" 53 54 #define MIPI_TRANSFER_MODE_SHIFT 0 55 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 56 #define MIPI_PORT_SHIFT 3 57 58 /* base offsets for gpio pads */ 59 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 60 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 61 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 62 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 63 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 64 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 65 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 66 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 67 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 68 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 69 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 70 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 71 72 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 73 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 74 75 struct gpio_map { 76 u16 base_offset; 77 bool init; 78 }; 79 80 static struct gpio_map vlv_gpio_table[] = { 81 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 82 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 83 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 84 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 85 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 86 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 87 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 88 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 89 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 90 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 91 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 92 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 93 }; 94 95 struct i2c_adapter_lookup { 96 u16 slave_addr; 97 struct intel_dsi *intel_dsi; 98 acpi_handle dev_handle; 99 }; 100 101 #define CHV_GPIO_IDX_START_N 0 102 #define CHV_GPIO_IDX_START_E 73 103 #define CHV_GPIO_IDX_START_SW 100 104 #define CHV_GPIO_IDX_START_SE 198 105 106 #define CHV_VBT_MAX_PINS_PER_FMLY 15 107 108 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 109 #define CHV_GPIO_GPIOEN (1 << 15) 110 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 111 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 112 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 113 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 114 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 115 116 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 117 #define CHV_GPIO_CFGLOCK (1 << 31) 118 119 /* ICL DSI Display GPIO Pins */ 120 #define ICL_GPIO_DDSP_HPD_A 0 121 #define ICL_GPIO_L_VDDEN_1 1 122 #define ICL_GPIO_L_BKLTEN_1 2 123 #define ICL_GPIO_DDPA_CTRLCLK_1 3 124 #define ICL_GPIO_DDPA_CTRLDATA_1 4 125 #define ICL_GPIO_DDSP_HPD_B 5 126 #define ICL_GPIO_L_VDDEN_2 6 127 #define ICL_GPIO_L_BKLTEN_2 7 128 #define ICL_GPIO_DDPA_CTRLCLK_2 8 129 #define ICL_GPIO_DDPA_CTRLDATA_2 9 130 131 static enum port intel_dsi_seq_port_to_port(struct intel_dsi *intel_dsi, 132 u8 seq_port) 133 { 134 /* 135 * If single link DSI is being used on any port, the VBT sequence block 136 * send packet apparently always has 0 for the port. Just use the port 137 * we have configured, and ignore the sequence block port. 138 */ 139 if (hweight8(intel_dsi->ports) == 1) 140 return ffs(intel_dsi->ports) - 1; 141 142 if (seq_port) { 143 if (intel_dsi->ports & BIT(PORT_B)) 144 return PORT_B; 145 else if (intel_dsi->ports & BIT(PORT_C)) 146 return PORT_C; 147 } 148 149 return PORT_A; 150 } 151 152 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 153 const u8 *data) 154 { 155 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 156 struct mipi_dsi_device *dsi_device; 157 u8 type, flags, seq_port; 158 u16 len; 159 enum port port; 160 161 drm_dbg_kms(&dev_priv->drm, "\n"); 162 163 flags = *data++; 164 type = *data++; 165 166 len = *((u16 *) data); 167 data += 2; 168 169 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 170 171 port = intel_dsi_seq_port_to_port(intel_dsi, seq_port); 172 173 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) 174 goto out; 175 176 dsi_device = intel_dsi->dsi_hosts[port]->device; 177 if (!dsi_device) { 178 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n", 179 port_name(port)); 180 goto out; 181 } 182 183 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 184 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 185 else 186 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 187 188 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 189 190 switch (type) { 191 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 192 mipi_dsi_generic_write(dsi_device, NULL, 0); 193 break; 194 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 195 mipi_dsi_generic_write(dsi_device, data, 1); 196 break; 197 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 198 mipi_dsi_generic_write(dsi_device, data, 2); 199 break; 200 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 201 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 202 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 203 drm_dbg(&dev_priv->drm, 204 "Generic Read not yet implemented or used\n"); 205 break; 206 case MIPI_DSI_GENERIC_LONG_WRITE: 207 mipi_dsi_generic_write(dsi_device, data, len); 208 break; 209 case MIPI_DSI_DCS_SHORT_WRITE: 210 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 211 break; 212 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 213 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 214 break; 215 case MIPI_DSI_DCS_READ: 216 drm_dbg(&dev_priv->drm, 217 "DCS Read not yet implemented or used\n"); 218 break; 219 case MIPI_DSI_DCS_LONG_WRITE: 220 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 221 break; 222 } 223 224 if (DISPLAY_VER(dev_priv) < 11) 225 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 226 227 out: 228 data += len; 229 230 return data; 231 } 232 233 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 234 { 235 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 236 u32 delay = *((const u32 *) data); 237 238 drm_dbg_kms(&i915->drm, "%d usecs\n", delay); 239 240 usleep_range(delay, delay + 10); 241 data += 4; 242 243 return data; 244 } 245 246 static void vlv_exec_gpio(struct intel_connector *connector, 247 u8 gpio_source, u8 gpio_index, bool value) 248 { 249 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 250 struct gpio_map *map; 251 u16 pconf0, padval; 252 u32 tmp; 253 u8 port; 254 255 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 256 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n", 257 gpio_index); 258 return; 259 } 260 261 map = &vlv_gpio_table[gpio_index]; 262 263 if (connector->panel.vbt.dsi.seq_version >= 3) { 264 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 265 port = IOSF_PORT_GPIO_NC; 266 } else { 267 if (gpio_source == 0) { 268 port = IOSF_PORT_GPIO_NC; 269 } else if (gpio_source == 1) { 270 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n"); 271 return; 272 } else { 273 drm_dbg_kms(&dev_priv->drm, 274 "unknown gpio source %u\n", gpio_source); 275 return; 276 } 277 } 278 279 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 280 padval = VLV_GPIO_PAD_VAL(map->base_offset); 281 282 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 283 if (!map->init) { 284 /* FIXME: remove constant below */ 285 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 286 map->init = true; 287 } 288 289 tmp = 0x4 | value; 290 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 291 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 292 } 293 294 static void chv_exec_gpio(struct intel_connector *connector, 295 u8 gpio_source, u8 gpio_index, bool value) 296 { 297 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 298 u16 cfg0, cfg1; 299 u16 family_num; 300 u8 port; 301 302 if (connector->panel.vbt.dsi.seq_version >= 3) { 303 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 304 /* XXX: it's unclear whether 255->57 is part of SE. */ 305 gpio_index -= CHV_GPIO_IDX_START_SE; 306 port = CHV_IOSF_PORT_GPIO_SE; 307 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 308 gpio_index -= CHV_GPIO_IDX_START_SW; 309 port = CHV_IOSF_PORT_GPIO_SW; 310 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 311 gpio_index -= CHV_GPIO_IDX_START_E; 312 port = CHV_IOSF_PORT_GPIO_E; 313 } else { 314 port = CHV_IOSF_PORT_GPIO_N; 315 } 316 } else { 317 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 318 if (gpio_source != 0) { 319 drm_dbg_kms(&dev_priv->drm, 320 "unknown gpio source %u\n", gpio_source); 321 return; 322 } 323 324 if (gpio_index >= CHV_GPIO_IDX_START_E) { 325 drm_dbg_kms(&dev_priv->drm, 326 "invalid gpio index %u for GPIO N\n", 327 gpio_index); 328 return; 329 } 330 331 port = CHV_IOSF_PORT_GPIO_N; 332 } 333 334 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 335 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 336 337 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 338 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 339 340 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 341 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 342 vlv_iosf_sb_write(dev_priv, port, cfg0, 343 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 344 CHV_GPIO_GPIOTXSTATE(value)); 345 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 346 } 347 348 static void bxt_exec_gpio(struct intel_connector *connector, 349 u8 gpio_source, u8 gpio_index, bool value) 350 { 351 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 352 /* XXX: this table is a quick ugly hack. */ 353 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 354 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 355 356 if (!gpio_desc) { 357 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 358 NULL, gpio_index, 359 value ? GPIOD_OUT_LOW : 360 GPIOD_OUT_HIGH); 361 362 if (IS_ERR_OR_NULL(gpio_desc)) { 363 drm_err(&dev_priv->drm, 364 "GPIO index %u request failed (%ld)\n", 365 gpio_index, PTR_ERR(gpio_desc)); 366 return; 367 } 368 369 bxt_gpio_table[gpio_index] = gpio_desc; 370 } 371 372 gpiod_set_value(gpio_desc, value); 373 } 374 375 static void icl_exec_gpio(struct intel_connector *connector, 376 u8 gpio_source, u8 gpio_index, bool value) 377 { 378 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 379 380 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n"); 381 } 382 383 enum { 384 MIPI_RESET_1 = 0, 385 MIPI_AVDD_EN_1, 386 MIPI_BKLT_EN_1, 387 MIPI_AVEE_EN_1, 388 MIPI_VIO_EN_1, 389 MIPI_RESET_2, 390 MIPI_AVDD_EN_2, 391 MIPI_BKLT_EN_2, 392 MIPI_AVEE_EN_2, 393 MIPI_VIO_EN_2, 394 }; 395 396 static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv, 397 int gpio, bool value) 398 { 399 int index; 400 401 if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2)) 402 return; 403 404 switch (gpio) { 405 case MIPI_RESET_1: 406 case MIPI_RESET_2: 407 index = gpio == MIPI_RESET_1 ? HPD_PORT_A : HPD_PORT_B; 408 409 /* 410 * Disable HPD to set the pin to output, and set output 411 * value. The HPD pin should not be enabled for DSI anyway, 412 * assuming the board design and VBT are sane, and the pin isn't 413 * used by a non-DSI encoder. 414 * 415 * The locking protects against concurrent SHOTPLUG_CTL_DDI 416 * modifications in irq setup and handling. 417 */ 418 spin_lock_irq(&dev_priv->irq_lock); 419 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI, 420 SHOTPLUG_CTL_DDI_HPD_ENABLE(index) | 421 SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index), 422 value ? SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(index) : 0); 423 spin_unlock_irq(&dev_priv->irq_lock); 424 break; 425 case MIPI_AVDD_EN_1: 426 case MIPI_AVDD_EN_2: 427 index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; 428 429 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, 430 value ? PANEL_POWER_ON : 0); 431 break; 432 case MIPI_BKLT_EN_1: 433 case MIPI_BKLT_EN_2: 434 index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; 435 436 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, 437 value ? EDP_BLC_ENABLE : 0); 438 break; 439 case MIPI_AVEE_EN_1: 440 case MIPI_AVEE_EN_2: 441 index = gpio == MIPI_AVEE_EN_1 ? 1 : 2; 442 443 intel_de_rmw(dev_priv, GPIO(dev_priv, index), 444 GPIO_CLOCK_VAL_OUT, 445 GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT | 446 GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0)); 447 break; 448 case MIPI_VIO_EN_1: 449 case MIPI_VIO_EN_2: 450 index = gpio == MIPI_VIO_EN_1 ? 1 : 2; 451 452 intel_de_rmw(dev_priv, GPIO(dev_priv, index), 453 GPIO_DATA_VAL_OUT, 454 GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT | 455 GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0)); 456 break; 457 default: 458 MISSING_CASE(gpio); 459 } 460 } 461 462 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 463 { 464 struct drm_device *dev = intel_dsi->base.base.dev; 465 struct drm_i915_private *dev_priv = to_i915(dev); 466 struct intel_connector *connector = intel_dsi->attached_connector; 467 u8 gpio_source, gpio_index = 0, gpio_number; 468 bool value; 469 bool native = DISPLAY_VER(dev_priv) >= 11; 470 471 if (connector->panel.vbt.dsi.seq_version >= 3) 472 gpio_index = *data++; 473 474 gpio_number = *data++; 475 476 /* gpio source in sequence v2 only */ 477 if (connector->panel.vbt.dsi.seq_version == 2) 478 gpio_source = (*data >> 1) & 3; 479 else 480 gpio_source = 0; 481 482 if (connector->panel.vbt.dsi.seq_version >= 4 && *data & BIT(1)) 483 native = false; 484 485 /* pull up/down */ 486 value = *data++ & 1; 487 488 drm_dbg_kms(&dev_priv->drm, "GPIO index %u, number %u, source %u, native %s, set to %s\n", 489 gpio_index, gpio_number, gpio_source, str_yes_no(native), str_on_off(value)); 490 491 if (native) 492 icl_native_gpio_set_value(dev_priv, gpio_number, value); 493 else if (DISPLAY_VER(dev_priv) >= 11) 494 icl_exec_gpio(connector, gpio_source, gpio_index, value); 495 else if (IS_VALLEYVIEW(dev_priv)) 496 vlv_exec_gpio(connector, gpio_source, gpio_number, value); 497 else if (IS_CHERRYVIEW(dev_priv)) 498 chv_exec_gpio(connector, gpio_source, gpio_number, value); 499 else 500 bxt_exec_gpio(connector, gpio_source, gpio_index, value); 501 502 return data; 503 } 504 505 #ifdef CONFIG_ACPI 506 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 507 { 508 struct i2c_adapter_lookup *lookup = data; 509 struct intel_dsi *intel_dsi = lookup->intel_dsi; 510 struct acpi_resource_i2c_serialbus *sb; 511 struct i2c_adapter *adapter; 512 acpi_handle adapter_handle; 513 acpi_status status; 514 515 if (!i2c_acpi_get_i2c_resource(ares, &sb)) 516 return 1; 517 518 if (lookup->slave_addr != sb->slave_address) 519 return 1; 520 521 status = acpi_get_handle(lookup->dev_handle, 522 sb->resource_source.string_ptr, 523 &adapter_handle); 524 if (ACPI_FAILURE(status)) 525 return 1; 526 527 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 528 if (adapter) 529 intel_dsi->i2c_bus_num = adapter->nr; 530 531 return 1; 532 } 533 534 static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 535 const u16 slave_addr) 536 { 537 struct drm_device *drm_dev = intel_dsi->base.base.dev; 538 struct acpi_device *adev = ACPI_COMPANION(drm_dev->dev); 539 struct i2c_adapter_lookup lookup = { 540 .slave_addr = slave_addr, 541 .intel_dsi = intel_dsi, 542 .dev_handle = acpi_device_handle(adev), 543 }; 544 LIST_HEAD(resource_list); 545 546 acpi_dev_get_resources(adev, &resource_list, i2c_adapter_lookup, &lookup); 547 acpi_dev_free_resource_list(&resource_list); 548 } 549 #else 550 static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi, 551 const u16 slave_addr) 552 { 553 } 554 #endif 555 556 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 557 { 558 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 559 struct i2c_adapter *adapter; 560 struct i2c_msg msg; 561 int ret; 562 u8 vbt_i2c_bus_num = *(data + 2); 563 u16 slave_addr = *(u16 *)(data + 3); 564 u8 reg_offset = *(data + 5); 565 u8 payload_size = *(data + 6); 566 u8 *payload_data; 567 568 drm_dbg_kms(&i915->drm, "bus %d client-addr 0x%02x reg 0x%02x data %*ph\n", 569 vbt_i2c_bus_num, slave_addr, reg_offset, payload_size, data + 7); 570 571 if (intel_dsi->i2c_bus_num < 0) { 572 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 573 i2c_acpi_find_adapter(intel_dsi, slave_addr); 574 } 575 576 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 577 if (!adapter) { 578 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n"); 579 goto err_bus; 580 } 581 582 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 583 if (!payload_data) 584 goto err_alloc; 585 586 payload_data[0] = reg_offset; 587 memcpy(&payload_data[1], (data + 7), payload_size); 588 589 msg.addr = slave_addr; 590 msg.flags = 0; 591 msg.len = payload_size + 1; 592 msg.buf = payload_data; 593 594 ret = i2c_transfer(adapter, &msg, 1); 595 if (ret < 0) 596 drm_err(&i915->drm, 597 "Failed to xfer payload of size (%u) to reg (%u)\n", 598 payload_size, reg_offset); 599 600 kfree(payload_data); 601 err_alloc: 602 i2c_put_adapter(adapter); 603 err_bus: 604 return data + payload_size + 7; 605 } 606 607 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 608 { 609 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 610 611 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n"); 612 613 return data + *(data + 5) + 6; 614 } 615 616 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 617 { 618 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 619 #ifdef CONFIG_PMIC_OPREGION 620 u32 value, mask, reg_address; 621 u16 i2c_address; 622 int ret; 623 624 /* byte 0 aka PMIC Flag is reserved */ 625 i2c_address = get_unaligned_le16(data + 1); 626 reg_address = get_unaligned_le32(data + 3); 627 value = get_unaligned_le32(data + 7); 628 mask = get_unaligned_le32(data + 11); 629 630 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 631 reg_address, 632 value, mask); 633 if (ret) 634 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret); 635 #else 636 drm_err(&i915->drm, 637 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 638 #endif 639 640 return data + 15; 641 } 642 643 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 644 const u8 *data); 645 static const fn_mipi_elem_exec exec_elem[] = { 646 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 647 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 648 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 649 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 650 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 651 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 652 }; 653 654 /* 655 * MIPI Sequence from VBT #53 parsing logic 656 * We have already separated each seqence during bios parsing 657 * Following is generic execution function for any sequence 658 */ 659 660 static const char * const seq_name[] = { 661 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 662 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 663 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 664 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 665 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 666 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 667 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 668 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 669 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 670 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 671 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 672 }; 673 674 static const char *sequence_name(enum mipi_seq seq_id) 675 { 676 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 677 return seq_name[seq_id]; 678 else 679 return "(unknown)"; 680 } 681 682 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 683 enum mipi_seq seq_id) 684 { 685 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 686 struct intel_connector *connector = intel_dsi->attached_connector; 687 const u8 *data; 688 fn_mipi_elem_exec mipi_elem_exec; 689 690 if (drm_WARN_ON(&dev_priv->drm, 691 seq_id >= ARRAY_SIZE(connector->panel.vbt.dsi.sequence))) 692 return; 693 694 data = connector->panel.vbt.dsi.sequence[seq_id]; 695 if (!data) 696 return; 697 698 drm_WARN_ON(&dev_priv->drm, *data != seq_id); 699 700 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n", 701 seq_id, sequence_name(seq_id)); 702 703 /* Skip Sequence Byte. */ 704 data++; 705 706 /* Skip Size of Sequence. */ 707 if (connector->panel.vbt.dsi.seq_version >= 3) 708 data += 4; 709 710 while (1) { 711 u8 operation_byte = *data++; 712 u8 operation_size = 0; 713 714 if (operation_byte == MIPI_SEQ_ELEM_END) 715 break; 716 717 if (operation_byte < ARRAY_SIZE(exec_elem)) 718 mipi_elem_exec = exec_elem[operation_byte]; 719 else 720 mipi_elem_exec = NULL; 721 722 /* Size of Operation. */ 723 if (connector->panel.vbt.dsi.seq_version >= 3) 724 operation_size = *data++; 725 726 if (mipi_elem_exec) { 727 const u8 *next = data + operation_size; 728 729 data = mipi_elem_exec(intel_dsi, data); 730 731 /* Consistency check if we have size. */ 732 if (operation_size && data != next) { 733 drm_err(&dev_priv->drm, 734 "Inconsistent operation size\n"); 735 return; 736 } 737 } else if (operation_size) { 738 /* We have size, skip. */ 739 drm_dbg_kms(&dev_priv->drm, 740 "Unsupported MIPI operation byte %u\n", 741 operation_byte); 742 data += operation_size; 743 } else { 744 /* No size, can't skip without parsing. */ 745 drm_err(&dev_priv->drm, 746 "Unsupported MIPI operation byte %u\n", 747 operation_byte); 748 return; 749 } 750 } 751 } 752 753 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 754 enum mipi_seq seq_id) 755 { 756 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 757 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 758 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 759 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 760 761 intel_dsi_vbt_exec(intel_dsi, seq_id); 762 763 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 764 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 765 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 766 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 767 } 768 769 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 770 { 771 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); 772 773 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk); 774 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n", 775 intel_dsi->pixel_overlap); 776 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count); 777 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 778 drm_dbg_kms(&i915->drm, "Video mode format %s\n", 779 intel_dsi->video_mode == NON_BURST_SYNC_PULSE ? 780 "non-burst with sync pulse" : 781 intel_dsi->video_mode == NON_BURST_SYNC_EVENTS ? 782 "non-burst with sync events" : 783 intel_dsi->video_mode == BURST_MODE ? 784 "burst" : "<unknown>"); 785 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n", 786 intel_dsi->burst_mode_ratio); 787 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val); 788 drm_dbg_kms(&i915->drm, "Eot %s\n", 789 str_enabled_disabled(intel_dsi->eotp_pkt)); 790 drm_dbg_kms(&i915->drm, "Clockstop %s\n", 791 str_enabled_disabled(!intel_dsi->clock_stop)); 792 drm_dbg_kms(&i915->drm, "Mode %s\n", 793 intel_dsi->operation_mode ? "command" : "video"); 794 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 795 drm_dbg_kms(&i915->drm, 796 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 797 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 798 drm_dbg_kms(&i915->drm, 799 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 800 else 801 drm_dbg_kms(&i915->drm, "Dual link: NONE\n"); 802 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format); 803 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div); 804 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n", 805 intel_dsi->lp_rx_timeout); 806 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n", 807 intel_dsi->turn_arnd_val); 808 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count); 809 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n", 810 intel_dsi->hs_to_lp_count); 811 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 812 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 813 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n", 814 intel_dsi->clk_lp_to_hs_count); 815 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n", 816 intel_dsi->clk_hs_to_lp_count); 817 drm_dbg_kms(&i915->drm, "BTA %s\n", 818 str_enabled_disabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 819 } 820 821 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 822 { 823 struct drm_device *dev = intel_dsi->base.base.dev; 824 struct drm_i915_private *dev_priv = to_i915(dev); 825 struct intel_connector *connector = intel_dsi->attached_connector; 826 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 827 struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; 828 struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode; 829 u16 burst_mode_ratio; 830 enum port port; 831 832 drm_dbg_kms(&dev_priv->drm, "\n"); 833 834 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 835 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 836 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 837 intel_dsi->pixel_format = 838 pixel_format_from_register_bits( 839 mipi_config->videomode_color_format << 7); 840 841 intel_dsi->dual_link = mipi_config->dual_link; 842 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 843 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 844 intel_dsi->video_mode = mipi_config->video_transfer_mode; 845 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 846 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 847 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 848 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 849 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 850 intel_dsi->init_count = mipi_config->master_init_timer; 851 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 852 intel_dsi->video_frmt_cfg_bits = 853 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 854 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 855 856 /* Starting point, adjusted depending on dual link and burst mode */ 857 intel_dsi->pclk = mode->clock; 858 859 /* In dual link mode each port needs half of pixel clock */ 860 if (intel_dsi->dual_link) { 861 intel_dsi->pclk /= 2; 862 863 /* we can enable pixel_overlap if needed by panel. In this 864 * case we need to increase the pixelclock for extra pixels 865 */ 866 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 867 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 868 } 869 } 870 871 /* Burst Mode Ratio 872 * Target ddr frequency from VBT / non burst ddr freq 873 * multiply by 100 to preserve remainder 874 */ 875 if (intel_dsi->video_mode == BURST_MODE) { 876 if (mipi_config->target_burst_mode_freq) { 877 u32 bitrate = intel_dsi_bitrate(intel_dsi); 878 879 /* 880 * Sometimes the VBT contains a slightly lower clock, 881 * then the bitrate we have calculated, in this case 882 * just replace it with the calculated bitrate. 883 */ 884 if (mipi_config->target_burst_mode_freq < bitrate && 885 intel_fuzzy_clock_check( 886 mipi_config->target_burst_mode_freq, 887 bitrate)) 888 mipi_config->target_burst_mode_freq = bitrate; 889 890 if (mipi_config->target_burst_mode_freq < bitrate) { 891 drm_err(&dev_priv->drm, 892 "Burst mode freq is less than computed\n"); 893 return false; 894 } 895 896 burst_mode_ratio = DIV_ROUND_UP( 897 mipi_config->target_burst_mode_freq * 100, 898 bitrate); 899 900 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 901 } else { 902 drm_err(&dev_priv->drm, 903 "Burst mode target is not set\n"); 904 return false; 905 } 906 } else 907 burst_mode_ratio = 100; 908 909 intel_dsi->burst_mode_ratio = burst_mode_ratio; 910 911 /* delays in VBT are in unit of 100us, so need to convert 912 * here in ms 913 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 914 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 915 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 916 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 917 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 918 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 919 920 intel_dsi->i2c_bus_num = -1; 921 922 /* a regular driver would get the device in probe */ 923 for_each_dsi_port(port, intel_dsi->ports) { 924 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 925 } 926 927 return true; 928 } 929 930 /* 931 * On some BYT/CHT devs some sequences are incomplete and we need to manually 932 * control some GPIOs. We need to add a GPIO lookup table before we get these. 933 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 934 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 935 */ 936 static struct gpiod_lookup_table pmic_panel_gpio_table = { 937 /* Intel GFX is consumer */ 938 .dev_id = "0000:00:02.0", 939 .table = { 940 /* Panel EN/DISABLE */ 941 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 942 { } 943 }, 944 }; 945 946 static struct gpiod_lookup_table soc_panel_gpio_table = { 947 .dev_id = "0000:00:02.0", 948 .table = { 949 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 950 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 951 { } 952 }, 953 }; 954 955 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 956 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 957 "pwm0_grp", "pwm"), 958 }; 959 960 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 961 { 962 struct drm_device *dev = intel_dsi->base.base.dev; 963 struct drm_i915_private *dev_priv = to_i915(dev); 964 struct intel_connector *connector = intel_dsi->attached_connector; 965 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 966 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 967 bool want_backlight_gpio = false; 968 bool want_panel_gpio = false; 969 struct pinctrl *pinctrl; 970 int ret; 971 972 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 973 mipi_config->pwm_blc == PPS_BLC_PMIC) { 974 gpiod_add_lookup_table(&pmic_panel_gpio_table); 975 want_panel_gpio = true; 976 } 977 978 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 979 gpiod_add_lookup_table(&soc_panel_gpio_table); 980 want_panel_gpio = true; 981 want_backlight_gpio = true; 982 983 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 984 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 985 ARRAY_SIZE(soc_pwm_pinctrl_map)); 986 if (ret) 987 drm_err(&dev_priv->drm, 988 "Failed to register pwm0 pinmux mapping\n"); 989 990 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 991 if (IS_ERR(pinctrl)) 992 drm_err(&dev_priv->drm, 993 "Failed to set pinmux to PWM\n"); 994 } 995 996 if (want_panel_gpio) { 997 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 998 if (IS_ERR(intel_dsi->gpio_panel)) { 999 drm_err(&dev_priv->drm, 1000 "Failed to own gpio for panel control\n"); 1001 intel_dsi->gpio_panel = NULL; 1002 } 1003 } 1004 1005 if (want_backlight_gpio) { 1006 intel_dsi->gpio_backlight = 1007 gpiod_get(dev->dev, "backlight", flags); 1008 if (IS_ERR(intel_dsi->gpio_backlight)) { 1009 drm_err(&dev_priv->drm, 1010 "Failed to own gpio for backlight control\n"); 1011 intel_dsi->gpio_backlight = NULL; 1012 } 1013 } 1014 } 1015 1016 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 1017 { 1018 struct drm_device *dev = intel_dsi->base.base.dev; 1019 struct drm_i915_private *dev_priv = to_i915(dev); 1020 struct intel_connector *connector = intel_dsi->attached_connector; 1021 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; 1022 1023 if (intel_dsi->gpio_panel) { 1024 gpiod_put(intel_dsi->gpio_panel); 1025 intel_dsi->gpio_panel = NULL; 1026 } 1027 1028 if (intel_dsi->gpio_backlight) { 1029 gpiod_put(intel_dsi->gpio_backlight); 1030 intel_dsi->gpio_backlight = NULL; 1031 } 1032 1033 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1034 mipi_config->pwm_blc == PPS_BLC_PMIC) 1035 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 1036 1037 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 1038 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 1039 gpiod_remove_lookup_table(&soc_panel_gpio_table); 1040 } 1041 } 1042