xref: /linux/drivers/gpu/drm/i915/display/intel_dsb.h (revision 06a130e42a5bfc84795464bff023bff4c16f58c5)
1 /* SPDX-License-Identifier: MIT
2  *
3  * Copyright © 2019 Intel Corporation
4  */
5 
6 #ifndef _INTEL_DSB_H
7 #define _INTEL_DSB_H
8 
9 #include <linux/types.h>
10 
11 #include "i915_reg_defs.h"
12 
13 struct intel_atomic_state;
14 struct intel_crtc;
15 struct intel_crtc_state;
16 struct intel_display;
17 struct intel_dsb;
18 
19 enum pipe;
20 
21 enum intel_dsb_id {
22 	INTEL_DSB_0,
23 	INTEL_DSB_1,
24 	INTEL_DSB_2,
25 
26 	I915_MAX_DSBS,
27 };
28 
29 struct intel_dsb *intel_dsb_prepare(struct intel_atomic_state *state,
30 				    struct intel_crtc *crtc,
31 				    enum intel_dsb_id dsb_id,
32 				    unsigned int max_cmds);
33 void intel_dsb_finish(struct intel_dsb *dsb);
34 void intel_dsb_cleanup(struct intel_dsb *dsb);
35 void intel_dsb_reg_write(struct intel_dsb *dsb,
36 			 i915_reg_t reg, u32 val);
37 void intel_dsb_reg_write_masked(struct intel_dsb *dsb,
38 				i915_reg_t reg, u32 mask, u32 val);
39 void intel_dsb_noop(struct intel_dsb *dsb, int count);
40 void intel_dsb_nonpost_start(struct intel_dsb *dsb);
41 void intel_dsb_nonpost_end(struct intel_dsb *dsb);
42 void intel_dsb_wait_scanline_in(struct intel_atomic_state *state,
43 				struct intel_dsb *dsb,
44 				int lower, int upper);
45 void intel_dsb_wait_scanline_out(struct intel_atomic_state *state,
46 				 struct intel_dsb *dsb,
47 				 int lower, int upper);
48 void intel_dsb_chain(struct intel_atomic_state *state,
49 		     struct intel_dsb *dsb,
50 		     struct intel_dsb *chained_dsb,
51 		     bool wait_for_vblank);
52 
53 void intel_dsb_commit(struct intel_dsb *dsb,
54 		      bool wait_for_vblank);
55 void intel_dsb_wait(struct intel_dsb *dsb);
56 
57 void intel_dsb_irq_handler(struct intel_display *display,
58 			   enum pipe pipe, enum intel_dsb_id dsb_id);
59 
60 #endif
61