1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 #include <linux/types.h> 29 30 #include "intel_wakeref.h" 31 32 #define for_each_shared_dpll(__i915, __pll, __i) \ 33 for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \ 34 ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++) 35 36 enum tc_port; 37 struct drm_i915_private; 38 struct intel_atomic_state; 39 struct intel_crtc; 40 struct intel_crtc_state; 41 struct intel_encoder; 42 struct intel_shared_dpll; 43 struct intel_shared_dpll_funcs; 44 45 /** 46 * enum intel_dpll_id - possible DPLL ids 47 * 48 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 49 */ 50 enum intel_dpll_id { 51 /** 52 * @DPLL_ID_PRIVATE: non-shared dpll in use 53 */ 54 DPLL_ID_PRIVATE = -1, 55 56 /** 57 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 58 */ 59 DPLL_ID_PCH_PLL_A = 0, 60 /** 61 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 62 */ 63 DPLL_ID_PCH_PLL_B = 1, 64 65 66 /** 67 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 68 */ 69 DPLL_ID_WRPLL1 = 0, 70 /** 71 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 72 */ 73 DPLL_ID_WRPLL2 = 1, 74 /** 75 * @DPLL_ID_SPLL: HSW and BDW SPLL 76 */ 77 DPLL_ID_SPLL = 2, 78 /** 79 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 80 */ 81 DPLL_ID_LCPLL_810 = 3, 82 /** 83 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 84 */ 85 DPLL_ID_LCPLL_1350 = 4, 86 /** 87 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 88 */ 89 DPLL_ID_LCPLL_2700 = 5, 90 91 92 /** 93 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 94 */ 95 DPLL_ID_SKL_DPLL0 = 0, 96 /** 97 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 98 */ 99 DPLL_ID_SKL_DPLL1 = 1, 100 /** 101 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 102 */ 103 DPLL_ID_SKL_DPLL2 = 2, 104 /** 105 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 106 */ 107 DPLL_ID_SKL_DPLL3 = 3, 108 109 110 /** 111 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 112 */ 113 DPLL_ID_ICL_DPLL0 = 0, 114 /** 115 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 116 */ 117 DPLL_ID_ICL_DPLL1 = 1, 118 /** 119 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 120 */ 121 DPLL_ID_EHL_DPLL4 = 2, 122 /** 123 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 124 */ 125 DPLL_ID_ICL_TBTPLL = 2, 126 /** 127 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 128 * TGL TC PLL 1 port 1 (TC1) 129 */ 130 DPLL_ID_ICL_MGPLL1 = 3, 131 /** 132 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 133 * TGL TC PLL 1 port 2 (TC2) 134 */ 135 DPLL_ID_ICL_MGPLL2 = 4, 136 /** 137 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 138 * TGL TC PLL 1 port 3 (TC3) 139 */ 140 DPLL_ID_ICL_MGPLL3 = 5, 141 /** 142 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 143 * TGL TC PLL 1 port 4 (TC4) 144 */ 145 DPLL_ID_ICL_MGPLL4 = 6, 146 /** 147 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 148 */ 149 DPLL_ID_TGL_MGPLL5 = 7, 150 /** 151 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 152 */ 153 DPLL_ID_TGL_MGPLL6 = 8, 154 155 /** 156 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 157 */ 158 DPLL_ID_DG1_DPLL0 = 0, 159 /** 160 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 161 */ 162 DPLL_ID_DG1_DPLL1 = 1, 163 /** 164 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 165 */ 166 DPLL_ID_DG1_DPLL2 = 2, 167 /** 168 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 169 */ 170 DPLL_ID_DG1_DPLL3 = 3, 171 }; 172 173 #define I915_NUM_PLLS 9 174 175 enum icl_port_dpll_id { 176 ICL_PORT_DPLL_DEFAULT, 177 ICL_PORT_DPLL_MG_PHY, 178 179 ICL_PORT_DPLL_COUNT, 180 }; 181 182 struct intel_dpll_hw_state { 183 /* i9xx, pch plls */ 184 u32 dpll; 185 u32 dpll_md; 186 u32 fp0; 187 u32 fp1; 188 189 /* hsw, bdw */ 190 u32 wrpll; 191 u32 spll; 192 193 /* skl */ 194 /* 195 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 196 * lower part of ctrl1 and they get shifted into position when writing 197 * the register. This allows us to easily compare the state to share 198 * the DPLL. 199 */ 200 u32 ctrl1; 201 /* HDMI only, 0 when used for DP */ 202 u32 cfgcr1, cfgcr2; 203 204 /* icl */ 205 u32 cfgcr0; 206 207 /* tgl */ 208 u32 div0; 209 210 /* bxt */ 211 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 212 213 /* 214 * ICL uses the following, already defined: 215 * u32 cfgcr0, cfgcr1; 216 */ 217 u32 mg_refclkin_ctl; 218 u32 mg_clktop2_coreclkctl1; 219 u32 mg_clktop2_hsclkctl; 220 u32 mg_pll_div0; 221 u32 mg_pll_div1; 222 u32 mg_pll_lf; 223 u32 mg_pll_frac_lock; 224 u32 mg_pll_ssc; 225 u32 mg_pll_bias; 226 u32 mg_pll_tdc_coldst_bias; 227 u32 mg_pll_bias_mask; 228 u32 mg_pll_tdc_coldst_bias_mask; 229 }; 230 231 /** 232 * struct intel_shared_dpll_state - hold the DPLL atomic state 233 * 234 * This structure holds an atomic state for the DPLL, that can represent 235 * either its current state (in struct &intel_shared_dpll) or a desired 236 * future state which would be applied by an atomic mode set (stored in 237 * a struct &intel_atomic_state). 238 * 239 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 240 */ 241 struct intel_shared_dpll_state { 242 /** 243 * @pipe_mask: mask of pipes using this DPLL, active or not 244 */ 245 u8 pipe_mask; 246 247 /** 248 * @hw_state: hardware configuration for the DPLL stored in 249 * struct &intel_dpll_hw_state. 250 */ 251 struct intel_dpll_hw_state hw_state; 252 }; 253 254 /** 255 * struct dpll_info - display PLL platform specific info 256 */ 257 struct dpll_info { 258 /** 259 * @name: DPLL name; used for logging 260 */ 261 const char *name; 262 263 /** 264 * @funcs: platform specific hooks 265 */ 266 const struct intel_shared_dpll_funcs *funcs; 267 268 /** 269 * @id: unique indentifier for this DPLL 270 */ 271 enum intel_dpll_id id; 272 273 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 274 /** 275 * @flags: 276 * 277 * INTEL_DPLL_ALWAYS_ON 278 * Inform the state checker that the DPLL is kept enabled even if 279 * not in use by any CRTC. 280 */ 281 u32 flags; 282 }; 283 284 /** 285 * struct intel_shared_dpll - display PLL with tracked state and users 286 */ 287 struct intel_shared_dpll { 288 /** 289 * @state: 290 * 291 * Store the state for the pll, including its hw state 292 * and CRTCs using it. 293 */ 294 struct intel_shared_dpll_state state; 295 296 /** 297 * @index: index for atomic state 298 */ 299 u8 index; 300 301 /** 302 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL 303 */ 304 u8 active_mask; 305 306 /** 307 * @on: is the PLL actually active? Disabled during modeset 308 */ 309 bool on; 310 311 /** 312 * @info: platform specific info 313 */ 314 const struct dpll_info *info; 315 316 /** 317 * @wakeref: In some platforms a device-level runtime pm reference may 318 * need to be grabbed to disable DC states while this DPLL is enabled 319 */ 320 intel_wakeref_t wakeref; 321 }; 322 323 #define SKL_DPLL0 0 324 #define SKL_DPLL1 1 325 #define SKL_DPLL2 2 326 #define SKL_DPLL3 3 327 328 /* shared dpll functions */ 329 struct intel_shared_dpll * 330 intel_get_shared_dpll_by_id(struct drm_i915_private *i915, 331 enum intel_dpll_id id); 332 void assert_shared_dpll(struct drm_i915_private *i915, 333 struct intel_shared_dpll *pll, 334 bool state); 335 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 336 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 337 int intel_compute_shared_dplls(struct intel_atomic_state *state, 338 struct intel_crtc *crtc, 339 struct intel_encoder *encoder); 340 int intel_reserve_shared_dplls(struct intel_atomic_state *state, 341 struct intel_crtc *crtc, 342 struct intel_encoder *encoder); 343 void intel_release_shared_dplls(struct intel_atomic_state *state, 344 struct intel_crtc *crtc); 345 void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, 346 const struct intel_shared_dpll *pll, 347 struct intel_shared_dpll_state *shared_dpll_state); 348 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 349 enum icl_port_dpll_id port_dpll_id); 350 void intel_update_active_dpll(struct intel_atomic_state *state, 351 struct intel_crtc *crtc, 352 struct intel_encoder *encoder); 353 int intel_dpll_get_freq(struct drm_i915_private *i915, 354 const struct intel_shared_dpll *pll, 355 const struct intel_dpll_hw_state *pll_state); 356 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, 357 struct intel_shared_dpll *pll, 358 struct intel_dpll_hw_state *hw_state); 359 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); 360 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); 361 void intel_shared_dpll_swap_state(struct intel_atomic_state *state); 362 void intel_shared_dpll_init(struct drm_i915_private *i915); 363 void intel_dpll_update_ref_clks(struct drm_i915_private *i915); 364 void intel_dpll_readout_hw_state(struct drm_i915_private *i915); 365 void intel_dpll_sanitize_state(struct drm_i915_private *i915); 366 367 void intel_dpll_dump_hw_state(struct drm_i915_private *i915, 368 const struct intel_dpll_hw_state *hw_state); 369 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 370 bool intel_dpll_is_combophy(enum intel_dpll_id id); 371 372 void intel_shared_dpll_state_verify(struct intel_atomic_state *state, 373 struct intel_crtc *crtc); 374 void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state); 375 376 #endif /* _INTEL_DPLL_MGR_H_ */ 377