1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 #include <linux/types.h> 29 30 #include "intel_display_power.h" 31 #include "intel_wakeref.h" 32 33 #define for_each_dpll(__display, __pll, __i) \ 34 for ((__i) = 0; (__i) < (__display)->dpll.num_dpll && \ 35 ((__pll) = &(__display)->dpll.dplls[(__i)]) ; (__i)++) 36 37 enum tc_port; 38 struct drm_printer; 39 struct intel_atomic_state; 40 struct intel_crtc; 41 struct intel_crtc_state; 42 struct intel_dpll_funcs; 43 struct intel_encoder; 44 struct intel_shared_dpll; 45 46 /** 47 * enum intel_dpll_id - possible DPLL ids 48 * 49 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 50 */ 51 enum intel_dpll_id { 52 /** 53 * @DPLL_ID_PRIVATE: non-shared dpll in use 54 */ 55 DPLL_ID_PRIVATE = -1, 56 57 /** 58 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 59 */ 60 DPLL_ID_PCH_PLL_A = 0, 61 /** 62 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 63 */ 64 DPLL_ID_PCH_PLL_B = 1, 65 66 67 /** 68 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 69 */ 70 DPLL_ID_WRPLL1 = 0, 71 /** 72 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 73 */ 74 DPLL_ID_WRPLL2 = 1, 75 /** 76 * @DPLL_ID_SPLL: HSW and BDW SPLL 77 */ 78 DPLL_ID_SPLL = 2, 79 /** 80 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 81 */ 82 DPLL_ID_LCPLL_810 = 3, 83 /** 84 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 85 */ 86 DPLL_ID_LCPLL_1350 = 4, 87 /** 88 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 89 */ 90 DPLL_ID_LCPLL_2700 = 5, 91 92 93 /** 94 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 95 */ 96 DPLL_ID_SKL_DPLL0 = 0, 97 /** 98 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 99 */ 100 DPLL_ID_SKL_DPLL1 = 1, 101 /** 102 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 103 */ 104 DPLL_ID_SKL_DPLL2 = 2, 105 /** 106 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 107 */ 108 DPLL_ID_SKL_DPLL3 = 3, 109 110 111 /** 112 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 113 */ 114 DPLL_ID_ICL_DPLL0 = 0, 115 /** 116 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 117 */ 118 DPLL_ID_ICL_DPLL1 = 1, 119 /** 120 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 121 */ 122 DPLL_ID_EHL_DPLL4 = 2, 123 /** 124 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 125 */ 126 DPLL_ID_ICL_TBTPLL = 2, 127 /** 128 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 129 * TGL TC PLL 1 port 1 (TC1) 130 */ 131 DPLL_ID_ICL_MGPLL1 = 3, 132 /** 133 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 134 * TGL TC PLL 1 port 2 (TC2) 135 */ 136 DPLL_ID_ICL_MGPLL2 = 4, 137 /** 138 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 139 * TGL TC PLL 1 port 3 (TC3) 140 */ 141 DPLL_ID_ICL_MGPLL3 = 5, 142 /** 143 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 144 * TGL TC PLL 1 port 4 (TC4) 145 */ 146 DPLL_ID_ICL_MGPLL4 = 6, 147 /** 148 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 149 */ 150 DPLL_ID_TGL_MGPLL5 = 7, 151 /** 152 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 153 */ 154 DPLL_ID_TGL_MGPLL6 = 8, 155 156 /** 157 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 158 */ 159 DPLL_ID_DG1_DPLL0 = 0, 160 /** 161 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 162 */ 163 DPLL_ID_DG1_DPLL1 = 1, 164 /** 165 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 166 */ 167 DPLL_ID_DG1_DPLL2 = 2, 168 /** 169 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 170 */ 171 DPLL_ID_DG1_DPLL3 = 3, 172 }; 173 174 #define I915_NUM_PLLS 9 175 176 enum icl_port_dpll_id { 177 ICL_PORT_DPLL_DEFAULT, 178 ICL_PORT_DPLL_MG_PHY, 179 180 ICL_PORT_DPLL_COUNT, 181 }; 182 183 struct i9xx_dpll_hw_state { 184 u32 dpll; 185 u32 dpll_md; 186 u32 fp0; 187 u32 fp1; 188 }; 189 190 struct hsw_dpll_hw_state { 191 u32 wrpll; 192 u32 spll; 193 }; 194 195 struct skl_dpll_hw_state { 196 /* 197 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 198 * lower part of ctrl1 and they get shifted into position when writing 199 * the register. This allows us to easily compare the state to share 200 * the DPLL. 201 */ 202 u32 ctrl1; 203 /* HDMI only, 0 when used for DP */ 204 u32 cfgcr1, cfgcr2; 205 }; 206 207 struct bxt_dpll_hw_state { 208 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 209 }; 210 211 struct icl_dpll_hw_state { 212 u32 cfgcr0, cfgcr1; 213 214 /* tgl */ 215 u32 div0; 216 217 u32 mg_refclkin_ctl; 218 u32 mg_clktop2_coreclkctl1; 219 u32 mg_clktop2_hsclkctl; 220 u32 mg_pll_div0; 221 u32 mg_pll_div1; 222 u32 mg_pll_lf; 223 u32 mg_pll_frac_lock; 224 u32 mg_pll_ssc; 225 u32 mg_pll_bias; 226 u32 mg_pll_tdc_coldst_bias; 227 u32 mg_pll_bias_mask; 228 u32 mg_pll_tdc_coldst_bias_mask; 229 }; 230 231 struct intel_mpllb_state { 232 u32 clock; /* in KHz */ 233 u32 ref_control; 234 u32 mpllb_cp; 235 u32 mpllb_div; 236 u32 mpllb_div2; 237 u32 mpllb_fracn1; 238 u32 mpllb_fracn2; 239 u32 mpllb_sscen; 240 u32 mpllb_sscstep; 241 }; 242 243 struct intel_c10pll_state { 244 u32 clock; /* in KHz */ 245 u8 tx; 246 u8 cmn; 247 u8 pll[20]; 248 }; 249 250 struct intel_c20pll_state { 251 u32 clock; /* in kHz */ 252 u16 tx[3]; 253 u16 cmn[4]; 254 union { 255 u16 mplla[10]; 256 u16 mpllb[11]; 257 }; 258 }; 259 260 struct intel_cx0pll_state { 261 union { 262 struct intel_c10pll_state c10; 263 struct intel_c20pll_state c20; 264 }; 265 bool ssc_enabled; 266 bool use_c10; 267 bool tbt_mode; 268 }; 269 270 struct intel_lt_phy_pll_state { 271 u32 clock; /* in kHz */ 272 u8 addr_msb[13]; 273 u8 addr_lsb[13]; 274 u8 data[13][4]; 275 u8 config[3]; 276 bool ssc_enabled; 277 bool tbt_mode; 278 }; 279 280 struct intel_dpll_hw_state { 281 union { 282 struct i9xx_dpll_hw_state i9xx; 283 struct hsw_dpll_hw_state hsw; 284 struct skl_dpll_hw_state skl; 285 struct bxt_dpll_hw_state bxt; 286 struct icl_dpll_hw_state icl; 287 struct intel_mpllb_state mpllb; 288 struct intel_cx0pll_state cx0pll; 289 struct intel_lt_phy_pll_state ltpll; 290 }; 291 }; 292 293 /** 294 * struct intel_dpll_state - hold the DPLL atomic state 295 * 296 * This structure holds an atomic state for the DPLL, that can represent 297 * either its current state (in struct &intel_shared_dpll) or a desired 298 * future state which would be applied by an atomic mode set (stored in 299 * a struct &intel_atomic_state). 300 * 301 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 302 */ 303 struct intel_dpll_state { 304 /** 305 * @pipe_mask: mask of pipes using this DPLL, active or not 306 */ 307 u8 pipe_mask; 308 309 /** 310 * @hw_state: hardware configuration for the DPLL stored in 311 * struct &intel_dpll_hw_state. 312 */ 313 struct intel_dpll_hw_state hw_state; 314 }; 315 316 /** 317 * struct dpll_info - display PLL platform specific info 318 */ 319 struct dpll_info { 320 /** 321 * @name: DPLL name; used for logging 322 */ 323 const char *name; 324 325 /** 326 * @funcs: platform specific hooks 327 */ 328 const struct intel_dpll_funcs *funcs; 329 330 /** 331 * @id: unique identifier for this DPLL 332 */ 333 enum intel_dpll_id id; 334 335 /** 336 * @power_domain: extra power domain required by the DPLL 337 */ 338 enum intel_display_power_domain power_domain; 339 340 /** 341 * @always_on: 342 * 343 * Inform the state checker that the DPLL is kept enabled even if 344 * not in use by any CRTC. 345 */ 346 bool always_on; 347 348 /** 349 * @is_alt_port_dpll: 350 * 351 * Inform the state checker that the DPLL can be used as a fallback 352 * (for TC->TBT fallback). 353 */ 354 bool is_alt_port_dpll; 355 }; 356 357 /** 358 * struct intel_dpll - display PLL with tracked state and users 359 */ 360 struct intel_dpll { 361 /** 362 * @state: 363 * 364 * Store the state for the pll, including its hw state 365 * and CRTCs using it. 366 */ 367 struct intel_dpll_state state; 368 369 /** 370 * @index: index for atomic state 371 */ 372 u8 index; 373 374 /** 375 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL 376 */ 377 u8 active_mask; 378 379 /** 380 * @on: is the PLL actually active? Disabled during modeset 381 */ 382 bool on; 383 384 /** 385 * @info: platform specific info 386 */ 387 const struct dpll_info *info; 388 389 /** 390 * @wakeref: In some platforms a device-level runtime pm reference may 391 * need to be grabbed to disable DC states while this DPLL is enabled 392 */ 393 intel_wakeref_t wakeref; 394 }; 395 396 #define SKL_DPLL0 0 397 #define SKL_DPLL1 1 398 #define SKL_DPLL2 2 399 #define SKL_DPLL3 3 400 401 /* dpll functions */ 402 struct intel_dpll * 403 intel_get_dpll_by_id(struct intel_display *display, 404 enum intel_dpll_id id); 405 void assert_dpll(struct intel_display *display, 406 struct intel_dpll *pll, 407 bool state); 408 #define assert_dpll_enabled(d, p) assert_dpll(d, p, true) 409 #define assert_dpll_disabled(d, p) assert_dpll(d, p, false) 410 int intel_dpll_compute(struct intel_atomic_state *state, 411 struct intel_crtc *crtc, 412 struct intel_encoder *encoder); 413 int intel_dpll_reserve(struct intel_atomic_state *state, 414 struct intel_crtc *crtc, 415 struct intel_encoder *encoder); 416 void intel_dpll_release(struct intel_atomic_state *state, 417 struct intel_crtc *crtc); 418 void intel_dpll_crtc_put(const struct intel_crtc *crtc, 419 const struct intel_dpll *pll, 420 struct intel_dpll_state *shared_dpll_state); 421 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 422 enum icl_port_dpll_id port_dpll_id); 423 void intel_dpll_update_active(struct intel_atomic_state *state, 424 struct intel_crtc *crtc, 425 struct intel_encoder *encoder); 426 int intel_dpll_get_freq(struct intel_display *display, 427 const struct intel_dpll *pll, 428 const struct intel_dpll_hw_state *dpll_hw_state); 429 bool intel_dpll_get_hw_state(struct intel_display *display, 430 struct intel_dpll *pll, 431 struct intel_dpll_hw_state *dpll_hw_state); 432 void intel_dpll_enable(const struct intel_crtc_state *crtc_state); 433 void intel_dpll_disable(const struct intel_crtc_state *crtc_state); 434 void intel_dpll_swap_state(struct intel_atomic_state *state); 435 void intel_dpll_init(struct intel_display *display); 436 void intel_dpll_update_ref_clks(struct intel_display *display); 437 void intel_dpll_readout_hw_state(struct intel_display *display); 438 void intel_dpll_sanitize_state(struct intel_display *display); 439 440 void intel_dpll_dump_hw_state(struct intel_display *display, 441 struct drm_printer *p, 442 const struct intel_dpll_hw_state *dpll_hw_state); 443 bool intel_dpll_compare_hw_state(struct intel_display *display, 444 const struct intel_dpll_hw_state *a, 445 const struct intel_dpll_hw_state *b); 446 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 447 bool intel_dpll_is_combophy(enum intel_dpll_id id); 448 449 void intel_dpll_state_verify(struct intel_atomic_state *state, 450 struct intel_crtc *crtc); 451 void intel_dpll_verify_disabled(struct intel_atomic_state *state); 452 453 #endif /* _INTEL_DPLL_MGR_H_ */ 454