xref: /linux/drivers/gpu/drm/i915/display/intel_dpll.h (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2020 Intel Corporation
4  */
5 
6 #ifndef _INTEL_DPLL_H_
7 #define _INTEL_DPLL_H_
8 
9 #include <linux/types.h>
10 
11 struct dpll;
12 struct drm_i915_private;
13 struct intel_atomic_state;
14 struct intel_crtc;
15 struct intel_crtc_state;
16 enum pipe;
17 
18 void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv);
19 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
20 				  struct intel_crtc *crtc);
21 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
22 				    struct intel_crtc *crtc);
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
27 void vlv_compute_dpll(struct intel_crtc_state *crtc_state);
28 void chv_compute_dpll(struct intel_crtc_state *crtc_state);
29 
30 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
31 		     const struct dpll *dpll);
32 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
33 
34 void chv_enable_pll(const struct intel_crtc_state *crtc_state);
35 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
36 void vlv_enable_pll(const struct intel_crtc_state *crtc_state);
37 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe);
38 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state);
39 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state);
40 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
41 			struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
43 
44 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe);
45 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe);
46 
47 #endif
48