1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DPIO_PHY_H__ 7 #define __INTEL_DPIO_PHY_H__ 8 9 #include <linux/types.h> 10 11 enum pipe; 12 enum port; 13 struct intel_crtc_state; 14 struct intel_digital_port; 15 struct intel_display; 16 struct intel_encoder; 17 18 enum dpio_channel { 19 DPIO_CH0, 20 DPIO_CH1, 21 }; 22 23 enum dpio_phy { 24 DPIO_PHY0, 25 DPIO_PHY1, 26 DPIO_PHY2, 27 }; 28 29 #ifdef I915 30 void bxt_port_to_phy_channel(struct intel_display *display, enum port port, 31 enum dpio_phy *phy, enum dpio_channel *ch); 32 void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, 33 const struct intel_crtc_state *crtc_state); 34 void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy); 35 void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy); 36 bool bxt_dpio_phy_is_enabled(struct intel_display *display, 37 enum dpio_phy phy); 38 bool bxt_dpio_phy_verify_state(struct intel_display *display, 39 enum dpio_phy phy); 40 u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count); 41 void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder, 42 u8 lane_lat_optim_mask); 43 u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); 44 45 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port); 46 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port); 47 enum dpio_phy vlv_pipe_to_phy(enum pipe pipe); 48 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe); 49 50 void chv_set_phy_signal_level(struct intel_encoder *encoder, 51 const struct intel_crtc_state *crtc_state, 52 u32 deemph_reg_value, u32 margin_reg_value, 53 bool uniq_trans_scale); 54 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 55 const struct intel_crtc_state *crtc_state, 56 bool reset); 57 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 58 const struct intel_crtc_state *crtc_state); 59 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 60 const struct intel_crtc_state *crtc_state); 61 void chv_phy_release_cl2_override(struct intel_encoder *encoder); 62 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 63 const struct intel_crtc_state *old_crtc_state); 64 65 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 66 const struct intel_crtc_state *crtc_state, 67 u32 demph_reg_value, u32 preemph_reg_value, 68 u32 uniqtranscale_reg_value, u32 tx3_demph); 69 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 70 const struct intel_crtc_state *crtc_state); 71 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 72 const struct intel_crtc_state *crtc_state); 73 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 74 const struct intel_crtc_state *old_crtc_state); 75 void vlv_wait_port_ready(struct intel_encoder *encoder, 76 unsigned int expected_mask); 77 #else 78 static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port, 79 enum dpio_phy *phy, enum dpio_channel *ch) 80 { 81 } 82 static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, 83 const struct intel_crtc_state *crtc_state) 84 { 85 } 86 static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) 87 { 88 } 89 static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy) 90 { 91 } 92 static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display, 93 enum dpio_phy phy) 94 { 95 return false; 96 } 97 static inline bool bxt_dpio_phy_verify_state(struct intel_display *display, 98 enum dpio_phy phy) 99 { 100 return true; 101 } 102 static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) 103 { 104 return 0; 105 } 106 static inline void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder, 107 u8 lane_lat_optim_mask) 108 { 109 } 110 static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 111 { 112 return 0; 113 } 114 static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 115 { 116 return DPIO_CH0; 117 } 118 static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 119 { 120 return DPIO_PHY0; 121 } 122 static inline enum dpio_phy vlv_pipe_to_phy(enum pipe pipe) 123 { 124 return DPIO_PHY0; 125 } 126 static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) 127 { 128 return DPIO_CH0; 129 } 130 static inline void chv_set_phy_signal_level(struct intel_encoder *encoder, 131 const struct intel_crtc_state *crtc_state, 132 u32 deemph_reg_value, u32 margin_reg_value, 133 bool uniq_trans_scale) 134 { 135 } 136 static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder, 137 const struct intel_crtc_state *crtc_state, 138 bool reset) 139 { 140 } 141 static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 142 const struct intel_crtc_state *crtc_state) 143 { 144 } 145 static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 146 const struct intel_crtc_state *crtc_state) 147 { 148 } 149 static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder) 150 { 151 } 152 static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder, 153 const struct intel_crtc_state *old_crtc_state) 154 { 155 } 156 157 static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder, 158 const struct intel_crtc_state *crtc_state, 159 u32 demph_reg_value, u32 preemph_reg_value, 160 u32 uniqtranscale_reg_value, u32 tx3_demph) 161 { 162 } 163 static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 164 const struct intel_crtc_state *crtc_state) 165 { 166 } 167 static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 168 const struct intel_crtc_state *crtc_state) 169 { 170 } 171 static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder, 172 const struct intel_crtc_state *old_crtc_state) 173 { 174 } 175 static inline void vlv_wait_port_ready(struct intel_encoder *encoder, 176 unsigned int expected_mask) 177 { 178 } 179 #endif 180 181 #endif /* __INTEL_DPIO_PHY_H__ */ 182