1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "bxt_dpio_phy_regs.h" 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 #include "intel_ddi.h" 28 #include "intel_ddi_buf_trans.h" 29 #include "intel_de.h" 30 #include "intel_display_power_well.h" 31 #include "intel_display_types.h" 32 #include "intel_dp.h" 33 #include "intel_dpio_phy.h" 34 #include "vlv_dpio_phy_regs.h" 35 #include "vlv_sideband.h" 36 37 /** 38 * DOC: DPIO 39 * 40 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 41 * ports. DPIO is the name given to such a display PHY. These PHYs 42 * don't follow the standard programming model using direct MMIO 43 * registers, and instead their registers must be accessed trough IOSF 44 * sideband. VLV has one such PHY for driving ports B and C, and CHV 45 * adds another PHY for driving port D. Each PHY responds to specific 46 * IOSF-SB port. 47 * 48 * Each display PHY is made up of one or two channels. Each channel 49 * houses a common lane part which contains the PLL and other common 50 * logic. CH0 common lane also contains the IOSF-SB logic for the 51 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 52 * must be running when any DPIO registers are accessed. 53 * 54 * In addition to having their own registers, the PHYs are also 55 * controlled through some dedicated signals from the display 56 * controller. These include PLL reference clock enable, PLL enable, 57 * and CRI clock selection, for example. 58 * 59 * Eeach channel also has two splines (also called data lanes), and 60 * each spline is made up of one Physical Access Coding Sub-Layer 61 * (PCS) block and two TX lanes. So each channel has two PCS blocks 62 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 63 * data/clock pairs depending on the output type. 64 * 65 * Additionally the PHY also contains an AUX lane with AUX blocks 66 * for each channel. This is used for DP AUX communication, but 67 * this fact isn't really relevant for the driver since AUX is 68 * controlled from the display controller side. No DPIO registers 69 * need to be accessed during AUX communication, 70 * 71 * Generally on VLV/CHV the common lane corresponds to the pipe and 72 * the spline (PCS/TX) corresponds to the port. 73 * 74 * For dual channel PHY (VLV/CHV): 75 * 76 * pipe A == CMN/PLL/REF CH0 77 * 78 * pipe B == CMN/PLL/REF CH1 79 * 80 * port B == PCS/TX CH0 81 * 82 * port C == PCS/TX CH1 83 * 84 * This is especially important when we cross the streams 85 * ie. drive port B with pipe B, or port C with pipe A. 86 * 87 * For single channel PHY (CHV): 88 * 89 * pipe C == CMN/PLL/REF CH0 90 * 91 * port D == PCS/TX CH0 92 * 93 * On BXT the entire PHY channel corresponds to the port. That means 94 * the PLL is also now associated with the port rather than the pipe, 95 * and so the clock needs to be routed to the appropriate transcoder. 96 * Port A PLL is directly connected to transcoder EDP and port B/C 97 * PLLs can be routed to any transcoder A/B/C. 98 * 99 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 100 * digital port D (CHV) or port A (BXT). :: 101 * 102 * 103 * Dual channel PHY (VLV/CHV/BXT) 104 * --------------------------------- 105 * | CH0 | CH1 | 106 * | CMN/PLL/REF | CMN/PLL/REF | 107 * |---------------|---------------| Display PHY 108 * | PCS01 | PCS23 | PCS01 | PCS23 | 109 * |-------|-------|-------|-------| 110 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 111 * --------------------------------- 112 * | DDI0 | DDI1 | DP/HDMI ports 113 * --------------------------------- 114 * 115 * Single channel PHY (CHV/BXT) 116 * ----------------- 117 * | CH0 | 118 * | CMN/PLL/REF | 119 * |---------------| Display PHY 120 * | PCS01 | PCS23 | 121 * |-------|-------| 122 * |TX0|TX1|TX2|TX3| 123 * ----------------- 124 * | DDI2 | DP/HDMI port 125 * ----------------- 126 */ 127 128 /** 129 * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy 130 */ 131 struct bxt_dpio_phy_info { 132 /** 133 * @dual_channel: true if this phy has a second channel. 134 */ 135 bool dual_channel; 136 137 /** 138 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 139 * Otherwise the GRC value will be copied from the phy indicated by 140 * this field. 141 */ 142 enum dpio_phy rcomp_phy; 143 144 /** 145 * @reset_delay: delay in us to wait before setting the common reset 146 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. 147 */ 148 int reset_delay; 149 150 /** 151 * @pwron_mask: Mask with the appropriate bit set that would cause the 152 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. 153 */ 154 u32 pwron_mask; 155 156 /** 157 * @channel: struct containing per channel information. 158 */ 159 struct { 160 /** 161 * @channel.port: which port maps to this channel. 162 */ 163 enum port port; 164 } channel[2]; 165 }; 166 167 static const struct bxt_dpio_phy_info bxt_dpio_phy_info[] = { 168 [DPIO_PHY0] = { 169 .dual_channel = true, 170 .rcomp_phy = DPIO_PHY1, 171 .pwron_mask = BIT(0), 172 173 .channel = { 174 [DPIO_CH0] = { .port = PORT_B }, 175 [DPIO_CH1] = { .port = PORT_C }, 176 } 177 }, 178 [DPIO_PHY1] = { 179 .dual_channel = false, 180 .rcomp_phy = -1, 181 .pwron_mask = BIT(1), 182 183 .channel = { 184 [DPIO_CH0] = { .port = PORT_A }, 185 } 186 }, 187 }; 188 189 static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = { 190 [DPIO_PHY0] = { 191 .dual_channel = false, 192 .rcomp_phy = DPIO_PHY1, 193 .pwron_mask = BIT(0), 194 .reset_delay = 20, 195 196 .channel = { 197 [DPIO_CH0] = { .port = PORT_B }, 198 } 199 }, 200 [DPIO_PHY1] = { 201 .dual_channel = false, 202 .rcomp_phy = -1, 203 .pwron_mask = BIT(3), 204 .reset_delay = 20, 205 206 .channel = { 207 [DPIO_CH0] = { .port = PORT_A }, 208 } 209 }, 210 [DPIO_PHY2] = { 211 .dual_channel = false, 212 .rcomp_phy = DPIO_PHY1, 213 .pwron_mask = BIT(1), 214 .reset_delay = 20, 215 216 .channel = { 217 [DPIO_CH0] = { .port = PORT_C }, 218 } 219 }, 220 }; 221 222 static const struct bxt_dpio_phy_info * 223 bxt_get_phy_list(struct intel_display *display, int *count) 224 { 225 struct drm_i915_private *dev_priv = to_i915(display->drm); 226 227 if (IS_GEMINILAKE(dev_priv)) { 228 *count = ARRAY_SIZE(glk_dpio_phy_info); 229 return glk_dpio_phy_info; 230 } else { 231 *count = ARRAY_SIZE(bxt_dpio_phy_info); 232 return bxt_dpio_phy_info; 233 } 234 } 235 236 static const struct bxt_dpio_phy_info * 237 bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy) 238 { 239 int count; 240 const struct bxt_dpio_phy_info *phy_list = 241 bxt_get_phy_list(display, &count); 242 243 return &phy_list[phy]; 244 } 245 246 void bxt_port_to_phy_channel(struct intel_display *display, enum port port, 247 enum dpio_phy *phy, enum dpio_channel *ch) 248 { 249 const struct bxt_dpio_phy_info *phy_info, *phys; 250 int i, count; 251 252 phys = bxt_get_phy_list(display, &count); 253 254 for (i = 0; i < count; i++) { 255 phy_info = &phys[i]; 256 257 if (port == phy_info->channel[DPIO_CH0].port) { 258 *phy = i; 259 *ch = DPIO_CH0; 260 return; 261 } 262 263 if (phy_info->dual_channel && 264 port == phy_info->channel[DPIO_CH1].port) { 265 *phy = i; 266 *ch = DPIO_CH1; 267 return; 268 } 269 } 270 271 drm_WARN(display->drm, 1, "PHY not found for PORT %c", 272 port_name(port)); 273 *phy = DPIO_PHY0; 274 *ch = DPIO_CH0; 275 } 276 277 /* 278 * Like intel_de_rmw() but reads from a single per-lane register and 279 * writes to the group register to write the same value to all the lanes. 280 */ 281 static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display, 282 i915_reg_t reg_single, 283 i915_reg_t reg_group, 284 u32 clear, u32 set) 285 { 286 u32 old, val; 287 288 old = intel_de_read(display, reg_single); 289 val = (old & ~clear) | set; 290 intel_de_write(display, reg_group, val); 291 292 return old; 293 } 294 295 void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder, 296 const struct intel_crtc_state *crtc_state) 297 { 298 struct intel_display *display = to_intel_display(encoder); 299 const struct intel_ddi_buf_trans *trans; 300 enum dpio_channel ch; 301 enum dpio_phy phy; 302 int lane, n_entries; 303 304 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 305 if (drm_WARN_ON_ONCE(display->drm, !trans)) 306 return; 307 308 bxt_port_to_phy_channel(display, encoder->port, &phy, &ch); 309 310 /* 311 * While we write to the group register to program all lanes at once we 312 * can read only lane registers and we pick lanes 0/1 for that. 313 */ 314 bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch), 315 BXT_PORT_PCS_DW10_GRP(phy, ch), 316 TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0); 317 318 for (lane = 0; lane < crtc_state->lane_count; lane++) { 319 int level = intel_ddi_level(encoder, crtc_state, lane); 320 321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), 322 MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK, 323 MARGIN_000(trans->entries[level].bxt.margin) | 324 UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale)); 325 } 326 327 for (lane = 0; lane < crtc_state->lane_count; lane++) { 328 int level = intel_ddi_level(encoder, crtc_state, lane); 329 u32 val; 330 331 intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane), 332 SCALE_DCOMP_METHOD, 333 trans->entries[level].bxt.enable ? 334 SCALE_DCOMP_METHOD : 0); 335 336 val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane)); 337 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 338 drm_err(display->drm, 339 "Disabled scaling while ouniqetrangenmethod was set"); 340 } 341 342 for (lane = 0; lane < crtc_state->lane_count; lane++) { 343 int level = intel_ddi_level(encoder, crtc_state, lane); 344 345 intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane), 346 DE_EMPHASIS_MASK, 347 DE_EMPHASIS(trans->entries[level].bxt.deemphasis)); 348 } 349 350 bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch), 351 BXT_PORT_PCS_DW10_GRP(phy, ch), 352 0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 353 } 354 355 bool bxt_dpio_phy_is_enabled(struct intel_display *display, 356 enum dpio_phy phy) 357 { 358 const struct bxt_dpio_phy_info *phy_info; 359 360 phy_info = bxt_get_phy_info(display, phy); 361 362 if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 363 return false; 364 365 if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) & 366 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 367 drm_dbg(display->drm, 368 "DDI PHY %d powered, but power hasn't settled\n", phy); 369 370 return false; 371 } 372 373 if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 374 drm_dbg(display->drm, 375 "DDI PHY %d powered, but still in reset\n", phy); 376 377 return false; 378 } 379 380 return true; 381 } 382 383 static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy) 384 { 385 u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy)); 386 387 return REG_FIELD_GET(GRC_CODE_MASK, val); 388 } 389 390 static void bxt_phy_wait_grc_done(struct intel_display *display, 391 enum dpio_phy phy) 392 { 393 if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10)) 394 drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy); 395 } 396 397 static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) 398 { 399 const struct bxt_dpio_phy_info *phy_info; 400 u32 val; 401 402 phy_info = bxt_get_phy_info(display, phy); 403 404 if (bxt_dpio_phy_is_enabled(display, phy)) { 405 /* Still read out the GRC value for state verification */ 406 if (phy_info->rcomp_phy != -1) 407 display->state.bxt_phy_grc = bxt_get_grc(display, phy); 408 409 if (bxt_dpio_phy_verify_state(display, phy)) { 410 drm_dbg(display->drm, "DDI PHY %d already enabled, " 411 "won't reprogram it\n", phy); 412 return; 413 } 414 415 drm_dbg(display->drm, 416 "DDI PHY %d enabled with invalid state, " 417 "force reprogramming it\n", phy); 418 } 419 420 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); 421 422 /* 423 * The PHY registers start out inaccessible and respond to reads with 424 * all 1s. Eventually they become accessible as they power up, then 425 * the reserved bit will give the default 0. Poll on the reserved bit 426 * becoming 0 to find when the PHY is accessible. 427 * The flag should get set in 100us according to the HW team, but 428 * use 1ms due to occasional timeouts observed with that. 429 */ 430 if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy), 431 PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1)) 432 drm_err(display->drm, "timeout during PHY%d power on\n", 433 phy); 434 435 /* Program PLL Rcomp code offset */ 436 intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy), 437 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4)); 438 439 intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy), 440 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4)); 441 442 /* Program power gating */ 443 intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0, 444 OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG); 445 446 if (phy_info->dual_channel) 447 intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0, 448 DW6_OLDO_DYN_PWR_DOWN_EN); 449 450 if (phy_info->rcomp_phy != -1) { 451 u32 grc_code; 452 453 bxt_phy_wait_grc_done(display, phy_info->rcomp_phy); 454 455 /* 456 * PHY0 isn't connected to an RCOMP resistor so copy over 457 * the corresponding calibrated value from PHY1, and disable 458 * the automatic calibration on PHY0. 459 */ 460 val = bxt_get_grc(display, phy_info->rcomp_phy); 461 display->state.bxt_phy_grc = val; 462 463 grc_code = GRC_CODE_FAST(val) | 464 GRC_CODE_SLOW(val) | 465 GRC_CODE_NOM(val); 466 intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code); 467 intel_de_rmw(display, BXT_PORT_REF_DW8(phy), 468 0, GRC_DIS | GRC_RDY_OVRD); 469 } 470 471 if (phy_info->reset_delay) 472 udelay(phy_info->reset_delay); 473 474 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); 475 } 476 477 void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy) 478 { 479 const struct bxt_dpio_phy_info *phy_info; 480 481 phy_info = bxt_get_phy_info(display, phy); 482 483 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); 484 485 intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); 486 } 487 488 void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy) 489 { 490 const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy); 491 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 492 bool was_enabled; 493 494 lockdep_assert_held(&display->power.domains.lock); 495 496 was_enabled = true; 497 if (rcomp_phy != -1) 498 was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy); 499 500 /* 501 * We need to copy the GRC calibration value from rcomp_phy, 502 * so make sure it's powered up. 503 */ 504 if (!was_enabled) 505 _bxt_dpio_phy_init(display, rcomp_phy); 506 507 _bxt_dpio_phy_init(display, phy); 508 509 if (!was_enabled) 510 bxt_dpio_phy_uninit(display, rcomp_phy); 511 } 512 513 static bool __printf(6, 7) 514 __phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy, 515 i915_reg_t reg, u32 mask, u32 expected, 516 const char *reg_fmt, ...) 517 { 518 struct va_format vaf; 519 va_list args; 520 u32 val; 521 522 val = intel_de_read(display, reg); 523 if ((val & mask) == expected) 524 return true; 525 526 va_start(args, reg_fmt); 527 vaf.fmt = reg_fmt; 528 vaf.va = &args; 529 530 drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " 531 "current %08x, expected %08x (mask %08x)\n", 532 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 533 mask); 534 535 va_end(args); 536 537 return false; 538 } 539 540 bool bxt_dpio_phy_verify_state(struct intel_display *display, 541 enum dpio_phy phy) 542 { 543 const struct bxt_dpio_phy_info *phy_info; 544 u32 mask; 545 bool ok; 546 547 phy_info = bxt_get_phy_info(display, phy); 548 549 #define _CHK(reg, mask, exp, fmt, ...) \ 550 __phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \ 551 ## __VA_ARGS__) 552 553 if (!bxt_dpio_phy_is_enabled(display, phy)) 554 return false; 555 556 ok = true; 557 558 /* PLL Rcomp code offset */ 559 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 560 IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xe4), 561 "BXT_PORT_CL1CM_DW9(%d)", phy); 562 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 563 IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xe4), 564 "BXT_PORT_CL1CM_DW10(%d)", phy); 565 566 /* Power gating */ 567 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 568 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 569 "BXT_PORT_CL1CM_DW28(%d)", phy); 570 571 if (phy_info->dual_channel) 572 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 573 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 574 "BXT_PORT_CL2CM_DW6(%d)", phy); 575 576 if (phy_info->rcomp_phy != -1) { 577 u32 grc_code = display->state.bxt_phy_grc; 578 579 grc_code = GRC_CODE_FAST(grc_code) | 580 GRC_CODE_SLOW(grc_code) | 581 GRC_CODE_NOM(grc_code); 582 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 583 GRC_CODE_NOM_MASK; 584 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 585 "BXT_PORT_REF_DW6(%d)", phy); 586 587 mask = GRC_DIS | GRC_RDY_OVRD; 588 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 589 "BXT_PORT_REF_DW8(%d)", phy); 590 } 591 592 return ok; 593 #undef _CHK 594 } 595 596 u8 597 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) 598 { 599 switch (lane_count) { 600 case 1: 601 return 0; 602 case 2: 603 return BIT(2) | BIT(0); 604 case 4: 605 return BIT(3) | BIT(2) | BIT(0); 606 default: 607 MISSING_CASE(lane_count); 608 609 return 0; 610 } 611 } 612 613 void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder, 614 u8 lane_lat_optim_mask) 615 { 616 struct intel_display *display = to_intel_display(encoder); 617 enum port port = encoder->port; 618 enum dpio_phy phy; 619 enum dpio_channel ch; 620 int lane; 621 622 bxt_port_to_phy_channel(display, port, &phy, &ch); 623 624 for (lane = 0; lane < 4; lane++) { 625 /* 626 * Note that on CHV this flag is called UPAR, but has 627 * the same function. 628 */ 629 intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane), 630 LATENCY_OPTIM, 631 lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0); 632 } 633 } 634 635 u8 636 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 637 { 638 struct intel_display *display = to_intel_display(encoder); 639 enum port port = encoder->port; 640 enum dpio_phy phy; 641 enum dpio_channel ch; 642 int lane; 643 u8 mask; 644 645 bxt_port_to_phy_channel(display, port, &phy, &ch); 646 647 mask = 0; 648 for (lane = 0; lane < 4; lane++) { 649 u32 val = intel_de_read(display, 650 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 651 652 if (val & LATENCY_OPTIM) 653 mask |= BIT(lane); 654 } 655 656 return mask; 657 } 658 659 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 660 { 661 switch (dig_port->base.port) { 662 default: 663 MISSING_CASE(dig_port->base.port); 664 fallthrough; 665 case PORT_B: 666 case PORT_D: 667 return DPIO_CH0; 668 case PORT_C: 669 return DPIO_CH1; 670 } 671 } 672 673 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 674 { 675 switch (dig_port->base.port) { 676 default: 677 MISSING_CASE(dig_port->base.port); 678 fallthrough; 679 case PORT_B: 680 case PORT_C: 681 return DPIO_PHY0; 682 case PORT_D: 683 return DPIO_PHY1; 684 } 685 } 686 687 enum dpio_phy vlv_pipe_to_phy(enum pipe pipe) 688 { 689 switch (pipe) { 690 default: 691 MISSING_CASE(pipe); 692 fallthrough; 693 case PIPE_A: 694 case PIPE_B: 695 return DPIO_PHY0; 696 case PIPE_C: 697 return DPIO_PHY1; 698 } 699 } 700 701 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) 702 { 703 switch (pipe) { 704 default: 705 MISSING_CASE(pipe); 706 fallthrough; 707 case PIPE_A: 708 case PIPE_C: 709 return DPIO_CH0; 710 case PIPE_B: 711 return DPIO_CH1; 712 } 713 } 714 715 void chv_set_phy_signal_level(struct intel_encoder *encoder, 716 const struct intel_crtc_state *crtc_state, 717 u32 deemph_reg_value, u32 margin_reg_value, 718 bool uniq_trans_scale) 719 { 720 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 721 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 722 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 723 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 724 u32 val; 725 int i; 726 727 vlv_dpio_get(dev_priv); 728 729 /* Clear calc init */ 730 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); 731 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 732 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 733 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 734 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); 735 736 if (crtc_state->lane_count > 2) { 737 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); 738 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 739 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 740 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 741 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); 742 } 743 744 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW9(ch)); 745 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 746 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 747 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW9(ch), val); 748 749 if (crtc_state->lane_count > 2) { 750 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW9(ch)); 751 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 752 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 753 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW9(ch), val); 754 } 755 756 /* Program swing deemph */ 757 for (i = 0; i < crtc_state->lane_count; i++) { 758 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); 759 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 760 val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); 761 vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val); 762 } 763 764 /* Program swing margin */ 765 for (i = 0; i < crtc_state->lane_count; i++) { 766 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); 767 768 val &= ~DPIO_SWING_MARGIN000_MASK; 769 val |= DPIO_SWING_MARGIN000(margin_reg_value); 770 771 /* 772 * Supposedly this value shouldn't matter when unique transition 773 * scale is disabled, but in fact it does matter. Let's just 774 * always program the same value and hope it's OK. 775 */ 776 val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; 777 val |= DPIO_UNIQ_TRANS_SCALE(0x9a); 778 779 vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val); 780 } 781 782 /* 783 * The document said it needs to set bit 27 for ch0 and bit 26 784 * for ch1. Might be a typo in the doc. 785 * For now, for this unique transition scale selection, set bit 786 * 27 for ch0 and ch1. 787 */ 788 for (i = 0; i < crtc_state->lane_count; i++) { 789 val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW3(ch, i)); 790 if (uniq_trans_scale) 791 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 792 else 793 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 794 vlv_dpio_write(dev_priv, phy, CHV_TX_DW3(ch, i), val); 795 } 796 797 /* Start swing calculation */ 798 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW10(ch)); 799 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 800 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW10(ch), val); 801 802 if (crtc_state->lane_count > 2) { 803 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW10(ch)); 804 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 805 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW10(ch), val); 806 } 807 808 vlv_dpio_put(dev_priv); 809 } 810 811 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 812 const struct intel_crtc_state *crtc_state, 813 bool reset) 814 { 815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 816 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 817 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 818 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 819 u32 val; 820 821 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); 822 if (reset) 823 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 824 else 825 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 826 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW0(ch), val); 827 828 if (crtc_state->lane_count > 2) { 829 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW0(ch)); 830 if (reset) 831 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 832 else 833 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 834 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW0(ch), val); 835 } 836 837 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW1(ch)); 838 val |= CHV_PCS_REQ_SOFTRESET_EN; 839 if (reset) 840 val &= ~DPIO_PCS_CLK_SOFT_RESET; 841 else 842 val |= DPIO_PCS_CLK_SOFT_RESET; 843 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW1(ch), val); 844 845 if (crtc_state->lane_count > 2) { 846 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW1(ch)); 847 val |= CHV_PCS_REQ_SOFTRESET_EN; 848 if (reset) 849 val &= ~DPIO_PCS_CLK_SOFT_RESET; 850 else 851 val |= DPIO_PCS_CLK_SOFT_RESET; 852 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW1(ch), val); 853 } 854 } 855 856 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 857 const struct intel_crtc_state *crtc_state) 858 { 859 struct intel_display *display = to_intel_display(encoder); 860 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 863 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 864 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 865 enum pipe pipe = crtc->pipe; 866 unsigned int lane_mask = 867 intel_dp_unused_lane_mask(crtc_state->lane_count); 868 u32 val; 869 870 /* 871 * Must trick the second common lane into life. 872 * Otherwise we can't even access the PLL. 873 */ 874 if (ch == DPIO_CH0 && pipe == PIPE_B) 875 dig_port->release_cl2_override = 876 !chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, true); 877 878 chv_phy_powergate_lanes(encoder, true, lane_mask); 879 880 vlv_dpio_get(dev_priv); 881 882 /* Assert data lane reset */ 883 chv_data_lane_soft_reset(encoder, crtc_state, true); 884 885 /* program left/right clock distribution */ 886 if (pipe != PIPE_B) { 887 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); 888 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 889 if (ch == DPIO_CH0) 890 val |= CHV_BUFLEFTENA1_FORCE; 891 if (ch == DPIO_CH1) 892 val |= CHV_BUFRIGHTENA1_FORCE; 893 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); 894 } else { 895 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); 896 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 897 if (ch == DPIO_CH0) 898 val |= CHV_BUFLEFTENA2_FORCE; 899 if (ch == DPIO_CH1) 900 val |= CHV_BUFRIGHTENA2_FORCE; 901 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); 902 } 903 904 /* program clock channel usage */ 905 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch)); 906 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 907 if (pipe == PIPE_B) 908 val |= DPIO_PCS_USEDCLKCHANNEL; 909 else 910 val &= ~DPIO_PCS_USEDCLKCHANNEL; 911 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val); 912 913 if (crtc_state->lane_count > 2) { 914 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch)); 915 val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 916 if (pipe == PIPE_B) 917 val |= DPIO_PCS_USEDCLKCHANNEL; 918 else 919 val &= ~DPIO_PCS_USEDCLKCHANNEL; 920 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val); 921 } 922 923 /* 924 * This a a bit weird since generally CL 925 * matches the pipe, but here we need to 926 * pick the CL based on the port. 927 */ 928 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch)); 929 if (pipe == PIPE_B) 930 val |= CHV_CMN_USEDCLKCHANNEL; 931 else 932 val &= ~CHV_CMN_USEDCLKCHANNEL; 933 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val); 934 935 vlv_dpio_put(dev_priv); 936 } 937 938 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 939 const struct intel_crtc_state *crtc_state) 940 { 941 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 942 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 944 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 945 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 946 int data, i, stagger; 947 u32 val; 948 949 vlv_dpio_get(dev_priv); 950 951 /* allow hardware to manage TX FIFO reset source */ 952 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); 953 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 954 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); 955 956 if (crtc_state->lane_count > 2) { 957 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); 958 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 959 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); 960 } 961 962 /* Program Tx lane latency optimal setting*/ 963 for (i = 0; i < crtc_state->lane_count; i++) { 964 /* Set the upar bit */ 965 if (crtc_state->lane_count == 1) 966 data = 0; 967 else 968 data = (i == 1) ? 0 : DPIO_UPAR; 969 vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data); 970 } 971 972 /* Data lane stagger programming */ 973 if (crtc_state->port_clock > 270000) 974 stagger = 0x18; 975 else if (crtc_state->port_clock > 135000) 976 stagger = 0xd; 977 else if (crtc_state->port_clock > 67500) 978 stagger = 0x7; 979 else if (crtc_state->port_clock > 33750) 980 stagger = 0x4; 981 else 982 stagger = 0x2; 983 984 val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW11(ch)); 985 val |= DPIO_TX2_STAGGER_MASK(0x1f); 986 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW11(ch), val); 987 988 if (crtc_state->lane_count > 2) { 989 val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW11(ch)); 990 val |= DPIO_TX2_STAGGER_MASK(0x1f); 991 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW11(ch), val); 992 } 993 994 vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW12(ch), 995 DPIO_LANESTAGGER_STRAP(stagger) | 996 DPIO_LANESTAGGER_STRAP_OVRD | 997 DPIO_TX1_STAGGER_MASK(0x1f) | 998 DPIO_TX1_STAGGER_MULT(6) | 999 DPIO_TX2_STAGGER_MULT(0)); 1000 1001 if (crtc_state->lane_count > 2) { 1002 vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW12(ch), 1003 DPIO_LANESTAGGER_STRAP(stagger) | 1004 DPIO_LANESTAGGER_STRAP_OVRD | 1005 DPIO_TX1_STAGGER_MASK(0x1f) | 1006 DPIO_TX1_STAGGER_MULT(7) | 1007 DPIO_TX2_STAGGER_MULT(5)); 1008 } 1009 1010 /* Deassert data lane reset */ 1011 chv_data_lane_soft_reset(encoder, crtc_state, false); 1012 1013 vlv_dpio_put(dev_priv); 1014 } 1015 1016 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 1017 { 1018 struct intel_display *display = to_intel_display(encoder); 1019 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1020 1021 if (dig_port->release_cl2_override) { 1022 chv_phy_powergate_ch(display, DPIO_PHY0, DPIO_CH1, false); 1023 dig_port->release_cl2_override = false; 1024 } 1025 } 1026 1027 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 1028 const struct intel_crtc_state *old_crtc_state) 1029 { 1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1031 enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); 1032 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; 1033 u32 val; 1034 1035 vlv_dpio_get(dev_priv); 1036 1037 /* disable left/right clock distribution */ 1038 if (pipe != PIPE_B) { 1039 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); 1040 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1041 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); 1042 } else { 1043 val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); 1044 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1045 vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); 1046 } 1047 1048 vlv_dpio_put(dev_priv); 1049 1050 /* 1051 * Leave the power down bit cleared for at least one 1052 * lane so that chv_powergate_phy_ch() will power 1053 * on something when the channel is otherwise unused. 1054 * When the port is off and the override is removed 1055 * the lanes power down anyway, so otherwise it doesn't 1056 * really matter what the state of power down bits is 1057 * after this. 1058 */ 1059 chv_phy_powergate_lanes(encoder, false, 0x0); 1060 } 1061 1062 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 1063 const struct intel_crtc_state *crtc_state, 1064 u32 demph_reg_value, u32 preemph_reg_value, 1065 u32 uniqtranscale_reg_value, u32 tx3_demph) 1066 { 1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1068 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1069 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1070 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1071 1072 vlv_dpio_get(dev_priv); 1073 1074 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000); 1075 vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); 1076 vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch), 1077 uniqtranscale_reg_value); 1078 vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); 1079 1080 if (tx3_demph) 1081 vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph); 1082 1083 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); 1084 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); 1085 vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); 1086 1087 vlv_dpio_put(dev_priv); 1088 } 1089 1090 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 1091 const struct intel_crtc_state *crtc_state) 1092 { 1093 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1095 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1096 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1097 1098 /* Program Tx lane resets to default */ 1099 vlv_dpio_get(dev_priv); 1100 1101 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 1102 DPIO_PCS_TX_LANE2_RESET | 1103 DPIO_PCS_TX_LANE1_RESET); 1104 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 1105 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1106 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1107 DPIO_PCS_CLK_DATAWIDTH_8_10 | 1108 DPIO_PCS_CLK_SOFT_RESET); 1109 1110 /* Fix up inter-pair skew failure */ 1111 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); 1112 vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500); 1113 vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000); 1114 1115 vlv_dpio_put(dev_priv); 1116 } 1117 1118 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 1119 const struct intel_crtc_state *crtc_state) 1120 { 1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1122 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1125 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1126 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1127 enum pipe pipe = crtc->pipe; 1128 u32 val; 1129 1130 vlv_dpio_get(dev_priv); 1131 1132 /* Enable clock channels for this port */ 1133 val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; 1134 if (pipe == PIPE_B) 1135 val |= DPIO_PCS_USEDCLKCHANNEL; 1136 val |= 0xc4; 1137 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val); 1138 1139 /* Program lane clock */ 1140 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); 1141 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); 1142 1143 vlv_dpio_put(dev_priv); 1144 } 1145 1146 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 1147 const struct intel_crtc_state *old_crtc_state) 1148 { 1149 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1151 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 1152 enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); 1153 1154 vlv_dpio_get(dev_priv); 1155 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); 1156 vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); 1157 vlv_dpio_put(dev_priv); 1158 } 1159